Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	809	1			T33	7		T14	4		T15	14
all_values[1]	809	1			T33	7		T14	4		T15	14
all_values[2]	809	1			T33	7		T14	4		T15	14
all_values[3]	809	1			T33	7		T14	4		T15	14
all_values[4]	809	1			T33	7		T14	4		T15	14
all_values[5]	809	1			T33	7		T14	4		T15	14
all_values[6]	809	1			T33	7		T14	4		T15	14
all_values[7]	809	1			T33	7		T14	4		T15	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3391

1

T33

32

T14

20

T15

49

auto[1]

3081

1

T33

24

T14

12

T15

63

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2657

1

T33

21

T14

14

T15

44

auto[1]

3815

1

T33

35

T14

18

T15

68

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3772

1

T33

30

T14

20

T15

64

auto[1]

2700

1

T33

26

T14

12

T15

48

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	166	1			T33	3		T14	4		T15	3
all_values[0]	auto[0]	auto[0]	auto[1]	83	1			T17	2		T18	1		T20	1
all_values[0]	auto[0]	auto[1]	auto[0]	150	1			T17	1		T18	1		T20	2
all_values[0]	auto[0]	auto[1]	auto[1]	83	1			T15	3		T17	1		T19	1
all_values[0]	auto[1]	auto[0]	auto[1]	170	1			T33	1		T15	3		T17	3
all_values[0]	auto[1]	auto[1]	auto[1]	157	1			T33	3		T15	5		T17	4
all_values[1]	auto[0]	auto[0]	auto[0]	174	1			T15	1		T17	3		T18	1
all_values[1]	auto[0]	auto[0]	auto[1]	67	1			T33	2		T17	3		T18	1
all_values[1]	auto[0]	auto[1]	auto[0]	156	1			T33	2		T14	4		T15	6
all_values[1]	auto[0]	auto[1]	auto[1]	79	1			T15	1		T19	2		T20	3
all_values[1]	auto[1]	auto[0]	auto[1]	180	1			T33	1		T15	2		T17	1
all_values[1]	auto[1]	auto[1]	auto[1]	153	1			T33	2		T15	4		T17	3
all_values[2]	auto[0]	auto[0]	auto[0]	174	1			T15	3		T17	2		T18	2
all_values[2]	auto[0]	auto[0]	auto[1]	69	1			T33	2		T15	1		T17	1
all_values[2]	auto[0]	auto[1]	auto[0]	145	1			T14	1		T15	1		T17	1
all_values[2]	auto[0]	auto[1]	auto[1]	90	1			T14	1		T15	4		T17	3
all_values[2]	auto[1]	auto[0]	auto[1]	194	1			T33	4		T14	1		T15	2
all_values[2]	auto[1]	auto[1]	auto[1]	137	1			T33	1		T14	1		T15	3
all_values[3]	auto[0]	auto[0]	auto[0]	166	1			T33	5		T15	2		T17	3
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T14	2		T15	1		T18	1
all_values[3]	auto[0]	auto[1]	auto[0]	141	1			T33	1		T15	2		T17	2
all_values[3]	auto[0]	auto[1]	auto[1]	87	1			T15	4		T17	2		T18	3
all_values[3]	auto[1]	auto[0]	auto[1]	182	1			T33	1		T14	1		T15	2
all_values[3]	auto[1]	auto[1]	auto[1]	160	1			T14	1		T15	3		T17	4
all_values[4]	auto[0]	auto[0]	auto[0]	160	1			T33	1		T15	5		T17	4
all_values[4]	auto[0]	auto[0]	auto[1]	80	1			T14	1		T17	2		T20	1
all_values[4]	auto[0]	auto[1]	auto[0]	143	1			T33	3		T14	1		T15	3
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T33	1		T15	1		T18	3
all_values[4]	auto[1]	auto[0]	auto[1]	193	1			T33	1		T14	2		T15	1
all_values[4]	auto[1]	auto[1]	auto[1]	160	1			T33	1		T15	4		T17	1
all_values[5]	auto[0]	auto[0]	auto[0]	268	1			T33	1		T14	2		T15	5
all_values[5]	auto[0]	auto[1]	auto[0]	222	1			T33	3		T15	2		T17	1
all_values[5]	auto[1]	auto[0]	auto[1]	163	1			T14	1		T15	3		T17	1
all_values[5]	auto[1]	auto[1]	auto[1]	156	1			T33	3		T14	1		T15	4
all_values[6]	auto[0]	auto[0]	auto[0]	160	1			T33	1		T14	1		T15	2
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T33	3		T14	1		T15	3
all_values[6]	auto[0]	auto[1]	auto[0]	138	1			T33	1		T15	1		T17	1
all_values[6]	auto[0]	auto[1]	auto[1]	81	1			T15	1		T20	3		T163	2
all_values[6]	auto[1]	auto[0]	auto[1]	197	1			T33	2		T14	2		T15	3
all_values[6]	auto[1]	auto[1]	auto[1]	155	1			T15	4		T17	2		T18	1
all_values[7]	auto[0]	auto[0]	auto[0]	144	1			T14	1		T15	3		T17	1
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T17	2		T18	1		T20	1
all_values[7]	auto[0]	auto[1]	auto[0]	150	1			T15	5		T17	2		T18	5
all_values[7]	auto[0]	auto[1]	auto[1]	93	1			T33	1		T14	1		T15	1
all_values[7]	auto[1]	auto[0]	auto[1]	171	1			T33	4		T14	1		T15	4
all_values[7]	auto[1]	auto[1]	auto[1]	172	1			T33	2		T14	1		T15	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal