Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1842

1

T11

6

T30

20

T31

19

auto[1]

1709

1

T11

2

T30

31

T31

15

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1843

1

T33

11

T34

5

T36

1

auto[1]

1708

1

T11

8

T30

51

T31

34

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2863

1

T11

8

T30

51

T31

34

auto[1]

688

1

T33

4

T34

4

T37

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	711	1			T11	2		T30	13		T31	7
valid[1]	717	1			T11	2		T30	10		T31	8
valid[2]	719	1			T11	1		T30	9		T31	7
valid[3]	714	1			T11	2		T30	9		T31	8
valid[4]	690	1			T11	1		T30	10		T31	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	110	1			T14	4		T25	2		T15	6
auto[0]	auto[0]	valid[0]	auto[1]	184	1			T11	1		T30	6		T31	4
auto[0]	auto[0]	valid[1]	auto[0]	140	1			T37	1		T14	4		T40	2
auto[0]	auto[0]	valid[1]	auto[1]	159	1			T11	2		T30	5		T31	4
auto[0]	auto[0]	valid[2]	auto[0]	110	1			T33	2		T37	1		T14	2
auto[0]	auto[0]	valid[2]	auto[1]	179	1			T11	1		T30	3		T31	4
auto[0]	auto[0]	valid[3]	auto[0]	103	1			T37	2		T14	2		T50	2
auto[0]	auto[0]	valid[3]	auto[1]	171	1			T11	1		T30	2		T31	5
auto[0]	auto[0]	valid[4]	auto[0]	135	1			T37	1		T14	1		T325	1
auto[0]	auto[0]	valid[4]	auto[1]	181	1			T11	1		T30	4		T31	2
auto[0]	auto[1]	valid[0]	auto[0]	118	1			T33	2		T36	1		T37	2
auto[0]	auto[1]	valid[0]	auto[1]	165	1			T11	1		T30	7		T31	3
auto[0]	auto[1]	valid[1]	auto[0]	107	1			T37	1		T14	2		T167	2
auto[0]	auto[1]	valid[1]	auto[1]	160	1			T30	5		T31	4		T25	1
auto[0]	auto[1]	valid[2]	auto[0]	120	1			T33	1		T37	1		T14	3
auto[0]	auto[1]	valid[2]	auto[1]	171	1			T30	6		T31	3		T326	2
auto[0]	auto[1]	valid[3]	auto[0]	106	1			T33	2		T34	1		T37	1
auto[0]	auto[1]	valid[3]	auto[1]	175	1			T11	1		T30	7		T31	3
auto[0]	auto[1]	valid[4]	auto[0]	106	1			T37	1		T40	1		T52	1
auto[0]	auto[1]	valid[4]	auto[1]	163	1			T30	6		T31	2		T32	1
auto[1]	auto[0]	valid[0]	auto[0]	70	1			T34	1		T15	1		T318	1
auto[1]	auto[0]	valid[1]	auto[0]	77	1			T34	1		T37	1		T25	1
auto[1]	auto[0]	valid[2]	auto[0]	78	1			T37	1		T14	2		T50	1
auto[1]	auto[0]	valid[3]	auto[0]	81	1			T33	2		T37	1		T25	1
auto[1]	auto[0]	valid[4]	auto[0]	64	1			T14	1		T16	2		T319	1
auto[1]	auto[1]	valid[0]	auto[0]	64	1			T34	1		T37	1		T14	1
auto[1]	auto[1]	valid[1]	auto[0]	74	1			T37	1		T14	1		T52	1
auto[1]	auto[1]	valid[2]	auto[0]	61	1			T33	1		T14	1		T25	1
auto[1]	auto[1]	valid[3]	auto[0]	78	1			T33	1		T34	1		T37	1
auto[1]	auto[1]	valid[4]	auto[0]	41	1			T14	1		T25	1		T50	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal