Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46578

1

T7

4

T33

121

T34

139

auto[1]

17867

1

T11

8

T30

580

T31

354

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47511

1

T7

2

T11

8

T30

580

auto[1]

16934

1

T7

2

T33

47

T34

49

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33258	1			T7	1		T11	8		T30	297
others[1]	5406	1			T30	51		T31	31		T33	18
others[2]	5469	1			T30	54		T31	37		T33	14
others[3]	6141	1			T30	49		T31	42		T33	12
interest[1]	3519	1			T7	1		T30	27		T31	21
interest[4]	21897	1			T7	1		T11	8		T30	200
interest[64]	10652	1			T7	2		T30	102		T31	61

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15145	1			T33	37		T34	49		T35	5
auto[0]	auto[0]	others[1]	2477	1			T33	7		T34	7		T36	1
auto[0]	auto[0]	others[2]	2612	1			T33	5		T34	10		T36	2
auto[0]	auto[0]	others[3]	2838	1			T33	7		T34	12		T36	3
auto[0]	auto[0]	interest[1]	1681	1			T7	1		T33	4		T34	4
auto[0]	auto[0]	interest[4]	9991	1			T33	18		T34	28		T35	4
auto[0]	auto[0]	interest[64]	4891	1			T7	1		T33	14		T34	8
auto[0]	auto[1]	others[0]	9376	1			T11	8		T30	297		T31	162
auto[0]	auto[1]	others[1]	1486	1			T30	51		T31	31		T33	7
auto[0]	auto[1]	others[2]	1406	1			T30	54		T31	37		T33	2
auto[0]	auto[1]	others[3]	1678	1			T30	49		T31	42		T33	4
auto[0]	auto[1]	interest[1]	931	1			T30	27		T31	21		T14	1
auto[0]	auto[1]	interest[4]	6189	1			T11	8		T30	200		T31	111
auto[0]	auto[1]	interest[64]	2990	1			T30	102		T31	61		T33	10
auto[1]	auto[0]	others[0]	8737	1			T7	1		T33	28		T34	29
auto[1]	auto[0]	others[1]	1443	1			T33	4		T34	1		T37	15
auto[1]	auto[0]	others[2]	1451	1			T33	7		T34	3		T36	3
auto[1]	auto[0]	others[3]	1625	1			T33	1		T34	4		T35	1
auto[1]	auto[0]	interest[1]	907	1			T33	1		T34	1		T37	9
auto[1]	auto[0]	interest[4]	5717	1			T7	1		T33	15		T34	22
auto[1]	auto[0]	interest[64]	2771	1			T7	1		T33	6		T34	11

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal