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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
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T122 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3898598794 Aug 10 07:18:42 PM PDT 24 Aug 10 07:18:57 PM PDT 24 918482559 ps
T1031 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1203037096 Aug 10 07:19:03 PM PDT 24 Aug 10 07:19:04 PM PDT 24 13311157 ps
T1032 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3733905801 Aug 10 07:18:55 PM PDT 24 Aug 10 07:18:57 PM PDT 24 65272851 ps
T1033 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1911345232 Aug 10 07:19:08 PM PDT 24 Aug 10 07:19:11 PM PDT 24 89208377 ps
T152 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1188089488 Aug 10 07:19:02 PM PDT 24 Aug 10 07:19:06 PM PDT 24 180982461 ps
T1034 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.303812602 Aug 10 07:18:58 PM PDT 24 Aug 10 07:19:01 PM PDT 24 162155838 ps
T1035 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3689547803 Aug 10 07:19:09 PM PDT 24 Aug 10 07:19:10 PM PDT 24 17618942 ps
T102 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.55729271 Aug 10 07:18:57 PM PDT 24 Aug 10 07:19:17 PM PDT 24 811953989 ps
T171 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3403866484 Aug 10 07:18:53 PM PDT 24 Aug 10 07:19:00 PM PDT 24 214214655 ps
T104 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1425069598 Aug 10 07:19:08 PM PDT 24 Aug 10 07:19:13 PM PDT 24 304524168 ps
T88 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2825011810 Aug 10 07:18:52 PM PDT 24 Aug 10 07:18:53 PM PDT 24 65418701 ps
T1036 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3864590003 Aug 10 07:19:08 PM PDT 24 Aug 10 07:19:09 PM PDT 24 36136269 ps
T123 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.9223822 Aug 10 07:19:00 PM PDT 24 Aug 10 07:19:02 PM PDT 24 237772358 ps
T177 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1371942438 Aug 10 07:18:46 PM PDT 24 Aug 10 07:18:59 PM PDT 24 196934689 ps
T1037 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.965740888 Aug 10 07:18:57 PM PDT 24 Aug 10 07:19:00 PM PDT 24 158101737 ps
T153 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3619977199 Aug 10 07:19:09 PM PDT 24 Aug 10 07:19:12 PM PDT 24 662195979 ps
T124 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2435198581 Aug 10 07:19:09 PM PDT 24 Aug 10 07:19:11 PM PDT 24 48274419 ps
T1038 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3231027749 Aug 10 07:19:04 PM PDT 24 Aug 10 07:19:07 PM PDT 24 210570286 ps
T1039 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3448759039 Aug 10 07:19:09 PM PDT 24 Aug 10 07:19:10 PM PDT 24 16056029 ps
T154 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3685057799 Aug 10 07:18:46 PM PDT 24 Aug 10 07:18:48 PM PDT 24 243330759 ps
T1040 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4160834301 Aug 10 07:19:12 PM PDT 24 Aug 10 07:19:13 PM PDT 24 45035529 ps
T125 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4214205852 Aug 10 07:18:56 PM PDT 24 Aug 10 07:18:57 PM PDT 24 50935785 ps
T1041 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2393506043 Aug 10 07:18:56 PM PDT 24 Aug 10 07:18:59 PM PDT 24 42482828 ps
T1042 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3731085802 Aug 10 07:18:57 PM PDT 24 Aug 10 07:19:18 PM PDT 24 765391503 ps
T1043 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3203243110 Aug 10 07:19:00 PM PDT 24 Aug 10 07:19:01 PM PDT 24 36321934 ps
T1044 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3526821948 Aug 10 07:19:01 PM PDT 24 Aug 10 07:19:02 PM PDT 24 37668195 ps
T172 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.43855421 Aug 10 07:18:42 PM PDT 24 Aug 10 07:19:04 PM PDT 24 1689743052 ps
T1045 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1813500086 Aug 10 07:19:10 PM PDT 24 Aug 10 07:19:11 PM PDT 24 14933437 ps
T1046 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3083798563 Aug 10 07:18:42 PM PDT 24 Aug 10 07:18:44 PM PDT 24 105438152 ps
T1047 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.273515443 Aug 10 07:19:05 PM PDT 24 Aug 10 07:19:06 PM PDT 24 56649148 ps
T173 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3026338152 Aug 10 07:19:06 PM PDT 24 Aug 10 07:19:24 PM PDT 24 301989515 ps
T1048 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.69404762 Aug 10 07:19:01 PM PDT 24 Aug 10 07:19:04 PM PDT 24 148690687 ps
T1049 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2956692251 Aug 10 07:19:00 PM PDT 24 Aug 10 07:19:02 PM PDT 24 202947889 ps
T1050 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2126508777 Aug 10 07:18:42 PM PDT 24 Aug 10 07:18:45 PM PDT 24 45014326 ps
T1051 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3703028399 Aug 10 07:19:12 PM PDT 24 Aug 10 07:19:13 PM PDT 24 60952420 ps
T1052 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.125837242 Aug 10 07:19:01 PM PDT 24 Aug 10 07:19:02 PM PDT 24 35736520 ps
T155 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1629821354 Aug 10 07:18:58 PM PDT 24 Aug 10 07:19:01 PM PDT 24 72678036 ps
T175 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.95607601 Aug 10 07:19:01 PM PDT 24 Aug 10 07:19:09 PM PDT 24 326900030 ps
T174 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3843546401 Aug 10 07:19:00 PM PDT 24 Aug 10 07:19:24 PM PDT 24 17482832905 ps
T126 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1734615859 Aug 10 07:18:55 PM PDT 24 Aug 10 07:19:16 PM PDT 24 303734252 ps
T1053 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4034916057 Aug 10 07:18:55 PM PDT 24 Aug 10 07:18:59 PM PDT 24 222469837 ps
T1054 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2292234422 Aug 10 07:18:51 PM PDT 24 Aug 10 07:18:54 PM PDT 24 298978714 ps
T1055 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3531173142 Aug 10 07:19:00 PM PDT 24 Aug 10 07:19:05 PM PDT 24 64083643 ps
T1056 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2883020586 Aug 10 07:19:00 PM PDT 24 Aug 10 07:19:01 PM PDT 24 42039195 ps
T1057 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1685469446 Aug 10 07:18:59 PM PDT 24 Aug 10 07:19:01 PM PDT 24 177011554 ps
T127 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.350062148 Aug 10 07:18:57 PM PDT 24 Aug 10 07:18:59 PM PDT 24 36174325 ps
T170 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1609006715 Aug 10 07:18:54 PM PDT 24 Aug 10 07:18:58 PM PDT 24 142270118 ps
T1058 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4084280597 Aug 10 07:19:06 PM PDT 24 Aug 10 07:19:07 PM PDT 24 38821957 ps
T1059 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2843464801 Aug 10 07:19:13 PM PDT 24 Aug 10 07:19:14 PM PDT 24 33544136 ps
T1060 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3315051634 Aug 10 07:18:59 PM PDT 24 Aug 10 07:19:04 PM PDT 24 730669865 ps
T1061 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.694474668 Aug 10 07:18:55 PM PDT 24 Aug 10 07:18:56 PM PDT 24 11518770 ps
T182 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.979862588 Aug 10 07:18:57 PM PDT 24 Aug 10 07:19:09 PM PDT 24 754552291 ps
T1062 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1903924187 Aug 10 07:19:00 PM PDT 24 Aug 10 07:19:06 PM PDT 24 176233010 ps
T181 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.983467408 Aug 10 07:19:01 PM PDT 24 Aug 10 07:19:08 PM PDT 24 433210146 ps
T1063 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.229470799 Aug 10 07:18:47 PM PDT 24 Aug 10 07:18:55 PM PDT 24 1488393785 ps
T1064 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3850647928 Aug 10 07:19:04 PM PDT 24 Aug 10 07:19:07 PM PDT 24 134467106 ps
T128 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1878414325 Aug 10 07:19:02 PM PDT 24 Aug 10 07:19:04 PM PDT 24 82249676 ps
T1065 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4149918493 Aug 10 07:19:01 PM PDT 24 Aug 10 07:19:02 PM PDT 24 14674186 ps
T1066 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3365783827 Aug 10 07:19:05 PM PDT 24 Aug 10 07:19:06 PM PDT 24 12144130 ps
T1067 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3979136866 Aug 10 07:18:45 PM PDT 24 Aug 10 07:18:48 PM PDT 24 57297925 ps
T176 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3681706460 Aug 10 07:18:57 PM PDT 24 Aug 10 07:19:20 PM PDT 24 1145233680 ps
T1068 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1675816650 Aug 10 07:19:00 PM PDT 24 Aug 10 07:19:01 PM PDT 24 14689129 ps
T1069 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.42404568 Aug 10 07:18:55 PM PDT 24 Aug 10 07:19:03 PM PDT 24 311608737 ps
T1070 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1215406741 Aug 10 07:19:16 PM PDT 24 Aug 10 07:19:16 PM PDT 24 11181382 ps
T1071 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2440262040 Aug 10 07:19:06 PM PDT 24 Aug 10 07:19:10 PM PDT 24 580867634 ps
T1072 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3173258095 Aug 10 07:18:58 PM PDT 24 Aug 10 07:19:00 PM PDT 24 225772894 ps
T1073 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1874579261 Aug 10 07:18:55 PM PDT 24 Aug 10 07:18:58 PM PDT 24 165525210 ps
T1074 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2338037480 Aug 10 07:19:13 PM PDT 24 Aug 10 07:19:14 PM PDT 24 24055055 ps
T1075 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4146446207 Aug 10 07:19:05 PM PDT 24 Aug 10 07:19:08 PM PDT 24 277725278 ps
T1076 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2946613975 Aug 10 07:18:51 PM PDT 24 Aug 10 07:18:53 PM PDT 24 70202037 ps
T1077 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2699172527 Aug 10 07:19:05 PM PDT 24 Aug 10 07:19:09 PM PDT 24 150717344 ps
T1078 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3440373910 Aug 10 07:18:51 PM PDT 24 Aug 10 07:18:55 PM PDT 24 51433669 ps
T1079 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1869826275 Aug 10 07:19:08 PM PDT 24 Aug 10 07:19:10 PM PDT 24 39015374 ps
T89 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1351199177 Aug 10 07:18:47 PM PDT 24 Aug 10 07:18:48 PM PDT 24 105036477 ps
T1080 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4086990343 Aug 10 07:18:57 PM PDT 24 Aug 10 07:19:00 PM PDT 24 332338335 ps
T1081 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4101469484 Aug 10 07:19:00 PM PDT 24 Aug 10 07:19:01 PM PDT 24 14249652 ps
T1082 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1663662084 Aug 10 07:19:12 PM PDT 24 Aug 10 07:19:12 PM PDT 24 14008141 ps
T1083 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4149780703 Aug 10 07:19:00 PM PDT 24 Aug 10 07:19:05 PM PDT 24 390699569 ps
T179 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.248269387 Aug 10 07:19:01 PM PDT 24 Aug 10 07:19:14 PM PDT 24 2761282868 ps
T1084 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2562572350 Aug 10 07:18:43 PM PDT 24 Aug 10 07:18:44 PM PDT 24 37380967 ps
T1085 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2462302285 Aug 10 07:19:09 PM PDT 24 Aug 10 07:19:10 PM PDT 24 18929341 ps
T1086 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.98280288 Aug 10 07:18:54 PM PDT 24 Aug 10 07:18:57 PM PDT 24 210114738 ps
T1087 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3384781442 Aug 10 07:18:59 PM PDT 24 Aug 10 07:19:02 PM PDT 24 256309509 ps
T1088 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1770974913 Aug 10 07:18:57 PM PDT 24 Aug 10 07:18:59 PM PDT 24 317000579 ps
T1089 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2302014761 Aug 10 07:19:13 PM PDT 24 Aug 10 07:19:14 PM PDT 24 42846022 ps
T1090 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1424266099 Aug 10 07:18:57 PM PDT 24 Aug 10 07:19:05 PM PDT 24 1198631803 ps
T1091 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2326457405 Aug 10 07:19:01 PM PDT 24 Aug 10 07:19:18 PM PDT 24 1690688371 ps
T1092 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1873676986 Aug 10 07:19:00 PM PDT 24 Aug 10 07:19:04 PM PDT 24 108549091 ps
T1093 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4205241960 Aug 10 07:18:52 PM PDT 24 Aug 10 07:18:53 PM PDT 24 22348550 ps
T1094 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1866949240 Aug 10 07:19:01 PM PDT 24 Aug 10 07:19:02 PM PDT 24 32131216 ps
T1095 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.717102431 Aug 10 07:18:57 PM PDT 24 Aug 10 07:18:59 PM PDT 24 215388159 ps
T1096 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1052179514 Aug 10 07:19:10 PM PDT 24 Aug 10 07:19:11 PM PDT 24 31410987 ps
T1097 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1078336351 Aug 10 07:18:56 PM PDT 24 Aug 10 07:18:58 PM PDT 24 97128508 ps
T1098 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1571400889 Aug 10 07:18:57 PM PDT 24 Aug 10 07:19:01 PM PDT 24 49951981 ps
T1099 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4205960802 Aug 10 07:19:01 PM PDT 24 Aug 10 07:19:03 PM PDT 24 66677850 ps
T1100 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3428085564 Aug 10 07:19:09 PM PDT 24 Aug 10 07:19:10 PM PDT 24 124741825 ps
T1101 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.900859261 Aug 10 07:18:43 PM PDT 24 Aug 10 07:18:44 PM PDT 24 13640499 ps
T1102 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1200847986 Aug 10 07:18:51 PM PDT 24 Aug 10 07:18:52 PM PDT 24 19625795 ps
T1103 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1188093446 Aug 10 07:18:46 PM PDT 24 Aug 10 07:18:47 PM PDT 24 41991920 ps
T178 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1833539551 Aug 10 07:19:04 PM PDT 24 Aug 10 07:19:26 PM PDT 24 4106597320 ps
T1104 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1467931948 Aug 10 07:18:43 PM PDT 24 Aug 10 07:18:44 PM PDT 24 20464858 ps
T1105 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.456447707 Aug 10 07:18:56 PM PDT 24 Aug 10 07:18:57 PM PDT 24 14717907 ps
T1106 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.602934289 Aug 10 07:18:56 PM PDT 24 Aug 10 07:18:59 PM PDT 24 720191570 ps
T1107 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1630025723 Aug 10 07:18:46 PM PDT 24 Aug 10 07:18:48 PM PDT 24 53145976 ps
T1108 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3823671143 Aug 10 07:19:11 PM PDT 24 Aug 10 07:19:11 PM PDT 24 37300796 ps
T1109 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.419584227 Aug 10 07:18:55 PM PDT 24 Aug 10 07:18:59 PM PDT 24 245957130 ps
T1110 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3210918726 Aug 10 07:18:55 PM PDT 24 Aug 10 07:18:59 PM PDT 24 500145289 ps
T1111 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3405495407 Aug 10 07:18:44 PM PDT 24 Aug 10 07:18:46 PM PDT 24 82206496 ps
T180 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3731173656 Aug 10 07:18:55 PM PDT 24 Aug 10 07:19:11 PM PDT 24 707263551 ps
T1112 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.247328825 Aug 10 07:18:55 PM PDT 24 Aug 10 07:18:56 PM PDT 24 38113347 ps
T1113 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4291832784 Aug 10 07:18:45 PM PDT 24 Aug 10 07:19:11 PM PDT 24 2609945687 ps
T1114 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.304324299 Aug 10 07:19:06 PM PDT 24 Aug 10 07:19:07 PM PDT 24 13116351 ps
T1115 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3153428127 Aug 10 07:18:42 PM PDT 24 Aug 10 07:18:44 PM PDT 24 44793775 ps
T1116 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.452208972 Aug 10 07:18:44 PM PDT 24 Aug 10 07:18:45 PM PDT 24 11050579 ps
T1117 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.555630498 Aug 10 07:18:43 PM PDT 24 Aug 10 07:19:04 PM PDT 24 730103222 ps
T1118 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.408868288 Aug 10 07:19:12 PM PDT 24 Aug 10 07:19:13 PM PDT 24 40276718 ps
T1119 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1458270904 Aug 10 07:18:49 PM PDT 24 Aug 10 07:18:53 PM PDT 24 2540049702 ps
T1120 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4162761412 Aug 10 07:18:53 PM PDT 24 Aug 10 07:18:53 PM PDT 24 25737763 ps
T90 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.184641155 Aug 10 07:18:44 PM PDT 24 Aug 10 07:18:45 PM PDT 24 20167940 ps
T1121 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3850163664 Aug 10 07:18:46 PM PDT 24 Aug 10 07:19:08 PM PDT 24 3888212237 ps
T91 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1487800347 Aug 10 07:18:57 PM PDT 24 Aug 10 07:18:59 PM PDT 24 24128621 ps
T1122 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.930332316 Aug 10 07:19:12 PM PDT 24 Aug 10 07:19:13 PM PDT 24 14140017 ps
T1123 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.769758544 Aug 10 07:19:09 PM PDT 24 Aug 10 07:19:10 PM PDT 24 27253357 ps
T1124 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2390443935 Aug 10 07:18:50 PM PDT 24 Aug 10 07:18:54 PM PDT 24 2273653421 ps
T1125 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2130503997 Aug 10 07:18:55 PM PDT 24 Aug 10 07:18:57 PM PDT 24 41318408 ps
T1126 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.809665541 Aug 10 07:18:59 PM PDT 24 Aug 10 07:19:01 PM PDT 24 40497416 ps
T1127 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2712970531 Aug 10 07:18:53 PM PDT 24 Aug 10 07:18:54 PM PDT 24 32117460 ps
T1128 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1237465012 Aug 10 07:19:01 PM PDT 24 Aug 10 07:19:05 PM PDT 24 866747660 ps
T1129 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3247703386 Aug 10 07:18:53 PM PDT 24 Aug 10 07:18:55 PM PDT 24 150935520 ps
T1130 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3298174503 Aug 10 07:18:58 PM PDT 24 Aug 10 07:19:12 PM PDT 24 808432763 ps
T1131 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4096515216 Aug 10 07:18:52 PM PDT 24 Aug 10 07:18:52 PM PDT 24 11923979 ps

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3153719921
Short name T2
Test name
Test status
Simulation time 2178559233 ps
CPU time 53.3 seconds
Started Aug 10 07:27:38 PM PDT 24
Finished Aug 10 07:28:32 PM PDT 24
Peak memory 250628 kb
Host smart-f67ce874-fc2f-4362-bb5c-f63958d20e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153719921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3153719921
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2669531343
Short name T34
Test name
Test status
Simulation time 28009849431 ps
CPU time 206.52 seconds
Started Aug 10 07:26:34 PM PDT 24
Finished Aug 10 07:30:00 PM PDT 24
Peak memory 249552 kb
Host smart-2b46bd8c-6cac-44d1-840d-61cbbbc4850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669531343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2669531343
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2070200288
Short name T14
Test name
Test status
Simulation time 283958335327 ps
CPU time 1513.26 seconds
Started Aug 10 07:25:52 PM PDT 24
Finished Aug 10 07:51:06 PM PDT 24
Peak memory 297000 kb
Host smart-bba8218b-9dde-47d0-96c9-d3be67533823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070200288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2070200288
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1398885567
Short name T110
Test name
Test status
Simulation time 201984801 ps
CPU time 2.6 seconds
Started Aug 10 07:19:01 PM PDT 24
Finished Aug 10 07:19:04 PM PDT 24
Peak memory 217032 kb
Host smart-4b4b1ec2-271d-430d-bc0e-6b669792c12c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398885567 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1398885567
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3210786266
Short name T18
Test name
Test status
Simulation time 18482336844 ps
CPU time 205.49 seconds
Started Aug 10 07:25:26 PM PDT 24
Finished Aug 10 07:28:52 PM PDT 24
Peak memory 256128 kb
Host smart-3037a0fb-6897-44a0-9cd6-c5646478f765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210786266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3210786266
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3888444231
Short name T4
Test name
Test status
Simulation time 16313957 ps
CPU time 0.77 seconds
Started Aug 10 07:24:33 PM PDT 24
Finished Aug 10 07:24:34 PM PDT 24
Peak memory 216460 kb
Host smart-9de6e199-35d3-46fd-8527-f5ef8da5219a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888444231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3888444231
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2010628699
Short name T198
Test name
Test status
Simulation time 424176891368 ps
CPU time 403.92 seconds
Started Aug 10 07:25:18 PM PDT 24
Finished Aug 10 07:32:02 PM PDT 24
Peak memory 266012 kb
Host smart-1d860ec7-2dbc-4ab8-b54d-375e4bd0cc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010628699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2010628699
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1471630307
Short name T19
Test name
Test status
Simulation time 295112408946 ps
CPU time 374.02 seconds
Started Aug 10 07:27:15 PM PDT 24
Finished Aug 10 07:33:29 PM PDT 24
Peak memory 268468 kb
Host smart-95e878f4-541e-4dec-b5b4-ff1efc7b6d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471630307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1471630307
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1145457993
Short name T25
Test name
Test status
Simulation time 241204096452 ps
CPU time 344.85 seconds
Started Aug 10 07:26:58 PM PDT 24
Finished Aug 10 07:32:43 PM PDT 24
Peak memory 274168 kb
Host smart-d72ce9d6-781b-4d14-a788-13aa56a25373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145457993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1145457993
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2727684029
Short name T100
Test name
Test status
Simulation time 5376206166 ps
CPU time 7.26 seconds
Started Aug 10 07:18:52 PM PDT 24
Finished Aug 10 07:19:00 PM PDT 24
Peak memory 215288 kb
Host smart-985c7219-a7b5-460f-8079-cfb0a9d776ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727684029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2727684029
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2119743086
Short name T163
Test name
Test status
Simulation time 179063431173 ps
CPU time 382.05 seconds
Started Aug 10 07:27:32 PM PDT 24
Finished Aug 10 07:33:54 PM PDT 24
Peak memory 271540 kb
Host smart-b6851000-37a8-41e4-b995-e0abb5907270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119743086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2119743086
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3854694862
Short name T145
Test name
Test status
Simulation time 374147133 ps
CPU time 8.63 seconds
Started Aug 10 07:27:22 PM PDT 24
Finished Aug 10 07:27:31 PM PDT 24
Peak memory 240180 kb
Host smart-a3385fa3-d8b0-4855-b02b-277f58b964b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854694862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3854694862
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2539685670
Short name T337
Test name
Test status
Simulation time 48249585 ps
CPU time 0.72 seconds
Started Aug 10 07:25:20 PM PDT 24
Finished Aug 10 07:25:20 PM PDT 24
Peak memory 205272 kb
Host smart-31590f28-a4b1-43de-a744-5cdbfaed251d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539685670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2539685670
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1725150201
Short name T190
Test name
Test status
Simulation time 41653735259 ps
CPU time 146 seconds
Started Aug 10 07:24:41 PM PDT 24
Finished Aug 10 07:27:07 PM PDT 24
Peak memory 273324 kb
Host smart-2cc0b711-390c-4282-a5ab-989aac6dff73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725150201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1725150201
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.318484620
Short name T191
Test name
Test status
Simulation time 25730789089 ps
CPU time 223.36 seconds
Started Aug 10 07:25:51 PM PDT 24
Finished Aug 10 07:29:34 PM PDT 24
Peak memory 256524 kb
Host smart-d900d47e-5441-4772-a751-c88d08c10088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318484620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.318484620
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.429397970
Short name T99
Test name
Test status
Simulation time 99305231 ps
CPU time 2.76 seconds
Started Aug 10 07:18:55 PM PDT 24
Finished Aug 10 07:18:58 PM PDT 24
Peak memory 215248 kb
Host smart-83dd40b5-6bfa-4b9b-a9d7-7a750825b866
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429397970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.429397970
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.635990434
Short name T297
Test name
Test status
Simulation time 68634022822 ps
CPU time 432.99 seconds
Started Aug 10 07:25:29 PM PDT 24
Finished Aug 10 07:32:42 PM PDT 24
Peak memory 285828 kb
Host smart-3667aec9-125b-462f-93a5-73307587947c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635990434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.635990434
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.405186662
Short name T115
Test name
Test status
Simulation time 974094527 ps
CPU time 2.52 seconds
Started Aug 10 07:18:59 PM PDT 24
Finished Aug 10 07:19:02 PM PDT 24
Peak memory 215236 kb
Host smart-246c2dbb-31b2-429d-bcc1-d557ded7f64f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405186662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.405186662
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2089852504
Short name T156
Test name
Test status
Simulation time 77205691274 ps
CPU time 617.6 seconds
Started Aug 10 07:26:26 PM PDT 24
Finished Aug 10 07:36:44 PM PDT 24
Peak memory 265504 kb
Host smart-976b32ff-da9e-455e-be7b-6b2c3578a70e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089852504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2089852504
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2229559355
Short name T279
Test name
Test status
Simulation time 49666853896 ps
CPU time 195.42 seconds
Started Aug 10 07:25:37 PM PDT 24
Finished Aug 10 07:28:53 PM PDT 24
Peak memory 289740 kb
Host smart-376019df-fc3c-43dd-90f5-a36025770bfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229559355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2229559355
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3755967283
Short name T506
Test name
Test status
Simulation time 6614856704 ps
CPU time 34.56 seconds
Started Aug 10 07:28:06 PM PDT 24
Finished Aug 10 07:28:40 PM PDT 24
Peak memory 252236 kb
Host smart-ab17d7d2-a9d5-4eca-bc5d-558b0a1b9a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755967283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3755967283
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2348366835
Short name T38
Test name
Test status
Simulation time 318976160 ps
CPU time 1.11 seconds
Started Aug 10 07:24:39 PM PDT 24
Finished Aug 10 07:24:41 PM PDT 24
Peak memory 236828 kb
Host smart-97aa10e6-b802-4cee-a60a-51e1431c9384
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348366835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2348366835
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1827078769
Short name T257
Test name
Test status
Simulation time 58351245537 ps
CPU time 160.93 seconds
Started Aug 10 07:24:45 PM PDT 24
Finished Aug 10 07:27:26 PM PDT 24
Peak memory 259952 kb
Host smart-ad669497-3412-4209-abb8-171724bca97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827078769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1827078769
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3961459505
Short name T188
Test name
Test status
Simulation time 5737770607 ps
CPU time 62.09 seconds
Started Aug 10 07:27:59 PM PDT 24
Finished Aug 10 07:29:01 PM PDT 24
Peak memory 254136 kb
Host smart-bf5cb5b1-801f-4708-a04a-047d723fc0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961459505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3961459505
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3858878109
Short name T210
Test name
Test status
Simulation time 346511833809 ps
CPU time 973.12 seconds
Started Aug 10 07:26:36 PM PDT 24
Finished Aug 10 07:42:50 PM PDT 24
Peak memory 274204 kb
Host smart-33ee47ce-364c-4902-9e8e-1bd848420513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858878109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3858878109
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2145126756
Short name T33
Test name
Test status
Simulation time 73527365951 ps
CPU time 671.16 seconds
Started Aug 10 07:26:58 PM PDT 24
Finished Aug 10 07:38:09 PM PDT 24
Peak memory 266980 kb
Host smart-073cb85a-0149-4444-aff7-a3266601c78e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145126756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2145126756
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3731173656
Short name T180
Test name
Test status
Simulation time 707263551 ps
CPU time 15.7 seconds
Started Aug 10 07:18:55 PM PDT 24
Finished Aug 10 07:19:11 PM PDT 24
Peak memory 223348 kb
Host smart-9e4b2554-8a7f-42cd-a759-3e886a27c08e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731173656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3731173656
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1217918885
Short name T214
Test name
Test status
Simulation time 42003950766 ps
CPU time 218.54 seconds
Started Aug 10 07:25:43 PM PDT 24
Finished Aug 10 07:29:21 PM PDT 24
Peak memory 250548 kb
Host smart-5508d7b1-3df2-46ef-8f31-f6103990c53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217918885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1217918885
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.971804619
Short name T30
Test name
Test status
Simulation time 2745139014 ps
CPU time 7.43 seconds
Started Aug 10 07:27:49 PM PDT 24
Finished Aug 10 07:27:57 PM PDT 24
Peak memory 216760 kb
Host smart-d8c90924-a666-4083-bee5-445132ba0c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971804619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.971804619
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3520879289
Short name T56
Test name
Test status
Simulation time 146256830169 ps
CPU time 230.81 seconds
Started Aug 10 07:25:24 PM PDT 24
Finished Aug 10 07:29:15 PM PDT 24
Peak memory 240404 kb
Host smart-a56e85a2-f6fe-49b1-8e58-afd4d56a1430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520879289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3520879289
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1903924187
Short name T1062
Test name
Test status
Simulation time 176233010 ps
CPU time 4.88 seconds
Started Aug 10 07:19:00 PM PDT 24
Finished Aug 10 07:19:06 PM PDT 24
Peak memory 215276 kb
Host smart-3fbc8c59-0ad2-4fc0-a69b-87f75d5f45f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903924187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1903924187
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1306826714
Short name T235
Test name
Test status
Simulation time 178075459928 ps
CPU time 509.08 seconds
Started Aug 10 07:24:43 PM PDT 24
Finished Aug 10 07:33:12 PM PDT 24
Peak memory 264520 kb
Host smart-fe73671f-d6a6-4097-a69a-c8ab33182ef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306826714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1306826714
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3920086432
Short name T168
Test name
Test status
Simulation time 8687421539 ps
CPU time 49.66 seconds
Started Aug 10 07:25:36 PM PDT 24
Finished Aug 10 07:26:26 PM PDT 24
Peak memory 256896 kb
Host smart-88510f64-a2e4-46cf-9c0b-77dafa21b269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920086432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3920086432
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1963739077
Short name T304
Test name
Test status
Simulation time 17848281545 ps
CPU time 23.29 seconds
Started Aug 10 07:26:06 PM PDT 24
Finished Aug 10 07:26:29 PM PDT 24
Peak memory 241388 kb
Host smart-2cadf981-a1fc-43d3-9e5d-19d7cfa48b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963739077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1963739077
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3702039219
Short name T269
Test name
Test status
Simulation time 43081385830 ps
CPU time 410.81 seconds
Started Aug 10 07:26:24 PM PDT 24
Finished Aug 10 07:33:15 PM PDT 24
Peak memory 256308 kb
Host smart-a3f81db7-060e-483e-a9df-b3ea6c23e5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702039219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3702039219
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2565700455
Short name T120
Test name
Test status
Simulation time 1183385954 ps
CPU time 2.5 seconds
Started Aug 10 07:19:05 PM PDT 24
Finished Aug 10 07:19:07 PM PDT 24
Peak memory 214656 kb
Host smart-830af5f7-070e-4cde-a963-63e8aad36bcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565700455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2565700455
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2542220699
Short name T207
Test name
Test status
Simulation time 943742724959 ps
CPU time 431.77 seconds
Started Aug 10 07:25:53 PM PDT 24
Finished Aug 10 07:33:05 PM PDT 24
Peak memory 274132 kb
Host smart-a0608c0c-2bd2-49af-8830-2a7596c7dc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542220699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2542220699
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.212773885
Short name T322
Test name
Test status
Simulation time 6917007209 ps
CPU time 19.05 seconds
Started Aug 10 07:25:43 PM PDT 24
Finished Aug 10 07:26:02 PM PDT 24
Peak memory 216828 kb
Host smart-b0ffa691-fed0-4fcf-ab71-fbcd594dafe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212773885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.212773885
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2332396363
Short name T294
Test name
Test status
Simulation time 114318562784 ps
CPU time 195.64 seconds
Started Aug 10 07:26:40 PM PDT 24
Finished Aug 10 07:29:56 PM PDT 24
Peak memory 250700 kb
Host smart-32c8d658-2246-4419-8901-cf20a6870aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332396363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2332396363
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2333794517
Short name T72
Test name
Test status
Simulation time 426403293 ps
CPU time 5.38 seconds
Started Aug 10 07:19:01 PM PDT 24
Finished Aug 10 07:19:07 PM PDT 24
Peak memory 215228 kb
Host smart-bf7cd927-0e0f-4eae-87bd-6d08e71df14f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333794517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2333794517
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3850163664
Short name T1121
Test name
Test status
Simulation time 3888212237 ps
CPU time 21.4 seconds
Started Aug 10 07:18:46 PM PDT 24
Finished Aug 10 07:19:08 PM PDT 24
Peak memory 215696 kb
Host smart-7ded1794-650e-498a-9082-695dd4433efb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850163664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3850163664
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.43855421
Short name T172
Test name
Test status
Simulation time 1689743052 ps
CPU time 21.89 seconds
Started Aug 10 07:18:42 PM PDT 24
Finished Aug 10 07:19:04 PM PDT 24
Peak memory 215264 kb
Host smart-a3b8c43c-d386-41fd-8624-b312de15d2c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43855421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_t
l_intg_err.43855421
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3022806111
Short name T186
Test name
Test status
Simulation time 281243989 ps
CPU time 2.47 seconds
Started Aug 10 07:24:39 PM PDT 24
Finished Aug 10 07:24:42 PM PDT 24
Peak memory 233092 kb
Host smart-dfa5ddf7-3ef8-4df6-8d82-0d373658658f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022806111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3022806111
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3293087011
Short name T227
Test name
Test status
Simulation time 73498297305 ps
CPU time 207.02 seconds
Started Aug 10 07:24:45 PM PDT 24
Finished Aug 10 07:28:12 PM PDT 24
Peak memory 265900 kb
Host smart-382def99-84e3-4ee1-9c00-538203062914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293087011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3293087011
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1355764870
Short name T205
Test name
Test status
Simulation time 2103727883 ps
CPU time 8.14 seconds
Started Aug 10 07:25:10 PM PDT 24
Finished Aug 10 07:25:18 PM PDT 24
Peak memory 233112 kb
Host smart-b773b097-0ab5-451d-adab-fa469e3bc2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355764870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1355764870
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1557157340
Short name T910
Test name
Test status
Simulation time 2647113949 ps
CPU time 64.33 seconds
Started Aug 10 07:25:20 PM PDT 24
Finished Aug 10 07:26:24 PM PDT 24
Peak memory 253584 kb
Host smart-8c7495d1-6f26-4277-ac62-f65da25b2b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557157340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1557157340
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1341530867
Short name T130
Test name
Test status
Simulation time 14152262167 ps
CPU time 40.79 seconds
Started Aug 10 07:25:49 PM PDT 24
Finished Aug 10 07:26:30 PM PDT 24
Peak memory 225004 kb
Host smart-fcffb6bd-f029-4eca-8e32-3e7009ff6315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341530867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1341530867
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2870696700
Short name T67
Test name
Test status
Simulation time 1567657083 ps
CPU time 8.1 seconds
Started Aug 10 07:25:50 PM PDT 24
Finished Aug 10 07:25:59 PM PDT 24
Peak memory 224868 kb
Host smart-a5f5fdf9-092e-49b7-bcf1-3477957594a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870696700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2870696700
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1487800347
Short name T91
Test name
Test status
Simulation time 24128621 ps
CPU time 1.41 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:18:59 PM PDT 24
Peak memory 216152 kb
Host smart-4960d158-835b-4a1d-ab99-ccfe472491cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487800347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1487800347
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.229470799
Short name T1063
Test name
Test status
Simulation time 1488393785 ps
CPU time 8 seconds
Started Aug 10 07:18:47 PM PDT 24
Finished Aug 10 07:18:55 PM PDT 24
Peak memory 215164 kb
Host smart-c45f8172-22b3-49b6-b261-bb72f976d92a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229470799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.229470799
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4291832784
Short name T1113
Test name
Test status
Simulation time 2609945687 ps
CPU time 25.56 seconds
Started Aug 10 07:18:45 PM PDT 24
Finished Aug 10 07:19:11 PM PDT 24
Peak memory 206968 kb
Host smart-7965751e-95b9-43d3-a4b3-716de0393cdd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291832784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4291832784
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1351199177
Short name T89
Test name
Test status
Simulation time 105036477 ps
CPU time 1.26 seconds
Started Aug 10 07:18:47 PM PDT 24
Finished Aug 10 07:18:48 PM PDT 24
Peak memory 207116 kb
Host smart-814d4f15-e40c-4bc6-b210-5bdf5e82b53f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351199177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1351199177
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1034166994
Short name T73
Test name
Test status
Simulation time 185994101 ps
CPU time 1.81 seconds
Started Aug 10 07:18:46 PM PDT 24
Finished Aug 10 07:18:48 PM PDT 24
Peak memory 215156 kb
Host smart-f9450657-4b89-4017-a3b8-7aa0fd02ed9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034166994 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1034166994
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1188093446
Short name T1103
Test name
Test status
Simulation time 41991920 ps
CPU time 1.32 seconds
Started Aug 10 07:18:46 PM PDT 24
Finished Aug 10 07:18:47 PM PDT 24
Peak memory 215136 kb
Host smart-28072511-f40a-42be-9280-5f59c898156f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188093446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
188093446
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.900859261
Short name T1101
Test name
Test status
Simulation time 13640499 ps
CPU time 0.7 seconds
Started Aug 10 07:18:43 PM PDT 24
Finished Aug 10 07:18:44 PM PDT 24
Peak memory 203680 kb
Host smart-b9d67c84-6eaa-4312-8593-53bd059e27f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900859261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.900859261
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3083798563
Short name T1046
Test name
Test status
Simulation time 105438152 ps
CPU time 1.78 seconds
Started Aug 10 07:18:42 PM PDT 24
Finished Aug 10 07:18:44 PM PDT 24
Peak memory 215124 kb
Host smart-6655fc85-5031-4372-9939-d8807c2da855
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083798563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3083798563
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1467931948
Short name T1104
Test name
Test status
Simulation time 20464858 ps
CPU time 0.65 seconds
Started Aug 10 07:18:43 PM PDT 24
Finished Aug 10 07:18:44 PM PDT 24
Peak memory 203656 kb
Host smart-250033f0-633e-4557-a5d3-c630eeef429a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467931948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1467931948
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1458270904
Short name T1119
Test name
Test status
Simulation time 2540049702 ps
CPU time 4.02 seconds
Started Aug 10 07:18:49 PM PDT 24
Finished Aug 10 07:18:53 PM PDT 24
Peak memory 215304 kb
Host smart-8986e894-5dd9-40c4-935b-c6507470bfef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458270904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1458270904
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3003774303
Short name T109
Test name
Test status
Simulation time 124494011 ps
CPU time 3.1 seconds
Started Aug 10 07:18:45 PM PDT 24
Finished Aug 10 07:18:48 PM PDT 24
Peak memory 216308 kb
Host smart-0eee37c3-91e8-47f3-8903-f7914e8291f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003774303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
003774303
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.767173396
Short name T1014
Test name
Test status
Simulation time 315290248 ps
CPU time 8.46 seconds
Started Aug 10 07:18:42 PM PDT 24
Finished Aug 10 07:18:51 PM PDT 24
Peak memory 215188 kb
Host smart-dcaed2a0-c3c6-475e-b707-682b8714e607
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767173396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.767173396
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.768337868
Short name T1013
Test name
Test status
Simulation time 185521037 ps
CPU time 11.19 seconds
Started Aug 10 07:18:45 PM PDT 24
Finished Aug 10 07:18:57 PM PDT 24
Peak memory 206964 kb
Host smart-48251c95-6b63-4398-b782-c45c43df5051
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768337868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.768337868
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.184641155
Short name T90
Test name
Test status
Simulation time 20167940 ps
CPU time 1.02 seconds
Started Aug 10 07:18:44 PM PDT 24
Finished Aug 10 07:18:45 PM PDT 24
Peak memory 206840 kb
Host smart-e44d4320-b10e-45fa-86ef-b2b35fac33cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184641155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.184641155
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3685057799
Short name T154
Test name
Test status
Simulation time 243330759 ps
CPU time 1.82 seconds
Started Aug 10 07:18:46 PM PDT 24
Finished Aug 10 07:18:48 PM PDT 24
Peak memory 215096 kb
Host smart-c66243d7-d0b5-48cb-921f-a45e969b5176
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685057799 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3685057799
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3405495407
Short name T1111
Test name
Test status
Simulation time 82206496 ps
CPU time 1.92 seconds
Started Aug 10 07:18:44 PM PDT 24
Finished Aug 10 07:18:46 PM PDT 24
Peak memory 206888 kb
Host smart-cea9c3f9-966e-43ef-a989-539b6da39824
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405495407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
405495407
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2562572350
Short name T1084
Test name
Test status
Simulation time 37380967 ps
CPU time 0.7 seconds
Started Aug 10 07:18:43 PM PDT 24
Finished Aug 10 07:18:44 PM PDT 24
Peak memory 203660 kb
Host smart-73c5fdbe-782b-4d21-a197-fe953b360fb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562572350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
562572350
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1630025723
Short name T1107
Test name
Test status
Simulation time 53145976 ps
CPU time 1.74 seconds
Started Aug 10 07:18:46 PM PDT 24
Finished Aug 10 07:18:48 PM PDT 24
Peak memory 215208 kb
Host smart-23bf94c2-1c8b-4899-8dff-a97cd6ca979e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630025723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1630025723
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1543727742
Short name T1015
Test name
Test status
Simulation time 26829725 ps
CPU time 0.66 seconds
Started Aug 10 07:18:43 PM PDT 24
Finished Aug 10 07:18:44 PM PDT 24
Peak memory 203644 kb
Host smart-46097b85-1c93-4628-b4e3-0dea0bb84a0b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543727742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1543727742
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2126508777
Short name T1050
Test name
Test status
Simulation time 45014326 ps
CPU time 2.91 seconds
Started Aug 10 07:18:42 PM PDT 24
Finished Aug 10 07:18:45 PM PDT 24
Peak memory 215216 kb
Host smart-393be1dd-ddba-4c4c-9c6d-5b80ed25eb37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126508777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2126508777
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3456143947
Short name T105
Test name
Test status
Simulation time 141178014 ps
CPU time 3.38 seconds
Started Aug 10 07:18:46 PM PDT 24
Finished Aug 10 07:18:50 PM PDT 24
Peak memory 215296 kb
Host smart-f7f02346-106e-4a61-b234-499f9b5c0189
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456143947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
456143947
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.602934289
Short name T1106
Test name
Test status
Simulation time 720191570 ps
CPU time 2.8 seconds
Started Aug 10 07:18:56 PM PDT 24
Finished Aug 10 07:18:59 PM PDT 24
Peak memory 216616 kb
Host smart-b00b717a-fa07-4f04-bd39-921d1544a8fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602934289 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.602934289
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.196010648
Short name T1025
Test name
Test status
Simulation time 788910469 ps
CPU time 2.4 seconds
Started Aug 10 07:18:56 PM PDT 24
Finished Aug 10 07:18:58 PM PDT 24
Peak memory 215168 kb
Host smart-d44a1811-4a2e-4f6e-a755-83a481e2a3a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196010648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.196010648
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3895857230
Short name T1017
Test name
Test status
Simulation time 49718210 ps
CPU time 0.78 seconds
Started Aug 10 07:18:56 PM PDT 24
Finished Aug 10 07:18:57 PM PDT 24
Peak memory 203928 kb
Host smart-5ba24f77-cfaa-484c-8821-23e4943dee5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895857230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3895857230
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1237465012
Short name T1128
Test name
Test status
Simulation time 866747660 ps
CPU time 3.75 seconds
Started Aug 10 07:19:01 PM PDT 24
Finished Aug 10 07:19:05 PM PDT 24
Peak memory 215232 kb
Host smart-deb0bb42-cb07-4064-8844-ecea2e0a0d78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237465012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1237465012
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4205960802
Short name T1099
Test name
Test status
Simulation time 66677850 ps
CPU time 2.36 seconds
Started Aug 10 07:19:01 PM PDT 24
Finished Aug 10 07:19:03 PM PDT 24
Peak memory 215344 kb
Host smart-f5479a00-2aad-47d9-b3d5-1a3aa6d5570b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205960802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4205960802
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3681706460
Short name T176
Test name
Test status
Simulation time 1145233680 ps
CPU time 23.49 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:19:20 PM PDT 24
Peak memory 216564 kb
Host smart-f606a805-4198-4f84-809e-400e988bd13d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681706460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3681706460
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2292234422
Short name T1054
Test name
Test status
Simulation time 298978714 ps
CPU time 2.65 seconds
Started Aug 10 07:18:51 PM PDT 24
Finished Aug 10 07:18:54 PM PDT 24
Peak memory 216292 kb
Host smart-766f4b4e-b8c7-4cdd-879d-507c43353cc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292234422 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2292234422
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2712970531
Short name T1127
Test name
Test status
Simulation time 32117460 ps
CPU time 0.68 seconds
Started Aug 10 07:18:53 PM PDT 24
Finished Aug 10 07:18:54 PM PDT 24
Peak memory 203692 kb
Host smart-e8b9f06a-8c5b-4add-b1d2-51fb9390f96d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712970531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2712970531
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3476145259
Short name T143
Test name
Test status
Simulation time 434184120 ps
CPU time 3.14 seconds
Started Aug 10 07:18:51 PM PDT 24
Finished Aug 10 07:18:54 PM PDT 24
Peak memory 215132 kb
Host smart-2dfc7e47-53ce-4b5b-96ec-689077ed46f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476145259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3476145259
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1874579261
Short name T1073
Test name
Test status
Simulation time 165525210 ps
CPU time 2.04 seconds
Started Aug 10 07:18:55 PM PDT 24
Finished Aug 10 07:18:58 PM PDT 24
Peak memory 215380 kb
Host smart-ca74ae89-1aba-434c-8e10-c0f4b45ba28f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874579261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1874579261
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3403866484
Short name T171
Test name
Test status
Simulation time 214214655 ps
CPU time 6.86 seconds
Started Aug 10 07:18:53 PM PDT 24
Finished Aug 10 07:19:00 PM PDT 24
Peak memory 215356 kb
Host smart-584283d5-1558-4d5e-843d-09b44178c39b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403866484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3403866484
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4146446207
Short name T1075
Test name
Test status
Simulation time 277725278 ps
CPU time 3.32 seconds
Started Aug 10 07:19:05 PM PDT 24
Finished Aug 10 07:19:08 PM PDT 24
Peak memory 216080 kb
Host smart-e50c9372-e7de-4d7c-84c2-b052dec7d5b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146446207 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4146446207
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3384781442
Short name T1087
Test name
Test status
Simulation time 256309509 ps
CPU time 2.5 seconds
Started Aug 10 07:18:59 PM PDT 24
Finished Aug 10 07:19:02 PM PDT 24
Peak memory 215288 kb
Host smart-c5de8df9-3e44-4864-95da-c2735efe6f92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384781442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3384781442
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.120382830
Short name T1028
Test name
Test status
Simulation time 87245105 ps
CPU time 0.72 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:18:58 PM PDT 24
Peak memory 203980 kb
Host smart-471960d1-449f-4b0c-8865-c1d4c1da043b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120382830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.120382830
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1629821354
Short name T155
Test name
Test status
Simulation time 72678036 ps
CPU time 1.9 seconds
Started Aug 10 07:18:58 PM PDT 24
Finished Aug 10 07:19:01 PM PDT 24
Peak memory 215116 kb
Host smart-0c735240-f71b-476b-9965-f1225483514a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629821354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1629821354
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.527105088
Short name T107
Test name
Test status
Simulation time 813721497 ps
CPU time 3.99 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:19:01 PM PDT 24
Peak memory 216300 kb
Host smart-27f51d91-0d2f-4327-8714-6fc3249ed2c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527105088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.527105088
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.55729271
Short name T102
Test name
Test status
Simulation time 811953989 ps
CPU time 19.65 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:19:17 PM PDT 24
Peak memory 215248 kb
Host smart-65e168ec-bd4b-4dc0-a285-3e51ccb89125
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55729271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_
tl_intg_err.55729271
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1188089488
Short name T152
Test name
Test status
Simulation time 180982461 ps
CPU time 3.76 seconds
Started Aug 10 07:19:02 PM PDT 24
Finished Aug 10 07:19:06 PM PDT 24
Peak memory 217360 kb
Host smart-d56ccc9b-93ed-4eea-9406-34036269a58a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188089488 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1188089488
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1869826275
Short name T1079
Test name
Test status
Simulation time 39015374 ps
CPU time 2.46 seconds
Started Aug 10 07:19:08 PM PDT 24
Finished Aug 10 07:19:10 PM PDT 24
Peak memory 215184 kb
Host smart-096c3388-6126-4c37-ad7e-e62d4eb3f7a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869826275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1869826275
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3367635260
Short name T1012
Test name
Test status
Simulation time 21335784 ps
CPU time 0.75 seconds
Started Aug 10 07:19:00 PM PDT 24
Finished Aug 10 07:19:01 PM PDT 24
Peak memory 203964 kb
Host smart-4a1c453b-6440-4fb9-b0c8-6aacda96a598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367635260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3367635260
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3173258095
Short name T1072
Test name
Test status
Simulation time 225772894 ps
CPU time 1.81 seconds
Started Aug 10 07:18:58 PM PDT 24
Finished Aug 10 07:19:00 PM PDT 24
Peak memory 215168 kb
Host smart-fce72328-a4b5-46fb-8f7a-871cda9a790a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173258095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3173258095
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3315051634
Short name T1060
Test name
Test status
Simulation time 730669865 ps
CPU time 4.26 seconds
Started Aug 10 07:18:59 PM PDT 24
Finished Aug 10 07:19:04 PM PDT 24
Peak memory 215316 kb
Host smart-9f8d2c78-8f5e-4951-8d32-447973edc1ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315051634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3315051634
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3843546401
Short name T174
Test name
Test status
Simulation time 17482832905 ps
CPU time 23.89 seconds
Started Aug 10 07:19:00 PM PDT 24
Finished Aug 10 07:19:24 PM PDT 24
Peak memory 215240 kb
Host smart-cbc92a32-3e21-4679-8aae-14aebcf7be84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843546401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3843546401
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3619977199
Short name T153
Test name
Test status
Simulation time 662195979 ps
CPU time 2.79 seconds
Started Aug 10 07:19:09 PM PDT 24
Finished Aug 10 07:19:12 PM PDT 24
Peak memory 216864 kb
Host smart-a7ccf3d1-2dfc-4746-a4f1-9eb42cb15c61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619977199 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3619977199
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3365783827
Short name T1066
Test name
Test status
Simulation time 12144130 ps
CPU time 0.69 seconds
Started Aug 10 07:19:05 PM PDT 24
Finished Aug 10 07:19:06 PM PDT 24
Peak memory 203608 kb
Host smart-f00788be-49c9-4eeb-b7ce-e82f4c6a7cb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365783827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3365783827
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2699172527
Short name T1077
Test name
Test status
Simulation time 150717344 ps
CPU time 4.22 seconds
Started Aug 10 07:19:05 PM PDT 24
Finished Aug 10 07:19:09 PM PDT 24
Peak memory 215328 kb
Host smart-94d4ac79-4f68-4f2a-9e91-20cf3815907a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699172527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2699172527
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.95607601
Short name T175
Test name
Test status
Simulation time 326900030 ps
CPU time 8.1 seconds
Started Aug 10 07:19:01 PM PDT 24
Finished Aug 10 07:19:09 PM PDT 24
Peak memory 215548 kb
Host smart-682d2640-7c25-4141-bdbf-f5455c7b4791
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95607601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_
tl_intg_err.95607601
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.9223822
Short name T123
Test name
Test status
Simulation time 237772358 ps
CPU time 2.62 seconds
Started Aug 10 07:19:00 PM PDT 24
Finished Aug 10 07:19:02 PM PDT 24
Peak memory 206984 kb
Host smart-8bef3174-a9e4-4088-8737-e05f72e8824e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9223822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.9223822
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3203243110
Short name T1043
Test name
Test status
Simulation time 36321934 ps
CPU time 0.71 seconds
Started Aug 10 07:19:00 PM PDT 24
Finished Aug 10 07:19:01 PM PDT 24
Peak memory 203652 kb
Host smart-cfa77d8f-369e-4aab-b2b4-e7d4284ab9f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203243110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3203243110
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1873676986
Short name T1092
Test name
Test status
Simulation time 108549091 ps
CPU time 3.49 seconds
Started Aug 10 07:19:00 PM PDT 24
Finished Aug 10 07:19:04 PM PDT 24
Peak memory 215176 kb
Host smart-e84d25a5-29aa-4ad0-a165-f57c52335124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873676986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1873676986
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.248269387
Short name T179
Test name
Test status
Simulation time 2761282868 ps
CPU time 13.15 seconds
Started Aug 10 07:19:01 PM PDT 24
Finished Aug 10 07:19:14 PM PDT 24
Peak memory 215252 kb
Host smart-75e57472-c266-4164-9717-37a5e525af8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248269387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.248269387
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2438547754
Short name T74
Test name
Test status
Simulation time 60441324 ps
CPU time 4.01 seconds
Started Aug 10 07:19:03 PM PDT 24
Finished Aug 10 07:19:08 PM PDT 24
Peak memory 216692 kb
Host smart-a8b39fae-c6d1-4113-8d1a-233c3eb23c28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438547754 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2438547754
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2956692251
Short name T1049
Test name
Test status
Simulation time 202947889 ps
CPU time 2.19 seconds
Started Aug 10 07:19:00 PM PDT 24
Finished Aug 10 07:19:02 PM PDT 24
Peak memory 215148 kb
Host smart-96c96eaf-27d5-4210-8709-cea56aab007b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956692251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2956692251
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1203037096
Short name T1031
Test name
Test status
Simulation time 13311157 ps
CPU time 0.7 seconds
Started Aug 10 07:19:03 PM PDT 24
Finished Aug 10 07:19:04 PM PDT 24
Peak memory 203680 kb
Host smart-d56e9a30-0fcd-4f86-b083-da0f74b5d408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203037096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1203037096
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2243787927
Short name T1023
Test name
Test status
Simulation time 54804370 ps
CPU time 1.76 seconds
Started Aug 10 07:19:01 PM PDT 24
Finished Aug 10 07:19:03 PM PDT 24
Peak memory 216296 kb
Host smart-3dd7c0ee-074e-4a92-bb25-894fb30e305f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243787927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2243787927
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1001746135
Short name T106
Test name
Test status
Simulation time 190680254 ps
CPU time 2.65 seconds
Started Aug 10 07:19:00 PM PDT 24
Finished Aug 10 07:19:03 PM PDT 24
Peak memory 215228 kb
Host smart-3d2c1641-0daf-44d0-a8e5-b25807d1f5bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001746135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1001746135
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.983467408
Short name T181
Test name
Test status
Simulation time 433210146 ps
CPU time 7.02 seconds
Started Aug 10 07:19:01 PM PDT 24
Finished Aug 10 07:19:08 PM PDT 24
Peak memory 215184 kb
Host smart-1500d5f4-89a4-4a4a-b569-012878dfe2af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983467408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.983467408
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.303812602
Short name T1034
Test name
Test status
Simulation time 162155838 ps
CPU time 2.94 seconds
Started Aug 10 07:18:58 PM PDT 24
Finished Aug 10 07:19:01 PM PDT 24
Peak memory 217196 kb
Host smart-7dd86a53-ed48-42c0-8320-e4ac6a9030f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303812602 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.303812602
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2435198581
Short name T124
Test name
Test status
Simulation time 48274419 ps
CPU time 1.75 seconds
Started Aug 10 07:19:09 PM PDT 24
Finished Aug 10 07:19:11 PM PDT 24
Peak memory 206908 kb
Host smart-4e63bc58-2bf0-42a2-8830-46a60b41f469
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435198581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2435198581
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.273515443
Short name T1047
Test name
Test status
Simulation time 56649148 ps
CPU time 0.74 seconds
Started Aug 10 07:19:05 PM PDT 24
Finished Aug 10 07:19:06 PM PDT 24
Peak memory 204080 kb
Host smart-decac9e6-fc1a-4324-b2f6-40757491b53e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273515443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.273515443
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2440262040
Short name T1071
Test name
Test status
Simulation time 580867634 ps
CPU time 3.95 seconds
Started Aug 10 07:19:06 PM PDT 24
Finished Aug 10 07:19:10 PM PDT 24
Peak memory 215156 kb
Host smart-be879c60-625e-4f74-9be5-15687f5ed5ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440262040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2440262040
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3531173142
Short name T1055
Test name
Test status
Simulation time 64083643 ps
CPU time 4.15 seconds
Started Aug 10 07:19:00 PM PDT 24
Finished Aug 10 07:19:05 PM PDT 24
Peak memory 215276 kb
Host smart-eb957791-0088-40ee-a76a-9d305c626894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531173142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3531173142
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1833539551
Short name T178
Test name
Test status
Simulation time 4106597320 ps
CPU time 22.54 seconds
Started Aug 10 07:19:04 PM PDT 24
Finished Aug 10 07:19:26 PM PDT 24
Peak memory 215272 kb
Host smart-f2cc6ff0-9843-4b71-b7a8-b2d4e3d946ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833539551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1833539551
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.69404762
Short name T1048
Test name
Test status
Simulation time 148690687 ps
CPU time 2.93 seconds
Started Aug 10 07:19:01 PM PDT 24
Finished Aug 10 07:19:04 PM PDT 24
Peak memory 216304 kb
Host smart-e1836c54-53fb-4510-a22a-a63ac48eae76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69404762 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.69404762
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1685469446
Short name T1057
Test name
Test status
Simulation time 177011554 ps
CPU time 1.4 seconds
Started Aug 10 07:18:59 PM PDT 24
Finished Aug 10 07:19:01 PM PDT 24
Peak memory 206900 kb
Host smart-85ba6518-c244-4292-8d90-4050744ea091
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685469446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1685469446
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1866949240
Short name T1094
Test name
Test status
Simulation time 32131216 ps
CPU time 0.72 seconds
Started Aug 10 07:19:01 PM PDT 24
Finished Aug 10 07:19:02 PM PDT 24
Peak memory 203908 kb
Host smart-0c7e763c-00fa-409f-bcf0-a3b1ef40db38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866949240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1866949240
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4149780703
Short name T1083
Test name
Test status
Simulation time 390699569 ps
CPU time 4.3 seconds
Started Aug 10 07:19:00 PM PDT 24
Finished Aug 10 07:19:05 PM PDT 24
Peak memory 215236 kb
Host smart-c7ce93f5-6266-49e8-80b3-69a7efe9cf22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149780703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4149780703
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3231027749
Short name T1038
Test name
Test status
Simulation time 210570286 ps
CPU time 2.16 seconds
Started Aug 10 07:19:04 PM PDT 24
Finished Aug 10 07:19:07 PM PDT 24
Peak memory 216356 kb
Host smart-48a52d7e-4841-4287-b531-a919511af3dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231027749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3231027749
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2326457405
Short name T1091
Test name
Test status
Simulation time 1690688371 ps
CPU time 17.24 seconds
Started Aug 10 07:19:01 PM PDT 24
Finished Aug 10 07:19:18 PM PDT 24
Peak memory 215696 kb
Host smart-dff521d8-5f56-4b2c-ae41-22d72df33fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326457405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2326457405
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1911345232
Short name T1033
Test name
Test status
Simulation time 89208377 ps
CPU time 2.7 seconds
Started Aug 10 07:19:08 PM PDT 24
Finished Aug 10 07:19:11 PM PDT 24
Peak memory 216240 kb
Host smart-2b9f13b1-e564-4984-8cd5-8b96dab1d891
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911345232 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1911345232
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1878414325
Short name T128
Test name
Test status
Simulation time 82249676 ps
CPU time 1.47 seconds
Started Aug 10 07:19:02 PM PDT 24
Finished Aug 10 07:19:04 PM PDT 24
Peak memory 215220 kb
Host smart-e1aeec6d-a11c-40be-a5c8-004583c56c54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878414325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1878414325
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2713133367
Short name T1016
Test name
Test status
Simulation time 46242989 ps
CPU time 0.73 seconds
Started Aug 10 07:19:02 PM PDT 24
Finished Aug 10 07:19:03 PM PDT 24
Peak memory 203676 kb
Host smart-a0719ca8-7b8e-4cb3-97df-f08ab2d712f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713133367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2713133367
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3850647928
Short name T1064
Test name
Test status
Simulation time 134467106 ps
CPU time 3.13 seconds
Started Aug 10 07:19:04 PM PDT 24
Finished Aug 10 07:19:07 PM PDT 24
Peak memory 215248 kb
Host smart-31e2494f-40ec-4d12-a868-46572155e41d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850647928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3850647928
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1425069598
Short name T104
Test name
Test status
Simulation time 304524168 ps
CPU time 4.42 seconds
Started Aug 10 07:19:08 PM PDT 24
Finished Aug 10 07:19:13 PM PDT 24
Peak memory 215268 kb
Host smart-3afe6afa-ca97-456c-b0c5-08fcd3d00e46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425069598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1425069598
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3026338152
Short name T173
Test name
Test status
Simulation time 301989515 ps
CPU time 17.48 seconds
Started Aug 10 07:19:06 PM PDT 24
Finished Aug 10 07:19:24 PM PDT 24
Peak memory 215136 kb
Host smart-41c7117b-212a-4486-9442-eb307b6b0698
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026338152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3026338152
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3898598794
Short name T122
Test name
Test status
Simulation time 918482559 ps
CPU time 15.62 seconds
Started Aug 10 07:18:42 PM PDT 24
Finished Aug 10 07:18:57 PM PDT 24
Peak memory 215244 kb
Host smart-7b5a9259-c4a3-4896-be98-4cb67706d466
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898598794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3898598794
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.555630498
Short name T1117
Test name
Test status
Simulation time 730103222 ps
CPU time 21.25 seconds
Started Aug 10 07:18:43 PM PDT 24
Finished Aug 10 07:19:04 PM PDT 24
Peak memory 215176 kb
Host smart-123b6f0f-3592-4a8a-a9b9-61a5b83e7d72
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555630498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.555630498
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3153428127
Short name T1115
Test name
Test status
Simulation time 44793775 ps
CPU time 0.97 seconds
Started Aug 10 07:18:42 PM PDT 24
Finished Aug 10 07:18:44 PM PDT 24
Peak memory 206656 kb
Host smart-ddf4d922-e710-4cc7-ad10-77664bb45468
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153428127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3153428127
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.419584227
Short name T1109
Test name
Test status
Simulation time 245957130 ps
CPU time 3.92 seconds
Started Aug 10 07:18:55 PM PDT 24
Finished Aug 10 07:18:59 PM PDT 24
Peak memory 218080 kb
Host smart-e2ff947d-4284-43da-a345-61d5febd0be6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419584227 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.419584227
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2275702324
Short name T114
Test name
Test status
Simulation time 113727341 ps
CPU time 1.88 seconds
Started Aug 10 07:18:45 PM PDT 24
Finished Aug 10 07:18:48 PM PDT 24
Peak memory 215180 kb
Host smart-928ee27d-f84e-4f53-a3a2-e68ae3fbe1fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275702324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
275702324
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.826693470
Short name T1021
Test name
Test status
Simulation time 62678541 ps
CPU time 0.77 seconds
Started Aug 10 07:18:46 PM PDT 24
Finished Aug 10 07:18:47 PM PDT 24
Peak memory 203660 kb
Host smart-1f79056e-dd42-469a-8664-aecef707f18b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826693470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.826693470
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.260559287
Short name T117
Test name
Test status
Simulation time 195373861 ps
CPU time 2.23 seconds
Started Aug 10 07:18:45 PM PDT 24
Finished Aug 10 07:18:48 PM PDT 24
Peak memory 214728 kb
Host smart-26b11ee2-1f25-45fd-8cdc-ec192cb573be
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260559287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.260559287
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.452208972
Short name T1116
Test name
Test status
Simulation time 11050579 ps
CPU time 0.67 seconds
Started Aug 10 07:18:44 PM PDT 24
Finished Aug 10 07:18:45 PM PDT 24
Peak memory 203616 kb
Host smart-8c27329b-293b-42cf-b420-c5250748ec5c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452208972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.452208972
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2390443935
Short name T1124
Test name
Test status
Simulation time 2273653421 ps
CPU time 4.29 seconds
Started Aug 10 07:18:50 PM PDT 24
Finished Aug 10 07:18:54 PM PDT 24
Peak memory 215328 kb
Host smart-3e3d007e-40f5-4a89-87dc-9f818ce43cc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390443935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2390443935
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3979136866
Short name T1067
Test name
Test status
Simulation time 57297925 ps
CPU time 1.82 seconds
Started Aug 10 07:18:45 PM PDT 24
Finished Aug 10 07:18:48 PM PDT 24
Peak memory 214868 kb
Host smart-91a014b3-bd0c-4af2-99b3-89d746ea1261
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979136866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
979136866
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1371942438
Short name T177
Test name
Test status
Simulation time 196934689 ps
CPU time 12.43 seconds
Started Aug 10 07:18:46 PM PDT 24
Finished Aug 10 07:18:59 PM PDT 24
Peak memory 215196 kb
Host smart-ad031fbd-12d4-4b0a-86cf-e570dbf3edbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371942438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1371942438
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.304324299
Short name T1114
Test name
Test status
Simulation time 13116351 ps
CPU time 0.71 seconds
Started Aug 10 07:19:06 PM PDT 24
Finished Aug 10 07:19:07 PM PDT 24
Peak memory 203616 kb
Host smart-3dc8132a-2777-4e60-912c-d1f5204947f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304324299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.304324299
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2095756072
Short name T1027
Test name
Test status
Simulation time 11951826 ps
CPU time 0.77 seconds
Started Aug 10 07:19:01 PM PDT 24
Finished Aug 10 07:19:02 PM PDT 24
Peak memory 203616 kb
Host smart-7f838332-ca5d-4345-a193-0dab32a1679b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095756072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2095756072
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3526821948
Short name T1044
Test name
Test status
Simulation time 37668195 ps
CPU time 0.73 seconds
Started Aug 10 07:19:01 PM PDT 24
Finished Aug 10 07:19:02 PM PDT 24
Peak memory 203932 kb
Host smart-121fbb74-136b-41fb-a441-3533771ace4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526821948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3526821948
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4149918493
Short name T1065
Test name
Test status
Simulation time 14674186 ps
CPU time 0.74 seconds
Started Aug 10 07:19:01 PM PDT 24
Finished Aug 10 07:19:02 PM PDT 24
Peak memory 203676 kb
Host smart-6fd09057-e175-43f0-9bb0-4ac101437160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149918493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4149918493
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4101469484
Short name T1081
Test name
Test status
Simulation time 14249652 ps
CPU time 0.8 seconds
Started Aug 10 07:19:00 PM PDT 24
Finished Aug 10 07:19:01 PM PDT 24
Peak memory 203656 kb
Host smart-0d64f2e4-04e7-4a32-9da3-54dbbcc2e9e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101469484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4101469484
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1675816650
Short name T1068
Test name
Test status
Simulation time 14689129 ps
CPU time 0.78 seconds
Started Aug 10 07:19:00 PM PDT 24
Finished Aug 10 07:19:01 PM PDT 24
Peak memory 203676 kb
Host smart-927206c9-ec7b-431c-976a-576044e2f12a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675816650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1675816650
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3448759039
Short name T1039
Test name
Test status
Simulation time 16056029 ps
CPU time 0.73 seconds
Started Aug 10 07:19:09 PM PDT 24
Finished Aug 10 07:19:10 PM PDT 24
Peak memory 203544 kb
Host smart-acae7fae-d719-417d-8028-6ac380a00a71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448759039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3448759039
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2843464801
Short name T1059
Test name
Test status
Simulation time 33544136 ps
CPU time 0.8 seconds
Started Aug 10 07:19:13 PM PDT 24
Finished Aug 10 07:19:14 PM PDT 24
Peak memory 203572 kb
Host smart-562e7107-93c0-4ab3-916e-0d9af026e99e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843464801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2843464801
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4084280597
Short name T1058
Test name
Test status
Simulation time 38821957 ps
CPU time 0.7 seconds
Started Aug 10 07:19:06 PM PDT 24
Finished Aug 10 07:19:07 PM PDT 24
Peak memory 203672 kb
Host smart-98db18ac-1971-4d5d-9516-a2f9fa490caf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084280597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
4084280597
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2462302285
Short name T1085
Test name
Test status
Simulation time 18929341 ps
CPU time 0.71 seconds
Started Aug 10 07:19:09 PM PDT 24
Finished Aug 10 07:19:10 PM PDT 24
Peak memory 203680 kb
Host smart-72c59ccf-3737-4d0b-8102-ceb5c8f2b38a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462302285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2462302285
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1734615859
Short name T126
Test name
Test status
Simulation time 303734252 ps
CPU time 21.2 seconds
Started Aug 10 07:18:55 PM PDT 24
Finished Aug 10 07:19:16 PM PDT 24
Peak memory 215184 kb
Host smart-11becad2-19dd-497d-b923-43f35845b754
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734615859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1734615859
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.565340928
Short name T121
Test name
Test status
Simulation time 366629906 ps
CPU time 21.71 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:19:19 PM PDT 24
Peak memory 206900 kb
Host smart-ab9945eb-1de5-4f87-b605-9239aa02b767
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565340928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.565340928
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2825011810
Short name T88
Test name
Test status
Simulation time 65418701 ps
CPU time 1.19 seconds
Started Aug 10 07:18:52 PM PDT 24
Finished Aug 10 07:18:53 PM PDT 24
Peak memory 206988 kb
Host smart-4ea7427f-d0e4-4d7a-a3d8-4b705ac32ee2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825011810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2825011810
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4034916057
Short name T1053
Test name
Test status
Simulation time 222469837 ps
CPU time 3.52 seconds
Started Aug 10 07:18:55 PM PDT 24
Finished Aug 10 07:18:59 PM PDT 24
Peak memory 218340 kb
Host smart-d0d0548b-af8d-42a6-bd18-1ac86ac964ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034916057 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.4034916057
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2883020586
Short name T1056
Test name
Test status
Simulation time 42039195 ps
CPU time 1.4 seconds
Started Aug 10 07:19:00 PM PDT 24
Finished Aug 10 07:19:01 PM PDT 24
Peak memory 215240 kb
Host smart-bbe62c2e-5914-4490-8650-13610815d348
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883020586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
883020586
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4162761412
Short name T1120
Test name
Test status
Simulation time 25737763 ps
CPU time 0.72 seconds
Started Aug 10 07:18:53 PM PDT 24
Finished Aug 10 07:18:53 PM PDT 24
Peak memory 203660 kb
Host smart-3dd6f093-c42e-4802-adaf-0b8e00975a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162761412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4
162761412
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1200847986
Short name T1102
Test name
Test status
Simulation time 19625795 ps
CPU time 1.29 seconds
Started Aug 10 07:18:51 PM PDT 24
Finished Aug 10 07:18:52 PM PDT 24
Peak memory 215092 kb
Host smart-78e51c9e-36b2-45b2-854c-211457f9bdb9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200847986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1200847986
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4096515216
Short name T1131
Test name
Test status
Simulation time 11923979 ps
CPU time 0.67 seconds
Started Aug 10 07:18:52 PM PDT 24
Finished Aug 10 07:18:52 PM PDT 24
Peak memory 203948 kb
Host smart-3b11f685-c998-470e-8e4c-b4cdf2cc8a06
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096515216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4096515216
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.550768315
Short name T144
Test name
Test status
Simulation time 473837992 ps
CPU time 2.84 seconds
Started Aug 10 07:18:54 PM PDT 24
Finished Aug 10 07:18:57 PM PDT 24
Peak memory 215088 kb
Host smart-4db70bfd-7067-4ad6-bc83-f643bcd84ad8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550768315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.550768315
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3440373910
Short name T1078
Test name
Test status
Simulation time 51433669 ps
CPU time 3.13 seconds
Started Aug 10 07:18:51 PM PDT 24
Finished Aug 10 07:18:55 PM PDT 24
Peak memory 215128 kb
Host smart-45d0876f-47d1-44b0-acec-87a5b0f67204
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440373910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
440373910
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.979862588
Short name T182
Test name
Test status
Simulation time 754552291 ps
CPU time 12.26 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:19:09 PM PDT 24
Peak memory 215136 kb
Host smart-fc2cfa50-e119-4ebf-8389-d83d646d92ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979862588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.979862588
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.930332316
Short name T1122
Test name
Test status
Simulation time 14140017 ps
CPU time 0.72 seconds
Started Aug 10 07:19:12 PM PDT 24
Finished Aug 10 07:19:13 PM PDT 24
Peak memory 203872 kb
Host smart-68f43b72-762d-4e7f-8c89-d0cd1bba6563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930332316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.930332316
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4160834301
Short name T1040
Test name
Test status
Simulation time 45035529 ps
CPU time 0.8 seconds
Started Aug 10 07:19:12 PM PDT 24
Finished Aug 10 07:19:13 PM PDT 24
Peak memory 203640 kb
Host smart-8a4016fa-5b97-4f7f-aa1a-0ccf7204cc05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160834301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4160834301
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2302014761
Short name T1089
Test name
Test status
Simulation time 42846022 ps
CPU time 0.85 seconds
Started Aug 10 07:19:13 PM PDT 24
Finished Aug 10 07:19:14 PM PDT 24
Peak memory 203560 kb
Host smart-e3ea25c7-5140-46b0-bd1d-3006f9fee464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302014761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2302014761
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3703028399
Short name T1051
Test name
Test status
Simulation time 60952420 ps
CPU time 0.72 seconds
Started Aug 10 07:19:12 PM PDT 24
Finished Aug 10 07:19:13 PM PDT 24
Peak memory 203928 kb
Host smart-75a6c2c2-81c9-474e-9208-2892dfafe96d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703028399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3703028399
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3864590003
Short name T1036
Test name
Test status
Simulation time 36136269 ps
CPU time 0.71 seconds
Started Aug 10 07:19:08 PM PDT 24
Finished Aug 10 07:19:09 PM PDT 24
Peak memory 203688 kb
Host smart-8e97e6e3-b027-4589-bbf7-4f2851dd5ae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864590003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3864590003
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2338037480
Short name T1074
Test name
Test status
Simulation time 24055055 ps
CPU time 0.73 seconds
Started Aug 10 07:19:13 PM PDT 24
Finished Aug 10 07:19:14 PM PDT 24
Peak memory 203568 kb
Host smart-254961db-e9e1-4575-975f-0b4536696ebf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338037480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2338037480
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.226090809
Short name T1022
Test name
Test status
Simulation time 12939564 ps
CPU time 0.74 seconds
Started Aug 10 07:19:09 PM PDT 24
Finished Aug 10 07:19:10 PM PDT 24
Peak memory 203992 kb
Host smart-81970b74-c138-4cfe-b545-87dfd1c5ddf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226090809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.226090809
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3428085564
Short name T1100
Test name
Test status
Simulation time 124741825 ps
CPU time 0.74 seconds
Started Aug 10 07:19:09 PM PDT 24
Finished Aug 10 07:19:10 PM PDT 24
Peak memory 203616 kb
Host smart-e15c8c06-cced-46f9-b298-4599a059258c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428085564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3428085564
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2114379338
Short name T1019
Test name
Test status
Simulation time 11942004 ps
CPU time 0.72 seconds
Started Aug 10 07:19:10 PM PDT 24
Finished Aug 10 07:19:10 PM PDT 24
Peak memory 203632 kb
Host smart-e2f2fd54-4fe6-469f-86da-c4eb8715085e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114379338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2114379338
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3689547803
Short name T1035
Test name
Test status
Simulation time 17618942 ps
CPU time 0.82 seconds
Started Aug 10 07:19:09 PM PDT 24
Finished Aug 10 07:19:10 PM PDT 24
Peak memory 203676 kb
Host smart-107f8c19-d611-476d-a06f-5f024c8262a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689547803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3689547803
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3781818759
Short name T118
Test name
Test status
Simulation time 809465171 ps
CPU time 16.18 seconds
Started Aug 10 07:18:55 PM PDT 24
Finished Aug 10 07:19:12 PM PDT 24
Peak memory 215192 kb
Host smart-d3332380-53ec-4062-9c48-0aa86de1a473
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781818759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3781818759
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3731085802
Short name T1042
Test name
Test status
Simulation time 765391503 ps
CPU time 20.91 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:19:18 PM PDT 24
Peak memory 206944 kb
Host smart-b2caca8d-3416-4123-9558-7dacc704e8d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731085802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3731085802
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4086990343
Short name T1080
Test name
Test status
Simulation time 332338335 ps
CPU time 2.71 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:19:00 PM PDT 24
Peak memory 217104 kb
Host smart-75ed9366-aef5-42cf-abb7-5c7c2992de78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086990343 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4086990343
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1770974913
Short name T1088
Test name
Test status
Simulation time 317000579 ps
CPU time 2.14 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:18:59 PM PDT 24
Peak memory 215068 kb
Host smart-d7d619d1-ad93-4f96-85c9-0dcffa3fe329
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770974913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
770974913
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.212146863
Short name T1026
Test name
Test status
Simulation time 50299313 ps
CPU time 0.81 seconds
Started Aug 10 07:18:56 PM PDT 24
Finished Aug 10 07:18:57 PM PDT 24
Peak memory 203624 kb
Host smart-c7368350-3b68-4f9c-82bc-bd68acf8b7ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212146863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.212146863
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.350062148
Short name T127
Test name
Test status
Simulation time 36174325 ps
CPU time 1.36 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:18:59 PM PDT 24
Peak memory 215144 kb
Host smart-4e497be5-6706-4c8d-86e7-066ffeb73293
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350062148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.350062148
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4205241960
Short name T1093
Test name
Test status
Simulation time 22348550 ps
CPU time 0.67 seconds
Started Aug 10 07:18:52 PM PDT 24
Finished Aug 10 07:18:53 PM PDT 24
Peak memory 203568 kb
Host smart-90816df7-1bc3-4889-b02d-2e9542fc5753
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205241960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4205241960
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2946613975
Short name T1076
Test name
Test status
Simulation time 70202037 ps
CPU time 1.74 seconds
Started Aug 10 07:18:51 PM PDT 24
Finished Aug 10 07:18:53 PM PDT 24
Peak memory 215184 kb
Host smart-56945d6a-833b-4fec-a2d4-b501fed4f837
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946613975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2946613975
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1819449101
Short name T98
Test name
Test status
Simulation time 35658722 ps
CPU time 1.32 seconds
Started Aug 10 07:18:55 PM PDT 24
Finished Aug 10 07:18:56 PM PDT 24
Peak memory 215308 kb
Host smart-dde6b9eb-3a75-415b-8dbc-22d27a69eebe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819449101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
819449101
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1424266099
Short name T1090
Test name
Test status
Simulation time 1198631803 ps
CPU time 7.83 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:19:05 PM PDT 24
Peak memory 215712 kb
Host smart-fa09b047-889c-457a-9ca6-ef4b9f2b4401
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424266099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1424266099
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1215406741
Short name T1070
Test name
Test status
Simulation time 11181382 ps
CPU time 0.68 seconds
Started Aug 10 07:19:16 PM PDT 24
Finished Aug 10 07:19:16 PM PDT 24
Peak memory 203664 kb
Host smart-14f79c7d-c7b8-4cec-849c-29969f46863e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215406741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1215406741
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1813500086
Short name T1045
Test name
Test status
Simulation time 14933437 ps
CPU time 0.74 seconds
Started Aug 10 07:19:10 PM PDT 24
Finished Aug 10 07:19:11 PM PDT 24
Peak memory 203940 kb
Host smart-d1f23345-0ecc-4163-8b55-67e9489dbb99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813500086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1813500086
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.769758544
Short name T1123
Test name
Test status
Simulation time 27253357 ps
CPU time 0.81 seconds
Started Aug 10 07:19:09 PM PDT 24
Finished Aug 10 07:19:10 PM PDT 24
Peak memory 203672 kb
Host smart-77ae0470-9314-4d6e-8e1c-9c796ec526ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769758544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.769758544
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1663662084
Short name T1082
Test name
Test status
Simulation time 14008141 ps
CPU time 0.76 seconds
Started Aug 10 07:19:12 PM PDT 24
Finished Aug 10 07:19:12 PM PDT 24
Peak memory 203688 kb
Host smart-409bb4e5-ce1b-4ac7-afa8-6518ebdde9c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663662084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1663662084
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1052179514
Short name T1096
Test name
Test status
Simulation time 31410987 ps
CPU time 0.76 seconds
Started Aug 10 07:19:10 PM PDT 24
Finished Aug 10 07:19:11 PM PDT 24
Peak memory 203688 kb
Host smart-7b133c5a-0fc8-407a-86d7-5841bf47001f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052179514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1052179514
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3697418268
Short name T1018
Test name
Test status
Simulation time 39632987 ps
CPU time 0.73 seconds
Started Aug 10 07:19:11 PM PDT 24
Finished Aug 10 07:19:12 PM PDT 24
Peak memory 203696 kb
Host smart-eccea5e7-f6bd-45d5-b7d8-6e26d1190235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697418268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3697418268
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3823671143
Short name T1108
Test name
Test status
Simulation time 37300796 ps
CPU time 0.71 seconds
Started Aug 10 07:19:11 PM PDT 24
Finished Aug 10 07:19:11 PM PDT 24
Peak memory 203672 kb
Host smart-15f764f2-ecd7-46bf-848e-c35bb0366dcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823671143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3823671143
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3414496675
Short name T1030
Test name
Test status
Simulation time 37962159 ps
CPU time 0.72 seconds
Started Aug 10 07:19:10 PM PDT 24
Finished Aug 10 07:19:10 PM PDT 24
Peak memory 203632 kb
Host smart-52811ad2-5394-4ae9-a82d-02f0337bf7ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414496675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3414496675
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.408868288
Short name T1118
Test name
Test status
Simulation time 40276718 ps
CPU time 0.7 seconds
Started Aug 10 07:19:12 PM PDT 24
Finished Aug 10 07:19:13 PM PDT 24
Peak memory 203556 kb
Host smart-3d919a5f-8ced-4a29-8429-24d0bec82f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408868288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.408868288
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.478744869
Short name T1024
Test name
Test status
Simulation time 29399263 ps
CPU time 0.73 seconds
Started Aug 10 07:19:11 PM PDT 24
Finished Aug 10 07:19:12 PM PDT 24
Peak memory 203616 kb
Host smart-c3de6fef-7a5b-4d0a-8ab4-a0fa0a7a13f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478744869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.478744869
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.582818530
Short name T111
Test name
Test status
Simulation time 33843151 ps
CPU time 1.62 seconds
Started Aug 10 07:18:52 PM PDT 24
Finished Aug 10 07:18:54 PM PDT 24
Peak memory 215128 kb
Host smart-b0bb7488-7204-4ce2-a1d6-f552255a6062
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582818530 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.582818530
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.247328825
Short name T1112
Test name
Test status
Simulation time 38113347 ps
CPU time 1.43 seconds
Started Aug 10 07:18:55 PM PDT 24
Finished Aug 10 07:18:56 PM PDT 24
Peak memory 206864 kb
Host smart-d6c8ee9c-144b-43c8-b444-70629650e802
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247328825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.247328825
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1478007461
Short name T1029
Test name
Test status
Simulation time 26891382 ps
CPU time 0.71 seconds
Started Aug 10 07:18:54 PM PDT 24
Finished Aug 10 07:18:55 PM PDT 24
Peak memory 203668 kb
Host smart-1ffe9253-ad94-4bfa-b900-02f2636c6ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478007461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
478007461
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.965740888
Short name T1037
Test name
Test status
Simulation time 158101737 ps
CPU time 2.58 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:19:00 PM PDT 24
Peak memory 215180 kb
Host smart-006d72bb-ef5c-4318-bec1-92c0a484338f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965740888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.965740888
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.809665541
Short name T1126
Test name
Test status
Simulation time 40497416 ps
CPU time 2.28 seconds
Started Aug 10 07:18:59 PM PDT 24
Finished Aug 10 07:19:01 PM PDT 24
Peak memory 215228 kb
Host smart-79a6512f-bfbc-4e7e-8663-7c633cfd851e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809665541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.809665541
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3210918726
Short name T1110
Test name
Test status
Simulation time 500145289 ps
CPU time 3.96 seconds
Started Aug 10 07:18:55 PM PDT 24
Finished Aug 10 07:18:59 PM PDT 24
Peak memory 218484 kb
Host smart-3d95d82f-5990-4da6-be57-38abf9905439
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210918726 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3210918726
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.637837876
Short name T119
Test name
Test status
Simulation time 123304004 ps
CPU time 3.06 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:19:00 PM PDT 24
Peak memory 215184 kb
Host smart-0bef193a-a838-4233-9f7b-cc3d5bd3951c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637837876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.637837876
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2572906996
Short name T1020
Test name
Test status
Simulation time 15626258 ps
CPU time 0.7 seconds
Started Aug 10 07:18:55 PM PDT 24
Finished Aug 10 07:18:56 PM PDT 24
Peak memory 203628 kb
Host smart-6036e5f6-8dd7-40f0-8d3c-1e22ac0e12b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572906996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
572906996
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3733905801
Short name T1032
Test name
Test status
Simulation time 65272851 ps
CPU time 1.98 seconds
Started Aug 10 07:18:55 PM PDT 24
Finished Aug 10 07:18:57 PM PDT 24
Peak memory 215228 kb
Host smart-2844df36-9ec2-4feb-b0b1-bfca2a86ed2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733905801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3733905801
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2821026280
Short name T108
Test name
Test status
Simulation time 597143127 ps
CPU time 3.95 seconds
Started Aug 10 07:18:52 PM PDT 24
Finished Aug 10 07:18:56 PM PDT 24
Peak memory 215236 kb
Host smart-9626c378-a67c-4c50-9b6b-977d72f8f964
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821026280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
821026280
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3298174503
Short name T1130
Test name
Test status
Simulation time 808432763 ps
CPU time 13.28 seconds
Started Aug 10 07:18:58 PM PDT 24
Finished Aug 10 07:19:12 PM PDT 24
Peak memory 215260 kb
Host smart-696baaf5-f74e-4f1b-bf77-4d4e12976b28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298174503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3298174503
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.98280288
Short name T1086
Test name
Test status
Simulation time 210114738 ps
CPU time 3.39 seconds
Started Aug 10 07:18:54 PM PDT 24
Finished Aug 10 07:18:57 PM PDT 24
Peak memory 217456 kb
Host smart-19c0ca7f-f8e4-43be-b93f-9fbbe5b6f829
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98280288 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.98280288
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4214205852
Short name T125
Test name
Test status
Simulation time 50935785 ps
CPU time 1.48 seconds
Started Aug 10 07:18:56 PM PDT 24
Finished Aug 10 07:18:57 PM PDT 24
Peak memory 215164 kb
Host smart-44a9ef96-cd0e-489b-96cd-d96793a8739d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214205852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4
214205852
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.694474668
Short name T1061
Test name
Test status
Simulation time 11518770 ps
CPU time 0.81 seconds
Started Aug 10 07:18:55 PM PDT 24
Finished Aug 10 07:18:56 PM PDT 24
Peak memory 203640 kb
Host smart-93be1bbc-a26d-447f-9102-02b89f476f9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694474668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.694474668
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1078336351
Short name T1097
Test name
Test status
Simulation time 97128508 ps
CPU time 1.76 seconds
Started Aug 10 07:18:56 PM PDT 24
Finished Aug 10 07:18:58 PM PDT 24
Peak memory 215144 kb
Host smart-bdfb0148-2e18-4a95-82d8-c0c0c78f8352
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078336351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1078336351
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3946033796
Short name T101
Test name
Test status
Simulation time 380426326 ps
CPU time 8.3 seconds
Started Aug 10 07:18:54 PM PDT 24
Finished Aug 10 07:19:02 PM PDT 24
Peak memory 215160 kb
Host smart-1dcda3c2-9815-4177-9a66-77b5c3449c87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946033796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3946033796
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.717102431
Short name T1095
Test name
Test status
Simulation time 215388159 ps
CPU time 1.91 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:18:59 PM PDT 24
Peak memory 216292 kb
Host smart-e0c530ed-f5a1-4610-94ce-c6fdf7738f2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717102431 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.717102431
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3247703386
Short name T1129
Test name
Test status
Simulation time 150935520 ps
CPU time 2.04 seconds
Started Aug 10 07:18:53 PM PDT 24
Finished Aug 10 07:18:55 PM PDT 24
Peak memory 215208 kb
Host smart-573aeece-c2ac-444b-8f48-0a6852836d38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247703386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
247703386
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.456447707
Short name T1105
Test name
Test status
Simulation time 14717907 ps
CPU time 0.71 seconds
Started Aug 10 07:18:56 PM PDT 24
Finished Aug 10 07:18:57 PM PDT 24
Peak memory 203980 kb
Host smart-c62995e1-ddc6-4b78-aa1f-a1e14d755e09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456447707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.456447707
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2393506043
Short name T1041
Test name
Test status
Simulation time 42482828 ps
CPU time 2.77 seconds
Started Aug 10 07:18:56 PM PDT 24
Finished Aug 10 07:18:59 PM PDT 24
Peak memory 215156 kb
Host smart-fc3131a3-77c7-4a15-9c43-3ed1ed03cd5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393506043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2393506043
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3412561285
Short name T103
Test name
Test status
Simulation time 169041758 ps
CPU time 3.02 seconds
Started Aug 10 07:18:56 PM PDT 24
Finished Aug 10 07:18:59 PM PDT 24
Peak memory 215392 kb
Host smart-8de1feca-cd36-4d4b-9470-9e268216d2ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412561285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
412561285
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1609006715
Short name T170
Test name
Test status
Simulation time 142270118 ps
CPU time 3.85 seconds
Started Aug 10 07:18:54 PM PDT 24
Finished Aug 10 07:18:58 PM PDT 24
Peak memory 216800 kb
Host smart-119a3cee-876d-460f-a284-b3834b3a4ba8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609006715 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1609006715
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4059995555
Short name T116
Test name
Test status
Simulation time 52032963 ps
CPU time 1.83 seconds
Started Aug 10 07:18:56 PM PDT 24
Finished Aug 10 07:18:58 PM PDT 24
Peak memory 206972 kb
Host smart-c4265780-9cab-479a-88ca-82829311cfc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059995555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4
059995555
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.125837242
Short name T1052
Test name
Test status
Simulation time 35736520 ps
CPU time 0.7 seconds
Started Aug 10 07:19:01 PM PDT 24
Finished Aug 10 07:19:02 PM PDT 24
Peak memory 203996 kb
Host smart-cbd80f35-1162-437e-8524-a490f74d023d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125837242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.125837242
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2130503997
Short name T1125
Test name
Test status
Simulation time 41318408 ps
CPU time 1.53 seconds
Started Aug 10 07:18:55 PM PDT 24
Finished Aug 10 07:18:57 PM PDT 24
Peak memory 215132 kb
Host smart-2fe12013-69be-4bcb-99fa-2a7a81b15d98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130503997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2130503997
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1571400889
Short name T1098
Test name
Test status
Simulation time 49951981 ps
CPU time 3.32 seconds
Started Aug 10 07:18:57 PM PDT 24
Finished Aug 10 07:19:01 PM PDT 24
Peak memory 215300 kb
Host smart-ec36de9e-9a75-4e63-a9f4-dc3730ee144d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571400889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
571400889
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.42404568
Short name T1069
Test name
Test status
Simulation time 311608737 ps
CPU time 7.73 seconds
Started Aug 10 07:18:55 PM PDT 24
Finished Aug 10 07:19:03 PM PDT 24
Peak memory 215172 kb
Host smart-d16343b9-e33e-476e-9156-e74c6a0b77cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42404568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_t
l_intg_err.42404568
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.144821354
Short name T443
Test name
Test status
Simulation time 14142614 ps
CPU time 0.74 seconds
Started Aug 10 07:24:40 PM PDT 24
Finished Aug 10 07:24:41 PM PDT 24
Peak memory 205172 kb
Host smart-b3b652c0-5f4c-4bf3-b672-6f08e5807206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144821354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.144821354
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3404369003
Short name T912
Test name
Test status
Simulation time 407844257 ps
CPU time 4.76 seconds
Started Aug 10 07:24:39 PM PDT 24
Finished Aug 10 07:24:44 PM PDT 24
Peak memory 224924 kb
Host smart-98ae9a20-99b1-4416-a2b5-c46ca7ac5cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404369003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3404369003
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2569278073
Short name T882
Test name
Test status
Simulation time 45102328 ps
CPU time 0.77 seconds
Started Aug 10 07:24:30 PM PDT 24
Finished Aug 10 07:24:31 PM PDT 24
Peak memory 207268 kb
Host smart-913e7cc4-0dce-423c-aeaf-f705fa8ed486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569278073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2569278073
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.413743209
Short name T570
Test name
Test status
Simulation time 18645824565 ps
CPU time 16.78 seconds
Started Aug 10 07:24:42 PM PDT 24
Finished Aug 10 07:24:58 PM PDT 24
Peak memory 236452 kb
Host smart-452efa12-c676-4897-b849-a2e9e0f7bf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413743209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.413743209
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.158800129
Short name T419
Test name
Test status
Simulation time 12635125436 ps
CPU time 98.97 seconds
Started Aug 10 07:24:39 PM PDT 24
Finished Aug 10 07:26:18 PM PDT 24
Peak memory 255532 kb
Host smart-ecf56958-e6d6-4ccb-9e5d-a6d7a22b77c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158800129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.158800129
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.94725812
Short name T840
Test name
Test status
Simulation time 9862996173 ps
CPU time 77.88 seconds
Started Aug 10 07:24:39 PM PDT 24
Finished Aug 10 07:25:58 PM PDT 24
Peak memory 249736 kb
Host smart-6690dab5-6fbd-4404-8d54-2adac30a6a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94725812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.94725812
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.4124219580
Short name T620
Test name
Test status
Simulation time 2100307707 ps
CPU time 33.31 seconds
Started Aug 10 07:24:38 PM PDT 24
Finished Aug 10 07:25:11 PM PDT 24
Peak memory 233124 kb
Host smart-77a88f47-c352-4998-bd27-d5bef09a2e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124219580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.4124219580
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2513427916
Short name T715
Test name
Test status
Simulation time 4752641220 ps
CPU time 7.34 seconds
Started Aug 10 07:24:41 PM PDT 24
Finished Aug 10 07:24:48 PM PDT 24
Peak memory 236320 kb
Host smart-392a0bc7-ffea-4675-8307-673c151a93af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513427916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2513427916
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4142335256
Short name T421
Test name
Test status
Simulation time 4938149713 ps
CPU time 6.86 seconds
Started Aug 10 07:24:41 PM PDT 24
Finished Aug 10 07:24:48 PM PDT 24
Peak memory 225040 kb
Host smart-3134a538-afe4-4190-8b66-d186f31cbdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142335256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4142335256
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3510899222
Short name T557
Test name
Test status
Simulation time 4945186417 ps
CPU time 59.05 seconds
Started Aug 10 07:24:42 PM PDT 24
Finished Aug 10 07:25:41 PM PDT 24
Peak memory 233028 kb
Host smart-42302206-9437-4241-895d-c6c0d3200325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510899222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3510899222
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1365307310
Short name T687
Test name
Test status
Simulation time 21335453923 ps
CPU time 5.76 seconds
Started Aug 10 07:24:35 PM PDT 24
Finished Aug 10 07:24:41 PM PDT 24
Peak memory 224996 kb
Host smart-de67f9d2-8b4f-4cce-ac4a-e239299ff69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365307310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1365307310
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.921072931
Short name T788
Test name
Test status
Simulation time 3043851401 ps
CPU time 4.12 seconds
Started Aug 10 07:24:44 PM PDT 24
Finished Aug 10 07:24:48 PM PDT 24
Peak memory 224964 kb
Host smart-f5b8120b-3898-41bb-b48d-9778c70b21b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921072931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.921072931
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3909443669
Short name T654
Test name
Test status
Simulation time 222376290 ps
CPU time 3.89 seconds
Started Aug 10 07:24:39 PM PDT 24
Finished Aug 10 07:24:43 PM PDT 24
Peak memory 221032 kb
Host smart-6be45a63-2046-488b-a2d8-2eadc24eeb98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3909443669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3909443669
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1352952923
Short name T868
Test name
Test status
Simulation time 1348303257 ps
CPU time 17.05 seconds
Started Aug 10 07:24:38 PM PDT 24
Finished Aug 10 07:24:55 PM PDT 24
Peak memory 220208 kb
Host smart-dbacf924-787c-4bdd-bb2e-b6c64a481393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352952923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1352952923
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.4061466356
Short name T568
Test name
Test status
Simulation time 5639101875 ps
CPU time 15.78 seconds
Started Aug 10 07:24:30 PM PDT 24
Finished Aug 10 07:24:46 PM PDT 24
Peak memory 216764 kb
Host smart-315bc33b-a76c-487a-8d27-cc34b05a19ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061466356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.4061466356
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.501619974
Short name T336
Test name
Test status
Simulation time 17305860 ps
CPU time 0.66 seconds
Started Aug 10 07:24:38 PM PDT 24
Finished Aug 10 07:24:39 PM PDT 24
Peak memory 206084 kb
Host smart-0c9ba82c-e826-440e-a5a9-887a4eaf5b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501619974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.501619974
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2579825837
Short name T334
Test name
Test status
Simulation time 18871414 ps
CPU time 0.72 seconds
Started Aug 10 07:24:42 PM PDT 24
Finished Aug 10 07:24:43 PM PDT 24
Peak memory 205996 kb
Host smart-11d706f7-d64a-40f7-9eef-bc558a9509c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579825837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2579825837
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1969240975
Short name T1005
Test name
Test status
Simulation time 549705078 ps
CPU time 3.39 seconds
Started Aug 10 07:24:39 PM PDT 24
Finished Aug 10 07:24:43 PM PDT 24
Peak memory 233108 kb
Host smart-fbdf4023-db91-4929-8fda-5c95ec12edaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969240975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1969240975
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1197534934
Short name T510
Test name
Test status
Simulation time 12665403 ps
CPU time 0.71 seconds
Started Aug 10 07:24:40 PM PDT 24
Finished Aug 10 07:24:41 PM PDT 24
Peak memory 205168 kb
Host smart-ecacdaba-67dc-4055-b6c5-3959888252be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197534934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
197534934
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1007508351
Short name T81
Test name
Test status
Simulation time 18071583 ps
CPU time 0.76 seconds
Started Aug 10 07:24:36 PM PDT 24
Finished Aug 10 07:24:37 PM PDT 24
Peak memory 205932 kb
Host smart-2d4fd770-be33-449d-92d5-f580cfc477cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007508351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1007508351
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1022490325
Short name T563
Test name
Test status
Simulation time 30847284065 ps
CPU time 104.91 seconds
Started Aug 10 07:24:39 PM PDT 24
Finished Aug 10 07:26:25 PM PDT 24
Peak memory 257948 kb
Host smart-131d59d9-1965-477e-b53e-b6e9d4ad23f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022490325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1022490325
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1889272118
Short name T941
Test name
Test status
Simulation time 33353042398 ps
CPU time 188.9 seconds
Started Aug 10 07:24:40 PM PDT 24
Finished Aug 10 07:27:49 PM PDT 24
Peak memory 256784 kb
Host smart-a37a845e-4a28-4106-9c13-7fad285a37e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889272118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1889272118
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.478409845
Short name T507
Test name
Test status
Simulation time 101987060 ps
CPU time 3.89 seconds
Started Aug 10 07:24:40 PM PDT 24
Finished Aug 10 07:24:44 PM PDT 24
Peak memory 233136 kb
Host smart-e9b810bf-032f-4aa0-8bc6-a0108016e6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478409845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.478409845
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1225432208
Short name T24
Test name
Test status
Simulation time 1219477195 ps
CPU time 16.96 seconds
Started Aug 10 07:24:40 PM PDT 24
Finished Aug 10 07:24:57 PM PDT 24
Peak memory 239712 kb
Host smart-92d25217-50c0-4d90-9fc5-b84d083f5a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225432208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1225432208
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3291082351
Short name T463
Test name
Test status
Simulation time 24024160091 ps
CPU time 13.86 seconds
Started Aug 10 07:24:42 PM PDT 24
Finished Aug 10 07:24:56 PM PDT 24
Peak memory 224808 kb
Host smart-a2035937-e79d-45ba-8b13-be6217d17849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291082351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3291082351
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3004617546
Short name T952
Test name
Test status
Simulation time 430643584 ps
CPU time 12.38 seconds
Started Aug 10 07:24:44 PM PDT 24
Finished Aug 10 07:24:56 PM PDT 24
Peak memory 240712 kb
Host smart-6809b47b-2547-4298-b952-67d741d271cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004617546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3004617546
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2704305372
Short name T628
Test name
Test status
Simulation time 85596750 ps
CPU time 2.54 seconds
Started Aug 10 07:24:41 PM PDT 24
Finished Aug 10 07:24:43 PM PDT 24
Peak memory 224936 kb
Host smart-d8941779-f844-48cb-87b4-04f0c7f9a5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704305372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2704305372
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.661544762
Short name T924
Test name
Test status
Simulation time 1481826541 ps
CPU time 10.59 seconds
Started Aug 10 07:24:44 PM PDT 24
Finished Aug 10 07:24:54 PM PDT 24
Peak memory 234184 kb
Host smart-4d22fb62-838f-40f2-833e-ab473a915a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661544762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.661544762
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2769161466
Short name T148
Test name
Test status
Simulation time 1160732989 ps
CPU time 4.96 seconds
Started Aug 10 07:24:43 PM PDT 24
Finished Aug 10 07:24:49 PM PDT 24
Peak memory 220748 kb
Host smart-8d414f20-4cef-4d64-8f26-781530d8fbbd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2769161466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2769161466
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3430417705
Short name T77
Test name
Test status
Simulation time 120615701 ps
CPU time 1.09 seconds
Started Aug 10 07:24:39 PM PDT 24
Finished Aug 10 07:24:41 PM PDT 24
Peak memory 237036 kb
Host smart-0b6288aa-822c-48ef-ba9d-bf7da3b0ed08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430417705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3430417705
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1310072573
Short name T580
Test name
Test status
Simulation time 59162211006 ps
CPU time 44.34 seconds
Started Aug 10 07:24:43 PM PDT 24
Finished Aug 10 07:25:27 PM PDT 24
Peak memory 216828 kb
Host smart-7c68fd27-8564-4fa0-b103-db3fb7d4399a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310072573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1310072573
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3007341144
Short name T903
Test name
Test status
Simulation time 329607391 ps
CPU time 2.62 seconds
Started Aug 10 07:24:41 PM PDT 24
Finished Aug 10 07:24:44 PM PDT 24
Peak memory 216704 kb
Host smart-07b67d2f-56a2-4e88-ad4e-b068b354a0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007341144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3007341144
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3893388954
Short name T895
Test name
Test status
Simulation time 13966812 ps
CPU time 0.74 seconds
Started Aug 10 07:24:43 PM PDT 24
Finished Aug 10 07:24:44 PM PDT 24
Peak memory 206400 kb
Host smart-4c4f75a5-b33d-436d-8508-87d34c4f9ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893388954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3893388954
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3693095289
Short name T486
Test name
Test status
Simulation time 26659585 ps
CPU time 0.77 seconds
Started Aug 10 07:24:39 PM PDT 24
Finished Aug 10 07:24:39 PM PDT 24
Peak memory 206364 kb
Host smart-8a79681a-4c89-4484-8724-8fcc98bb7434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693095289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3693095289
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.459899859
Short name T389
Test name
Test status
Simulation time 1388474313 ps
CPU time 4.07 seconds
Started Aug 10 07:24:47 PM PDT 24
Finished Aug 10 07:24:51 PM PDT 24
Peak memory 224952 kb
Host smart-3781d02a-5cf5-4e9f-830a-99340a9ddb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459899859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.459899859
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3605031815
Short name T835
Test name
Test status
Simulation time 26664492 ps
CPU time 0.75 seconds
Started Aug 10 07:25:09 PM PDT 24
Finished Aug 10 07:25:10 PM PDT 24
Peak memory 205232 kb
Host smart-ba859d0e-0efc-457a-8178-94d906bf48f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605031815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3605031815
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2936681067
Short name T80
Test name
Test status
Simulation time 138608251 ps
CPU time 2.45 seconds
Started Aug 10 07:25:14 PM PDT 24
Finished Aug 10 07:25:16 PM PDT 24
Peak memory 233128 kb
Host smart-dd7af531-5aa9-4e14-bca1-b8ecd863da30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936681067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2936681067
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.905882052
Short name T929
Test name
Test status
Simulation time 19632793 ps
CPU time 0.8 seconds
Started Aug 10 07:25:12 PM PDT 24
Finished Aug 10 07:25:13 PM PDT 24
Peak memory 207000 kb
Host smart-e1e6098c-66ff-4036-9f66-044faa81492a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905882052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.905882052
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.4168585690
Short name T931
Test name
Test status
Simulation time 10002448458 ps
CPU time 70.42 seconds
Started Aug 10 07:25:11 PM PDT 24
Finished Aug 10 07:26:21 PM PDT 24
Peak memory 256168 kb
Host smart-2f7595b6-690c-4556-8eb2-7ccabadc3e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168585690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.4168585690
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1736446498
Short name T141
Test name
Test status
Simulation time 6661931962 ps
CPU time 54.28 seconds
Started Aug 10 07:25:10 PM PDT 24
Finished Aug 10 07:26:05 PM PDT 24
Peak memory 249628 kb
Host smart-6eab6c62-29a9-4c3e-8efa-279355b42622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736446498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1736446498
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3350943055
Short name T708
Test name
Test status
Simulation time 8946151633 ps
CPU time 120.01 seconds
Started Aug 10 07:25:11 PM PDT 24
Finished Aug 10 07:27:11 PM PDT 24
Peak memory 251148 kb
Host smart-8a3d9109-505a-42b5-8ab8-9a3c3be4755a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350943055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3350943055
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.4068797846
Short name T392
Test name
Test status
Simulation time 117938244 ps
CPU time 4.82 seconds
Started Aug 10 07:25:09 PM PDT 24
Finished Aug 10 07:25:14 PM PDT 24
Peak memory 224896 kb
Host smart-2e052ebf-95ad-4688-8099-71c7bff65bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068797846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.4068797846
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3548781720
Short name T754
Test name
Test status
Simulation time 53332316 ps
CPU time 0.76 seconds
Started Aug 10 07:25:12 PM PDT 24
Finished Aug 10 07:25:13 PM PDT 24
Peak memory 216104 kb
Host smart-aeff6955-9eaa-4784-9213-6da381219fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548781720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3548781720
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2130126604
Short name T219
Test name
Test status
Simulation time 1268750498 ps
CPU time 14.69 seconds
Started Aug 10 07:25:09 PM PDT 24
Finished Aug 10 07:25:24 PM PDT 24
Peak memory 233172 kb
Host smart-404caac4-054e-4367-9014-672b24c66c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130126604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2130126604
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.165601409
Short name T492
Test name
Test status
Simulation time 1179992246 ps
CPU time 11.31 seconds
Started Aug 10 07:25:11 PM PDT 24
Finished Aug 10 07:25:22 PM PDT 24
Peak memory 224684 kb
Host smart-13fc7a7b-cc0f-44a1-af7e-6c630aa41bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165601409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.165601409
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2824107450
Short name T761
Test name
Test status
Simulation time 8568673853 ps
CPU time 24.1 seconds
Started Aug 10 07:25:10 PM PDT 24
Finished Aug 10 07:25:34 PM PDT 24
Peak memory 233120 kb
Host smart-d4b7e911-e829-4c94-a152-70a8a515c5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824107450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2824107450
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2754540635
Short name T329
Test name
Test status
Simulation time 123663576 ps
CPU time 2.46 seconds
Started Aug 10 07:25:09 PM PDT 24
Finished Aug 10 07:25:12 PM PDT 24
Peak memory 232776 kb
Host smart-75ed54b7-9d47-41a0-9eb0-6adf31809e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754540635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2754540635
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4105954799
Short name T508
Test name
Test status
Simulation time 142536575 ps
CPU time 4.13 seconds
Started Aug 10 07:25:09 PM PDT 24
Finished Aug 10 07:25:14 PM PDT 24
Peak memory 219584 kb
Host smart-6d6ab61e-0511-4cbc-8bd5-8c84a5832535
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4105954799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4105954799
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3091881806
Short name T595
Test name
Test status
Simulation time 166014099 ps
CPU time 0.95 seconds
Started Aug 10 07:25:10 PM PDT 24
Finished Aug 10 07:25:11 PM PDT 24
Peak memory 206980 kb
Host smart-5dcd66d4-ec77-4cad-a70e-12943847c0b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091881806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3091881806
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2198699423
Short name T528
Test name
Test status
Simulation time 2456685449 ps
CPU time 14.98 seconds
Started Aug 10 07:25:10 PM PDT 24
Finished Aug 10 07:25:25 PM PDT 24
Peak memory 216728 kb
Host smart-70e1622e-823f-48d0-b19c-e9f6f66a32e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198699423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2198699423
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1520231789
Short name T819
Test name
Test status
Simulation time 1003677070 ps
CPU time 4.99 seconds
Started Aug 10 07:25:12 PM PDT 24
Finished Aug 10 07:25:17 PM PDT 24
Peak memory 216548 kb
Host smart-7e9ab15e-224d-4f93-9592-0c0098db1948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520231789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1520231789
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2997760688
Short name T668
Test name
Test status
Simulation time 108974975 ps
CPU time 1.29 seconds
Started Aug 10 07:25:08 PM PDT 24
Finished Aug 10 07:25:09 PM PDT 24
Peak memory 208284 kb
Host smart-32a0deb0-332c-42f2-b333-4e205ac1accb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997760688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2997760688
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.617048099
Short name T965
Test name
Test status
Simulation time 87873947 ps
CPU time 0.78 seconds
Started Aug 10 07:25:11 PM PDT 24
Finished Aug 10 07:25:12 PM PDT 24
Peak memory 205240 kb
Host smart-de3008ff-fe0a-4dca-8b5b-4baa1c7fc625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617048099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.617048099
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2695506243
Short name T230
Test name
Test status
Simulation time 1243607301 ps
CPU time 10.66 seconds
Started Aug 10 07:25:09 PM PDT 24
Finished Aug 10 07:25:20 PM PDT 24
Peak memory 233120 kb
Host smart-64b69711-a760-4b54-9849-d4ea7a86d940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695506243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2695506243
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2242467320
Short name T529
Test name
Test status
Simulation time 16968510 ps
CPU time 0.75 seconds
Started Aug 10 07:25:21 PM PDT 24
Finished Aug 10 07:25:22 PM PDT 24
Peak memory 205232 kb
Host smart-b7c6d69d-7102-416b-80cd-902fb787558c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242467320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2242467320
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1720156951
Short name T785
Test name
Test status
Simulation time 2225668399 ps
CPU time 12.59 seconds
Started Aug 10 07:25:25 PM PDT 24
Finished Aug 10 07:25:37 PM PDT 24
Peak memory 233180 kb
Host smart-e432079e-663c-41a4-92b7-84f73d0e5965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720156951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1720156951
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.746907819
Short name T335
Test name
Test status
Simulation time 41332659 ps
CPU time 0.74 seconds
Started Aug 10 07:25:09 PM PDT 24
Finished Aug 10 07:25:10 PM PDT 24
Peak memory 207280 kb
Host smart-e4f17835-fb7c-420e-8dd1-989eb61d0b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746907819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.746907819
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.813155420
Short name T970
Test name
Test status
Simulation time 85480291094 ps
CPU time 137.45 seconds
Started Aug 10 07:25:19 PM PDT 24
Finished Aug 10 07:27:37 PM PDT 24
Peak memory 249792 kb
Host smart-fae47238-48e4-481a-90cc-87f3ee563b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813155420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.813155420
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1749577546
Short name T167
Test name
Test status
Simulation time 6174800939 ps
CPU time 66.23 seconds
Started Aug 10 07:25:19 PM PDT 24
Finished Aug 10 07:26:25 PM PDT 24
Peak memory 249928 kb
Host smart-31993f69-c7cc-4fe4-9a80-2bf417359481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749577546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1749577546
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2222262233
Short name T679
Test name
Test status
Simulation time 55224916 ps
CPU time 3.26 seconds
Started Aug 10 07:25:23 PM PDT 24
Finished Aug 10 07:25:26 PM PDT 24
Peak memory 224944 kb
Host smart-15348ca0-3a5d-46f2-89ac-45a8d3fe87f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222262233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2222262233
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.4202857384
Short name T195
Test name
Test status
Simulation time 155578132209 ps
CPU time 284.25 seconds
Started Aug 10 07:25:21 PM PDT 24
Finished Aug 10 07:30:05 PM PDT 24
Peak memory 256724 kb
Host smart-abed2bc3-6c71-4ec5-8233-23ceb98a13ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202857384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.4202857384
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3268550674
Short name T504
Test name
Test status
Simulation time 648906962 ps
CPU time 3.1 seconds
Started Aug 10 07:25:11 PM PDT 24
Finished Aug 10 07:25:14 PM PDT 24
Peak memory 219288 kb
Host smart-08c96763-bb60-462f-b67f-89572a5773b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268550674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3268550674
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.369548424
Short name T667
Test name
Test status
Simulation time 418009140 ps
CPU time 4.6 seconds
Started Aug 10 07:25:08 PM PDT 24
Finished Aug 10 07:25:13 PM PDT 24
Peak memory 224916 kb
Host smart-352d7ff7-9911-428c-a6ef-69056a13dc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369548424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.369548424
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3485168271
Short name T259
Test name
Test status
Simulation time 322294422 ps
CPU time 4.13 seconds
Started Aug 10 07:25:11 PM PDT 24
Finished Aug 10 07:25:15 PM PDT 24
Peak memory 233100 kb
Host smart-b6ca5988-dc99-4c54-9281-3ad1191b211c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485168271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3485168271
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3467174655
Short name T372
Test name
Test status
Simulation time 15760531894 ps
CPU time 19.99 seconds
Started Aug 10 07:25:19 PM PDT 24
Finished Aug 10 07:25:39 PM PDT 24
Peak memory 222076 kb
Host smart-e5f01dee-c3d5-42f6-9c73-6c1395321559
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3467174655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3467174655
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1125692284
Short name T129
Test name
Test status
Simulation time 57518941500 ps
CPU time 489.54 seconds
Started Aug 10 07:25:25 PM PDT 24
Finished Aug 10 07:33:35 PM PDT 24
Peak memory 264532 kb
Host smart-ef727931-fc4b-48bc-bd0a-990115ac9a36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125692284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1125692284
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1988665368
Short name T922
Test name
Test status
Simulation time 8377015421 ps
CPU time 43.1 seconds
Started Aug 10 07:25:10 PM PDT 24
Finished Aug 10 07:25:53 PM PDT 24
Peak memory 216748 kb
Host smart-7f047678-0b05-49a1-8dc9-f3df30f1a0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988665368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1988665368
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1040627744
Short name T585
Test name
Test status
Simulation time 437255169 ps
CPU time 1.81 seconds
Started Aug 10 07:25:10 PM PDT 24
Finished Aug 10 07:25:12 PM PDT 24
Peak memory 216476 kb
Host smart-e8f3434d-b75c-42d3-bd43-41296a9bf8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040627744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1040627744
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1324053927
Short name T393
Test name
Test status
Simulation time 79605459 ps
CPU time 1.26 seconds
Started Aug 10 07:25:09 PM PDT 24
Finished Aug 10 07:25:10 PM PDT 24
Peak memory 216660 kb
Host smart-6627c9d1-88a2-42b7-b133-14d0052d1dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324053927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1324053927
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3311709017
Short name T612
Test name
Test status
Simulation time 47106861 ps
CPU time 0.74 seconds
Started Aug 10 07:25:09 PM PDT 24
Finished Aug 10 07:25:10 PM PDT 24
Peak memory 206336 kb
Host smart-2bca6b57-3314-4c97-b1ee-c92421e9bbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311709017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3311709017
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2746335759
Short name T822
Test name
Test status
Simulation time 80809701 ps
CPU time 2.07 seconds
Started Aug 10 07:25:10 PM PDT 24
Finished Aug 10 07:25:12 PM PDT 24
Peak memory 224572 kb
Host smart-04d531dd-5996-439f-95e5-e16400bd4055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746335759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2746335759
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.884121075
Short name T512
Test name
Test status
Simulation time 112232677 ps
CPU time 2.53 seconds
Started Aug 10 07:25:21 PM PDT 24
Finished Aug 10 07:25:23 PM PDT 24
Peak memory 224924 kb
Host smart-ddd7cc18-cd54-4b57-b51b-5771fb7e345d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884121075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.884121075
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.703988353
Short name T66
Test name
Test status
Simulation time 31890390 ps
CPU time 0.84 seconds
Started Aug 10 07:25:19 PM PDT 24
Finished Aug 10 07:25:20 PM PDT 24
Peak memory 207136 kb
Host smart-eed2363f-d39d-4cc1-9860-329af26007f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703988353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.703988353
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2304926100
Short name T940
Test name
Test status
Simulation time 3643455907 ps
CPU time 70.61 seconds
Started Aug 10 07:25:19 PM PDT 24
Finished Aug 10 07:26:30 PM PDT 24
Peak memory 265984 kb
Host smart-3a8b3dbd-134e-4380-99c7-6a6325160e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304926100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2304926100
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1199254605
Short name T935
Test name
Test status
Simulation time 4545608887 ps
CPU time 73.95 seconds
Started Aug 10 07:25:21 PM PDT 24
Finished Aug 10 07:26:35 PM PDT 24
Peak memory 250884 kb
Host smart-3497edd0-ba19-44ea-9342-4ee6318d3a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199254605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1199254605
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2818060130
Short name T57
Test name
Test status
Simulation time 281777438037 ps
CPU time 664.08 seconds
Started Aug 10 07:25:20 PM PDT 24
Finished Aug 10 07:36:24 PM PDT 24
Peak memory 268028 kb
Host smart-68c0b765-8ad4-458c-80af-2d0a58e2dc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818060130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2818060130
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3966214878
Short name T631
Test name
Test status
Simulation time 1741930302 ps
CPU time 6.71 seconds
Started Aug 10 07:25:20 PM PDT 24
Finished Aug 10 07:25:27 PM PDT 24
Peak memory 224996 kb
Host smart-1fa9b8d7-9111-4ba9-8ea2-de26da5de36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966214878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3966214878
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.128998658
Short name T676
Test name
Test status
Simulation time 3164671673 ps
CPU time 30.4 seconds
Started Aug 10 07:25:18 PM PDT 24
Finished Aug 10 07:25:49 PM PDT 24
Peak memory 233172 kb
Host smart-85bf2f1c-89a1-436e-9164-2d84546d4209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128998658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.128998658
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.73419153
Short name T220
Test name
Test status
Simulation time 383569528 ps
CPU time 7.58 seconds
Started Aug 10 07:25:20 PM PDT 24
Finished Aug 10 07:25:27 PM PDT 24
Peak memory 239112 kb
Host smart-85c843c7-777a-4ed9-ade5-22b7a7edd280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73419153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.73419153
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2981208407
Short name T812
Test name
Test status
Simulation time 510100211 ps
CPU time 2.58 seconds
Started Aug 10 07:25:19 PM PDT 24
Finished Aug 10 07:25:21 PM PDT 24
Peak memory 225008 kb
Host smart-70e7890f-c2f9-40de-a720-115a24998ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981208407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2981208407
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3631274257
Short name T255
Test name
Test status
Simulation time 2273393049 ps
CPU time 5.76 seconds
Started Aug 10 07:25:18 PM PDT 24
Finished Aug 10 07:25:24 PM PDT 24
Peak memory 239144 kb
Host smart-627e2a03-0fb6-4165-8645-700fac375b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631274257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3631274257
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3109160685
Short name T475
Test name
Test status
Simulation time 586701788 ps
CPU time 7.61 seconds
Started Aug 10 07:25:21 PM PDT 24
Finished Aug 10 07:25:28 PM PDT 24
Peak memory 222372 kb
Host smart-fa405271-4729-47f8-b632-c496c10e927f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3109160685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3109160685
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1869723693
Short name T1007
Test name
Test status
Simulation time 218985917 ps
CPU time 1.09 seconds
Started Aug 10 07:25:18 PM PDT 24
Finished Aug 10 07:25:19 PM PDT 24
Peak memory 207620 kb
Host smart-fbe6e85e-cbe9-4d82-b262-28dfb5efcae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869723693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1869723693
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2818691606
Short name T694
Test name
Test status
Simulation time 81982955889 ps
CPU time 48.65 seconds
Started Aug 10 07:25:19 PM PDT 24
Finished Aug 10 07:26:08 PM PDT 24
Peak memory 216768 kb
Host smart-1569a905-c135-4dd2-8a92-7b94ab345e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818691606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2818691606
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3391309322
Short name T961
Test name
Test status
Simulation time 3607806196 ps
CPU time 4.67 seconds
Started Aug 10 07:25:25 PM PDT 24
Finished Aug 10 07:25:30 PM PDT 24
Peak memory 216820 kb
Host smart-508b246f-0c80-42d9-a4e7-78f81139b68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391309322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3391309322
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.4105597492
Short name T7
Test name
Test status
Simulation time 61596518 ps
CPU time 1.07 seconds
Started Aug 10 07:25:20 PM PDT 24
Finished Aug 10 07:25:21 PM PDT 24
Peak memory 207348 kb
Host smart-a80e34b5-4e5d-42a8-b041-3c733238447d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105597492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4105597492
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3739830865
Short name T404
Test name
Test status
Simulation time 57534624 ps
CPU time 0.87 seconds
Started Aug 10 07:25:20 PM PDT 24
Finished Aug 10 07:25:21 PM PDT 24
Peak memory 206328 kb
Host smart-582b52ca-d24f-4269-97be-0f3e8c55a901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739830865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3739830865
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3453720666
Short name T588
Test name
Test status
Simulation time 7862939449 ps
CPU time 3.37 seconds
Started Aug 10 07:25:21 PM PDT 24
Finished Aug 10 07:25:24 PM PDT 24
Peak memory 224976 kb
Host smart-1f2d790b-3ece-45b0-aa42-778ac3c45fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453720666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3453720666
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3995133645
Short name T344
Test name
Test status
Simulation time 34926306 ps
CPU time 0.7 seconds
Started Aug 10 07:25:27 PM PDT 24
Finished Aug 10 07:25:28 PM PDT 24
Peak memory 206224 kb
Host smart-bf053380-6f06-4c7f-8165-1dce7dcb786a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995133645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3995133645
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1233438615
Short name T742
Test name
Test status
Simulation time 131985474 ps
CPU time 2.8 seconds
Started Aug 10 07:25:21 PM PDT 24
Finished Aug 10 07:25:24 PM PDT 24
Peak memory 224908 kb
Host smart-b826282f-f3b1-43bd-a3ab-1d605f5c0d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233438615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1233438615
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.406701606
Short name T79
Test name
Test status
Simulation time 16568538 ps
CPU time 0.75 seconds
Started Aug 10 07:25:20 PM PDT 24
Finished Aug 10 07:25:21 PM PDT 24
Peak memory 205924 kb
Host smart-4175fb01-3ac6-4cfd-85a0-9016502fbe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406701606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.406701606
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3751192570
Short name T381
Test name
Test status
Simulation time 2623676751 ps
CPU time 56.56 seconds
Started Aug 10 07:25:20 PM PDT 24
Finished Aug 10 07:26:17 PM PDT 24
Peak memory 264072 kb
Host smart-d7a3eb3f-4a1a-4b6c-b83b-6498b5e723e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751192570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3751192570
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1395969358
Short name T608
Test name
Test status
Simulation time 6861842213 ps
CPU time 23.64 seconds
Started Aug 10 07:25:18 PM PDT 24
Finished Aug 10 07:25:42 PM PDT 24
Peak memory 217944 kb
Host smart-0aed39d3-1749-4047-8e00-3b16fd18bc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395969358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1395969358
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2490490821
Short name T211
Test name
Test status
Simulation time 76136083317 ps
CPU time 234.15 seconds
Started Aug 10 07:25:25 PM PDT 24
Finished Aug 10 07:29:19 PM PDT 24
Peak memory 263744 kb
Host smart-9ed9ceb2-52c3-413f-b8a8-02e6ace0f190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490490821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2490490821
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2819179267
Short name T454
Test name
Test status
Simulation time 9916099396 ps
CPU time 19.18 seconds
Started Aug 10 07:25:22 PM PDT 24
Finished Aug 10 07:25:42 PM PDT 24
Peak memory 241392 kb
Host smart-8723c42f-398d-4395-86ad-e928e8ef2d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819179267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2819179267
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.654466292
Short name T992
Test name
Test status
Simulation time 7554592087 ps
CPU time 53.28 seconds
Started Aug 10 07:25:18 PM PDT 24
Finished Aug 10 07:26:11 PM PDT 24
Peak memory 241424 kb
Host smart-85c26a03-9016-4ec7-adb7-7bf6c46b00d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654466292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.654466292
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.765803709
Short name T367
Test name
Test status
Simulation time 50877732 ps
CPU time 2.06 seconds
Started Aug 10 07:25:20 PM PDT 24
Finished Aug 10 07:25:22 PM PDT 24
Peak memory 224568 kb
Host smart-9cf40376-39ef-4bb4-8f01-cc4d5330e856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765803709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.765803709
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2353944455
Short name T866
Test name
Test status
Simulation time 5207060490 ps
CPU time 38.28 seconds
Started Aug 10 07:25:20 PM PDT 24
Finished Aug 10 07:25:58 PM PDT 24
Peak memory 240964 kb
Host smart-5625bc64-8115-4ff3-8d72-54ae98f5b268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353944455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2353944455
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1649564667
Short name T646
Test name
Test status
Simulation time 316260512 ps
CPU time 6.05 seconds
Started Aug 10 07:25:20 PM PDT 24
Finished Aug 10 07:25:26 PM PDT 24
Peak memory 233184 kb
Host smart-88546167-1d54-490a-bbf3-6f1d9d2e57c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649564667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1649564667
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2719197570
Short name T996
Test name
Test status
Simulation time 3392383245 ps
CPU time 13.21 seconds
Started Aug 10 07:25:20 PM PDT 24
Finished Aug 10 07:25:34 PM PDT 24
Peak memory 233100 kb
Host smart-6316e0a5-bbe9-4354-93d0-40f03eabbc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719197570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2719197570
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3805881986
Short name T933
Test name
Test status
Simulation time 298312073 ps
CPU time 3.58 seconds
Started Aug 10 07:25:19 PM PDT 24
Finished Aug 10 07:25:23 PM PDT 24
Peak memory 221248 kb
Host smart-c6995ef6-e227-429b-b5f3-21e8884f2177
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3805881986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3805881986
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2324627835
Short name T480
Test name
Test status
Simulation time 32808868 ps
CPU time 0.72 seconds
Started Aug 10 07:25:18 PM PDT 24
Finished Aug 10 07:25:19 PM PDT 24
Peak memory 206380 kb
Host smart-9506d013-ce3a-4a72-a886-16cc4cd0c3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324627835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2324627835
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.623080044
Short name T388
Test name
Test status
Simulation time 4718829540 ps
CPU time 2.13 seconds
Started Aug 10 07:25:18 PM PDT 24
Finished Aug 10 07:25:20 PM PDT 24
Peak memory 208088 kb
Host smart-f49fffa4-edcc-4592-abb6-f6de3c653730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623080044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.623080044
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2519548780
Short name T356
Test name
Test status
Simulation time 86884771 ps
CPU time 1.74 seconds
Started Aug 10 07:25:21 PM PDT 24
Finished Aug 10 07:25:23 PM PDT 24
Peak memory 216664 kb
Host smart-73968bf8-d706-4936-85bf-551df1c13cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519548780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2519548780
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.193823512
Short name T1004
Test name
Test status
Simulation time 107334140 ps
CPU time 0.9 seconds
Started Aug 10 07:25:19 PM PDT 24
Finished Aug 10 07:25:20 PM PDT 24
Peak memory 206356 kb
Host smart-460d39f3-e662-4ac9-9cd7-46d1a72ff07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193823512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.193823512
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3938733150
Short name T376
Test name
Test status
Simulation time 1053714366 ps
CPU time 8.77 seconds
Started Aug 10 07:25:19 PM PDT 24
Finished Aug 10 07:25:28 PM PDT 24
Peak memory 233288 kb
Host smart-32955df9-9143-4791-97e6-7ba5251a3a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938733150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3938733150
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.406121344
Short name T526
Test name
Test status
Simulation time 12151734 ps
CPU time 0.68 seconds
Started Aug 10 07:25:25 PM PDT 24
Finished Aug 10 07:25:26 PM PDT 24
Peak memory 205312 kb
Host smart-4e3a2fb7-81e4-4361-960c-29e1501ba0a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406121344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.406121344
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.824256966
Short name T720
Test name
Test status
Simulation time 942372001 ps
CPU time 10.93 seconds
Started Aug 10 07:25:34 PM PDT 24
Finished Aug 10 07:25:45 PM PDT 24
Peak memory 233124 kb
Host smart-c333843b-3c3e-4341-b202-d0b33166a838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824256966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.824256966
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2656915200
Short name T472
Test name
Test status
Simulation time 57309844 ps
CPU time 0.8 seconds
Started Aug 10 07:25:30 PM PDT 24
Finished Aug 10 07:25:31 PM PDT 24
Peak memory 206996 kb
Host smart-f6db921a-a333-42f1-ad0e-0bac5efdc7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656915200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2656915200
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1213086753
Short name T301
Test name
Test status
Simulation time 59672188852 ps
CPU time 228.01 seconds
Started Aug 10 07:25:29 PM PDT 24
Finished Aug 10 07:29:17 PM PDT 24
Peak memory 266036 kb
Host smart-952f831d-cf41-4354-bb1a-aafa2ecf9513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213086753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1213086753
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1335495451
Short name T657
Test name
Test status
Simulation time 28259963049 ps
CPU time 158.06 seconds
Started Aug 10 07:25:27 PM PDT 24
Finished Aug 10 07:28:05 PM PDT 24
Peak memory 249784 kb
Host smart-396d2183-9934-4311-a3a7-4491b93ea778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335495451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1335495451
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.197072778
Short name T139
Test name
Test status
Simulation time 7967672765 ps
CPU time 86.38 seconds
Started Aug 10 07:25:34 PM PDT 24
Finished Aug 10 07:27:00 PM PDT 24
Peak memory 249684 kb
Host smart-71b6d916-4071-4c88-9682-649a36f57215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197072778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.197072778
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1708504986
Short name T826
Test name
Test status
Simulation time 503551045 ps
CPU time 6.48 seconds
Started Aug 10 07:25:27 PM PDT 24
Finished Aug 10 07:25:34 PM PDT 24
Peak memory 224880 kb
Host smart-9d30a814-814c-407c-9af1-c3c43dc8ab39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708504986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1708504986
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3157664224
Short name T296
Test name
Test status
Simulation time 36845739601 ps
CPU time 254.88 seconds
Started Aug 10 07:25:30 PM PDT 24
Finished Aug 10 07:29:45 PM PDT 24
Peak memory 254324 kb
Host smart-f657652e-41e2-4f91-a975-1c7aab448757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157664224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3157664224
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3816679278
Short name T428
Test name
Test status
Simulation time 37575058 ps
CPU time 2.37 seconds
Started Aug 10 07:25:29 PM PDT 24
Finished Aug 10 07:25:32 PM PDT 24
Peak memory 233188 kb
Host smart-db20105a-0c64-4171-a920-1a225e0bd060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816679278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3816679278
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3628175786
Short name T610
Test name
Test status
Simulation time 1758729541 ps
CPU time 16.33 seconds
Started Aug 10 07:25:30 PM PDT 24
Finished Aug 10 07:25:47 PM PDT 24
Peak memory 224904 kb
Host smart-62ce9c53-107a-4b42-a80c-13110c7163a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628175786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3628175786
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1752064380
Short name T808
Test name
Test status
Simulation time 2270219555 ps
CPU time 8.98 seconds
Started Aug 10 07:25:28 PM PDT 24
Finished Aug 10 07:25:37 PM PDT 24
Peak memory 236568 kb
Host smart-26d4e218-bc03-417c-8a76-4b9b696d3972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752064380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1752064380
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2165604674
Short name T998
Test name
Test status
Simulation time 3310793980 ps
CPU time 12.08 seconds
Started Aug 10 07:25:33 PM PDT 24
Finished Aug 10 07:25:45 PM PDT 24
Peak memory 225032 kb
Host smart-5c33d24f-375b-4958-a04e-467290e82d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165604674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2165604674
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1458364590
Short name T577
Test name
Test status
Simulation time 434094463 ps
CPU time 5.62 seconds
Started Aug 10 07:25:28 PM PDT 24
Finished Aug 10 07:25:33 PM PDT 24
Peak memory 222540 kb
Host smart-3d52015e-f17a-4f6c-b931-fbb784c48040
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1458364590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1458364590
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.185059060
Short name T831
Test name
Test status
Simulation time 4633582577 ps
CPU time 25.77 seconds
Started Aug 10 07:25:30 PM PDT 24
Finished Aug 10 07:25:56 PM PDT 24
Peak memory 220884 kb
Host smart-78447f70-8780-4e1b-b99a-123a1a086598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185059060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.185059060
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.658490825
Short name T339
Test name
Test status
Simulation time 4450040862 ps
CPU time 8.15 seconds
Started Aug 10 07:25:26 PM PDT 24
Finished Aug 10 07:25:35 PM PDT 24
Peak memory 216704 kb
Host smart-b9ccf8bc-9a59-4421-a692-4de426ca6fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658490825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.658490825
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1979680655
Short name T749
Test name
Test status
Simulation time 70851401 ps
CPU time 3.2 seconds
Started Aug 10 07:25:27 PM PDT 24
Finished Aug 10 07:25:30 PM PDT 24
Peak memory 216508 kb
Host smart-146a9990-ffc4-4c3e-a938-1a64b0f9861d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979680655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1979680655
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1488729955
Short name T32
Test name
Test status
Simulation time 554050108 ps
CPU time 0.82 seconds
Started Aug 10 07:25:31 PM PDT 24
Finished Aug 10 07:25:32 PM PDT 24
Peak memory 206404 kb
Host smart-78a02cf0-2ffa-4c6a-abd3-ed9ff6e9c65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488729955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1488729955
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2551586748
Short name T487
Test name
Test status
Simulation time 17682564166 ps
CPU time 29.96 seconds
Started Aug 10 07:25:33 PM PDT 24
Finished Aug 10 07:26:03 PM PDT 24
Peak memory 233276 kb
Host smart-ceacfdc8-400b-447c-bf7f-b9b98a874f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551586748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2551586748
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1354700463
Short name T412
Test name
Test status
Simulation time 38046800 ps
CPU time 0.74 seconds
Started Aug 10 07:25:30 PM PDT 24
Finished Aug 10 07:25:31 PM PDT 24
Peak memory 205900 kb
Host smart-8c6a59ee-9fe0-40d0-91f5-b8a96b5185bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354700463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1354700463
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1320015985
Short name T948
Test name
Test status
Simulation time 3112345099 ps
CPU time 8.99 seconds
Started Aug 10 07:25:30 PM PDT 24
Finished Aug 10 07:25:39 PM PDT 24
Peak memory 233136 kb
Host smart-aac2d0d9-76c0-4882-98a7-4d528357a6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320015985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1320015985
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.491026389
Short name T450
Test name
Test status
Simulation time 54060253 ps
CPU time 0.8 seconds
Started Aug 10 07:25:26 PM PDT 24
Finished Aug 10 07:25:27 PM PDT 24
Peak memory 206920 kb
Host smart-6fd03a56-b4d9-4b02-b3a2-e2001a13b3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491026389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.491026389
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3036508243
Short name T291
Test name
Test status
Simulation time 33541654361 ps
CPU time 255.58 seconds
Started Aug 10 07:25:28 PM PDT 24
Finished Aug 10 07:29:44 PM PDT 24
Peak memory 256520 kb
Host smart-71693e28-e204-4823-af9f-76e77ba303eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036508243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3036508243
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2506426822
Short name T86
Test name
Test status
Simulation time 4119513303 ps
CPU time 106.39 seconds
Started Aug 10 07:25:27 PM PDT 24
Finished Aug 10 07:27:14 PM PDT 24
Peak memory 252416 kb
Host smart-047f4a72-4ea0-4541-877b-83b9f149b46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506426822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2506426822
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1473240658
Short name T714
Test name
Test status
Simulation time 202909044 ps
CPU time 5.06 seconds
Started Aug 10 07:25:27 PM PDT 24
Finished Aug 10 07:25:33 PM PDT 24
Peak memory 241368 kb
Host smart-9874f7c4-431e-4950-9c4f-861845f0179c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473240658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1473240658
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3794362430
Short name T967
Test name
Test status
Simulation time 34626010608 ps
CPU time 32.85 seconds
Started Aug 10 07:25:33 PM PDT 24
Finished Aug 10 07:26:06 PM PDT 24
Peak memory 233264 kb
Host smart-48d4ba5f-6b0a-4833-8a38-1df23969c099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794362430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3794362430
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.363478749
Short name T204
Test name
Test status
Simulation time 1126696269 ps
CPU time 10.99 seconds
Started Aug 10 07:25:34 PM PDT 24
Finished Aug 10 07:25:45 PM PDT 24
Peak memory 224924 kb
Host smart-b17f9ae6-0710-4ba1-bdf3-0abbc008b7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363478749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.363478749
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1319517621
Short name T994
Test name
Test status
Simulation time 36003978 ps
CPU time 2.57 seconds
Started Aug 10 07:25:26 PM PDT 24
Finished Aug 10 07:25:28 PM PDT 24
Peak memory 232836 kb
Host smart-3f03b2a7-4d28-46be-8d0b-f2b69f77d931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319517621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1319517621
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3015598846
Short name T229
Test name
Test status
Simulation time 2360222461 ps
CPU time 6.44 seconds
Started Aug 10 07:25:33 PM PDT 24
Finished Aug 10 07:25:40 PM PDT 24
Peak memory 225032 kb
Host smart-941ba8e1-005d-47b8-b40d-805380cf4d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015598846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3015598846
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1737077084
Short name T538
Test name
Test status
Simulation time 31998986 ps
CPU time 2.14 seconds
Started Aug 10 07:25:28 PM PDT 24
Finished Aug 10 07:25:30 PM PDT 24
Peak memory 232880 kb
Host smart-d746a206-1780-41fa-bfe4-7de9ca51aa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737077084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1737077084
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3113975366
Short name T807
Test name
Test status
Simulation time 591732809 ps
CPU time 3.64 seconds
Started Aug 10 07:25:35 PM PDT 24
Finished Aug 10 07:25:39 PM PDT 24
Peak memory 223024 kb
Host smart-d65c8dbc-b784-4090-95a7-6327786632d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3113975366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3113975366
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1900899439
Short name T288
Test name
Test status
Simulation time 159298488784 ps
CPU time 316.1 seconds
Started Aug 10 07:25:27 PM PDT 24
Finished Aug 10 07:30:43 PM PDT 24
Peak memory 282452 kb
Host smart-49e53fb3-d981-4ba2-adf8-ac01af0d1f29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900899439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1900899439
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3718134776
Short name T609
Test name
Test status
Simulation time 14187421 ps
CPU time 0.74 seconds
Started Aug 10 07:25:27 PM PDT 24
Finished Aug 10 07:25:28 PM PDT 24
Peak memory 206072 kb
Host smart-cfad9041-c931-4887-b16c-962cb64c52d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718134776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3718134776
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3009838929
Short name T402
Test name
Test status
Simulation time 2077174248 ps
CPU time 6.55 seconds
Started Aug 10 07:25:33 PM PDT 24
Finished Aug 10 07:25:40 PM PDT 24
Peak memory 216744 kb
Host smart-118fd320-ef6a-4763-8315-d4ed85386963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009838929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3009838929
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.443827895
Short name T516
Test name
Test status
Simulation time 41060434 ps
CPU time 0.65 seconds
Started Aug 10 07:25:27 PM PDT 24
Finished Aug 10 07:25:28 PM PDT 24
Peak memory 206008 kb
Host smart-5e80761d-b74b-4718-bd95-80576c9e171f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443827895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.443827895
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.663416548
Short name T349
Test name
Test status
Simulation time 152179942 ps
CPU time 1.06 seconds
Started Aug 10 07:25:27 PM PDT 24
Finished Aug 10 07:25:28 PM PDT 24
Peak memory 207364 kb
Host smart-86f2aaee-939e-441e-8933-073b3fe38497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663416548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.663416548
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2953547989
Short name T663
Test name
Test status
Simulation time 4804853159 ps
CPU time 14.94 seconds
Started Aug 10 07:25:30 PM PDT 24
Finished Aug 10 07:25:45 PM PDT 24
Peak memory 249944 kb
Host smart-1e83ae95-4119-4ef8-8147-ff8ce44a30bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953547989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2953547989
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.895515033
Short name T403
Test name
Test status
Simulation time 44285432 ps
CPU time 0.73 seconds
Started Aug 10 07:25:36 PM PDT 24
Finished Aug 10 07:25:37 PM PDT 24
Peak memory 206172 kb
Host smart-614700da-1a3e-447a-9ae9-23d3a65c75d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895515033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.895515033
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2943672261
Short name T500
Test name
Test status
Simulation time 15668504310 ps
CPU time 22.61 seconds
Started Aug 10 07:25:37 PM PDT 24
Finished Aug 10 07:26:00 PM PDT 24
Peak memory 233220 kb
Host smart-515077b6-b434-487a-a4d9-9b3501d71ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943672261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2943672261
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1729161893
Short name T681
Test name
Test status
Simulation time 70326957 ps
CPU time 0.74 seconds
Started Aug 10 07:25:29 PM PDT 24
Finished Aug 10 07:25:29 PM PDT 24
Peak memory 205976 kb
Host smart-aeb5ceac-39b1-40f8-92dd-7c4143ede825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729161893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1729161893
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3343204788
Short name T968
Test name
Test status
Simulation time 28535082853 ps
CPU time 192.5 seconds
Started Aug 10 07:25:36 PM PDT 24
Finished Aug 10 07:28:49 PM PDT 24
Peak memory 252696 kb
Host smart-a95471c0-7941-4826-991d-db4ef12e1ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343204788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3343204788
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3854260255
Short name T833
Test name
Test status
Simulation time 6999563462 ps
CPU time 114.99 seconds
Started Aug 10 07:25:36 PM PDT 24
Finished Aug 10 07:27:31 PM PDT 24
Peak memory 251204 kb
Host smart-730a6137-1138-4c1f-b5ce-28f1516ed1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854260255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3854260255
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3105761505
Short name T635
Test name
Test status
Simulation time 11270090380 ps
CPU time 33.67 seconds
Started Aug 10 07:25:38 PM PDT 24
Finished Aug 10 07:26:12 PM PDT 24
Peak memory 241144 kb
Host smart-f3f5025b-922a-4633-bb68-1c6661cc1769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105761505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3105761505
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1587034793
Short name T341
Test name
Test status
Simulation time 330267144 ps
CPU time 3.32 seconds
Started Aug 10 07:25:34 PM PDT 24
Finished Aug 10 07:25:38 PM PDT 24
Peak memory 233276 kb
Host smart-975b2359-dd48-44b8-88e2-8df6deb4dd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587034793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1587034793
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2423526147
Short name T776
Test name
Test status
Simulation time 6294090935 ps
CPU time 73.19 seconds
Started Aug 10 07:25:39 PM PDT 24
Finished Aug 10 07:26:52 PM PDT 24
Peak memory 252284 kb
Host smart-d3903738-a19a-44bd-8c5e-f1a77a6365f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423526147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2423526147
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1300646188
Short name T871
Test name
Test status
Simulation time 3433051541 ps
CPU time 17.81 seconds
Started Aug 10 07:25:35 PM PDT 24
Finished Aug 10 07:25:53 PM PDT 24
Peak memory 233228 kb
Host smart-9ad7fe2a-8445-4f4f-b296-05c9e6e0d820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300646188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1300646188
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.847336435
Short name T449
Test name
Test status
Simulation time 518978285 ps
CPU time 2.86 seconds
Started Aug 10 07:25:35 PM PDT 24
Finished Aug 10 07:25:38 PM PDT 24
Peak memory 233088 kb
Host smart-e50a81cd-24f1-41aa-8e39-e460be1977bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847336435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.847336435
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2851849458
Short name T390
Test name
Test status
Simulation time 5759172662 ps
CPU time 18.94 seconds
Started Aug 10 07:25:27 PM PDT 24
Finished Aug 10 07:25:46 PM PDT 24
Peak memory 233208 kb
Host smart-504df8a6-af66-47c7-8eb6-59b77f711146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851849458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2851849458
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3406686733
Short name T1010
Test name
Test status
Simulation time 4075181107 ps
CPU time 5.67 seconds
Started Aug 10 07:25:28 PM PDT 24
Finished Aug 10 07:25:34 PM PDT 24
Peak memory 225000 kb
Host smart-28912e88-e5d0-4444-9a18-9f66cf39329b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406686733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3406686733
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1720795278
Short name T5
Test name
Test status
Simulation time 743986565 ps
CPU time 6.37 seconds
Started Aug 10 07:25:35 PM PDT 24
Finished Aug 10 07:25:41 PM PDT 24
Peak memory 219256 kb
Host smart-827aa571-687f-4981-b572-fde2d88530d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1720795278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1720795278
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3941904462
Short name T160
Test name
Test status
Simulation time 1480426392 ps
CPU time 23.27 seconds
Started Aug 10 07:25:37 PM PDT 24
Finished Aug 10 07:26:01 PM PDT 24
Peak memory 241428 kb
Host smart-668d832d-6186-483b-b231-1d776896fe2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941904462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3941904462
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2868964590
Short name T691
Test name
Test status
Simulation time 10953679718 ps
CPU time 55.12 seconds
Started Aug 10 07:25:27 PM PDT 24
Finished Aug 10 07:26:22 PM PDT 24
Peak memory 221712 kb
Host smart-6da61a48-deca-4177-bf54-f0b8cd6872c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868964590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2868964590
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.54611174
Short name T582
Test name
Test status
Simulation time 2652275431 ps
CPU time 9.6 seconds
Started Aug 10 07:25:30 PM PDT 24
Finished Aug 10 07:25:40 PM PDT 24
Peak memory 216812 kb
Host smart-e77f7193-9ca8-4d86-b7ea-a91256e1c270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54611174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.54611174
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2364409872
Short name T551
Test name
Test status
Simulation time 22874204 ps
CPU time 1.25 seconds
Started Aug 10 07:25:27 PM PDT 24
Finished Aug 10 07:25:28 PM PDT 24
Peak memory 216760 kb
Host smart-e52281db-0ee1-4a69-95fc-7167b6c0ace7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364409872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2364409872
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.865498786
Short name T410
Test name
Test status
Simulation time 20367631 ps
CPU time 0.77 seconds
Started Aug 10 07:25:27 PM PDT 24
Finished Aug 10 07:25:28 PM PDT 24
Peak memory 206296 kb
Host smart-16f5ecfc-53b0-4f0a-8f9b-948b9891ae9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865498786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.865498786
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.74986824
Short name T523
Test name
Test status
Simulation time 11017777417 ps
CPU time 14.27 seconds
Started Aug 10 07:25:36 PM PDT 24
Finished Aug 10 07:25:50 PM PDT 24
Peak memory 225012 kb
Host smart-aaac31bd-4e55-42e0-a71f-6d3d830f8ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74986824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.74986824
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.890563934
Short name T796
Test name
Test status
Simulation time 96861337 ps
CPU time 0.81 seconds
Started Aug 10 07:25:39 PM PDT 24
Finished Aug 10 07:25:40 PM PDT 24
Peak memory 205788 kb
Host smart-2dfe2058-8d3a-4f75-87e0-f5a855e4ae78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890563934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.890563934
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1287205086
Short name T621
Test name
Test status
Simulation time 320617194 ps
CPU time 2.39 seconds
Started Aug 10 07:25:38 PM PDT 24
Finished Aug 10 07:25:41 PM PDT 24
Peak memory 233124 kb
Host smart-22ef7ac8-33f8-4752-aa74-0263ca7a6ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287205086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1287205086
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2929616352
Short name T470
Test name
Test status
Simulation time 38503096 ps
CPU time 0.75 seconds
Started Aug 10 07:25:39 PM PDT 24
Finished Aug 10 07:25:40 PM PDT 24
Peak memory 206924 kb
Host smart-c4edc88d-d9d8-440f-bad5-6c618549de74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929616352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2929616352
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2137222170
Short name T703
Test name
Test status
Simulation time 1035102090 ps
CPU time 9.64 seconds
Started Aug 10 07:25:36 PM PDT 24
Finished Aug 10 07:25:46 PM PDT 24
Peak memory 217984 kb
Host smart-a821dba3-f477-4c2d-98eb-8ab91ded96a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137222170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2137222170
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3935241937
Short name T678
Test name
Test status
Simulation time 2005646830 ps
CPU time 21.95 seconds
Started Aug 10 07:25:36 PM PDT 24
Finished Aug 10 07:25:58 PM PDT 24
Peak memory 237200 kb
Host smart-ec3b89a5-369a-4c72-8941-059946958d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935241937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3935241937
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.4131787780
Short name T84
Test name
Test status
Simulation time 2757384269 ps
CPU time 18.89 seconds
Started Aug 10 07:25:35 PM PDT 24
Finished Aug 10 07:25:54 PM PDT 24
Peak memory 224984 kb
Host smart-89a82901-f85e-45bb-beff-369b3b2ccdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131787780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.4131787780
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2799649292
Short name T930
Test name
Test status
Simulation time 3621422876 ps
CPU time 24.41 seconds
Started Aug 10 07:25:35 PM PDT 24
Finished Aug 10 07:26:00 PM PDT 24
Peak memory 249588 kb
Host smart-fa5e439a-e7b2-41ed-8cc5-2637429505e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799649292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2799649292
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.785074296
Short name T617
Test name
Test status
Simulation time 35553952 ps
CPU time 2.6 seconds
Started Aug 10 07:25:41 PM PDT 24
Finished Aug 10 07:25:43 PM PDT 24
Peak memory 233188 kb
Host smart-2ed1d76d-ffae-4d7d-86da-9ca5c84de5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785074296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.785074296
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2354530641
Short name T1
Test name
Test status
Simulation time 237191549 ps
CPU time 4.78 seconds
Started Aug 10 07:25:40 PM PDT 24
Finished Aug 10 07:25:45 PM PDT 24
Peak memory 224972 kb
Host smart-12e1c96b-66a1-4854-84f9-5bd2e2985b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354530641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2354530641
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.4221979143
Short name T598
Test name
Test status
Simulation time 294153930 ps
CPU time 6.78 seconds
Started Aug 10 07:25:37 PM PDT 24
Finished Aug 10 07:25:44 PM PDT 24
Peak memory 241388 kb
Host smart-3de8eba3-9ce4-4e93-82d8-9674310caa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221979143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.4221979143
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.95286292
Short name T46
Test name
Test status
Simulation time 9074514526 ps
CPU time 8.36 seconds
Started Aug 10 07:25:39 PM PDT 24
Finished Aug 10 07:25:47 PM PDT 24
Peak memory 233132 kb
Host smart-1d1e7e27-ecee-4b0b-b033-b3612446acf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95286292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.95286292
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.320587800
Short name T548
Test name
Test status
Simulation time 4842779041 ps
CPU time 8.45 seconds
Started Aug 10 07:25:37 PM PDT 24
Finished Aug 10 07:25:45 PM PDT 24
Peak memory 219856 kb
Host smart-9510d812-f3bd-43ca-842a-725894b98dd9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=320587800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.320587800
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1940746337
Short name T456
Test name
Test status
Simulation time 20760903141 ps
CPU time 47.49 seconds
Started Aug 10 07:25:36 PM PDT 24
Finished Aug 10 07:26:24 PM PDT 24
Peak memory 216692 kb
Host smart-35be85cf-1416-4e02-a39f-c190fd1d02f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940746337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1940746337
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2635447025
Short name T872
Test name
Test status
Simulation time 3470590296 ps
CPU time 8.54 seconds
Started Aug 10 07:25:36 PM PDT 24
Finished Aug 10 07:25:44 PM PDT 24
Peak memory 216660 kb
Host smart-a0bade5e-8423-45b3-85cd-45b9acc6190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635447025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2635447025
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.267608362
Short name T775
Test name
Test status
Simulation time 104238626 ps
CPU time 4.04 seconds
Started Aug 10 07:25:36 PM PDT 24
Finished Aug 10 07:25:40 PM PDT 24
Peak memory 216500 kb
Host smart-a80c0d9b-7eaf-4692-b953-a32b9ef25054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267608362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.267608362
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3122082060
Short name T340
Test name
Test status
Simulation time 78873080 ps
CPU time 0.88 seconds
Started Aug 10 07:25:34 PM PDT 24
Finished Aug 10 07:25:35 PM PDT 24
Peak memory 206404 kb
Host smart-a8fae5b0-e70d-41ad-885b-34691b5fea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122082060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3122082060
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3872685664
Short name T200
Test name
Test status
Simulation time 3344151665 ps
CPU time 11.5 seconds
Started Aug 10 07:25:35 PM PDT 24
Finished Aug 10 07:25:47 PM PDT 24
Peak memory 233184 kb
Host smart-707fe56a-3dbf-495d-bb64-782909af40ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872685664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3872685664
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2372952556
Short name T355
Test name
Test status
Simulation time 13150001 ps
CPU time 0.69 seconds
Started Aug 10 07:25:43 PM PDT 24
Finished Aug 10 07:25:43 PM PDT 24
Peak memory 205308 kb
Host smart-0bfcea0e-ee65-48ac-9ed1-2127172d58fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372952556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2372952556
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2373221700
Short name T791
Test name
Test status
Simulation time 366861159 ps
CPU time 6.18 seconds
Started Aug 10 07:25:44 PM PDT 24
Finished Aug 10 07:25:50 PM PDT 24
Peak memory 233152 kb
Host smart-e50d4d3a-9b5d-4ddf-9280-c008497c2a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373221700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2373221700
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3850449834
Short name T360
Test name
Test status
Simulation time 22221370 ps
CPU time 0.8 seconds
Started Aug 10 07:25:37 PM PDT 24
Finished Aug 10 07:25:38 PM PDT 24
Peak memory 206916 kb
Host smart-2940fe9c-f1cd-4ea4-9995-e5819c99018c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850449834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3850449834
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2875469834
Short name T215
Test name
Test status
Simulation time 6044760191 ps
CPU time 84.84 seconds
Started Aug 10 07:25:43 PM PDT 24
Finished Aug 10 07:27:08 PM PDT 24
Peak memory 255900 kb
Host smart-63ab1b69-4e81-491c-957a-cf890112759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875469834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2875469834
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2344489397
Short name T451
Test name
Test status
Simulation time 25766329131 ps
CPU time 47.85 seconds
Started Aug 10 07:25:42 PM PDT 24
Finished Aug 10 07:26:30 PM PDT 24
Peak memory 249636 kb
Host smart-038349de-56d1-417a-aa48-2637a86d1ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344489397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2344489397
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2519100449
Short name T51
Test name
Test status
Simulation time 55906330128 ps
CPU time 416.71 seconds
Started Aug 10 07:25:41 PM PDT 24
Finished Aug 10 07:32:38 PM PDT 24
Peak memory 264588 kb
Host smart-d0edbdb7-9b9f-460a-b65d-1c36f98ba6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519100449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2519100449
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2696971953
Short name T999
Test name
Test status
Simulation time 1344450455 ps
CPU time 9.22 seconds
Started Aug 10 07:25:43 PM PDT 24
Finished Aug 10 07:25:53 PM PDT 24
Peak memory 224936 kb
Host smart-4727e61e-6125-4c8c-870f-833c60c65860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696971953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2696971953
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.59172713
Short name T966
Test name
Test status
Simulation time 5860171851 ps
CPU time 24.03 seconds
Started Aug 10 07:25:44 PM PDT 24
Finished Aug 10 07:26:08 PM PDT 24
Peak memory 233112 kb
Host smart-0c60a880-6e43-43e0-8e6f-f4bd86e0de45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59172713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.59172713
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.428647642
Short name T734
Test name
Test status
Simulation time 325603940 ps
CPU time 6.69 seconds
Started Aug 10 07:25:41 PM PDT 24
Finished Aug 10 07:25:48 PM PDT 24
Peak memory 233028 kb
Host smart-8d408fa6-00dc-4659-be4b-d77359be009e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428647642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.428647642
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1195168227
Short name T260
Test name
Test status
Simulation time 1556588669 ps
CPU time 4.47 seconds
Started Aug 10 07:25:44 PM PDT 24
Finished Aug 10 07:25:49 PM PDT 24
Peak memory 233200 kb
Host smart-e0784b14-78df-4dcc-ad1e-290ac6431e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195168227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1195168227
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1200287404
Short name T604
Test name
Test status
Simulation time 298528491 ps
CPU time 3.05 seconds
Started Aug 10 07:25:43 PM PDT 24
Finished Aug 10 07:25:46 PM PDT 24
Peak memory 224848 kb
Host smart-28e1492a-ecec-40b2-9e74-5dd893f25550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200287404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1200287404
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3232707938
Short name T870
Test name
Test status
Simulation time 719175701 ps
CPU time 6.91 seconds
Started Aug 10 07:25:43 PM PDT 24
Finished Aug 10 07:25:50 PM PDT 24
Peak memory 223504 kb
Host smart-777acadc-bbc5-41a4-af5d-0776e38917f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3232707938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3232707938
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3817854435
Short name T561
Test name
Test status
Simulation time 41212002 ps
CPU time 0.94 seconds
Started Aug 10 07:25:43 PM PDT 24
Finished Aug 10 07:25:44 PM PDT 24
Peak memory 207872 kb
Host smart-a30d4ec3-37a9-423f-be56-deebc151ad45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817854435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3817854435
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.844325574
Short name T316
Test name
Test status
Simulation time 208537479 ps
CPU time 3.58 seconds
Started Aug 10 07:25:43 PM PDT 24
Finished Aug 10 07:25:46 PM PDT 24
Peak memory 216940 kb
Host smart-8db44e5b-841b-4fb0-bb36-7eabe3f8314f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844325574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.844325574
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1033350787
Short name T60
Test name
Test status
Simulation time 300301288 ps
CPU time 2.32 seconds
Started Aug 10 07:25:36 PM PDT 24
Finished Aug 10 07:25:38 PM PDT 24
Peak memory 216724 kb
Host smart-ec4e2896-8631-4ac1-aec6-43f2f4645c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033350787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1033350787
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.275657394
Short name T532
Test name
Test status
Simulation time 490933013 ps
CPU time 1.84 seconds
Started Aug 10 07:25:43 PM PDT 24
Finished Aug 10 07:25:45 PM PDT 24
Peak memory 216628 kb
Host smart-7411de44-78b7-4c09-a72b-98ffec6ab1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275657394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.275657394
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.661681678
Short name T784
Test name
Test status
Simulation time 38605925 ps
CPU time 0.8 seconds
Started Aug 10 07:25:43 PM PDT 24
Finished Aug 10 07:25:44 PM PDT 24
Peak memory 206400 kb
Host smart-216a3e42-7857-44db-8417-5a5daee85018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661681678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.661681678
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.259679029
Short name T709
Test name
Test status
Simulation time 375358164 ps
CPU time 2.97 seconds
Started Aug 10 07:25:43 PM PDT 24
Finished Aug 10 07:25:46 PM PDT 24
Peak memory 233132 kb
Host smart-50f6b008-1ef0-477f-b27e-08a47b107360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259679029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.259679029
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3153648685
Short name T921
Test name
Test status
Simulation time 24602516 ps
CPU time 0.74 seconds
Started Aug 10 07:25:56 PM PDT 24
Finished Aug 10 07:25:57 PM PDT 24
Peak memory 206172 kb
Host smart-e146c536-4e57-412f-96d5-a769914d4dfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153648685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3153648685
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1003613703
Short name T96
Test name
Test status
Simulation time 11794741477 ps
CPU time 10.55 seconds
Started Aug 10 07:25:51 PM PDT 24
Finished Aug 10 07:26:02 PM PDT 24
Peak memory 224904 kb
Host smart-b619b6fa-9eb5-4ce7-87a2-1f837f47a180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003613703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1003613703
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1332968128
Short name T348
Test name
Test status
Simulation time 13692338 ps
CPU time 0.75 seconds
Started Aug 10 07:25:41 PM PDT 24
Finished Aug 10 07:25:42 PM PDT 24
Peak memory 205984 kb
Host smart-1c558db0-eb74-478f-9cb7-7dfe72029304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332968128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1332968128
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1315750541
Short name T606
Test name
Test status
Simulation time 21778658 ps
CPU time 0.74 seconds
Started Aug 10 07:25:51 PM PDT 24
Finished Aug 10 07:25:52 PM PDT 24
Peak memory 216160 kb
Host smart-de03f37a-18fc-42f0-8a87-af341782552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315750541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1315750541
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.27085302
Short name T692
Test name
Test status
Simulation time 122211628395 ps
CPU time 218.22 seconds
Started Aug 10 07:25:53 PM PDT 24
Finished Aug 10 07:29:31 PM PDT 24
Peak memory 257816 kb
Host smart-3dc1c0c8-5741-4fa5-becd-0660f7b1a0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27085302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.27085302
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1588231311
Short name T753
Test name
Test status
Simulation time 5803310942 ps
CPU time 30.83 seconds
Started Aug 10 07:25:50 PM PDT 24
Finished Aug 10 07:26:22 PM PDT 24
Peak memory 250340 kb
Host smart-136f11e1-ce0a-4697-9ac9-8f2d759412ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588231311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1588231311
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4139972995
Short name T878
Test name
Test status
Simulation time 96095396 ps
CPU time 5.21 seconds
Started Aug 10 07:25:51 PM PDT 24
Finished Aug 10 07:25:56 PM PDT 24
Peak memory 233144 kb
Host smart-a5a56efe-7830-45d7-a90c-abeca24fb0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139972995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4139972995
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2203028445
Short name T583
Test name
Test status
Simulation time 6745308224 ps
CPU time 62.82 seconds
Started Aug 10 07:25:52 PM PDT 24
Finished Aug 10 07:26:55 PM PDT 24
Peak memory 249528 kb
Host smart-5ff23415-f61d-41f7-891a-62a97aa9da35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203028445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2203028445
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.470647353
Short name T347
Test name
Test status
Simulation time 2308595585 ps
CPU time 5.29 seconds
Started Aug 10 07:25:50 PM PDT 24
Finished Aug 10 07:25:55 PM PDT 24
Peak memory 224856 kb
Host smart-24c9fbbf-c701-47a0-ac1c-046635346fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470647353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.470647353
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.4088633485
Short name T674
Test name
Test status
Simulation time 596870883 ps
CPU time 2.06 seconds
Started Aug 10 07:25:49 PM PDT 24
Finished Aug 10 07:25:51 PM PDT 24
Peak memory 224568 kb
Host smart-e614c97f-5286-41ac-af55-18c92f824640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088633485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.4088633485
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3684764758
Short name T832
Test name
Test status
Simulation time 1467891269 ps
CPU time 13.29 seconds
Started Aug 10 07:25:51 PM PDT 24
Finished Aug 10 07:26:04 PM PDT 24
Peak memory 220800 kb
Host smart-060195eb-3445-4de0-94c6-fe7534d626ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3684764758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3684764758
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.243796258
Short name T511
Test name
Test status
Simulation time 15472580291 ps
CPU time 43.06 seconds
Started Aug 10 07:25:48 PM PDT 24
Finished Aug 10 07:26:31 PM PDT 24
Peak memory 249704 kb
Host smart-789f4435-b0c5-46d2-a640-727ccec7528d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243796258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.243796258
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.4073602976
Short name T353
Test name
Test status
Simulation time 245840633 ps
CPU time 1.22 seconds
Started Aug 10 07:25:44 PM PDT 24
Finished Aug 10 07:25:46 PM PDT 24
Peak memory 208320 kb
Host smart-8bfc2f16-233f-4067-9622-ae5dbb289159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073602976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4073602976
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1959552010
Short name T330
Test name
Test status
Simulation time 61767415 ps
CPU time 3.75 seconds
Started Aug 10 07:25:51 PM PDT 24
Finished Aug 10 07:25:55 PM PDT 24
Peak memory 208356 kb
Host smart-df001577-4c11-47c3-aeef-25ce9e4b95fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959552010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1959552010
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4204651824
Short name T491
Test name
Test status
Simulation time 54177887 ps
CPU time 0.97 seconds
Started Aug 10 07:25:50 PM PDT 24
Finished Aug 10 07:25:52 PM PDT 24
Peak memory 207252 kb
Host smart-3ef71604-023b-4930-9a67-4e1ccdc303a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204651824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4204651824
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1723111734
Short name T441
Test name
Test status
Simulation time 152764041 ps
CPU time 3.75 seconds
Started Aug 10 07:25:49 PM PDT 24
Finished Aug 10 07:25:53 PM PDT 24
Peak memory 233128 kb
Host smart-73bb6879-3660-483a-94ef-7c79e9d54a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723111734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1723111734
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1124031677
Short name T710
Test name
Test status
Simulation time 13231131 ps
CPU time 0.75 seconds
Started Aug 10 07:24:49 PM PDT 24
Finished Aug 10 07:24:49 PM PDT 24
Peak memory 205224 kb
Host smart-fbe8a985-d267-41fa-a70f-74da07873fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124031677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
124031677
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2698664033
Short name T738
Test name
Test status
Simulation time 249441267 ps
CPU time 3.93 seconds
Started Aug 10 07:24:41 PM PDT 24
Finished Aug 10 07:24:45 PM PDT 24
Peak memory 224868 kb
Host smart-c4769033-60c9-4270-888e-1379d37c5f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698664033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2698664033
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2394957584
Short name T723
Test name
Test status
Simulation time 86739265 ps
CPU time 0.79 seconds
Started Aug 10 07:24:44 PM PDT 24
Finished Aug 10 07:24:45 PM PDT 24
Peak memory 206944 kb
Host smart-8fdfaf7d-3cda-4163-8cc6-409b09d3a8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394957584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2394957584
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1638550481
Short name T37
Test name
Test status
Simulation time 2570247853 ps
CPU time 46.63 seconds
Started Aug 10 07:24:45 PM PDT 24
Finished Aug 10 07:25:32 PM PDT 24
Peak memory 249916 kb
Host smart-4dcc9801-44e5-40a3-9e8f-a1066d3f983a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638550481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1638550481
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1782841565
Short name T302
Test name
Test status
Simulation time 4765738412 ps
CPU time 49.02 seconds
Started Aug 10 07:24:46 PM PDT 24
Finished Aug 10 07:25:36 PM PDT 24
Peak memory 254684 kb
Host smart-93938a11-b386-4f86-aec5-463d2d3af284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782841565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1782841565
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.765871613
Short name T757
Test name
Test status
Simulation time 2070073979 ps
CPU time 7.51 seconds
Started Aug 10 07:24:41 PM PDT 24
Finished Aug 10 07:24:49 PM PDT 24
Peak memory 241372 kb
Host smart-5a386dc5-ddc1-4560-b4aa-aaf3cb84853c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765871613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.765871613
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1197652425
Short name T665
Test name
Test status
Simulation time 116818082896 ps
CPU time 220.52 seconds
Started Aug 10 07:24:44 PM PDT 24
Finished Aug 10 07:28:25 PM PDT 24
Peak memory 250680 kb
Host smart-64e5c3cd-18fe-4830-a501-baf1a5232c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197652425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1197652425
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.306157359
Short name T673
Test name
Test status
Simulation time 319260915 ps
CPU time 3.98 seconds
Started Aug 10 07:24:45 PM PDT 24
Finished Aug 10 07:24:49 PM PDT 24
Peak memory 224896 kb
Host smart-8a03bc72-ebe3-4b44-80f7-fd853eea2f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306157359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.306157359
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3171952545
Short name T234
Test name
Test status
Simulation time 33212073129 ps
CPU time 90.87 seconds
Started Aug 10 07:24:47 PM PDT 24
Finished Aug 10 07:26:18 PM PDT 24
Peak memory 233224 kb
Host smart-02a18364-de0c-430d-9fb7-edcf3ae076d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171952545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3171952545
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.453088650
Short name T793
Test name
Test status
Simulation time 418426389 ps
CPU time 8.89 seconds
Started Aug 10 07:24:39 PM PDT 24
Finished Aug 10 07:24:48 PM PDT 24
Peak memory 239968 kb
Host smart-3a604969-0fc6-4d44-aae6-86cd5adb52fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453088650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
453088650
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3704105492
Short name T622
Test name
Test status
Simulation time 321099127 ps
CPU time 4.12 seconds
Started Aug 10 07:24:45 PM PDT 24
Finished Aug 10 07:24:49 PM PDT 24
Peak memory 224892 kb
Host smart-4ed5b8fb-206e-46d5-b8c5-48e770a8c32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704105492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3704105492
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3237927660
Short name T805
Test name
Test status
Simulation time 124902902 ps
CPU time 3.91 seconds
Started Aug 10 07:24:50 PM PDT 24
Finished Aug 10 07:24:54 PM PDT 24
Peak memory 222960 kb
Host smart-5aa96600-bf16-4738-8869-ed01bba7f668
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3237927660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3237927660
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1401225879
Short name T78
Test name
Test status
Simulation time 250922607 ps
CPU time 0.97 seconds
Started Aug 10 07:24:44 PM PDT 24
Finished Aug 10 07:24:45 PM PDT 24
Peak memory 236344 kb
Host smart-ebbb0644-07ff-4166-9b0b-dc388973879a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401225879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1401225879
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.879991032
Short name T707
Test name
Test status
Simulation time 12594689963 ps
CPU time 65.14 seconds
Started Aug 10 07:24:46 PM PDT 24
Finished Aug 10 07:25:51 PM PDT 24
Peak memory 266004 kb
Host smart-0186c6db-15e9-4248-b9a1-ad17df7e7bfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879991032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.879991032
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1915171604
Short name T531
Test name
Test status
Simulation time 54200061844 ps
CPU time 40.57 seconds
Started Aug 10 07:24:45 PM PDT 24
Finished Aug 10 07:25:26 PM PDT 24
Peak memory 221144 kb
Host smart-b73b1c76-a06e-4013-b040-3b972a4ff7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915171604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1915171604
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2840824137
Short name T338
Test name
Test status
Simulation time 228865401 ps
CPU time 1.87 seconds
Started Aug 10 07:24:44 PM PDT 24
Finished Aug 10 07:24:46 PM PDT 24
Peak memory 216700 kb
Host smart-ee502a81-91c7-46d8-9d7e-d623c0a8b8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840824137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2840824137
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2765881256
Short name T425
Test name
Test status
Simulation time 33886716 ps
CPU time 0.9 seconds
Started Aug 10 07:24:44 PM PDT 24
Finished Aug 10 07:24:45 PM PDT 24
Peak memory 207436 kb
Host smart-f6d2e22a-1532-4ba9-9906-aaec8bdb4046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765881256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2765881256
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4162295027
Short name T630
Test name
Test status
Simulation time 356966517 ps
CPU time 1 seconds
Started Aug 10 07:24:41 PM PDT 24
Finished Aug 10 07:24:43 PM PDT 24
Peak memory 207356 kb
Host smart-bcfbfad7-c4a0-470f-a6f6-97dec83b78b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162295027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4162295027
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2895955158
Short name T249
Test name
Test status
Simulation time 12840288998 ps
CPU time 9.38 seconds
Started Aug 10 07:24:39 PM PDT 24
Finished Aug 10 07:24:49 PM PDT 24
Peak memory 230344 kb
Host smart-718f20bb-b805-489b-8875-597dd314d610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895955158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2895955158
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2463440896
Short name T988
Test name
Test status
Simulation time 14512131 ps
CPU time 0.76 seconds
Started Aug 10 07:25:52 PM PDT 24
Finished Aug 10 07:25:53 PM PDT 24
Peak memory 205800 kb
Host smart-a4119328-e1c8-444a-aaa4-c3b8e343f4ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463440896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2463440896
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1646141048
Short name T93
Test name
Test status
Simulation time 2103158434 ps
CPU time 6.96 seconds
Started Aug 10 07:25:49 PM PDT 24
Finished Aug 10 07:25:56 PM PDT 24
Peak memory 233136 kb
Host smart-a52b1a62-29a6-428a-9a5e-7f35a1e8b594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646141048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1646141048
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2544921552
Short name T946
Test name
Test status
Simulation time 41578964 ps
CPU time 0.77 seconds
Started Aug 10 07:25:55 PM PDT 24
Finished Aug 10 07:25:56 PM PDT 24
Peak memory 206984 kb
Host smart-ead387cb-3d1b-4859-9a75-e64a2547b4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544921552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2544921552
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3820977589
Short name T285
Test name
Test status
Simulation time 36593531371 ps
CPU time 204.14 seconds
Started Aug 10 07:25:48 PM PDT 24
Finished Aug 10 07:29:13 PM PDT 24
Peak memory 256032 kb
Host smart-31a3349d-56bb-4b49-b0f2-fef56df1dbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820977589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3820977589
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.528752550
Short name T891
Test name
Test status
Simulation time 5786284814 ps
CPU time 38.2 seconds
Started Aug 10 07:25:53 PM PDT 24
Finished Aug 10 07:26:31 PM PDT 24
Peak memory 218184 kb
Host smart-77825b49-b0ea-4f37-8da3-999364898ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528752550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.528752550
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2786384931
Short name T142
Test name
Test status
Simulation time 5023850108 ps
CPU time 49.17 seconds
Started Aug 10 07:25:50 PM PDT 24
Finished Aug 10 07:26:40 PM PDT 24
Peak memory 256572 kb
Host smart-81b82ef8-3093-4391-b779-4c7bfcc34f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786384931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2786384931
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4213636590
Short name T625
Test name
Test status
Simulation time 419152216 ps
CPU time 7.89 seconds
Started Aug 10 07:25:50 PM PDT 24
Finished Aug 10 07:25:58 PM PDT 24
Peak memory 233208 kb
Host smart-a0f0dd55-f6ed-4c89-86a4-ce826d3b46e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213636590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4213636590
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2758256120
Short name T162
Test name
Test status
Simulation time 1116498328 ps
CPU time 14.04 seconds
Started Aug 10 07:25:49 PM PDT 24
Finished Aug 10 07:26:03 PM PDT 24
Peak memory 249420 kb
Host smart-57dbcb5d-81da-4dc4-b51a-0724db13b6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758256120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2758256120
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.96634825
Short name T644
Test name
Test status
Simulation time 13330320576 ps
CPU time 15.78 seconds
Started Aug 10 07:25:57 PM PDT 24
Finished Aug 10 07:26:13 PM PDT 24
Peak memory 233072 kb
Host smart-83cbb269-6082-400f-a8da-1d8a9c64ea27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96634825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.96634825
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1878039216
Short name T273
Test name
Test status
Simulation time 2390645185 ps
CPU time 5.26 seconds
Started Aug 10 07:25:50 PM PDT 24
Finished Aug 10 07:25:56 PM PDT 24
Peak memory 233228 kb
Host smart-17ae35a5-5b0b-4e7f-a89d-6853670b6a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878039216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1878039216
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2068870170
Short name T614
Test name
Test status
Simulation time 357938488 ps
CPU time 4.11 seconds
Started Aug 10 07:25:51 PM PDT 24
Finished Aug 10 07:25:55 PM PDT 24
Peak memory 220488 kb
Host smart-286396b0-e9be-4090-8a53-aa02d81b268c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2068870170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2068870170
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.567545288
Short name T927
Test name
Test status
Simulation time 11136861051 ps
CPU time 34.4 seconds
Started Aug 10 07:25:48 PM PDT 24
Finished Aug 10 07:26:23 PM PDT 24
Peak memory 216684 kb
Host smart-cb3fca94-ad8d-457b-969f-b299a27e1748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567545288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.567545288
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4099609243
Short name T855
Test name
Test status
Simulation time 9230243323 ps
CPU time 24.8 seconds
Started Aug 10 07:25:49 PM PDT 24
Finished Aug 10 07:26:14 PM PDT 24
Peak memory 216712 kb
Host smart-be85036b-df7c-4930-ac85-6c3c24b26d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099609243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4099609243
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1477998938
Short name T830
Test name
Test status
Simulation time 149279324 ps
CPU time 2.81 seconds
Started Aug 10 07:25:49 PM PDT 24
Finished Aug 10 07:25:52 PM PDT 24
Peak memory 216716 kb
Host smart-4e1f60d3-07ca-4346-beee-9e29eff51932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477998938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1477998938
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.4242262463
Short name T672
Test name
Test status
Simulation time 348214908 ps
CPU time 0.94 seconds
Started Aug 10 07:25:52 PM PDT 24
Finished Aug 10 07:25:53 PM PDT 24
Peak memory 206292 kb
Host smart-e6c527f2-c189-4ac0-a4e3-7d8f7a993298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242262463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4242262463
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.372040963
Short name T497
Test name
Test status
Simulation time 260459850 ps
CPU time 3.67 seconds
Started Aug 10 07:25:52 PM PDT 24
Finished Aug 10 07:25:56 PM PDT 24
Peak memory 233168 kb
Host smart-62bf08fa-f024-4159-9a16-5748c4dec002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372040963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.372040963
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3260376720
Short name T576
Test name
Test status
Simulation time 18458843 ps
CPU time 0.72 seconds
Started Aug 10 07:25:58 PM PDT 24
Finished Aug 10 07:25:59 PM PDT 24
Peak memory 205848 kb
Host smart-802b0986-c725-4293-8cdf-63c41d6ae7dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260376720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3260376720
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3840575831
Short name T906
Test name
Test status
Simulation time 80210081 ps
CPU time 2.4 seconds
Started Aug 10 07:25:51 PM PDT 24
Finished Aug 10 07:25:54 PM PDT 24
Peak memory 224908 kb
Host smart-d713d8e2-8b37-4575-aa5f-eca3db0a0e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840575831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3840575831
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2348340220
Short name T379
Test name
Test status
Simulation time 20084482 ps
CPU time 0.83 seconds
Started Aug 10 07:25:50 PM PDT 24
Finished Aug 10 07:25:51 PM PDT 24
Peak memory 206980 kb
Host smart-b7858243-2317-461f-bec1-6ad26fda9e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348340220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2348340220
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2344116630
Short name T898
Test name
Test status
Simulation time 5753767681 ps
CPU time 65.93 seconds
Started Aug 10 07:26:01 PM PDT 24
Finished Aug 10 07:27:07 PM PDT 24
Peak memory 249548 kb
Host smart-0a34b651-0cd5-4c17-ae38-662e681e6e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344116630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2344116630
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.51437369
Short name T135
Test name
Test status
Simulation time 142978659179 ps
CPU time 509.68 seconds
Started Aug 10 07:25:58 PM PDT 24
Finished Aug 10 07:34:28 PM PDT 24
Peak memory 273520 kb
Host smart-34dc88bc-3865-479f-b505-1dca275393c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51437369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.51437369
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2942452220
Short name T137
Test name
Test status
Simulation time 2293297877 ps
CPU time 52.72 seconds
Started Aug 10 07:26:06 PM PDT 24
Finished Aug 10 07:26:59 PM PDT 24
Peak memory 249640 kb
Host smart-731cabef-1c27-4159-8abf-7b47c2665917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942452220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2942452220
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1858386295
Short name T535
Test name
Test status
Simulation time 6235717363 ps
CPU time 16.1 seconds
Started Aug 10 07:25:51 PM PDT 24
Finished Aug 10 07:26:07 PM PDT 24
Peak memory 233464 kb
Host smart-c0eae366-38ff-4f96-b948-513a032abf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858386295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1858386295
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.252234780
Short name T240
Test name
Test status
Simulation time 112564302831 ps
CPU time 98.26 seconds
Started Aug 10 07:25:57 PM PDT 24
Finished Aug 10 07:27:36 PM PDT 24
Peak memory 241412 kb
Host smart-d6ed8c23-2324-497a-a553-6a147c03099c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252234780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.252234780
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2886348405
Short name T607
Test name
Test status
Simulation time 27910816288 ps
CPU time 38.02 seconds
Started Aug 10 07:25:52 PM PDT 24
Finished Aug 10 07:26:30 PM PDT 24
Peak memory 224952 kb
Host smart-54561b04-7906-42fe-8a65-aff94dd099e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886348405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2886348405
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1040814324
Short name T820
Test name
Test status
Simulation time 1128081688 ps
CPU time 14.88 seconds
Started Aug 10 07:25:53 PM PDT 24
Finished Aug 10 07:26:08 PM PDT 24
Peak memory 239236 kb
Host smart-1822cd68-fc80-4108-ae79-1c00425c6e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040814324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1040814324
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3276959208
Short name T268
Test name
Test status
Simulation time 87972421 ps
CPU time 3 seconds
Started Aug 10 07:25:56 PM PDT 24
Finished Aug 10 07:25:59 PM PDT 24
Peak memory 233144 kb
Host smart-c3578214-f7fc-4e93-8e98-a5c68f7a34ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276959208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3276959208
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1215048062
Short name T806
Test name
Test status
Simulation time 4683176740 ps
CPU time 15.52 seconds
Started Aug 10 07:25:52 PM PDT 24
Finished Aug 10 07:26:07 PM PDT 24
Peak memory 233164 kb
Host smart-bf963d43-2b8b-45cb-b742-3381ccae482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215048062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1215048062
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.407438618
Short name T634
Test name
Test status
Simulation time 3583193614 ps
CPU time 10.85 seconds
Started Aug 10 07:25:59 PM PDT 24
Finished Aug 10 07:26:10 PM PDT 24
Peak memory 222592 kb
Host smart-a30bcd3b-7ecf-4da1-82ab-fab6d5e0e02b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=407438618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.407438618
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3067835731
Short name T939
Test name
Test status
Simulation time 5362256294 ps
CPU time 9.78 seconds
Started Aug 10 07:25:58 PM PDT 24
Finished Aug 10 07:26:08 PM PDT 24
Peak memory 224932 kb
Host smart-29dd4364-6913-43e1-a255-c42e7d7d2c3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067835731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3067835731
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3560710525
Short name T39
Test name
Test status
Simulation time 11156465 ps
CPU time 0.78 seconds
Started Aug 10 07:25:52 PM PDT 24
Finished Aug 10 07:25:53 PM PDT 24
Peak memory 206144 kb
Host smart-f4362381-fd86-4c69-963a-217e29d9421a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560710525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3560710525
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.243121763
Short name T990
Test name
Test status
Simulation time 2571597157 ps
CPU time 6.17 seconds
Started Aug 10 07:25:51 PM PDT 24
Finished Aug 10 07:25:57 PM PDT 24
Peak memory 216624 kb
Host smart-a493f1dd-2b42-4265-94a4-bde5ead4477b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243121763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.243121763
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.184547542
Short name T1003
Test name
Test status
Simulation time 221451114 ps
CPU time 2.06 seconds
Started Aug 10 07:25:55 PM PDT 24
Finished Aug 10 07:25:58 PM PDT 24
Peak memory 216628 kb
Host smart-7e74456c-51cd-45ab-ada5-012664e58e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184547542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.184547542
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1302666568
Short name T351
Test name
Test status
Simulation time 67113682 ps
CPU time 0.9 seconds
Started Aug 10 07:25:51 PM PDT 24
Finished Aug 10 07:25:52 PM PDT 24
Peak memory 206260 kb
Host smart-c493d518-df82-4265-b4e9-c5a7f31e01cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302666568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1302666568
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.806160511
Short name T26
Test name
Test status
Simulation time 143042509 ps
CPU time 2.5 seconds
Started Aug 10 07:25:53 PM PDT 24
Finished Aug 10 07:25:56 PM PDT 24
Peak memory 224612 kb
Host smart-6de4c860-c834-4ce4-8517-9d1f2c7e5c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806160511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.806160511
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2590982115
Short name T69
Test name
Test status
Simulation time 26596080 ps
CPU time 0.72 seconds
Started Aug 10 07:26:02 PM PDT 24
Finished Aug 10 07:26:03 PM PDT 24
Peak memory 205832 kb
Host smart-a517e2d8-ea39-4ad3-a2b8-d5691ac3991c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590982115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2590982115
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2769840464
Short name T656
Test name
Test status
Simulation time 256479928 ps
CPU time 5.09 seconds
Started Aug 10 07:26:02 PM PDT 24
Finished Aug 10 07:26:07 PM PDT 24
Peak memory 233092 kb
Host smart-90d2be87-da98-439f-95e4-2f94f1ef7635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769840464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2769840464
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3024295617
Short name T536
Test name
Test status
Simulation time 33897230 ps
CPU time 0.76 seconds
Started Aug 10 07:26:01 PM PDT 24
Finished Aug 10 07:26:02 PM PDT 24
Peak memory 206916 kb
Host smart-f378aa79-a9e0-4ed0-95c8-3201c4141695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024295617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3024295617
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.307515384
Short name T226
Test name
Test status
Simulation time 12411682275 ps
CPU time 34.65 seconds
Started Aug 10 07:26:07 PM PDT 24
Finished Aug 10 07:26:41 PM PDT 24
Peak memory 250908 kb
Host smart-7f2c90cd-5e12-45a5-a706-3086aa6e1006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307515384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.307515384
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3370826861
Short name T197
Test name
Test status
Simulation time 22566824100 ps
CPU time 154.3 seconds
Started Aug 10 07:26:05 PM PDT 24
Finished Aug 10 07:28:40 PM PDT 24
Peak memory 272340 kb
Host smart-5b1d599b-452c-4af4-ae7b-c74b5426d64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370826861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3370826861
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.84940034
Short name T202
Test name
Test status
Simulation time 2285534024 ps
CPU time 62.25 seconds
Started Aug 10 07:26:06 PM PDT 24
Finished Aug 10 07:27:09 PM PDT 24
Peak memory 255044 kb
Host smart-0a4e5985-ef26-407d-909c-b56e5efcd540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84940034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.84940034
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.581412206
Short name T857
Test name
Test status
Simulation time 6840700075 ps
CPU time 50.61 seconds
Started Aug 10 07:25:58 PM PDT 24
Finished Aug 10 07:26:49 PM PDT 24
Peak memory 249588 kb
Host smart-bf2deefb-d725-46dd-98cf-ea097b3d1816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581412206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.581412206
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2043199200
Short name T363
Test name
Test status
Simulation time 1168384992 ps
CPU time 3.96 seconds
Started Aug 10 07:25:58 PM PDT 24
Finished Aug 10 07:26:02 PM PDT 24
Peak memory 224820 kb
Host smart-60a779ce-e3c4-40fb-b031-0c80ec9ed762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043199200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2043199200
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3903027753
Short name T478
Test name
Test status
Simulation time 305168360 ps
CPU time 9.53 seconds
Started Aug 10 07:26:00 PM PDT 24
Finished Aug 10 07:26:09 PM PDT 24
Peak memory 233084 kb
Host smart-02e47afb-c29d-4408-acd1-8bcc969bd38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903027753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3903027753
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.55531339
Short name T223
Test name
Test status
Simulation time 4380430045 ps
CPU time 21.89 seconds
Started Aug 10 07:26:05 PM PDT 24
Finished Aug 10 07:26:27 PM PDT 24
Peak memory 235004 kb
Host smart-f8d5018b-9bbb-48d3-ac80-61cfac7cb5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55531339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.55531339
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1913869160
Short name T533
Test name
Test status
Simulation time 11438308195 ps
CPU time 5.22 seconds
Started Aug 10 07:25:58 PM PDT 24
Finished Aug 10 07:26:03 PM PDT 24
Peak memory 225040 kb
Host smart-e1aff5e8-315e-4435-95d2-2b5fc52ba9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913869160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1913869160
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1612215087
Short name T45
Test name
Test status
Simulation time 4947736129 ps
CPU time 9.8 seconds
Started Aug 10 07:25:57 PM PDT 24
Finished Aug 10 07:26:07 PM PDT 24
Peak memory 223584 kb
Host smart-1a28d553-b431-440f-a710-77bf85f1f4f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1612215087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1612215087
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2027390628
Short name T328
Test name
Test status
Simulation time 13569114800 ps
CPU time 151.96 seconds
Started Aug 10 07:26:02 PM PDT 24
Finished Aug 10 07:28:34 PM PDT 24
Peak memory 266008 kb
Host smart-dd750f3c-e877-4ba3-a5aa-a9c797d6c00c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027390628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2027390628
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2849285819
Short name T739
Test name
Test status
Simulation time 8472342970 ps
CPU time 18.62 seconds
Started Aug 10 07:26:05 PM PDT 24
Finished Aug 10 07:26:24 PM PDT 24
Peak memory 216756 kb
Host smart-8e55420f-365c-43b5-abd4-fee5981dc865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849285819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2849285819
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3553693632
Short name T649
Test name
Test status
Simulation time 326450642 ps
CPU time 1.56 seconds
Started Aug 10 07:25:58 PM PDT 24
Finished Aug 10 07:26:00 PM PDT 24
Peak memory 208376 kb
Host smart-1072e1f2-2c88-4ce2-9a87-45a3005ee3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553693632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3553693632
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.741180109
Short name T318
Test name
Test status
Simulation time 856883715 ps
CPU time 3.92 seconds
Started Aug 10 07:26:06 PM PDT 24
Finished Aug 10 07:26:10 PM PDT 24
Peak memory 216672 kb
Host smart-835bbc0c-4420-4992-93de-45ea80f623a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741180109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.741180109
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.4032020557
Short name T936
Test name
Test status
Simulation time 117983283 ps
CPU time 0.77 seconds
Started Aug 10 07:25:58 PM PDT 24
Finished Aug 10 07:25:59 PM PDT 24
Peak memory 206560 kb
Host smart-49ba7e86-ddbb-49c1-9312-5d737a9cdc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032020557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.4032020557
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.853283311
Short name T594
Test name
Test status
Simulation time 1036131867 ps
CPU time 3.93 seconds
Started Aug 10 07:26:00 PM PDT 24
Finished Aug 10 07:26:04 PM PDT 24
Peak memory 233092 kb
Host smart-9449a208-2c10-49e7-ad0b-0930aed8bfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853283311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.853283311
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1783831120
Short name T518
Test name
Test status
Simulation time 30438783 ps
CPU time 0.79 seconds
Started Aug 10 07:26:07 PM PDT 24
Finished Aug 10 07:26:08 PM PDT 24
Peak memory 205896 kb
Host smart-bc59c808-a376-4140-8dc7-6a44cc1a69e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783831120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1783831120
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.30946317
Short name T880
Test name
Test status
Simulation time 132666247 ps
CPU time 4.28 seconds
Started Aug 10 07:26:08 PM PDT 24
Finished Aug 10 07:26:12 PM PDT 24
Peak memory 224860 kb
Host smart-4739e0f6-0746-4002-84c1-6aec11acef52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30946317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.30946317
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1081827460
Short name T418
Test name
Test status
Simulation time 21444751 ps
CPU time 0.79 seconds
Started Aug 10 07:26:03 PM PDT 24
Finished Aug 10 07:26:04 PM PDT 24
Peak memory 206968 kb
Host smart-83e19a0e-656b-4f00-a1f1-4889e6e027be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081827460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1081827460
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.385789793
Short name T725
Test name
Test status
Simulation time 55762326 ps
CPU time 0.76 seconds
Started Aug 10 07:26:12 PM PDT 24
Finished Aug 10 07:26:13 PM PDT 24
Peak memory 216100 kb
Host smart-58c81d81-de69-4af4-8d00-16b1fddab467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385789793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.385789793
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2660390943
Short name T695
Test name
Test status
Simulation time 4221199872 ps
CPU time 79.93 seconds
Started Aug 10 07:26:07 PM PDT 24
Finished Aug 10 07:27:27 PM PDT 24
Peak memory 249756 kb
Host smart-53aecb66-0292-479c-94bc-56a9f02b2dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660390943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2660390943
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2556919522
Short name T786
Test name
Test status
Simulation time 78086006958 ps
CPU time 383.05 seconds
Started Aug 10 07:26:05 PM PDT 24
Finished Aug 10 07:32:28 PM PDT 24
Peak memory 265816 kb
Host smart-d561f953-7e6b-4181-92c3-94b1b517b911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556919522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2556919522
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3392381184
Short name T306
Test name
Test status
Simulation time 577239425 ps
CPU time 13.83 seconds
Started Aug 10 07:26:05 PM PDT 24
Finished Aug 10 07:26:19 PM PDT 24
Peak memory 233152 kb
Host smart-660eb55f-beb6-428e-b14b-89648f1ebe9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392381184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3392381184
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3987164150
Short name T94
Test name
Test status
Simulation time 171129696988 ps
CPU time 112.81 seconds
Started Aug 10 07:26:06 PM PDT 24
Finished Aug 10 07:27:59 PM PDT 24
Peak memory 249820 kb
Host smart-2048352a-16ac-4b5e-8bac-06c8eab10072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987164150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3987164150
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.306582995
Short name T920
Test name
Test status
Simulation time 1728884671 ps
CPU time 19.37 seconds
Started Aug 10 07:26:06 PM PDT 24
Finished Aug 10 07:26:25 PM PDT 24
Peak memory 233128 kb
Host smart-e55c5203-d9e9-4653-9fed-a32b7d94ff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306582995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.306582995
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3848212913
Short name T1011
Test name
Test status
Simulation time 252512705 ps
CPU time 5.91 seconds
Started Aug 10 07:26:07 PM PDT 24
Finished Aug 10 07:26:13 PM PDT 24
Peak memory 224916 kb
Host smart-76278169-a34e-47ec-a133-23133df3871e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848212913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3848212913
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1660303161
Short name T264
Test name
Test status
Simulation time 2711226965 ps
CPU time 9.78 seconds
Started Aug 10 07:26:18 PM PDT 24
Finished Aug 10 07:26:28 PM PDT 24
Peak memory 233176 kb
Host smart-ca3b00fe-9ed1-4bd3-aa62-0111c5d61e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660303161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1660303161
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1307902407
Short name T242
Test name
Test status
Simulation time 2633540038 ps
CPU time 7.21 seconds
Started Aug 10 07:26:06 PM PDT 24
Finished Aug 10 07:26:13 PM PDT 24
Peak memory 233220 kb
Host smart-d06ef953-4c4b-47a5-9dfd-68d9aa6317e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307902407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1307902407
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.766519427
Short name T779
Test name
Test status
Simulation time 600336732 ps
CPU time 4.21 seconds
Started Aug 10 07:26:05 PM PDT 24
Finished Aug 10 07:26:09 PM PDT 24
Peak memory 220932 kb
Host smart-86302a76-09a8-4b66-926c-71fcc2014b29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=766519427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.766519427
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1631329439
Short name T549
Test name
Test status
Simulation time 17498473167 ps
CPU time 47.44 seconds
Started Aug 10 07:26:05 PM PDT 24
Finished Aug 10 07:26:53 PM PDT 24
Peak memory 224852 kb
Host smart-f63415b1-1701-4be5-ab13-7c2c36bfd9f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631329439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1631329439
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.261576893
Short name T629
Test name
Test status
Simulation time 701816237 ps
CPU time 6.24 seconds
Started Aug 10 07:25:59 PM PDT 24
Finished Aug 10 07:26:05 PM PDT 24
Peak memory 216676 kb
Host smart-c2ef474e-4a15-4806-aba4-ba62f98cc645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261576893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.261576893
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3072325784
Short name T686
Test name
Test status
Simulation time 10946606311 ps
CPU time 13.51 seconds
Started Aug 10 07:26:02 PM PDT 24
Finished Aug 10 07:26:16 PM PDT 24
Peak memory 216716 kb
Host smart-25b0641a-a0a5-4f92-85cc-45f414da86ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072325784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3072325784
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2416311777
Short name T971
Test name
Test status
Simulation time 36159029 ps
CPU time 0.71 seconds
Started Aug 10 07:26:06 PM PDT 24
Finished Aug 10 07:26:07 PM PDT 24
Peak memory 205996 kb
Host smart-0773cb80-0dd5-47ca-8094-1c880e6d5c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416311777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2416311777
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1585824109
Short name T916
Test name
Test status
Simulation time 86313297 ps
CPU time 0.94 seconds
Started Aug 10 07:26:07 PM PDT 24
Finished Aug 10 07:26:08 PM PDT 24
Peak memory 206336 kb
Host smart-b50c1e39-3517-4aaa-8420-aa17c60f643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585824109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1585824109
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3753884019
Short name T953
Test name
Test status
Simulation time 3864910356 ps
CPU time 13.96 seconds
Started Aug 10 07:26:05 PM PDT 24
Finished Aug 10 07:26:19 PM PDT 24
Peak memory 225080 kb
Host smart-668e45fd-cdf4-414a-af00-917be0ed3a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753884019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3753884019
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3633640660
Short name T413
Test name
Test status
Simulation time 140141787 ps
CPU time 0.75 seconds
Started Aug 10 07:26:12 PM PDT 24
Finished Aug 10 07:26:13 PM PDT 24
Peak memory 205236 kb
Host smart-2ae6c303-938d-4911-8479-e05bd23b39ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633640660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3633640660
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.336247276
Short name T256
Test name
Test status
Simulation time 2701581853 ps
CPU time 26.12 seconds
Started Aug 10 07:26:05 PM PDT 24
Finished Aug 10 07:26:31 PM PDT 24
Peak memory 233160 kb
Host smart-772303f7-183a-4aa0-b2fc-a54877ba3a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336247276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.336247276
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1727755259
Short name T352
Test name
Test status
Simulation time 45955580 ps
CPU time 0.74 seconds
Started Aug 10 07:26:12 PM PDT 24
Finished Aug 10 07:26:13 PM PDT 24
Peak memory 206932 kb
Host smart-00cede10-afa0-458d-9bdf-4b0293de5f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727755259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1727755259
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3777635447
Short name T282
Test name
Test status
Simulation time 18808951783 ps
CPU time 155.45 seconds
Started Aug 10 07:26:04 PM PDT 24
Finished Aug 10 07:28:40 PM PDT 24
Peak memory 255584 kb
Host smart-af7a2767-16b9-476d-94ca-55c8f72f0ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777635447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3777635447
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3332523849
Short name T974
Test name
Test status
Simulation time 5171751323 ps
CPU time 63.37 seconds
Started Aug 10 07:26:07 PM PDT 24
Finished Aug 10 07:27:10 PM PDT 24
Peak memory 266664 kb
Host smart-291ee093-5b26-4cf1-befc-348ee76be1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332523849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3332523849
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3290933799
Short name T828
Test name
Test status
Simulation time 9561381242 ps
CPU time 63.04 seconds
Started Aug 10 07:26:08 PM PDT 24
Finished Aug 10 07:27:11 PM PDT 24
Peak memory 241036 kb
Host smart-f3e79721-ad7c-4bfa-a6b8-9f32e6342360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290933799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3290933799
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3247049064
Short name T795
Test name
Test status
Simulation time 316417626 ps
CPU time 4.52 seconds
Started Aug 10 07:26:07 PM PDT 24
Finished Aug 10 07:26:12 PM PDT 24
Peak memory 233116 kb
Host smart-15cb4fa2-4071-4788-845e-b74dc120ca02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247049064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3247049064
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2864703721
Short name T816
Test name
Test status
Simulation time 24783304252 ps
CPU time 28.05 seconds
Started Aug 10 07:26:07 PM PDT 24
Finished Aug 10 07:26:35 PM PDT 24
Peak memory 236568 kb
Host smart-7c4d0bf8-471d-49aa-b46b-49abd1070f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864703721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2864703721
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4105705001
Short name T887
Test name
Test status
Simulation time 237396619 ps
CPU time 2.9 seconds
Started Aug 10 07:26:07 PM PDT 24
Finished Aug 10 07:26:10 PM PDT 24
Peak memory 233200 kb
Host smart-d35df47c-321b-4d17-b90b-c3037b87be18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105705001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4105705001
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1642833466
Short name T752
Test name
Test status
Simulation time 7409396891 ps
CPU time 36.47 seconds
Started Aug 10 07:26:05 PM PDT 24
Finished Aug 10 07:26:42 PM PDT 24
Peak memory 240824 kb
Host smart-f873de10-3a48-4d36-87a5-079d9f0b7508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642833466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1642833466
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.886339329
Short name T59
Test name
Test status
Simulation time 1653007948 ps
CPU time 6.96 seconds
Started Aug 10 07:26:06 PM PDT 24
Finished Aug 10 07:26:13 PM PDT 24
Peak memory 224984 kb
Host smart-339f9334-d76f-4088-8bcb-0565b83d2e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886339329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.886339329
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2896901561
Short name T823
Test name
Test status
Simulation time 399731552 ps
CPU time 7.5 seconds
Started Aug 10 07:26:07 PM PDT 24
Finished Aug 10 07:26:14 PM PDT 24
Peak memory 250484 kb
Host smart-ba649411-aaf2-493a-bffb-5ddb4472642a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896901561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2896901561
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1467808527
Short name T469
Test name
Test status
Simulation time 1062801571 ps
CPU time 7.06 seconds
Started Aug 10 07:26:07 PM PDT 24
Finished Aug 10 07:26:14 PM PDT 24
Peak memory 221944 kb
Host smart-b7204c8f-ab60-4c54-98a5-74ba2d25f370
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1467808527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1467808527
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1736492531
Short name T586
Test name
Test status
Simulation time 256342498507 ps
CPU time 98.54 seconds
Started Aug 10 07:26:08 PM PDT 24
Finished Aug 10 07:27:47 PM PDT 24
Peak memory 241632 kb
Host smart-630138d3-6f5a-4e40-8640-02972dd0fc01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736492531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1736492531
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3717967195
Short name T539
Test name
Test status
Simulation time 5667674517 ps
CPU time 30.34 seconds
Started Aug 10 07:26:08 PM PDT 24
Finished Aug 10 07:26:38 PM PDT 24
Peak memory 216736 kb
Host smart-0bf5932c-60c6-499c-ba28-ee6ba5573b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717967195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3717967195
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3253338638
Short name T332
Test name
Test status
Simulation time 946932041 ps
CPU time 3.49 seconds
Started Aug 10 07:26:12 PM PDT 24
Finished Aug 10 07:26:15 PM PDT 24
Peak memory 216608 kb
Host smart-a5cab41a-1f00-48e9-8af4-0afde78fc97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253338638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3253338638
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3112903459
Short name T859
Test name
Test status
Simulation time 55082924 ps
CPU time 0.9 seconds
Started Aug 10 07:26:06 PM PDT 24
Finished Aug 10 07:26:07 PM PDT 24
Peak memory 206396 kb
Host smart-5855e884-ae56-4965-8f53-3976593f6394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112903459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3112903459
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1616701838
Short name T437
Test name
Test status
Simulation time 33084723 ps
CPU time 0.79 seconds
Started Aug 10 07:26:05 PM PDT 24
Finished Aug 10 07:26:05 PM PDT 24
Peak memory 206392 kb
Host smart-5bb8fd64-0a27-4487-a766-a78929850c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616701838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1616701838
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3823152188
Short name T241
Test name
Test status
Simulation time 1561221665 ps
CPU time 5.86 seconds
Started Aug 10 07:26:12 PM PDT 24
Finished Aug 10 07:26:18 PM PDT 24
Peak memory 224900 kb
Host smart-546407c4-108f-4537-82a2-dce8b06f397e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823152188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3823152188
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.935521261
Short name T575
Test name
Test status
Simulation time 11334039 ps
CPU time 0.73 seconds
Started Aug 10 07:26:14 PM PDT 24
Finished Aug 10 07:26:15 PM PDT 24
Peak memory 205336 kb
Host smart-66aa3776-5365-44e9-9243-18cc2cb5acc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935521261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.935521261
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2750224291
Short name T246
Test name
Test status
Simulation time 2665664747 ps
CPU time 11.41 seconds
Started Aug 10 07:26:14 PM PDT 24
Finished Aug 10 07:26:26 PM PDT 24
Peak memory 224984 kb
Host smart-b6ab331b-962e-4e84-847c-85f8c1f0047f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750224291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2750224291
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1279903554
Short name T858
Test name
Test status
Simulation time 39342039 ps
CPU time 0.82 seconds
Started Aug 10 07:26:07 PM PDT 24
Finished Aug 10 07:26:08 PM PDT 24
Peak memory 206304 kb
Host smart-b13fce01-e9d6-4051-acf5-26467d6636d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279903554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1279903554
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2214420924
Short name T224
Test name
Test status
Simulation time 14874002808 ps
CPU time 70.87 seconds
Started Aug 10 07:26:12 PM PDT 24
Finished Aug 10 07:27:23 PM PDT 24
Peak memory 241280 kb
Host smart-650e6a3b-bbc7-43bb-b101-217995f75852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214420924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2214420924
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.717976004
Short name T52
Test name
Test status
Simulation time 33025228571 ps
CPU time 227.04 seconds
Started Aug 10 07:26:12 PM PDT 24
Finished Aug 10 07:29:59 PM PDT 24
Peak memory 251720 kb
Host smart-9f39b5cd-8ab1-4eb9-8acc-7a4f46730903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717976004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.717976004
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1368551955
Short name T187
Test name
Test status
Simulation time 21327107265 ps
CPU time 194.8 seconds
Started Aug 10 07:26:13 PM PDT 24
Finished Aug 10 07:29:27 PM PDT 24
Peak memory 249668 kb
Host smart-a937258f-aee1-4042-999e-74d8e91ad8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368551955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1368551955
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2036782994
Short name T1008
Test name
Test status
Simulation time 393585469 ps
CPU time 4.39 seconds
Started Aug 10 07:26:13 PM PDT 24
Finished Aug 10 07:26:17 PM PDT 24
Peak memory 233104 kb
Host smart-a8007f5c-2d6e-4075-944e-a274afde5357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036782994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2036782994
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.4140744684
Short name T817
Test name
Test status
Simulation time 33513858490 ps
CPU time 66.83 seconds
Started Aug 10 07:26:13 PM PDT 24
Finished Aug 10 07:27:20 PM PDT 24
Peak memory 254876 kb
Host smart-27327f01-778b-4c1c-9b82-b5c6572582cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140744684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.4140744684
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1619936935
Short name T721
Test name
Test status
Simulation time 1707224519 ps
CPU time 19.5 seconds
Started Aug 10 07:26:13 PM PDT 24
Finished Aug 10 07:26:32 PM PDT 24
Peak memory 224816 kb
Host smart-7d167f35-27b4-4c9b-8d82-e3c1cb2e89c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619936935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1619936935
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1960914802
Short name T464
Test name
Test status
Simulation time 926944533 ps
CPU time 10.71 seconds
Started Aug 10 07:26:13 PM PDT 24
Finished Aug 10 07:26:24 PM PDT 24
Peak memory 239960 kb
Host smart-d4a654f5-0f55-407f-91dc-19ac8f908c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960914802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1960914802
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2180249440
Short name T618
Test name
Test status
Simulation time 554792403 ps
CPU time 2.77 seconds
Started Aug 10 07:26:13 PM PDT 24
Finished Aug 10 07:26:16 PM PDT 24
Peak memory 233140 kb
Host smart-5224962c-ec41-4f49-87e9-ca0444693c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180249440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2180249440
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.16863795
Short name T915
Test name
Test status
Simulation time 1535048630 ps
CPU time 2.66 seconds
Started Aug 10 07:26:12 PM PDT 24
Finished Aug 10 07:26:15 PM PDT 24
Peak memory 224944 kb
Host smart-6c199d22-1751-4c09-86e8-87eda876946e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16863795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.16863795
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3696159043
Short name T434
Test name
Test status
Simulation time 259820646 ps
CPU time 6.21 seconds
Started Aug 10 07:26:16 PM PDT 24
Finished Aug 10 07:26:22 PM PDT 24
Peak memory 219716 kb
Host smart-5235ecba-2e2c-4781-ad21-28d09fec01a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3696159043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3696159043
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2431622744
Short name T633
Test name
Test status
Simulation time 39279202 ps
CPU time 0.96 seconds
Started Aug 10 07:26:15 PM PDT 24
Finished Aug 10 07:26:16 PM PDT 24
Peak memory 206976 kb
Host smart-e6250cc3-641a-46a2-8504-5641b4062237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431622744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2431622744
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1944786802
Short name T324
Test name
Test status
Simulation time 11075288403 ps
CPU time 55.52 seconds
Started Aug 10 07:26:08 PM PDT 24
Finished Aug 10 07:27:04 PM PDT 24
Peak memory 216796 kb
Host smart-f58e202f-a15c-4abd-9885-d2ee5c742505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944786802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1944786802
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1854663903
Short name T647
Test name
Test status
Simulation time 13996271662 ps
CPU time 9.69 seconds
Started Aug 10 07:26:06 PM PDT 24
Finished Aug 10 07:26:16 PM PDT 24
Peak memory 216660 kb
Host smart-5bbc0de9-7613-47a7-bf7e-dd61abd38fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854663903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1854663903
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1110290403
Short name T592
Test name
Test status
Simulation time 12258483 ps
CPU time 0.69 seconds
Started Aug 10 07:26:13 PM PDT 24
Finished Aug 10 07:26:14 PM PDT 24
Peak memory 206100 kb
Host smart-d3e69ed5-8ccc-4e56-9e4b-2c882025009e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110290403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1110290403
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.487282011
Short name T773
Test name
Test status
Simulation time 188808070 ps
CPU time 0.97 seconds
Started Aug 10 07:26:05 PM PDT 24
Finished Aug 10 07:26:06 PM PDT 24
Peak memory 206292 kb
Host smart-cbce6a23-8d87-40ef-8b34-2f6a2ff99a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487282011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.487282011
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2626728370
Short name T375
Test name
Test status
Simulation time 426102330 ps
CPU time 4.56 seconds
Started Aug 10 07:26:14 PM PDT 24
Finished Aug 10 07:26:18 PM PDT 24
Peak memory 224896 kb
Host smart-4dbe929f-ec33-4c37-a254-6e490f540f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626728370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2626728370
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.280227952
Short name T71
Test name
Test status
Simulation time 66490087 ps
CPU time 0.73 seconds
Started Aug 10 07:26:25 PM PDT 24
Finished Aug 10 07:26:26 PM PDT 24
Peak memory 205324 kb
Host smart-d506c11a-9591-4ed9-8e63-c0c5af0d7e5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280227952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.280227952
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2558756970
Short name T893
Test name
Test status
Simulation time 1062172738 ps
CPU time 7.78 seconds
Started Aug 10 07:26:13 PM PDT 24
Finished Aug 10 07:26:21 PM PDT 24
Peak memory 224940 kb
Host smart-31c3e8dc-2f28-4844-bf8a-a59bba1a62ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558756970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2558756970
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1153357879
Short name T417
Test name
Test status
Simulation time 16101601 ps
CPU time 0.75 seconds
Started Aug 10 07:26:13 PM PDT 24
Finished Aug 10 07:26:13 PM PDT 24
Peak memory 207420 kb
Host smart-0cdfc332-d3e9-4534-acc8-438c9a6db6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153357879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1153357879
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2848075031
Short name T1006
Test name
Test status
Simulation time 3793487339 ps
CPU time 23.39 seconds
Started Aug 10 07:26:22 PM PDT 24
Finished Aug 10 07:26:46 PM PDT 24
Peak memory 224996 kb
Host smart-f8335b10-f351-4402-abb5-036066e4473c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848075031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2848075031
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.980975783
Short name T777
Test name
Test status
Simulation time 4625397218 ps
CPU time 60.43 seconds
Started Aug 10 07:26:27 PM PDT 24
Finished Aug 10 07:27:28 PM PDT 24
Peak memory 249580 kb
Host smart-4e8a93d4-60bb-4a88-b30f-4ec070651530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980975783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.980975783
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1167242003
Short name T41
Test name
Test status
Simulation time 101216545059 ps
CPU time 220.01 seconds
Started Aug 10 07:26:25 PM PDT 24
Finished Aug 10 07:30:05 PM PDT 24
Peak memory 253080 kb
Host smart-fd910701-ff13-417f-a080-2b5658983ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167242003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1167242003
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.49986319
Short name T303
Test name
Test status
Simulation time 2071022488 ps
CPU time 26.34 seconds
Started Aug 10 07:26:20 PM PDT 24
Finished Aug 10 07:26:46 PM PDT 24
Peak memory 249508 kb
Host smart-2a6f930a-f5e4-48c2-a02a-517ce48df21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49986319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.49986319
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1301167154
Short name T216
Test name
Test status
Simulation time 3534702385 ps
CPU time 85.97 seconds
Started Aug 10 07:26:24 PM PDT 24
Finished Aug 10 07:27:50 PM PDT 24
Peak memory 274212 kb
Host smart-3bb51751-11df-49df-a1ef-439acf418c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301167154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1301167154
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2385706905
Short name T849
Test name
Test status
Simulation time 479510438 ps
CPU time 4.18 seconds
Started Aug 10 07:26:13 PM PDT 24
Finished Aug 10 07:26:17 PM PDT 24
Peak memory 224900 kb
Host smart-bfa1a95b-d8a2-475f-aefc-822f0d7a660a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385706905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2385706905
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1704706143
Short name T208
Test name
Test status
Simulation time 42493093248 ps
CPU time 128.23 seconds
Started Aug 10 07:26:16 PM PDT 24
Finished Aug 10 07:28:24 PM PDT 24
Peak memory 224992 kb
Host smart-72ecdec8-4ed7-4820-96ac-94bcadbe15f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704706143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1704706143
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1073015451
Short name T265
Test name
Test status
Simulation time 3147715353 ps
CPU time 10.26 seconds
Started Aug 10 07:26:13 PM PDT 24
Finished Aug 10 07:26:23 PM PDT 24
Peak memory 224996 kb
Host smart-bc4e8572-9aa1-476e-958a-2a401f5ad763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073015451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1073015451
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3910750111
Short name T624
Test name
Test status
Simulation time 5066511783 ps
CPU time 16.08 seconds
Started Aug 10 07:26:16 PM PDT 24
Finished Aug 10 07:26:32 PM PDT 24
Peak memory 224996 kb
Host smart-212f36c7-834e-4829-a12c-9232649d23f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910750111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3910750111
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1619683594
Short name T362
Test name
Test status
Simulation time 95355039 ps
CPU time 3.93 seconds
Started Aug 10 07:26:22 PM PDT 24
Finished Aug 10 07:26:26 PM PDT 24
Peak memory 220868 kb
Host smart-7bc51d56-fab1-4467-9d30-8d19498837e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1619683594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1619683594
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1721164171
Short name T317
Test name
Test status
Simulation time 2922144731 ps
CPU time 5.94 seconds
Started Aug 10 07:26:13 PM PDT 24
Finished Aug 10 07:26:19 PM PDT 24
Peak memory 216708 kb
Host smart-27d2eb6c-cedf-438c-b5e7-c0c2e4c82d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721164171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1721164171
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2874381737
Short name T361
Test name
Test status
Simulation time 1911303073 ps
CPU time 2.25 seconds
Started Aug 10 07:26:14 PM PDT 24
Finished Aug 10 07:26:16 PM PDT 24
Peak memory 208200 kb
Host smart-19c9be58-bb24-4cfb-b226-b1c2a490854c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874381737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2874381737
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2828317807
Short name T325
Test name
Test status
Simulation time 174187932 ps
CPU time 1.09 seconds
Started Aug 10 07:26:13 PM PDT 24
Finished Aug 10 07:26:14 PM PDT 24
Peak memory 207344 kb
Host smart-908fd923-0613-4aae-92e7-8812937eb356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828317807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2828317807
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4116724699
Short name T430
Test name
Test status
Simulation time 89625248 ps
CPU time 0.81 seconds
Started Aug 10 07:26:12 PM PDT 24
Finished Aug 10 07:26:13 PM PDT 24
Peak memory 206380 kb
Host smart-e761ac21-2305-47e2-9a05-f67a77fdee75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116724699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4116724699
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2216293361
Short name T222
Test name
Test status
Simulation time 8492454380 ps
CPU time 9.27 seconds
Started Aug 10 07:26:14 PM PDT 24
Finished Aug 10 07:26:24 PM PDT 24
Peak memory 225048 kb
Host smart-7519e5b4-5016-4381-b822-bc152f3bbe19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216293361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2216293361
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.419423187
Short name T885
Test name
Test status
Simulation time 19364683 ps
CPU time 0.74 seconds
Started Aug 10 07:26:22 PM PDT 24
Finished Aug 10 07:26:23 PM PDT 24
Peak memory 205296 kb
Host smart-c473e007-7f4a-4ca6-9e38-261c945ed77e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419423187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.419423187
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1725190975
Short name T399
Test name
Test status
Simulation time 189439306 ps
CPU time 2.88 seconds
Started Aug 10 07:26:24 PM PDT 24
Finished Aug 10 07:26:27 PM PDT 24
Peak memory 224816 kb
Host smart-90043e5c-dd6c-4fc0-98bd-368850639789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725190975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1725190975
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1004704337
Short name T396
Test name
Test status
Simulation time 53333502 ps
CPU time 0.82 seconds
Started Aug 10 07:26:25 PM PDT 24
Finished Aug 10 07:26:26 PM PDT 24
Peak memory 207304 kb
Host smart-885ad99d-32b9-423a-8b92-a0496ca70ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004704337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1004704337
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3882273792
Short name T299
Test name
Test status
Simulation time 7346622539 ps
CPU time 57.21 seconds
Started Aug 10 07:26:24 PM PDT 24
Finished Aug 10 07:27:21 PM PDT 24
Peak memory 249648 kb
Host smart-dfd3eda5-25a9-496f-a672-e37cce9e3f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882273792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3882273792
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2297296700
Short name T954
Test name
Test status
Simulation time 113337595220 ps
CPU time 503.25 seconds
Started Aug 10 07:26:23 PM PDT 24
Finished Aug 10 07:34:46 PM PDT 24
Peak memory 252260 kb
Host smart-bfd0e0dc-836e-483b-9ca7-09ed43ca4f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297296700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2297296700
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2484746208
Short name T981
Test name
Test status
Simulation time 353741915 ps
CPU time 4.04 seconds
Started Aug 10 07:26:23 PM PDT 24
Finished Aug 10 07:26:28 PM PDT 24
Peak memory 241364 kb
Host smart-2997bdf0-615c-4757-aec9-c0a9a4c3fc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484746208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2484746208
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3383508076
Short name T494
Test name
Test status
Simulation time 26390294606 ps
CPU time 54.4 seconds
Started Aug 10 07:26:23 PM PDT 24
Finished Aug 10 07:27:17 PM PDT 24
Peak memory 249596 kb
Host smart-c0c94aae-9194-4046-aaa8-bc6f0e3feefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383508076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3383508076
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3845383802
Short name T196
Test name
Test status
Simulation time 838303167 ps
CPU time 5.98 seconds
Started Aug 10 07:26:24 PM PDT 24
Finished Aug 10 07:26:30 PM PDT 24
Peak memory 224904 kb
Host smart-882f3b5d-fda0-4227-b591-cd0a697d101e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845383802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3845383802
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3342498699
Short name T745
Test name
Test status
Simulation time 47223622371 ps
CPU time 100.67 seconds
Started Aug 10 07:26:25 PM PDT 24
Finished Aug 10 07:28:06 PM PDT 24
Peak memory 249616 kb
Host smart-d9dc48b4-b681-4e1d-a2e8-cade78ef75b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342498699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3342498699
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3845218228
Short name T401
Test name
Test status
Simulation time 1878592672 ps
CPU time 11.96 seconds
Started Aug 10 07:26:24 PM PDT 24
Finished Aug 10 07:26:36 PM PDT 24
Peak memory 233320 kb
Host smart-b78a05f7-2d46-4951-ae11-4674e6f3c21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845218228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3845218228
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1231039616
Short name T29
Test name
Test status
Simulation time 15290120077 ps
CPU time 21.28 seconds
Started Aug 10 07:26:24 PM PDT 24
Finished Aug 10 07:26:46 PM PDT 24
Peak memory 249472 kb
Host smart-bbd855fb-1601-471c-a643-378fbc7de5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231039616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1231039616
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2044145309
Short name T457
Test name
Test status
Simulation time 2947169100 ps
CPU time 6.67 seconds
Started Aug 10 07:26:26 PM PDT 24
Finished Aug 10 07:26:32 PM PDT 24
Peak memory 222648 kb
Host smart-e8d98aa8-8be4-483e-812d-6afd92d3e8d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2044145309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2044145309
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3118520911
Short name T159
Test name
Test status
Simulation time 49626776121 ps
CPU time 82.32 seconds
Started Aug 10 07:26:23 PM PDT 24
Finished Aug 10 07:27:46 PM PDT 24
Peak memory 251656 kb
Host smart-1fed0d50-881e-40ea-97f6-95c23bcfeea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118520911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3118520911
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1346904904
Short name T750
Test name
Test status
Simulation time 521446083 ps
CPU time 2.92 seconds
Started Aug 10 07:26:23 PM PDT 24
Finished Aug 10 07:26:26 PM PDT 24
Peak memory 217804 kb
Host smart-a1af54f0-8609-4446-ad5f-0230be8bc0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346904904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1346904904
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1550882040
Short name T136
Test name
Test status
Simulation time 8267432485 ps
CPU time 11.8 seconds
Started Aug 10 07:26:25 PM PDT 24
Finished Aug 10 07:26:37 PM PDT 24
Peak memory 216784 kb
Host smart-e358a296-0cb2-4911-ab52-9dbc4a99ee15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550882040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1550882040
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1413408135
Short name T713
Test name
Test status
Simulation time 20661338 ps
CPU time 0.98 seconds
Started Aug 10 07:26:26 PM PDT 24
Finished Aug 10 07:26:27 PM PDT 24
Peak memory 207388 kb
Host smart-ee8180a1-cca7-4018-96db-35396db6f713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413408135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1413408135
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1470552600
Short name T619
Test name
Test status
Simulation time 34085876 ps
CPU time 0.75 seconds
Started Aug 10 07:26:25 PM PDT 24
Finished Aug 10 07:26:26 PM PDT 24
Peak memory 206376 kb
Host smart-eed9509f-8fe8-48b8-b361-8a9fe6b411af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470552600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1470552600
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1135724584
Short name T489
Test name
Test status
Simulation time 363194322 ps
CPU time 5.03 seconds
Started Aug 10 07:26:25 PM PDT 24
Finished Aug 10 07:26:30 PM PDT 24
Peak memory 224916 kb
Host smart-79c438f8-a482-4eaf-b6af-8ef0429a0dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135724584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1135724584
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.939491053
Short name T369
Test name
Test status
Simulation time 12652275 ps
CPU time 0.73 seconds
Started Aug 10 07:26:36 PM PDT 24
Finished Aug 10 07:26:37 PM PDT 24
Peak memory 205844 kb
Host smart-b9ef2f69-3c71-456e-879b-2f06b0d54451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939491053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.939491053
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.212581499
Short name T554
Test name
Test status
Simulation time 497556473 ps
CPU time 6.13 seconds
Started Aug 10 07:26:22 PM PDT 24
Finished Aug 10 07:26:29 PM PDT 24
Peak memory 224824 kb
Host smart-29bda8c5-c3f2-462a-81d6-26c96613f6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212581499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.212581499
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2007357425
Short name T587
Test name
Test status
Simulation time 26427067 ps
CPU time 0.77 seconds
Started Aug 10 07:26:27 PM PDT 24
Finished Aug 10 07:26:28 PM PDT 24
Peak memory 207236 kb
Host smart-4702c909-5323-4691-98b6-6a5418de8318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007357425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2007357425
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2597579504
Short name T748
Test name
Test status
Simulation time 18476089904 ps
CPU time 69.12 seconds
Started Aug 10 07:26:23 PM PDT 24
Finished Aug 10 07:27:32 PM PDT 24
Peak memory 235552 kb
Host smart-12444cea-76d7-4784-bb0b-c3de60ded6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597579504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2597579504
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.146017054
Short name T321
Test name
Test status
Simulation time 99420896765 ps
CPU time 241.45 seconds
Started Aug 10 07:26:31 PM PDT 24
Finished Aug 10 07:30:33 PM PDT 24
Peak memory 250300 kb
Host smart-3cfbcbf8-815b-4d8a-8228-3e08828df280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146017054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.146017054
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3312806940
Short name T358
Test name
Test status
Simulation time 7829987634 ps
CPU time 13.74 seconds
Started Aug 10 07:26:26 PM PDT 24
Finished Aug 10 07:26:39 PM PDT 24
Peak memory 225008 kb
Host smart-0e9bd067-9821-4c8b-b8c2-e858f9a8c941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312806940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3312806940
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3972127504
Short name T574
Test name
Test status
Simulation time 31871449884 ps
CPU time 50.78 seconds
Started Aug 10 07:26:21 PM PDT 24
Finished Aug 10 07:27:12 PM PDT 24
Peak memory 253544 kb
Host smart-69246c69-7d11-41a7-ab7c-f469b5c19a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972127504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3972127504
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3209073960
Short name T803
Test name
Test status
Simulation time 2812207995 ps
CPU time 8.02 seconds
Started Aug 10 07:26:26 PM PDT 24
Finished Aug 10 07:26:34 PM PDT 24
Peak memory 233212 kb
Host smart-7072d663-4701-4b0d-933f-f31cbe79b9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209073960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3209073960
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.937089420
Short name T446
Test name
Test status
Simulation time 333130646 ps
CPU time 5.13 seconds
Started Aug 10 07:26:22 PM PDT 24
Finished Aug 10 07:26:27 PM PDT 24
Peak memory 224860 kb
Host smart-d5554535-cda6-4096-8b3d-1099791d297c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937089420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.937089420
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2103199620
Short name T331
Test name
Test status
Simulation time 177068066 ps
CPU time 2.35 seconds
Started Aug 10 07:26:26 PM PDT 24
Finished Aug 10 07:26:28 PM PDT 24
Peak memory 224228 kb
Host smart-3c61de69-e115-4f4a-89f4-97ca87469115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103199620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2103199620
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.894814941
Short name T770
Test name
Test status
Simulation time 4939478326 ps
CPU time 15.13 seconds
Started Aug 10 07:26:25 PM PDT 24
Finished Aug 10 07:26:40 PM PDT 24
Peak memory 233188 kb
Host smart-868d1b39-9777-4611-98e9-d4f453f59987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894814941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.894814941
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.397607469
Short name T146
Test name
Test status
Simulation time 619408530 ps
CPU time 5.95 seconds
Started Aug 10 07:26:25 PM PDT 24
Finished Aug 10 07:26:31 PM PDT 24
Peak memory 223600 kb
Host smart-1d8e5170-4ed1-45d8-81f2-12adbc7a294e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=397607469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.397607469
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3638432576
Short name T615
Test name
Test status
Simulation time 8700437723 ps
CPU time 9.76 seconds
Started Aug 10 07:26:27 PM PDT 24
Finished Aug 10 07:26:37 PM PDT 24
Peak memory 216684 kb
Host smart-bb867ad1-946d-460b-8f95-16f55bb5f96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638432576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3638432576
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3064255008
Short name T958
Test name
Test status
Simulation time 4097600398 ps
CPU time 9.03 seconds
Started Aug 10 07:26:24 PM PDT 24
Finished Aug 10 07:26:33 PM PDT 24
Peak memory 216804 kb
Host smart-f56dae5e-d7a4-4be7-9979-ad05c7bb96a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064255008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3064255008
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3010784832
Short name T809
Test name
Test status
Simulation time 13513754 ps
CPU time 0.7 seconds
Started Aug 10 07:26:22 PM PDT 24
Finished Aug 10 07:26:23 PM PDT 24
Peak memory 206088 kb
Host smart-348edcdc-6d56-4982-83fc-0f108e14871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010784832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3010784832
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.885759757
Short name T875
Test name
Test status
Simulation time 46195347 ps
CPU time 0.82 seconds
Started Aug 10 07:26:26 PM PDT 24
Finished Aug 10 07:26:27 PM PDT 24
Peak memory 206388 kb
Host smart-553c1937-383a-4477-bbff-37fdaa71cf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885759757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.885759757
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3027125215
Short name T213
Test name
Test status
Simulation time 5432228797 ps
CPU time 7.75 seconds
Started Aug 10 07:26:25 PM PDT 24
Finished Aug 10 07:26:33 PM PDT 24
Peak memory 225028 kb
Host smart-53ecb888-4cba-4ed1-be22-7d7fbec59cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027125215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3027125215
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3177364199
Short name T889
Test name
Test status
Simulation time 12509253 ps
CPU time 0.72 seconds
Started Aug 10 07:26:34 PM PDT 24
Finished Aug 10 07:26:35 PM PDT 24
Peak memory 205844 kb
Host smart-d3941004-a539-4c93-97fe-7a5a042b1d08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177364199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3177364199
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1786486457
Short name T436
Test name
Test status
Simulation time 139522520 ps
CPU time 3.72 seconds
Started Aug 10 07:26:37 PM PDT 24
Finished Aug 10 07:26:41 PM PDT 24
Peak memory 233124 kb
Host smart-a92d3c7f-1e98-48c4-8b71-a2dfb6c95aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786486457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1786486457
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1767140336
Short name T740
Test name
Test status
Simulation time 54310647 ps
CPU time 0.81 seconds
Started Aug 10 07:26:35 PM PDT 24
Finished Aug 10 07:26:36 PM PDT 24
Peak memory 207244 kb
Host smart-aadffef8-7f93-4a1e-ace5-32ccf1b38e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767140336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1767140336
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.38661928
Short name T298
Test name
Test status
Simulation time 74699562000 ps
CPU time 292.52 seconds
Started Aug 10 07:26:34 PM PDT 24
Finished Aug 10 07:31:26 PM PDT 24
Peak memory 266160 kb
Host smart-340a127d-f9b8-40f6-a7a5-252e2db2a11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38661928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.38661928
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.756490636
Short name T54
Test name
Test status
Simulation time 57000788697 ps
CPU time 589.44 seconds
Started Aug 10 07:26:33 PM PDT 24
Finished Aug 10 07:36:23 PM PDT 24
Peak memory 264620 kb
Host smart-8ff458af-4e94-4c52-8df4-8b7eede67e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756490636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.756490636
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1454687297
Short name T42
Test name
Test status
Simulation time 25093784160 ps
CPU time 219.2 seconds
Started Aug 10 07:26:35 PM PDT 24
Finished Aug 10 07:30:14 PM PDT 24
Peak memory 255652 kb
Host smart-6d2f5134-8d91-4629-9fd0-e9e59224f471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454687297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1454687297
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3553295302
Short name T716
Test name
Test status
Simulation time 29055791526 ps
CPU time 23.44 seconds
Started Aug 10 07:26:33 PM PDT 24
Finished Aug 10 07:26:57 PM PDT 24
Peak memory 241380 kb
Host smart-b35e23e0-61a3-465b-a24c-a3a43548f5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553295302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3553295302
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2411221844
Short name T387
Test name
Test status
Simulation time 10049475369 ps
CPU time 66.04 seconds
Started Aug 10 07:26:35 PM PDT 24
Finished Aug 10 07:27:41 PM PDT 24
Peak memory 250424 kb
Host smart-e3a6d5fa-765f-4515-8353-44344582e663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411221844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2411221844
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2157025192
Short name T95
Test name
Test status
Simulation time 1410974682 ps
CPU time 7.76 seconds
Started Aug 10 07:26:33 PM PDT 24
Finished Aug 10 07:26:41 PM PDT 24
Peak memory 233172 kb
Host smart-cf7dc6f7-29a3-4d3f-8386-68a96d489e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157025192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2157025192
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3276507457
Short name T698
Test name
Test status
Simulation time 5763458568 ps
CPU time 32.24 seconds
Started Aug 10 07:26:33 PM PDT 24
Finished Aug 10 07:27:06 PM PDT 24
Peak memory 224936 kb
Host smart-e0d883a2-70d1-4288-a699-41aedb763c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276507457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3276507457
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3207321501
Short name T10
Test name
Test status
Simulation time 2084816073 ps
CPU time 11.22 seconds
Started Aug 10 07:26:36 PM PDT 24
Finished Aug 10 07:26:47 PM PDT 24
Peak memory 233164 kb
Host smart-98ba6404-3a3b-46a1-8ab5-e3685c67270b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207321501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3207321501
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3824395567
Short name T799
Test name
Test status
Simulation time 32328201819 ps
CPU time 23.22 seconds
Started Aug 10 07:26:34 PM PDT 24
Finished Aug 10 07:26:57 PM PDT 24
Peak memory 238296 kb
Host smart-1988a566-83e5-43d6-a247-e60f9596e5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824395567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3824395567
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2329496930
Short name T453
Test name
Test status
Simulation time 5672065315 ps
CPU time 11.93 seconds
Started Aug 10 07:26:31 PM PDT 24
Finished Aug 10 07:26:44 PM PDT 24
Peak memory 221408 kb
Host smart-94422e0e-f23e-4d5a-83b0-95bd256ecd83
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2329496930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2329496930
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3392060831
Short name T926
Test name
Test status
Simulation time 31658385589 ps
CPU time 297.39 seconds
Started Aug 10 07:26:32 PM PDT 24
Finished Aug 10 07:31:30 PM PDT 24
Peak memory 257356 kb
Host smart-db517930-1a69-4471-8d18-2d8e8173cd38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392060831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3392060831
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1858062951
Short name T741
Test name
Test status
Simulation time 12903517556 ps
CPU time 34.49 seconds
Started Aug 10 07:26:33 PM PDT 24
Finished Aug 10 07:27:08 PM PDT 24
Peak memory 216812 kb
Host smart-e968ee02-20d6-4e51-8db5-c9d8eb7a4db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858062951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1858062951
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.61961923
Short name T326
Test name
Test status
Simulation time 18718703846 ps
CPU time 15.99 seconds
Started Aug 10 07:26:33 PM PDT 24
Finished Aug 10 07:26:49 PM PDT 24
Peak memory 216752 kb
Host smart-69840c03-0f67-4dff-a009-26405591b7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61961923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.61961923
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.4009739851
Short name T342
Test name
Test status
Simulation time 771146169 ps
CPU time 2.44 seconds
Started Aug 10 07:26:36 PM PDT 24
Finished Aug 10 07:26:38 PM PDT 24
Peak memory 216572 kb
Host smart-0e019364-59b0-4bfa-b661-eee76d64c7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009739851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.4009739851
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3100984220
Short name T950
Test name
Test status
Simulation time 30195500 ps
CPU time 0.77 seconds
Started Aug 10 07:26:34 PM PDT 24
Finished Aug 10 07:26:35 PM PDT 24
Peak memory 206396 kb
Host smart-f789fd27-abc6-46be-9ec9-3b5be355f247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100984220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3100984220
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1687253589
Short name T12
Test name
Test status
Simulation time 331031118 ps
CPU time 2.77 seconds
Started Aug 10 07:26:34 PM PDT 24
Finished Aug 10 07:26:37 PM PDT 24
Peak memory 224760 kb
Host smart-64d9f133-627d-460c-adfb-d4babc57a053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687253589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1687253589
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.899302454
Short name T374
Test name
Test status
Simulation time 45734888 ps
CPU time 0.8 seconds
Started Aug 10 07:24:45 PM PDT 24
Finished Aug 10 07:24:46 PM PDT 24
Peak memory 205320 kb
Host smart-35768eb2-a1e2-4c90-b97b-5cfa923e7a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899302454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.899302454
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3390857999
Short name T525
Test name
Test status
Simulation time 73949734 ps
CPU time 2.94 seconds
Started Aug 10 07:24:50 PM PDT 24
Finished Aug 10 07:24:53 PM PDT 24
Peak memory 233172 kb
Host smart-76181860-1fd4-4780-9e03-bf5597aabed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390857999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3390857999
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3063891886
Short name T818
Test name
Test status
Simulation time 16216715 ps
CPU time 0.76 seconds
Started Aug 10 07:24:50 PM PDT 24
Finished Aug 10 07:24:50 PM PDT 24
Peak memory 206316 kb
Host smart-6b2eba1b-025b-4110-935d-9dd2430d4023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063891886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3063891886
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2631447917
Short name T267
Test name
Test status
Simulation time 3410967616 ps
CPU time 48.83 seconds
Started Aug 10 07:24:45 PM PDT 24
Finished Aug 10 07:25:34 PM PDT 24
Peak memory 241400 kb
Host smart-2962f581-1758-4f1f-b858-91e89b427f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631447917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2631447917
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3976326974
Short name T864
Test name
Test status
Simulation time 88987932176 ps
CPU time 51.74 seconds
Started Aug 10 07:24:51 PM PDT 24
Finished Aug 10 07:25:43 PM PDT 24
Peak memory 241320 kb
Host smart-ab958d58-ced4-499d-8823-8e582914a0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976326974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3976326974
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1136627366
Short name T899
Test name
Test status
Simulation time 37630287013 ps
CPU time 338.8 seconds
Started Aug 10 07:24:49 PM PDT 24
Finished Aug 10 07:30:28 PM PDT 24
Peak memory 263684 kb
Host smart-11b12eb6-5538-4769-a960-d614873ed5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136627366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1136627366
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3849085740
Short name T829
Test name
Test status
Simulation time 241263591 ps
CPU time 4.26 seconds
Started Aug 10 07:24:45 PM PDT 24
Finished Aug 10 07:24:50 PM PDT 24
Peak memory 233184 kb
Host smart-84c240dc-8522-4576-9580-aabcdbe5ef5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849085740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3849085740
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1449556384
Short name T300
Test name
Test status
Simulation time 14926820298 ps
CPU time 148.46 seconds
Started Aug 10 07:24:43 PM PDT 24
Finished Aug 10 07:27:11 PM PDT 24
Peak memory 273288 kb
Host smart-b77fa716-e7b4-4a05-878e-6bf1660b4fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449556384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1449556384
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.86865188
Short name T517
Test name
Test status
Simulation time 44539426 ps
CPU time 2.57 seconds
Started Aug 10 07:24:48 PM PDT 24
Finished Aug 10 07:24:51 PM PDT 24
Peak memory 232792 kb
Host smart-8b27f5a3-9bc0-4574-81b0-c5dd70e9d41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86865188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.86865188
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1630760099
Short name T728
Test name
Test status
Simulation time 21300146595 ps
CPU time 46.14 seconds
Started Aug 10 07:24:50 PM PDT 24
Finished Aug 10 07:25:36 PM PDT 24
Peak memory 249360 kb
Host smart-261759b0-d4f2-462d-a517-f2bb52940175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630760099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1630760099
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3700195192
Short name T488
Test name
Test status
Simulation time 3057618110 ps
CPU time 3.63 seconds
Started Aug 10 07:24:46 PM PDT 24
Finished Aug 10 07:24:50 PM PDT 24
Peak memory 225024 kb
Host smart-12315072-0fc5-42ec-a0de-cd6964a566e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700195192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3700195192
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.4250984679
Short name T755
Test name
Test status
Simulation time 1947282380 ps
CPU time 5.18 seconds
Started Aug 10 07:24:47 PM PDT 24
Finished Aug 10 07:24:52 PM PDT 24
Peak memory 224828 kb
Host smart-1b795c56-776e-45b6-ba8c-e651a85e9b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250984679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.4250984679
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1399223275
Short name T960
Test name
Test status
Simulation time 136085392 ps
CPU time 3.78 seconds
Started Aug 10 07:24:46 PM PDT 24
Finished Aug 10 07:24:50 PM PDT 24
Peak memory 223296 kb
Host smart-944e9fe5-7a38-4833-9110-a902cb56b38a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1399223275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1399223275
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3317291683
Short name T76
Test name
Test status
Simulation time 35074000 ps
CPU time 1.07 seconds
Started Aug 10 07:24:46 PM PDT 24
Finished Aug 10 07:24:48 PM PDT 24
Peak memory 236900 kb
Host smart-4b58cf64-1527-40b2-9579-88abe34e2bcd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317291683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3317291683
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3727374441
Short name T17
Test name
Test status
Simulation time 97603000 ps
CPU time 1.17 seconds
Started Aug 10 07:24:47 PM PDT 24
Finished Aug 10 07:24:48 PM PDT 24
Peak memory 207360 kb
Host smart-2feeba51-d3eb-44df-881d-6a7f98485da2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727374441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3727374441
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.771545305
Short name T790
Test name
Test status
Simulation time 750639998 ps
CPU time 6.87 seconds
Started Aug 10 07:24:46 PM PDT 24
Finished Aug 10 07:24:53 PM PDT 24
Peak memory 216664 kb
Host smart-9dd3b2f1-e037-49d2-a4c4-02ac176adb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771545305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.771545305
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3631002287
Short name T697
Test name
Test status
Simulation time 2759014518 ps
CPU time 4.63 seconds
Started Aug 10 07:24:45 PM PDT 24
Finished Aug 10 07:24:50 PM PDT 24
Peak memory 216756 kb
Host smart-f199c4d0-3356-451e-84b6-e0c67d196e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631002287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3631002287
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.117968484
Short name T945
Test name
Test status
Simulation time 733756006 ps
CPU time 1.29 seconds
Started Aug 10 07:24:46 PM PDT 24
Finished Aug 10 07:24:48 PM PDT 24
Peak memory 216632 kb
Host smart-9802f554-8732-4ca2-b605-d909d2261e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117968484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.117968484
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2390116829
Short name T11
Test name
Test status
Simulation time 75227661 ps
CPU time 0.82 seconds
Started Aug 10 07:24:44 PM PDT 24
Finished Aug 10 07:24:45 PM PDT 24
Peak memory 206312 kb
Host smart-0c6f546b-636f-493d-ad0f-15a81df9153c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390116829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2390116829
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3713824901
Short name T382
Test name
Test status
Simulation time 166344695 ps
CPU time 3.01 seconds
Started Aug 10 07:24:46 PM PDT 24
Finished Aug 10 07:24:49 PM PDT 24
Peak memory 233196 kb
Host smart-f5e37bb1-af3e-4b6c-8698-b8df3c052343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713824901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3713824901
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3011485855
Short name T345
Test name
Test status
Simulation time 18779434 ps
CPU time 0.73 seconds
Started Aug 10 07:26:41 PM PDT 24
Finished Aug 10 07:26:42 PM PDT 24
Peak memory 205864 kb
Host smart-0141b397-8836-46aa-9f99-bc48b7e11e33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011485855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3011485855
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.825940380
Short name T185
Test name
Test status
Simulation time 212751514 ps
CPU time 3.88 seconds
Started Aug 10 07:26:37 PM PDT 24
Finished Aug 10 07:26:41 PM PDT 24
Peak memory 224888 kb
Host smart-a434b02d-1a71-4199-8752-beec3960c7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825940380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.825940380
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.338527865
Short name T515
Test name
Test status
Simulation time 18521489 ps
CPU time 0.74 seconds
Started Aug 10 07:26:37 PM PDT 24
Finished Aug 10 07:26:38 PM PDT 24
Peak memory 205988 kb
Host smart-1d04ca06-5cff-4713-b102-bf545bbbc5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338527865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.338527865
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1348793850
Short name T221
Test name
Test status
Simulation time 5763113927 ps
CPU time 27.05 seconds
Started Aug 10 07:26:49 PM PDT 24
Finished Aug 10 07:27:16 PM PDT 24
Peak memory 236896 kb
Host smart-5dc87b2f-53c6-49aa-a1cc-00d5e8c1f02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348793850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1348793850
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2600587048
Short name T131
Test name
Test status
Simulation time 160122446523 ps
CPU time 242.68 seconds
Started Aug 10 07:26:49 PM PDT 24
Finished Aug 10 07:30:52 PM PDT 24
Peak memory 256096 kb
Host smart-1a5286cb-7d54-4059-b4e0-4ad95af5c09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600587048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2600587048
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2959591144
Short name T277
Test name
Test status
Simulation time 26465578693 ps
CPU time 90.78 seconds
Started Aug 10 07:26:41 PM PDT 24
Finished Aug 10 07:28:12 PM PDT 24
Peak memory 248640 kb
Host smart-9d5de478-7e23-4f60-9ea0-6e2bbb25f5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959591144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2959591144
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2698693384
Short name T309
Test name
Test status
Simulation time 2999663863 ps
CPU time 30.98 seconds
Started Aug 10 07:26:32 PM PDT 24
Finished Aug 10 07:27:03 PM PDT 24
Peak memory 240712 kb
Host smart-dafdbf0d-9b50-405b-b194-73c355a7fb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698693384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2698693384
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.4227843721
Short name T373
Test name
Test status
Simulation time 2848650639 ps
CPU time 23.13 seconds
Started Aug 10 07:26:36 PM PDT 24
Finished Aug 10 07:26:59 PM PDT 24
Peak memory 233224 kb
Host smart-62d69623-6088-46c4-a1e5-5423f7fc3ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227843721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.4227843721
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.565727537
Short name T250
Test name
Test status
Simulation time 694422177 ps
CPU time 6.13 seconds
Started Aug 10 07:26:36 PM PDT 24
Finished Aug 10 07:26:43 PM PDT 24
Peak memory 224888 kb
Host smart-4325befd-b48a-437b-b2d4-f22f94512091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565727537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.565727537
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.4180737070
Short name T905
Test name
Test status
Simulation time 9684498572 ps
CPU time 98.48 seconds
Started Aug 10 07:26:35 PM PDT 24
Finished Aug 10 07:28:14 PM PDT 24
Peak memory 233212 kb
Host smart-ea4ec90a-5d3d-494c-9f8b-4388d3fc59e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180737070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4180737070
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3184677529
Short name T800
Test name
Test status
Simulation time 106267213 ps
CPU time 2.49 seconds
Started Aug 10 07:26:36 PM PDT 24
Finished Aug 10 07:26:39 PM PDT 24
Peak memory 232816 kb
Host smart-7355fd12-7af9-40c4-b2d3-e8e69b3cfaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184677529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3184677529
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1684750753
Short name T47
Test name
Test status
Simulation time 92027119 ps
CPU time 2.29 seconds
Started Aug 10 07:26:36 PM PDT 24
Finished Aug 10 07:26:38 PM PDT 24
Peak memory 224808 kb
Host smart-df121ec1-929b-46c9-b0d6-b86e9806b61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684750753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1684750753
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1244496256
Short name T879
Test name
Test status
Simulation time 844074581 ps
CPU time 13.29 seconds
Started Aug 10 07:26:40 PM PDT 24
Finished Aug 10 07:26:53 PM PDT 24
Peak memory 220916 kb
Host smart-72eb4a19-3694-4d45-9902-982ddb2cb511
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1244496256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1244496256
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1204867317
Short name T161
Test name
Test status
Simulation time 2369648908 ps
CPU time 39.25 seconds
Started Aug 10 07:26:42 PM PDT 24
Finished Aug 10 07:27:21 PM PDT 24
Peak memory 251520 kb
Host smart-2e627ad0-b5b5-42fc-b8ca-8d831ec8025f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204867317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1204867317
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3611488093
Short name T378
Test name
Test status
Simulation time 299056646 ps
CPU time 3.53 seconds
Started Aug 10 07:26:34 PM PDT 24
Finished Aug 10 07:26:38 PM PDT 24
Peak memory 218996 kb
Host smart-6c04af46-2c4b-4058-9aef-54886030b398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611488093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3611488093
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.371849352
Short name T460
Test name
Test status
Simulation time 1665940478 ps
CPU time 4.78 seconds
Started Aug 10 07:26:37 PM PDT 24
Finished Aug 10 07:26:42 PM PDT 24
Peak memory 216664 kb
Host smart-b3b6508b-fdd1-40c0-9347-02d45a07735f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371849352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.371849352
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3293907167
Short name T493
Test name
Test status
Simulation time 16488922 ps
CPU time 0.99 seconds
Started Aug 10 07:26:35 PM PDT 24
Finished Aug 10 07:26:36 PM PDT 24
Peak memory 207400 kb
Host smart-c4d85937-0ec8-4d3d-b6ff-7712c261e91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293907167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3293907167
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.169681224
Short name T680
Test name
Test status
Simulation time 48633482 ps
CPU time 0.76 seconds
Started Aug 10 07:26:33 PM PDT 24
Finished Aug 10 07:26:33 PM PDT 24
Peak memory 206296 kb
Host smart-16276a95-4bd7-4efc-9e08-49aed2bbe0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169681224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.169681224
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3313522658
Short name T113
Test name
Test status
Simulation time 38110154 ps
CPU time 2.49 seconds
Started Aug 10 07:26:35 PM PDT 24
Finished Aug 10 07:26:37 PM PDT 24
Peak memory 224556 kb
Host smart-f185f8ea-5898-415b-ae37-166262d9e036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313522658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3313522658
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1014336395
Short name T455
Test name
Test status
Simulation time 12697783 ps
CPU time 0.69 seconds
Started Aug 10 07:26:45 PM PDT 24
Finished Aug 10 07:26:46 PM PDT 24
Peak memory 206184 kb
Host smart-66132a10-3d8c-42e7-aa41-e22033f094cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014336395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1014336395
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.772905304
Short name T836
Test name
Test status
Simulation time 236688934 ps
CPU time 5.04 seconds
Started Aug 10 07:26:49 PM PDT 24
Finished Aug 10 07:26:54 PM PDT 24
Peak memory 224484 kb
Host smart-71eb2fac-3aea-4aa3-9207-a3f55b22f9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772905304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.772905304
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.4157166583
Short name T877
Test name
Test status
Simulation time 61554153 ps
CPU time 0.75 seconds
Started Aug 10 07:26:40 PM PDT 24
Finished Aug 10 07:26:41 PM PDT 24
Peak memory 206920 kb
Host smart-4a989fdb-c315-496a-96f0-73cc5d9e060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157166583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.4157166583
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3634197156
Short name T286
Test name
Test status
Simulation time 86765974087 ps
CPU time 363.86 seconds
Started Aug 10 07:26:41 PM PDT 24
Finished Aug 10 07:32:45 PM PDT 24
Peak memory 266060 kb
Host smart-fa233cc4-f607-43eb-96a2-0b4a303cd22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634197156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3634197156
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.34252766
Short name T134
Test name
Test status
Simulation time 63780144923 ps
CPU time 153.51 seconds
Started Aug 10 07:26:41 PM PDT 24
Finished Aug 10 07:29:15 PM PDT 24
Peak memory 256584 kb
Host smart-61c458e9-3885-479a-aaf4-8511f690cde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34252766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.34252766
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.79210124
Short name T63
Test name
Test status
Simulation time 2522983627 ps
CPU time 73.47 seconds
Started Aug 10 07:26:41 PM PDT 24
Finished Aug 10 07:27:54 PM PDT 24
Peak memory 250612 kb
Host smart-38fa35bf-011a-42a6-9366-d81abb685655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79210124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.79210124
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1642893602
Short name T650
Test name
Test status
Simulation time 2549796634 ps
CPU time 9.87 seconds
Started Aug 10 07:26:46 PM PDT 24
Finished Aug 10 07:26:56 PM PDT 24
Peak memory 224948 kb
Host smart-eef23bb9-b98e-44d9-a144-678188f84174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642893602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1642893602
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.4065991177
Short name T762
Test name
Test status
Simulation time 53769809 ps
CPU time 0.93 seconds
Started Aug 10 07:26:49 PM PDT 24
Finished Aug 10 07:26:50 PM PDT 24
Peak memory 216412 kb
Host smart-7975f624-7b6d-4da7-9500-a8b4f91050b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065991177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.4065991177
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.447687241
Short name T705
Test name
Test status
Simulation time 855435930 ps
CPU time 3.95 seconds
Started Aug 10 07:26:41 PM PDT 24
Finished Aug 10 07:26:45 PM PDT 24
Peak memory 224824 kb
Host smart-885bc942-e36b-4671-8685-795c0a086ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447687241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.447687241
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.571887442
Short name T957
Test name
Test status
Simulation time 3386725301 ps
CPU time 26.55 seconds
Started Aug 10 07:26:41 PM PDT 24
Finished Aug 10 07:27:08 PM PDT 24
Peak memory 233260 kb
Host smart-d827c80d-2a53-492f-a399-48a22d009f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571887442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.571887442
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.469443125
Short name T900
Test name
Test status
Simulation time 29880470 ps
CPU time 2.3 seconds
Started Aug 10 07:26:40 PM PDT 24
Finished Aug 10 07:26:42 PM PDT 24
Peak memory 232852 kb
Host smart-777c8fde-5762-4855-886e-e03867291bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469443125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.469443125
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2888738689
Short name T627
Test name
Test status
Simulation time 37320339390 ps
CPU time 31.81 seconds
Started Aug 10 07:26:40 PM PDT 24
Finished Aug 10 07:27:12 PM PDT 24
Peak memory 225120 kb
Host smart-6b89188c-7965-4f13-95fc-e1dd08075650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888738689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2888738689
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4183075111
Short name T852
Test name
Test status
Simulation time 579115588 ps
CPU time 4.45 seconds
Started Aug 10 07:26:43 PM PDT 24
Finished Aug 10 07:26:47 PM PDT 24
Peak memory 223200 kb
Host smart-3b249f72-2f90-4a86-952b-073dd7fd90a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4183075111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4183075111
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.858126924
Short name T524
Test name
Test status
Simulation time 57502278 ps
CPU time 0.92 seconds
Started Aug 10 07:26:41 PM PDT 24
Finished Aug 10 07:26:42 PM PDT 24
Peak memory 207044 kb
Host smart-b093b9e2-28b8-46bb-a238-98f0aa054a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858126924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.858126924
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1888564265
Short name T327
Test name
Test status
Simulation time 2696477129 ps
CPU time 19.73 seconds
Started Aug 10 07:26:40 PM PDT 24
Finished Aug 10 07:26:59 PM PDT 24
Peak memory 216736 kb
Host smart-1104e88f-c6fe-410a-a55e-a86f14cf3592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888564265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1888564265
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4285094309
Short name T911
Test name
Test status
Simulation time 4277871080 ps
CPU time 7.04 seconds
Started Aug 10 07:26:42 PM PDT 24
Finished Aug 10 07:26:49 PM PDT 24
Peak memory 216700 kb
Host smart-938fbd6f-76df-42da-b7a7-911eee264cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285094309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4285094309
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1444783364
Short name T869
Test name
Test status
Simulation time 167067609 ps
CPU time 2.27 seconds
Started Aug 10 07:26:40 PM PDT 24
Finished Aug 10 07:26:43 PM PDT 24
Peak memory 216656 kb
Host smart-09e641fa-0083-46cc-8393-9e72b3a3fc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444783364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1444783364
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1280664525
Short name T839
Test name
Test status
Simulation time 203544656 ps
CPU time 0.89 seconds
Started Aug 10 07:26:44 PM PDT 24
Finished Aug 10 07:26:45 PM PDT 24
Peak memory 206364 kb
Host smart-f8248667-b19e-4d41-b0b9-32f6610ee263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280664525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1280664525
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3773838901
Short name T579
Test name
Test status
Simulation time 35284906337 ps
CPU time 28.29 seconds
Started Aug 10 07:26:49 PM PDT 24
Finished Aug 10 07:27:18 PM PDT 24
Peak memory 240956 kb
Host smart-610a13d7-d837-4355-807d-675afccebaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773838901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3773838901
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2700912007
Short name T810
Test name
Test status
Simulation time 58129509 ps
CPU time 0.75 seconds
Started Aug 10 07:26:50 PM PDT 24
Finished Aug 10 07:26:51 PM PDT 24
Peak memory 205208 kb
Host smart-dfe0403b-8641-4773-ae79-18d3890c2be3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700912007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2700912007
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2233592727
Short name T481
Test name
Test status
Simulation time 110988577 ps
CPU time 2.71 seconds
Started Aug 10 07:26:46 PM PDT 24
Finished Aug 10 07:26:49 PM PDT 24
Peak memory 224788 kb
Host smart-1ddbd5c7-93cf-438a-af0d-ee5b3a01038d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233592727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2233592727
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3266373800
Short name T989
Test name
Test status
Simulation time 17983026 ps
CPU time 0.82 seconds
Started Aug 10 07:26:41 PM PDT 24
Finished Aug 10 07:26:42 PM PDT 24
Peak memory 206952 kb
Host smart-2b1332f2-796e-49e6-8071-7261ca091b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266373800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3266373800
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.36089950
Short name T652
Test name
Test status
Simulation time 362075564745 ps
CPU time 222.93 seconds
Started Aug 10 07:26:48 PM PDT 24
Finished Aug 10 07:30:31 PM PDT 24
Peak memory 254156 kb
Host smart-792346fd-d9d7-4dda-b4c9-422e5845b779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36089950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.36089950
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1238841298
Short name T813
Test name
Test status
Simulation time 14777349373 ps
CPU time 27.44 seconds
Started Aug 10 07:26:41 PM PDT 24
Finished Aug 10 07:27:09 PM PDT 24
Peak memory 233188 kb
Host smart-4ce75364-4a99-4250-92cd-2cbdcd153d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238841298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1238841298
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1866685083
Short name T61
Test name
Test status
Simulation time 175082072482 ps
CPU time 435.13 seconds
Started Aug 10 07:26:50 PM PDT 24
Finished Aug 10 07:34:05 PM PDT 24
Peak memory 257428 kb
Host smart-fe44620c-2186-4430-ac58-a1c9720cbc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866685083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1866685083
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.685097708
Short name T433
Test name
Test status
Simulation time 7572209073 ps
CPU time 31.51 seconds
Started Aug 10 07:26:50 PM PDT 24
Finished Aug 10 07:27:21 PM PDT 24
Peak memory 233224 kb
Host smart-e7a6e626-bbd8-404f-ae5f-01a2914af884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685097708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.685097708
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1453193855
Short name T258
Test name
Test status
Simulation time 205584072 ps
CPU time 5.46 seconds
Started Aug 10 07:26:40 PM PDT 24
Finished Aug 10 07:26:46 PM PDT 24
Peak memory 229956 kb
Host smart-e959cc64-de96-432c-9102-8693fc62d1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453193855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1453193855
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2083261887
Short name T693
Test name
Test status
Simulation time 692401813 ps
CPU time 4.9 seconds
Started Aug 10 07:26:44 PM PDT 24
Finished Aug 10 07:26:49 PM PDT 24
Peak memory 233160 kb
Host smart-532b77a9-471b-4dc8-a4f0-d0263c4f4377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083261887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2083261887
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1581391880
Short name T49
Test name
Test status
Simulation time 20196685492 ps
CPU time 11.12 seconds
Started Aug 10 07:26:46 PM PDT 24
Finished Aug 10 07:26:58 PM PDT 24
Peak memory 233128 kb
Host smart-d83cd134-32b7-4905-b239-459e43656f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581391880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1581391880
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1522248281
Short name T792
Test name
Test status
Simulation time 159577684 ps
CPU time 3.19 seconds
Started Aug 10 07:26:41 PM PDT 24
Finished Aug 10 07:26:45 PM PDT 24
Peak memory 224956 kb
Host smart-8a59918b-8776-45f6-bd06-aecc4ce4d959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522248281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1522248281
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3275444913
Short name T781
Test name
Test status
Simulation time 2142671566 ps
CPU time 3.91 seconds
Started Aug 10 07:26:40 PM PDT 24
Finished Aug 10 07:26:44 PM PDT 24
Peak memory 219868 kb
Host smart-ec36762d-5da9-4618-a33b-89c4453a97d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3275444913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3275444913
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2653614537
Short name T845
Test name
Test status
Simulation time 2941009557 ps
CPU time 16.24 seconds
Started Aug 10 07:26:50 PM PDT 24
Finished Aug 10 07:27:07 PM PDT 24
Peak memory 241436 kb
Host smart-87437c4c-88a0-4de3-ae6b-cb9360a6d402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653614537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2653614537
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.483278589
Short name T323
Test name
Test status
Simulation time 89374371098 ps
CPU time 48.35 seconds
Started Aug 10 07:26:50 PM PDT 24
Finished Aug 10 07:27:38 PM PDT 24
Peak memory 216676 kb
Host smart-4a50a1e2-228f-49e6-9cf9-5dfee738e783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483278589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.483278589
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.569375716
Short name T727
Test name
Test status
Simulation time 2470625292 ps
CPU time 5.95 seconds
Started Aug 10 07:26:40 PM PDT 24
Finished Aug 10 07:26:46 PM PDT 24
Peak memory 216752 kb
Host smart-067aa8e1-1ad9-437a-8cef-8ed0a0d64fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569375716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.569375716
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2709979604
Short name T566
Test name
Test status
Simulation time 248346608 ps
CPU time 1.52 seconds
Started Aug 10 07:26:49 PM PDT 24
Finished Aug 10 07:26:51 PM PDT 24
Peak memory 208460 kb
Host smart-2554032d-aadf-4093-aade-c5c37aa27e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709979604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2709979604
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1972333020
Short name T1009
Test name
Test status
Simulation time 197835522 ps
CPU time 0.88 seconds
Started Aug 10 07:26:46 PM PDT 24
Finished Aug 10 07:26:47 PM PDT 24
Peak memory 206288 kb
Host smart-6af8d96b-81f6-4a1e-b21c-06b97e60046e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972333020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1972333020
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.302579549
Short name T8
Test name
Test status
Simulation time 135667096 ps
CPU time 2.29 seconds
Started Aug 10 07:26:40 PM PDT 24
Finished Aug 10 07:26:43 PM PDT 24
Peak memory 224872 kb
Host smart-7eede21d-62bc-4fec-9e5a-f4d63a108fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302579549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.302579549
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2397630465
Short name T359
Test name
Test status
Simulation time 22615592 ps
CPU time 0.73 seconds
Started Aug 10 07:26:55 PM PDT 24
Finished Aug 10 07:26:55 PM PDT 24
Peak memory 205272 kb
Host smart-a0cd400c-6945-46bb-bdc4-706ba7c07445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397630465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2397630465
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1405155320
Short name T272
Test name
Test status
Simulation time 4152064512 ps
CPU time 11.58 seconds
Started Aug 10 07:26:50 PM PDT 24
Finished Aug 10 07:27:01 PM PDT 24
Peak memory 225008 kb
Host smart-7de58d65-4ea9-46b2-8b5f-11146dbdf506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405155320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1405155320
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2535121225
Short name T798
Test name
Test status
Simulation time 86984618 ps
CPU time 0.75 seconds
Started Aug 10 07:26:57 PM PDT 24
Finished Aug 10 07:26:58 PM PDT 24
Peak memory 207024 kb
Host smart-0fd79279-b02f-4c14-accb-cdcfef026342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535121225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2535121225
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2828559863
Short name T228
Test name
Test status
Simulation time 12437986026 ps
CPU time 41.77 seconds
Started Aug 10 07:26:54 PM PDT 24
Finished Aug 10 07:27:36 PM PDT 24
Peak memory 249584 kb
Host smart-e91b0aa4-5d8e-459b-8cb2-8a6022607f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828559863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2828559863
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2368950570
Short name T239
Test name
Test status
Simulation time 50720055270 ps
CPU time 95.67 seconds
Started Aug 10 07:26:51 PM PDT 24
Finished Aug 10 07:28:27 PM PDT 24
Peak memory 249928 kb
Host smart-cf847094-ca5f-48ff-82b4-e000786c2a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368950570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2368950570
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1969179149
Short name T896
Test name
Test status
Simulation time 239731387 ps
CPU time 3.07 seconds
Started Aug 10 07:26:54 PM PDT 24
Finished Aug 10 07:26:57 PM PDT 24
Peak memory 241352 kb
Host smart-fdb06670-bdc5-47ae-a5d5-145ef6d2b854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969179149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1969179149
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2558918571
Short name T947
Test name
Test status
Simulation time 5262197195 ps
CPU time 28.81 seconds
Started Aug 10 07:26:51 PM PDT 24
Finished Aug 10 07:27:19 PM PDT 24
Peak memory 256224 kb
Host smart-d6999aa5-4e96-47f0-b946-5ccaab0b96fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558918571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2558918571
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3039013152
Short name T550
Test name
Test status
Simulation time 55238504 ps
CPU time 2.99 seconds
Started Aug 10 07:26:56 PM PDT 24
Finished Aug 10 07:26:59 PM PDT 24
Peak memory 233188 kb
Host smart-e70eec60-62de-4ffc-b7b2-84082b3bd766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039013152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3039013152
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3162349314
Short name T112
Test name
Test status
Simulation time 34236548 ps
CPU time 2.52 seconds
Started Aug 10 07:26:52 PM PDT 24
Finished Aug 10 07:26:55 PM PDT 24
Peak memory 232848 kb
Host smart-08816d80-5129-4bed-b66e-3ba05e11a1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162349314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3162349314
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3479111083
Short name T815
Test name
Test status
Simulation time 2663161455 ps
CPU time 9.29 seconds
Started Aug 10 07:26:57 PM PDT 24
Finished Aug 10 07:27:06 PM PDT 24
Peak memory 224872 kb
Host smart-fd1b8994-4660-4e57-bda2-d426db71ad3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479111083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3479111083
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2927841540
Short name T731
Test name
Test status
Simulation time 878450189 ps
CPU time 4.13 seconds
Started Aug 10 07:26:49 PM PDT 24
Finished Aug 10 07:26:54 PM PDT 24
Peak memory 224940 kb
Host smart-26b50d21-ea21-4e00-bfcd-a8d3c9427998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927841540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2927841540
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3585232412
Short name T397
Test name
Test status
Simulation time 1036450274 ps
CPU time 9.04 seconds
Started Aug 10 07:26:51 PM PDT 24
Finished Aug 10 07:27:00 PM PDT 24
Peak memory 220536 kb
Host smart-d1b4b915-60ed-48dc-9c13-092ae28d7a0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3585232412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3585232412
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.428779932
Short name T15
Test name
Test status
Simulation time 201518399063 ps
CPU time 450.92 seconds
Started Aug 10 07:26:54 PM PDT 24
Finished Aug 10 07:34:26 PM PDT 24
Peak memory 257548 kb
Host smart-698783dc-d302-47c1-9913-572430aef309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428779932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.428779932
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.34007816
Short name T496
Test name
Test status
Simulation time 2151205727 ps
CPU time 6.27 seconds
Started Aug 10 07:26:53 PM PDT 24
Finished Aug 10 07:27:00 PM PDT 24
Peak memory 216776 kb
Host smart-1305b51b-3e65-426d-be8b-c084cdca7461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34007816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.34007816
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1872911043
Short name T364
Test name
Test status
Simulation time 1809890786 ps
CPU time 4.15 seconds
Started Aug 10 07:26:51 PM PDT 24
Finished Aug 10 07:26:55 PM PDT 24
Peak memory 216632 kb
Host smart-0df60632-2e78-4725-b156-ccbd92019cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872911043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1872911043
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.158497907
Short name T366
Test name
Test status
Simulation time 11110580 ps
CPU time 0.69 seconds
Started Aug 10 07:26:52 PM PDT 24
Finished Aug 10 07:26:53 PM PDT 24
Peak memory 206016 kb
Host smart-829fd4a8-0bf7-4edb-9fa8-e10d86325edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158497907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.158497907
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2592248673
Short name T876
Test name
Test status
Simulation time 115652678 ps
CPU time 0.96 seconds
Started Aug 10 07:26:52 PM PDT 24
Finished Aug 10 07:26:53 PM PDT 24
Peak memory 206712 kb
Host smart-50d45d9f-377f-458a-874e-a1290fdf695f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592248673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2592248673
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3978019353
Short name T653
Test name
Test status
Simulation time 3454470588 ps
CPU time 15.45 seconds
Started Aug 10 07:26:52 PM PDT 24
Finished Aug 10 07:27:08 PM PDT 24
Peak memory 241380 kb
Host smart-93b28ce3-0e7b-4796-bca9-c9bed205ace6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978019353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3978019353
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.806760432
Short name T70
Test name
Test status
Simulation time 40838683 ps
CPU time 0.74 seconds
Started Aug 10 07:27:11 PM PDT 24
Finished Aug 10 07:27:12 PM PDT 24
Peak memory 205244 kb
Host smart-2daed651-d756-44d5-b791-ea52c90afa68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806760432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.806760432
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2779190150
Short name T892
Test name
Test status
Simulation time 861945100 ps
CPU time 5.24 seconds
Started Aug 10 07:26:50 PM PDT 24
Finished Aug 10 07:26:55 PM PDT 24
Peak memory 233164 kb
Host smart-7cc3d140-d3db-4678-975b-836c32489fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779190150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2779190150
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1089854214
Short name T944
Test name
Test status
Simulation time 87514008 ps
CPU time 0.74 seconds
Started Aug 10 07:26:51 PM PDT 24
Finished Aug 10 07:26:52 PM PDT 24
Peak memory 205964 kb
Host smart-582b5a76-1cbd-4275-9c01-0411d175f892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089854214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1089854214
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2333043624
Short name T534
Test name
Test status
Simulation time 8595581746 ps
CPU time 54.89 seconds
Started Aug 10 07:26:57 PM PDT 24
Finished Aug 10 07:27:52 PM PDT 24
Peak memory 238968 kb
Host smart-0a0345f1-5751-4f04-a3e7-12974a85fea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333043624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2333043624
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.534955099
Short name T660
Test name
Test status
Simulation time 38315802433 ps
CPU time 225.62 seconds
Started Aug 10 07:27:10 PM PDT 24
Finished Aug 10 07:30:56 PM PDT 24
Peak memory 243960 kb
Host smart-1acd2086-fa75-4231-b0e8-ffd40111f998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534955099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.534955099
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1090619864
Short name T237
Test name
Test status
Simulation time 7628456063 ps
CPU time 51.6 seconds
Started Aug 10 07:26:58 PM PDT 24
Finished Aug 10 07:27:49 PM PDT 24
Peak memory 236156 kb
Host smart-8dcb2055-527b-439d-904e-bfd0b1c343da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090619864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1090619864
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1773271676
Short name T28
Test name
Test status
Simulation time 106007406 ps
CPU time 5.19 seconds
Started Aug 10 07:26:54 PM PDT 24
Finished Aug 10 07:26:59 PM PDT 24
Peak memory 240024 kb
Host smart-5c0d48cf-fdd1-45d8-b25e-a4332a87abd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773271676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1773271676
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.306211591
Short name T544
Test name
Test status
Simulation time 8647765999 ps
CPU time 51.64 seconds
Started Aug 10 07:26:57 PM PDT 24
Finished Aug 10 07:27:49 PM PDT 24
Peak memory 249960 kb
Host smart-40e8c6aa-593b-42fe-8b7c-b0e2d6151337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306211591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.306211591
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2331326335
Short name T884
Test name
Test status
Simulation time 3594676355 ps
CPU time 13.04 seconds
Started Aug 10 07:26:51 PM PDT 24
Finished Aug 10 07:27:04 PM PDT 24
Peak memory 224964 kb
Host smart-e978987a-7796-4598-a755-dbb5f9b726d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331326335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2331326335
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1629644899
Short name T247
Test name
Test status
Simulation time 431922662 ps
CPU time 2.36 seconds
Started Aug 10 07:26:54 PM PDT 24
Finished Aug 10 07:26:56 PM PDT 24
Peak memory 224964 kb
Host smart-2faf1e0d-e337-47df-a87f-87d752ea4673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629644899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1629644899
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3123958862
Short name T827
Test name
Test status
Simulation time 99437200 ps
CPU time 2.2 seconds
Started Aug 10 07:26:51 PM PDT 24
Finished Aug 10 07:26:53 PM PDT 24
Peak memory 232852 kb
Host smart-ee6e37e0-eb76-4dbf-82f1-d42293027f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123958862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3123958862
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.625426950
Short name T677
Test name
Test status
Simulation time 140875402 ps
CPU time 2.6 seconds
Started Aug 10 07:26:54 PM PDT 24
Finished Aug 10 07:26:57 PM PDT 24
Peak memory 224880 kb
Host smart-03f63282-2fc3-4cbe-8752-ac799c5f4a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625426950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.625426950
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1360532746
Short name T651
Test name
Test status
Simulation time 843958174 ps
CPU time 5.5 seconds
Started Aug 10 07:26:59 PM PDT 24
Finished Aug 10 07:27:04 PM PDT 24
Peak memory 223512 kb
Host smart-41e1c602-a75f-4e36-816c-e53ead19f171
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1360532746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1360532746
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1014161437
Short name T942
Test name
Test status
Simulation time 40905662 ps
CPU time 0.99 seconds
Started Aug 10 07:26:57 PM PDT 24
Finished Aug 10 07:26:59 PM PDT 24
Peak memory 207288 kb
Host smart-18e9610c-1f06-4ec9-b358-03d04a648e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014161437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1014161437
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3401645770
Short name T420
Test name
Test status
Simulation time 11599704747 ps
CPU time 6.86 seconds
Started Aug 10 07:26:58 PM PDT 24
Finished Aug 10 07:27:05 PM PDT 24
Peak memory 219948 kb
Host smart-06601b33-9dfa-4b7a-907a-b456e4e74454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401645770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3401645770
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2483188381
Short name T462
Test name
Test status
Simulation time 57585273672 ps
CPU time 11.75 seconds
Started Aug 10 07:26:57 PM PDT 24
Finished Aug 10 07:27:09 PM PDT 24
Peak memory 216708 kb
Host smart-b0412b26-8c0b-457e-92d5-2bfb4736e460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483188381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2483188381
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1582521662
Short name T427
Test name
Test status
Simulation time 14704264 ps
CPU time 0.83 seconds
Started Aug 10 07:26:51 PM PDT 24
Finished Aug 10 07:26:52 PM PDT 24
Peak memory 206948 kb
Host smart-f95bcc69-7c01-45f4-9fe1-29e8d6bc204a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582521662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1582521662
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4078229505
Short name T886
Test name
Test status
Simulation time 10898501 ps
CPU time 0.7 seconds
Started Aug 10 07:26:50 PM PDT 24
Finished Aug 10 07:26:51 PM PDT 24
Peak memory 206044 kb
Host smart-f25c9427-b89d-49f2-82fe-f5aa3b0b0b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078229505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4078229505
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.400694599
Short name T987
Test name
Test status
Simulation time 976706361 ps
CPU time 5.44 seconds
Started Aug 10 07:26:51 PM PDT 24
Finished Aug 10 07:26:57 PM PDT 24
Peak memory 233092 kb
Host smart-a1c54adc-fe79-4f2e-b67a-54682a615323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400694599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.400694599
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3347021599
Short name T573
Test name
Test status
Simulation time 18897813 ps
CPU time 0.72 seconds
Started Aug 10 07:27:10 PM PDT 24
Finished Aug 10 07:27:10 PM PDT 24
Peak memory 205844 kb
Host smart-cc49ad81-4a6f-41c5-b397-9332b1ba6641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347021599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3347021599
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1793993347
Short name T386
Test name
Test status
Simulation time 1593846896 ps
CPU time 5.76 seconds
Started Aug 10 07:26:57 PM PDT 24
Finished Aug 10 07:27:03 PM PDT 24
Peak memory 225000 kb
Host smart-8e40ba5e-0ecf-47cc-9237-b704ab8416aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793993347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1793993347
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.4050477594
Short name T485
Test name
Test status
Simulation time 14531958 ps
CPU time 0.82 seconds
Started Aug 10 07:27:11 PM PDT 24
Finished Aug 10 07:27:12 PM PDT 24
Peak memory 207324 kb
Host smart-545de850-8529-4e16-8b97-0ab0273a3d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050477594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4050477594
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3576701157
Short name T718
Test name
Test status
Simulation time 22463910 ps
CPU time 0.79 seconds
Started Aug 10 07:27:10 PM PDT 24
Finished Aug 10 07:27:10 PM PDT 24
Peak memory 216336 kb
Host smart-4ebba994-b3a3-4884-ac2a-369f12edd3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576701157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3576701157
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2876429016
Short name T861
Test name
Test status
Simulation time 97719325112 ps
CPU time 254.66 seconds
Started Aug 10 07:27:11 PM PDT 24
Finished Aug 10 07:31:26 PM PDT 24
Peak memory 266020 kb
Host smart-6c0fd125-a91a-4ca5-9e82-b35bfd854c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876429016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2876429016
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.174050949
Short name T194
Test name
Test status
Simulation time 31544359083 ps
CPU time 58.58 seconds
Started Aug 10 07:26:59 PM PDT 24
Finished Aug 10 07:27:57 PM PDT 24
Peak memory 264620 kb
Host smart-b3d885e0-caab-426f-889f-37b2e7f39a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174050949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.174050949
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.162397489
Short name T391
Test name
Test status
Simulation time 289684006 ps
CPU time 3.88 seconds
Started Aug 10 07:26:58 PM PDT 24
Finished Aug 10 07:27:02 PM PDT 24
Peak memory 241264 kb
Host smart-8945d710-6e0d-4d3c-b839-b45b353e55f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162397489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.162397489
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.605869142
Short name T711
Test name
Test status
Simulation time 19054632241 ps
CPU time 123.34 seconds
Started Aug 10 07:26:56 PM PDT 24
Finished Aug 10 07:29:00 PM PDT 24
Peak memory 249864 kb
Host smart-bf53a399-1d81-4288-ade9-0c6d8bcf1ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605869142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.605869142
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2424445765
Short name T684
Test name
Test status
Simulation time 336968348 ps
CPU time 5.42 seconds
Started Aug 10 07:26:56 PM PDT 24
Finished Aug 10 07:27:01 PM PDT 24
Peak memory 233136 kb
Host smart-6f71a102-736d-46e4-b44b-a9837aeaf7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424445765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2424445765
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3633869053
Short name T465
Test name
Test status
Simulation time 3810928806 ps
CPU time 45.47 seconds
Started Aug 10 07:26:59 PM PDT 24
Finished Aug 10 07:27:44 PM PDT 24
Peak memory 249556 kb
Host smart-7491bd6f-06cb-401b-9d23-4e2d229fe08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633869053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3633869053
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3942394341
Short name T274
Test name
Test status
Simulation time 45430208636 ps
CPU time 9.46 seconds
Started Aug 10 07:26:59 PM PDT 24
Finished Aug 10 07:27:08 PM PDT 24
Peak memory 224964 kb
Host smart-6cdaf2b4-a6e3-47d3-b97b-c0f85ab438a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942394341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3942394341
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.270281142
Short name T862
Test name
Test status
Simulation time 52782916433 ps
CPU time 36.89 seconds
Started Aug 10 07:26:57 PM PDT 24
Finished Aug 10 07:27:34 PM PDT 24
Peak memory 233112 kb
Host smart-678e3601-3c09-4cb1-a233-b82cc9bfb00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270281142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.270281142
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3658421792
Short name T591
Test name
Test status
Simulation time 193595700 ps
CPU time 3.84 seconds
Started Aug 10 07:26:59 PM PDT 24
Finished Aug 10 07:27:02 PM PDT 24
Peak memory 221056 kb
Host smart-c3bb22b7-1761-40e0-bd00-e251c67afcc9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3658421792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3658421792
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2009379533
Short name T435
Test name
Test status
Simulation time 704116779 ps
CPU time 8.19 seconds
Started Aug 10 07:26:55 PM PDT 24
Finished Aug 10 07:27:04 PM PDT 24
Peak memory 216832 kb
Host smart-869fed66-a8dc-41a6-a1ea-5f6742e8448e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009379533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2009379533
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2634734935
Short name T438
Test name
Test status
Simulation time 10214790858 ps
CPU time 6.2 seconds
Started Aug 10 07:26:57 PM PDT 24
Finished Aug 10 07:27:03 PM PDT 24
Peak memory 216600 kb
Host smart-3b3d4239-1929-46f4-acc2-094bbe211842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634734935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2634734935
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.708976740
Short name T416
Test name
Test status
Simulation time 96406623 ps
CPU time 1.09 seconds
Started Aug 10 07:26:57 PM PDT 24
Finished Aug 10 07:26:59 PM PDT 24
Peak memory 207424 kb
Host smart-c376f66e-d6ff-44d3-a465-c32f57c9d4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708976740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.708976740
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3539644494
Short name T482
Test name
Test status
Simulation time 39128079 ps
CPU time 0.8 seconds
Started Aug 10 07:26:57 PM PDT 24
Finished Aug 10 07:26:58 PM PDT 24
Peak memory 206360 kb
Host smart-a60f75d6-48f5-403a-9648-89e5203fdd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539644494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3539644494
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2181376895
Short name T873
Test name
Test status
Simulation time 78972376 ps
CPU time 2.89 seconds
Started Aug 10 07:26:56 PM PDT 24
Finished Aug 10 07:26:59 PM PDT 24
Peak memory 233220 kb
Host smart-d9ad932f-9bfb-4d8b-a696-5d38f2570164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181376895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2181376895
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.461928232
Short name T603
Test name
Test status
Simulation time 15490138 ps
CPU time 0.72 seconds
Started Aug 10 07:27:06 PM PDT 24
Finished Aug 10 07:27:07 PM PDT 24
Peak memory 205284 kb
Host smart-f8c975fd-f207-44e8-a006-78a1800a4ad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461928232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.461928232
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3812366337
Short name T851
Test name
Test status
Simulation time 3555852906 ps
CPU time 32.04 seconds
Started Aug 10 07:27:07 PM PDT 24
Finished Aug 10 07:27:39 PM PDT 24
Peak memory 224972 kb
Host smart-446f2ced-cd37-4214-8ad8-5c7080dbed1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812366337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3812366337
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2985421155
Short name T743
Test name
Test status
Simulation time 14739372 ps
CPU time 0.77 seconds
Started Aug 10 07:27:10 PM PDT 24
Finished Aug 10 07:27:11 PM PDT 24
Peak memory 206300 kb
Host smart-4c4992f3-f7e2-4623-828e-9df48bdcb812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985421155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2985421155
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1723910076
Short name T659
Test name
Test status
Simulation time 94338444975 ps
CPU time 165.42 seconds
Started Aug 10 07:27:07 PM PDT 24
Finished Aug 10 07:29:52 PM PDT 24
Peak memory 253888 kb
Host smart-3e69ac02-12b8-4d3c-b84e-82197aa12ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723910076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1723910076
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3676164469
Short name T733
Test name
Test status
Simulation time 7553554084 ps
CPU time 75.09 seconds
Started Aug 10 07:27:09 PM PDT 24
Finished Aug 10 07:28:24 PM PDT 24
Peak memory 249624 kb
Host smart-4cb8167a-8575-4d36-8e6b-a4bde497ba4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676164469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3676164469
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1906872194
Short name T722
Test name
Test status
Simulation time 36852590186 ps
CPU time 218.29 seconds
Started Aug 10 07:27:06 PM PDT 24
Finished Aug 10 07:30:45 PM PDT 24
Peak memory 273400 kb
Host smart-f31489ab-f453-43ab-823a-bee9d72d76f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906872194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1906872194
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.709395554
Short name T150
Test name
Test status
Simulation time 475715266 ps
CPU time 4.91 seconds
Started Aug 10 07:27:07 PM PDT 24
Finished Aug 10 07:27:12 PM PDT 24
Peak memory 233192 kb
Host smart-678826ad-5f80-4ae5-bf80-6f8ebce3f1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709395554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.709395554
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3772344941
Short name T287
Test name
Test status
Simulation time 179907659526 ps
CPU time 487.71 seconds
Started Aug 10 07:27:08 PM PDT 24
Finished Aug 10 07:35:15 PM PDT 24
Peak memory 272180 kb
Host smart-d385d9d6-ffa0-4d06-bfb6-05edfc01ac6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772344941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3772344941
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2861161803
Short name T767
Test name
Test status
Simulation time 30833090 ps
CPU time 2.36 seconds
Started Aug 10 07:27:10 PM PDT 24
Finished Aug 10 07:27:12 PM PDT 24
Peak memory 232780 kb
Host smart-8bdbe544-b215-4229-a108-2897bea39584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861161803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2861161803
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1553528738
Short name T600
Test name
Test status
Simulation time 16508055952 ps
CPU time 39.55 seconds
Started Aug 10 07:27:06 PM PDT 24
Finished Aug 10 07:27:46 PM PDT 24
Peak memory 225044 kb
Host smart-c7a34ea1-1a89-4333-99e1-249ac8bea772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553528738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1553528738
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3573969277
Short name T841
Test name
Test status
Simulation time 193667786 ps
CPU time 2.64 seconds
Started Aug 10 07:27:05 PM PDT 24
Finished Aug 10 07:27:08 PM PDT 24
Peak memory 232916 kb
Host smart-9b290883-40bb-4a38-8d7a-a5777510569f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573969277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3573969277
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.415884627
Short name T914
Test name
Test status
Simulation time 6495370250 ps
CPU time 4.6 seconds
Started Aug 10 07:27:06 PM PDT 24
Finished Aug 10 07:27:10 PM PDT 24
Peak memory 224860 kb
Host smart-91d55e09-6325-4170-ba8c-d5e0450b2d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415884627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.415884627
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2731578240
Short name T860
Test name
Test status
Simulation time 234446996 ps
CPU time 3.91 seconds
Started Aug 10 07:27:08 PM PDT 24
Finished Aug 10 07:27:12 PM PDT 24
Peak memory 221040 kb
Host smart-9d645de5-81e2-479c-b0c7-2a5d1f526285
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2731578240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2731578240
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2158831808
Short name T295
Test name
Test status
Simulation time 18388096957 ps
CPU time 109.71 seconds
Started Aug 10 07:27:09 PM PDT 24
Finished Aug 10 07:28:59 PM PDT 24
Peak memory 257528 kb
Host smart-399b98e1-842d-48df-b1df-7764be9f5054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158831808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2158831808
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2657171624
Short name T637
Test name
Test status
Simulation time 17420550832 ps
CPU time 31.91 seconds
Started Aug 10 07:27:09 PM PDT 24
Finished Aug 10 07:27:41 PM PDT 24
Peak memory 216724 kb
Host smart-a9e55508-aa8b-49bf-a90c-5541f018171c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657171624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2657171624
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3387803565
Short name T479
Test name
Test status
Simulation time 41488650 ps
CPU time 0.74 seconds
Started Aug 10 07:27:11 PM PDT 24
Finished Aug 10 07:27:12 PM PDT 24
Peak memory 205984 kb
Host smart-185b2fe9-b072-44e9-b37e-3baea1cf41d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387803565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3387803565
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1211507543
Short name T350
Test name
Test status
Simulation time 291346572 ps
CPU time 1.36 seconds
Started Aug 10 07:27:05 PM PDT 24
Finished Aug 10 07:27:07 PM PDT 24
Peak memory 216664 kb
Host smart-f504cf92-8a45-412d-a715-36ac972bcdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211507543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1211507543
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2768490618
Short name T365
Test name
Test status
Simulation time 51064250 ps
CPU time 0.72 seconds
Started Aug 10 07:27:08 PM PDT 24
Finished Aug 10 07:27:09 PM PDT 24
Peak memory 206292 kb
Host smart-6f4d0888-26cd-4dd1-adc7-90e613aec039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768490618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2768490618
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4175162661
Short name T217
Test name
Test status
Simulation time 3681461883 ps
CPU time 7.57 seconds
Started Aug 10 07:27:07 PM PDT 24
Finished Aug 10 07:27:15 PM PDT 24
Peak memory 233148 kb
Host smart-9020f044-65e5-4b87-b31c-4624db9efa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175162661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4175162661
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.4201993198
Short name T902
Test name
Test status
Simulation time 35287510 ps
CPU time 0.72 seconds
Started Aug 10 07:27:08 PM PDT 24
Finished Aug 10 07:27:09 PM PDT 24
Peak memory 205820 kb
Host smart-6fc860b2-bde4-4154-af71-8119e435a830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201993198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
4201993198
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2404602054
Short name T459
Test name
Test status
Simulation time 266271896 ps
CPU time 6.44 seconds
Started Aug 10 07:27:05 PM PDT 24
Finished Aug 10 07:27:12 PM PDT 24
Peak memory 233120 kb
Host smart-f8e3ff5c-1bf6-4081-93ab-ee237614b49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404602054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2404602054
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3556612254
Short name T894
Test name
Test status
Simulation time 38221114 ps
CPU time 0.79 seconds
Started Aug 10 07:27:07 PM PDT 24
Finished Aug 10 07:27:07 PM PDT 24
Peak memory 206964 kb
Host smart-d1a2485d-b5e1-49f6-b643-9a2f809d2983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556612254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3556612254
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3172061935
Short name T284
Test name
Test status
Simulation time 526638961 ps
CPU time 7.15 seconds
Started Aug 10 07:27:09 PM PDT 24
Finished Aug 10 07:27:17 PM PDT 24
Peak memory 234224 kb
Host smart-7b9f12e7-7d26-47b9-888f-dfff809ee3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172061935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3172061935
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.32069398
Short name T133
Test name
Test status
Simulation time 10508065205 ps
CPU time 49.4 seconds
Started Aug 10 07:27:05 PM PDT 24
Finished Aug 10 07:27:54 PM PDT 24
Peak memory 241472 kb
Host smart-96843c5c-88d6-464a-939a-1ba7c2adf21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32069398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.32069398
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.241244154
Short name T847
Test name
Test status
Simulation time 7995869841 ps
CPU time 76.69 seconds
Started Aug 10 07:27:10 PM PDT 24
Finished Aug 10 07:28:26 PM PDT 24
Peak memory 250044 kb
Host smart-3bf61bd8-c466-4cf4-a85c-7e8d389980e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241244154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.241244154
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.595674486
Short name T305
Test name
Test status
Simulation time 919672977 ps
CPU time 18.88 seconds
Started Aug 10 07:27:07 PM PDT 24
Finished Aug 10 07:27:26 PM PDT 24
Peak memory 233180 kb
Host smart-c3187ddb-3ea4-4074-9500-4f2ed678e220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595674486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.595674486
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.4070996555
Short name T423
Test name
Test status
Simulation time 23385822524 ps
CPU time 167.88 seconds
Started Aug 10 07:27:11 PM PDT 24
Finished Aug 10 07:29:59 PM PDT 24
Peak memory 250636 kb
Host smart-c93f2ce3-ed4d-4bb2-af10-e94f32e82480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070996555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.4070996555
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4058406899
Short name T746
Test name
Test status
Simulation time 816250747 ps
CPU time 5.5 seconds
Started Aug 10 07:27:09 PM PDT 24
Finished Aug 10 07:27:14 PM PDT 24
Peak memory 233136 kb
Host smart-0335a4e5-3861-48aa-8011-1541c7d6efe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058406899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4058406899
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1619825693
Short name T850
Test name
Test status
Simulation time 22010362444 ps
CPU time 50.67 seconds
Started Aug 10 07:27:09 PM PDT 24
Finished Aug 10 07:28:00 PM PDT 24
Peak memory 241160 kb
Host smart-f72dc3e4-22b1-46da-97af-91c935c98ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619825693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1619825693
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1748817440
Short name T519
Test name
Test status
Simulation time 60424966872 ps
CPU time 9.99 seconds
Started Aug 10 07:27:07 PM PDT 24
Finished Aug 10 07:27:17 PM PDT 24
Peak memory 224960 kb
Host smart-788d2317-cf75-4f06-8c07-9c9decf17b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748817440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1748817440
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1079431665
Short name T199
Test name
Test status
Simulation time 5470334861 ps
CPU time 16.45 seconds
Started Aug 10 07:27:07 PM PDT 24
Finished Aug 10 07:27:23 PM PDT 24
Peak memory 224868 kb
Host smart-a1bc305a-59dc-4669-a7be-8987b82cefed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079431665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1079431665
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1498923991
Short name T938
Test name
Test status
Simulation time 493169312 ps
CPU time 6.75 seconds
Started Aug 10 07:27:09 PM PDT 24
Finished Aug 10 07:27:16 PM PDT 24
Peak memory 222448 kb
Host smart-b1450526-b0de-4b8f-abd9-d2d606d6b516
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1498923991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1498923991
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3248700082
Short name T140
Test name
Test status
Simulation time 50559564527 ps
CPU time 193.01 seconds
Started Aug 10 07:27:05 PM PDT 24
Finished Aug 10 07:30:19 PM PDT 24
Peak memory 264692 kb
Host smart-8b2d5579-7bbe-4e48-99e5-f10c2c8d7081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248700082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3248700082
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2094179070
Short name T774
Test name
Test status
Simulation time 2728279110 ps
CPU time 8.25 seconds
Started Aug 10 07:27:08 PM PDT 24
Finished Aug 10 07:27:16 PM PDT 24
Peak memory 219776 kb
Host smart-62983859-b4de-4724-b62d-d6af1b19ad48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094179070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2094179070
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1153488647
Short name T732
Test name
Test status
Simulation time 10710026695 ps
CPU time 12.22 seconds
Started Aug 10 07:27:08 PM PDT 24
Finished Aug 10 07:27:21 PM PDT 24
Peak memory 216620 kb
Host smart-7f954e81-ed37-4ba6-bad7-6bb709c7fb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153488647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1153488647
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1108835140
Short name T567
Test name
Test status
Simulation time 173187617 ps
CPU time 1.35 seconds
Started Aug 10 07:27:06 PM PDT 24
Finished Aug 10 07:27:07 PM PDT 24
Peak memory 216696 kb
Host smart-51cdffc3-59eb-46e6-b796-7b806eeb5abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108835140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1108835140
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2436276328
Short name T346
Test name
Test status
Simulation time 75597229 ps
CPU time 0.97 seconds
Started Aug 10 07:27:07 PM PDT 24
Finished Aug 10 07:27:08 PM PDT 24
Peak memory 207324 kb
Host smart-aa9d4f7a-0a40-4fc6-b473-dd443890b6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436276328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2436276328
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1026145851
Short name T648
Test name
Test status
Simulation time 1635243073 ps
CPU time 7.86 seconds
Started Aug 10 07:27:07 PM PDT 24
Finished Aug 10 07:27:15 PM PDT 24
Peak memory 224932 kb
Host smart-b4b01de3-e9ff-4d02-9604-43979dddc0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026145851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1026145851
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4144924077
Short name T495
Test name
Test status
Simulation time 13627855 ps
CPU time 0.7 seconds
Started Aug 10 07:27:16 PM PDT 24
Finished Aug 10 07:27:17 PM PDT 24
Peak memory 205824 kb
Host smart-d98022c6-18e1-4976-8a84-3a152737a3c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144924077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4144924077
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.729027516
Short name T564
Test name
Test status
Simulation time 37659473 ps
CPU time 2.46 seconds
Started Aug 10 07:27:18 PM PDT 24
Finished Aug 10 07:27:21 PM PDT 24
Peak memory 233112 kb
Host smart-1549b8ae-b685-4a63-bc71-8d2984520738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729027516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.729027516
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1330760691
Short name T932
Test name
Test status
Simulation time 64272220 ps
CPU time 0.8 seconds
Started Aug 10 07:27:06 PM PDT 24
Finished Aug 10 07:27:07 PM PDT 24
Peak memory 206972 kb
Host smart-f3183b01-01c6-4cc7-af37-33ef1fa5d767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330760691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1330760691
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3758698970
Short name T735
Test name
Test status
Simulation time 10513782854 ps
CPU time 52.65 seconds
Started Aug 10 07:27:16 PM PDT 24
Finished Aug 10 07:28:09 PM PDT 24
Peak memory 249556 kb
Host smart-933b5ee5-24c5-4968-b1fa-cbba65ab2ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758698970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3758698970
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2476044167
Short name T737
Test name
Test status
Simulation time 18503200216 ps
CPU time 148.96 seconds
Started Aug 10 07:27:13 PM PDT 24
Finished Aug 10 07:29:42 PM PDT 24
Peak memory 250248 kb
Host smart-ff31e0f9-5e47-4e78-96f4-824f9c3830e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476044167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2476044167
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2870711046
Short name T908
Test name
Test status
Simulation time 15967730992 ps
CPU time 178.6 seconds
Started Aug 10 07:27:17 PM PDT 24
Finished Aug 10 07:30:16 PM PDT 24
Peak memory 253424 kb
Host smart-3f470844-4fe1-4fda-a151-b6b0dd0242cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870711046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2870711046
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1172782017
Short name T310
Test name
Test status
Simulation time 445435813 ps
CPU time 8.85 seconds
Started Aug 10 07:27:14 PM PDT 24
Finished Aug 10 07:27:23 PM PDT 24
Peak memory 224936 kb
Host smart-3fd8235a-266f-46f9-abeb-fcf002045955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172782017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1172782017
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1706815067
Short name T183
Test name
Test status
Simulation time 55347815031 ps
CPU time 107.4 seconds
Started Aug 10 07:27:12 PM PDT 24
Finished Aug 10 07:29:00 PM PDT 24
Peak memory 249600 kb
Host smart-d9453c16-7850-4dc2-8b61-5379e18cb3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706815067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1706815067
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1718897491
Short name T982
Test name
Test status
Simulation time 5666743138 ps
CPU time 13.51 seconds
Started Aug 10 07:27:15 PM PDT 24
Finished Aug 10 07:27:29 PM PDT 24
Peak memory 233268 kb
Host smart-4c777697-62f6-4ec2-9129-b15365fa3c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718897491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1718897491
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.28734523
Short name T821
Test name
Test status
Simulation time 378849397 ps
CPU time 6.95 seconds
Started Aug 10 07:27:16 PM PDT 24
Finished Aug 10 07:27:23 PM PDT 24
Peak memory 224820 kb
Host smart-6024d59b-b519-43ad-920a-610a83e3f679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28734523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.28734523
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2734379141
Short name T293
Test name
Test status
Simulation time 754924347 ps
CPU time 5.93 seconds
Started Aug 10 07:27:15 PM PDT 24
Finished Aug 10 07:27:21 PM PDT 24
Peak memory 233184 kb
Host smart-82ca8b55-f7e1-41c6-b4db-27d9e3dd3cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734379141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2734379141
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2211998987
Short name T238
Test name
Test status
Simulation time 1544963405 ps
CPU time 5.59 seconds
Started Aug 10 07:27:15 PM PDT 24
Finished Aug 10 07:27:20 PM PDT 24
Peak memory 224940 kb
Host smart-ffee3cad-c8ce-4884-8429-b76e28842360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211998987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2211998987
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3045178431
Short name T964
Test name
Test status
Simulation time 8432032702 ps
CPU time 24.52 seconds
Started Aug 10 07:27:13 PM PDT 24
Finished Aug 10 07:27:38 PM PDT 24
Peak memory 219892 kb
Host smart-4b8ff2e5-9c9e-4b3e-8822-6a6ac3a013f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3045178431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3045178431
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3559426797
Short name T638
Test name
Test status
Simulation time 55130688 ps
CPU time 0.71 seconds
Started Aug 10 07:27:13 PM PDT 24
Finished Aug 10 07:27:14 PM PDT 24
Peak memory 205988 kb
Host smart-6d64cfaf-6e3d-41f6-aabc-7308e2a73f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559426797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3559426797
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.606592569
Short name T400
Test name
Test status
Simulation time 14215862444 ps
CPU time 11.86 seconds
Started Aug 10 07:27:06 PM PDT 24
Finished Aug 10 07:27:18 PM PDT 24
Peak memory 216700 kb
Host smart-d912cf1c-864a-4933-b204-bd1c987d2ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606592569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.606592569
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2278416810
Short name T552
Test name
Test status
Simulation time 186046359 ps
CPU time 1.09 seconds
Started Aug 10 07:27:16 PM PDT 24
Finished Aug 10 07:27:17 PM PDT 24
Peak memory 208012 kb
Host smart-438ae1a0-c2be-4e58-b920-80453924e1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278416810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2278416810
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.500527414
Short name T783
Test name
Test status
Simulation time 89957884 ps
CPU time 0.94 seconds
Started Aug 10 07:27:12 PM PDT 24
Finished Aug 10 07:27:13 PM PDT 24
Peak memory 206300 kb
Host smart-1cd5c55e-8f93-4d5d-b8c9-aaf3494e5df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500527414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.500527414
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2204304702
Short name T165
Test name
Test status
Simulation time 331902870 ps
CPU time 2.85 seconds
Started Aug 10 07:27:17 PM PDT 24
Finished Aug 10 07:27:20 PM PDT 24
Peak memory 233052 kb
Host smart-daa3f172-c9b0-406b-8a2b-63ab26cd90db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204304702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2204304702
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3490715580
Short name T837
Test name
Test status
Simulation time 18706029 ps
CPU time 0.71 seconds
Started Aug 10 07:27:23 PM PDT 24
Finished Aug 10 07:27:24 PM PDT 24
Peak memory 205840 kb
Host smart-5c606161-5adb-4ff1-bd19-3e486e45a767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490715580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3490715580
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3545936257
Short name T505
Test name
Test status
Simulation time 886893333 ps
CPU time 11.18 seconds
Started Aug 10 07:27:15 PM PDT 24
Finished Aug 10 07:27:26 PM PDT 24
Peak memory 233160 kb
Host smart-255911d8-ac2c-47f3-8870-f773f006dbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545936257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3545936257
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.513669437
Short name T682
Test name
Test status
Simulation time 145648555 ps
CPU time 0.73 seconds
Started Aug 10 07:27:14 PM PDT 24
Finished Aug 10 07:27:15 PM PDT 24
Peak memory 207272 kb
Host smart-3f8aa404-a327-4f28-94a4-9e399e22d5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513669437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.513669437
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2897522795
Short name T701
Test name
Test status
Simulation time 12159002647 ps
CPU time 61.5 seconds
Started Aug 10 07:27:27 PM PDT 24
Finished Aug 10 07:28:28 PM PDT 24
Peak memory 249612 kb
Host smart-587ac8d9-4ce8-4fa3-aebf-06da9d1898be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897522795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2897522795
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2410314233
Short name T521
Test name
Test status
Simulation time 22885351487 ps
CPU time 179.02 seconds
Started Aug 10 07:27:22 PM PDT 24
Finished Aug 10 07:30:21 PM PDT 24
Peak memory 255572 kb
Host smart-a7e4ce2c-83b6-49bc-b86b-941722370830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410314233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2410314233
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.960952313
Short name T357
Test name
Test status
Simulation time 24743018 ps
CPU time 0.83 seconds
Started Aug 10 07:27:19 PM PDT 24
Finished Aug 10 07:27:20 PM PDT 24
Peak memory 217348 kb
Host smart-8a009108-165b-47c1-b065-831cd822eaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960952313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.960952313
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.74322979
Short name T769
Test name
Test status
Simulation time 346357694 ps
CPU time 8.25 seconds
Started Aug 10 07:27:14 PM PDT 24
Finished Aug 10 07:27:22 PM PDT 24
Peak memory 224964 kb
Host smart-7f3a884a-2939-42c9-a016-299434d2744a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74322979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.74322979
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3756505974
Short name T193
Test name
Test status
Simulation time 1562871663 ps
CPU time 34.52 seconds
Started Aug 10 07:27:19 PM PDT 24
Finished Aug 10 07:27:53 PM PDT 24
Peak memory 256588 kb
Host smart-51747538-3cda-4f5f-ad4c-7e5f56bd689d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756505974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3756505974
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3583295473
Short name T422
Test name
Test status
Simulation time 1286900191 ps
CPU time 7.76 seconds
Started Aug 10 07:27:16 PM PDT 24
Finished Aug 10 07:27:24 PM PDT 24
Peak memory 233152 kb
Host smart-cbd80ec5-3169-48f8-b840-fb5e7205c555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583295473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3583295473
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1252753411
Short name T918
Test name
Test status
Simulation time 648072408 ps
CPU time 2.33 seconds
Started Aug 10 07:27:13 PM PDT 24
Finished Aug 10 07:27:16 PM PDT 24
Peak memory 233204 kb
Host smart-b932f192-b651-4304-bf67-cca5f5eff55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252753411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1252753411
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1276819134
Short name T278
Test name
Test status
Simulation time 1207003959 ps
CPU time 8.9 seconds
Started Aug 10 07:27:16 PM PDT 24
Finished Aug 10 07:27:25 PM PDT 24
Peak memory 233032 kb
Host smart-973f8485-6664-4d19-b39f-4ebd0d5057b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276819134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1276819134
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.843742063
Short name T203
Test name
Test status
Simulation time 9014174738 ps
CPU time 7.35 seconds
Started Aug 10 07:27:14 PM PDT 24
Finished Aug 10 07:27:21 PM PDT 24
Peak memory 224992 kb
Host smart-3ea9f334-589c-4ade-862d-2847a285d50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843742063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.843742063
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.873267597
Short name T499
Test name
Test status
Simulation time 197764931 ps
CPU time 5.34 seconds
Started Aug 10 07:27:16 PM PDT 24
Finished Aug 10 07:27:21 PM PDT 24
Peak memory 219404 kb
Host smart-50b88647-99c6-4f05-aeb4-75e1272cbb7a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=873267597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.873267597
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3493372772
Short name T157
Test name
Test status
Simulation time 26759690388 ps
CPU time 233.35 seconds
Started Aug 10 07:27:23 PM PDT 24
Finished Aug 10 07:31:16 PM PDT 24
Peak memory 240924 kb
Host smart-12c35a46-414e-4dec-a30d-5b990594c42d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493372772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3493372772
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1550632383
Short name T383
Test name
Test status
Simulation time 1311976030 ps
CPU time 13.78 seconds
Started Aug 10 07:27:14 PM PDT 24
Finished Aug 10 07:27:28 PM PDT 24
Peak memory 216940 kb
Host smart-c83323b7-9b50-4fe8-af4c-068c365cb3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550632383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1550632383
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3436587619
Short name T729
Test name
Test status
Simulation time 11804329191 ps
CPU time 14.31 seconds
Started Aug 10 07:27:15 PM PDT 24
Finished Aug 10 07:27:29 PM PDT 24
Peak memory 216732 kb
Host smart-038f2511-021f-4f44-aaf4-c689530c5324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436587619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3436587619
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3945913356
Short name T571
Test name
Test status
Simulation time 70796846 ps
CPU time 0.77 seconds
Started Aug 10 07:27:14 PM PDT 24
Finished Aug 10 07:27:14 PM PDT 24
Peak memory 206412 kb
Host smart-7e0b26ed-1090-4f0c-a1c5-d38dad40b993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945913356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3945913356
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.381353915
Short name T865
Test name
Test status
Simulation time 106279717 ps
CPU time 0.76 seconds
Started Aug 10 07:27:14 PM PDT 24
Finished Aug 10 07:27:15 PM PDT 24
Peak memory 206376 kb
Host smart-f9b60951-ccc5-4969-bbde-0de4dd125d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381353915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.381353915
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2945774555
Short name T501
Test name
Test status
Simulation time 3317201605 ps
CPU time 15.02 seconds
Started Aug 10 07:27:18 PM PDT 24
Finished Aug 10 07:27:33 PM PDT 24
Peak memory 234164 kb
Host smart-4633f260-559e-417c-9afc-756fa41b28ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945774555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2945774555
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.4290071311
Short name T973
Test name
Test status
Simulation time 13042080 ps
CPU time 0.71 seconds
Started Aug 10 07:24:45 PM PDT 24
Finished Aug 10 07:24:46 PM PDT 24
Peak memory 205724 kb
Host smart-ec6da5fd-cd2b-46c0-937c-5fb542d87555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290071311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.4
290071311
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1096042344
Short name T688
Test name
Test status
Simulation time 790245795 ps
CPU time 7.12 seconds
Started Aug 10 07:24:47 PM PDT 24
Finished Aug 10 07:24:54 PM PDT 24
Peak memory 224868 kb
Host smart-1a5fa5ed-f8a6-4acf-8ef2-e58d75aae9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096042344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1096042344
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3973964582
Short name T689
Test name
Test status
Simulation time 18757312 ps
CPU time 0.82 seconds
Started Aug 10 07:24:44 PM PDT 24
Finished Aug 10 07:24:45 PM PDT 24
Peak memory 207016 kb
Host smart-e8235c65-cd63-4a34-9e6d-6e655dbe5058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973964582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3973964582
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.127524019
Short name T963
Test name
Test status
Simulation time 11602585801 ps
CPU time 108.25 seconds
Started Aug 10 07:24:46 PM PDT 24
Finished Aug 10 07:26:34 PM PDT 24
Peak memory 265000 kb
Host smart-a64e9f4b-e65e-4514-99f0-25a863e14ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127524019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.127524019
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3739976618
Short name T252
Test name
Test status
Simulation time 3307761524 ps
CPU time 37.51 seconds
Started Aug 10 07:24:47 PM PDT 24
Finished Aug 10 07:25:25 PM PDT 24
Peak memory 233204 kb
Host smart-6c727adf-8381-4e49-bb29-802f2186024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739976618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3739976618
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.477506718
Short name T312
Test name
Test status
Simulation time 79927909316 ps
CPU time 89.1 seconds
Started Aug 10 07:24:46 PM PDT 24
Finished Aug 10 07:26:15 PM PDT 24
Peak memory 252636 kb
Host smart-4b370614-6ea4-4338-8be3-bc33d64eaa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477506718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
477506718
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3310433158
Short name T983
Test name
Test status
Simulation time 1086834219 ps
CPU time 10.28 seconds
Started Aug 10 07:24:47 PM PDT 24
Finished Aug 10 07:24:57 PM PDT 24
Peak memory 249488 kb
Host smart-6f40d048-9ff5-4da4-a98c-5d67c97ce7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310433158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3310433158
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.4122073935
Short name T292
Test name
Test status
Simulation time 12385967373 ps
CPU time 66.7 seconds
Started Aug 10 07:24:49 PM PDT 24
Finished Aug 10 07:25:56 PM PDT 24
Peak memory 249580 kb
Host smart-52c780fa-408d-4988-ac6f-1ba0346eac9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122073935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.4122073935
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3067006689
Short name T253
Test name
Test status
Simulation time 501935258 ps
CPU time 4.8 seconds
Started Aug 10 07:24:44 PM PDT 24
Finished Aug 10 07:24:49 PM PDT 24
Peak memory 233136 kb
Host smart-cf2f9b43-6cd6-46e6-8340-8710b5f5eb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067006689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3067006689
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3347124208
Short name T270
Test name
Test status
Simulation time 29582454562 ps
CPU time 30.36 seconds
Started Aug 10 07:24:51 PM PDT 24
Finished Aug 10 07:25:22 PM PDT 24
Peak memory 241188 kb
Host smart-9eb17d1c-717f-4260-a36a-d092da35d711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347124208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3347124208
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1488890179
Short name T271
Test name
Test status
Simulation time 3256295814 ps
CPU time 12.42 seconds
Started Aug 10 07:24:46 PM PDT 24
Finished Aug 10 07:24:59 PM PDT 24
Peak memory 233092 kb
Host smart-e0c8b0d2-cf37-4a51-aad2-35613d669ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488890179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1488890179
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2643787978
Short name T243
Test name
Test status
Simulation time 153968074 ps
CPU time 2.81 seconds
Started Aug 10 07:24:45 PM PDT 24
Finished Aug 10 07:24:48 PM PDT 24
Peak memory 224852 kb
Host smart-77eb18bf-9a51-4c5d-ad56-173bb0bf91b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643787978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2643787978
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2385583042
Short name T685
Test name
Test status
Simulation time 1170985569 ps
CPU time 7.36 seconds
Started Aug 10 07:24:51 PM PDT 24
Finished Aug 10 07:24:59 PM PDT 24
Peak memory 222996 kb
Host smart-b42cbe1c-0899-45ba-940e-66ead32fba1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2385583042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2385583042
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.4276338397
Short name T75
Test name
Test status
Simulation time 122688627 ps
CPU time 1.09 seconds
Started Aug 10 07:24:45 PM PDT 24
Finished Aug 10 07:24:46 PM PDT 24
Peak memory 235768 kb
Host smart-651e4ec2-27ea-480b-bba6-8b916ff2cb2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276338397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4276338397
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1255481671
Short name T158
Test name
Test status
Simulation time 56565038 ps
CPU time 1.07 seconds
Started Aug 10 07:24:48 PM PDT 24
Finished Aug 10 07:24:49 PM PDT 24
Peak memory 207468 kb
Host smart-43c62766-303c-4bae-bf90-1fa1781ca6a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255481671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1255481671
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2989310209
Short name T984
Test name
Test status
Simulation time 1512325876 ps
CPU time 14.34 seconds
Started Aug 10 07:24:44 PM PDT 24
Finished Aug 10 07:24:59 PM PDT 24
Peak memory 217016 kb
Host smart-35b8a0f2-52c4-4225-ad61-096e0a8bda75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989310209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2989310209
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.418413168
Short name T385
Test name
Test status
Simulation time 17211053232 ps
CPU time 3.98 seconds
Started Aug 10 07:24:46 PM PDT 24
Finished Aug 10 07:24:50 PM PDT 24
Peak memory 216684 kb
Host smart-db80d0b4-6ced-4959-9ee6-d527e9e791b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418413168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.418413168
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2952934825
Short name T35
Test name
Test status
Simulation time 228426770 ps
CPU time 1.08 seconds
Started Aug 10 07:24:46 PM PDT 24
Finished Aug 10 07:24:48 PM PDT 24
Peak memory 208044 kb
Host smart-e2ef0337-3a33-4fde-9c6e-414763099d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952934825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2952934825
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3318310854
Short name T537
Test name
Test status
Simulation time 75593829 ps
CPU time 0.88 seconds
Started Aug 10 07:24:48 PM PDT 24
Finished Aug 10 07:24:48 PM PDT 24
Peak memory 206396 kb
Host smart-b8dfc80c-2b4f-46d8-9d5e-5cea5ead2e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318310854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3318310854
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.757815526
Short name T605
Test name
Test status
Simulation time 81666935757 ps
CPU time 32.65 seconds
Started Aug 10 07:24:46 PM PDT 24
Finished Aug 10 07:25:19 PM PDT 24
Peak memory 233160 kb
Host smart-124dfa72-1567-450d-ab13-7eb8ffa55995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757815526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.757815526
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1454352880
Short name T797
Test name
Test status
Simulation time 44719170 ps
CPU time 0.75 seconds
Started Aug 10 07:27:22 PM PDT 24
Finished Aug 10 07:27:23 PM PDT 24
Peak memory 206196 kb
Host smart-fa39db6b-32e5-460a-a690-8ba87f486bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454352880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1454352880
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1769576853
Short name T975
Test name
Test status
Simulation time 530678559 ps
CPU time 2.48 seconds
Started Aug 10 07:27:27 PM PDT 24
Finished Aug 10 07:27:30 PM PDT 24
Peak memory 233124 kb
Host smart-8be9a817-efab-4ca8-b07e-eac46dd945ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769576853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1769576853
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3771855962
Short name T632
Test name
Test status
Simulation time 26765214 ps
CPU time 0.72 seconds
Started Aug 10 07:27:21 PM PDT 24
Finished Aug 10 07:27:21 PM PDT 24
Peak memory 206004 kb
Host smart-18bd2461-81dd-4195-a936-e21d898170f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771855962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3771855962
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2210175746
Short name T639
Test name
Test status
Simulation time 11962035162 ps
CPU time 117.1 seconds
Started Aug 10 07:27:23 PM PDT 24
Finished Aug 10 07:29:20 PM PDT 24
Peak memory 249148 kb
Host smart-274e4f83-6d79-4a28-b394-eb7326ccd79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210175746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2210175746
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3239877368
Short name T675
Test name
Test status
Simulation time 34738313664 ps
CPU time 383.9 seconds
Started Aug 10 07:27:28 PM PDT 24
Finished Aug 10 07:33:52 PM PDT 24
Peak memory 254924 kb
Host smart-cc3f1c0e-f524-43c5-ba97-95f0aa680f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239877368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3239877368
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1885957949
Short name T55
Test name
Test status
Simulation time 204805836236 ps
CPU time 411.67 seconds
Started Aug 10 07:27:20 PM PDT 24
Finished Aug 10 07:34:12 PM PDT 24
Peak memory 271764 kb
Host smart-c7f03917-9ccc-4d3a-bcc2-a897b1d45682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885957949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1885957949
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.92278384
Short name T169
Test name
Test status
Simulation time 2645366904 ps
CPU time 56.8 seconds
Started Aug 10 07:27:23 PM PDT 24
Finished Aug 10 07:28:20 PM PDT 24
Peak memory 256260 kb
Host smart-b54cb126-1228-44a5-aa9a-f0fac99d4152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92278384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.92278384
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3175459985
Short name T789
Test name
Test status
Simulation time 1208447081 ps
CPU time 8.38 seconds
Started Aug 10 07:27:22 PM PDT 24
Finished Aug 10 07:27:30 PM PDT 24
Peak memory 224884 kb
Host smart-a5480929-9fe8-49e4-bcb1-5c300f02f1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175459985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3175459985
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2564914392
Short name T962
Test name
Test status
Simulation time 10470654662 ps
CPU time 79.8 seconds
Started Aug 10 07:27:22 PM PDT 24
Finished Aug 10 07:28:42 PM PDT 24
Peak memory 233100 kb
Host smart-9b013eed-8838-49d1-93ac-e8afbc7ed291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564914392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2564914392
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3415030931
Short name T811
Test name
Test status
Simulation time 464351734 ps
CPU time 4.61 seconds
Started Aug 10 07:27:27 PM PDT 24
Finished Aug 10 07:27:32 PM PDT 24
Peak memory 233128 kb
Host smart-23fcf1c6-e5ac-406a-adc3-5aa3196ce7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415030931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3415030931
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3070601227
Short name T979
Test name
Test status
Simulation time 15234015251 ps
CPU time 11.64 seconds
Started Aug 10 07:27:22 PM PDT 24
Finished Aug 10 07:27:34 PM PDT 24
Peak memory 224936 kb
Host smart-16fe9eed-8040-4c9b-9f5c-8108df7f1f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070601227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3070601227
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3587114035
Short name T461
Test name
Test status
Simulation time 960100747 ps
CPU time 6.99 seconds
Started Aug 10 07:27:27 PM PDT 24
Finished Aug 10 07:27:34 PM PDT 24
Peak memory 224656 kb
Host smart-7a74bf92-4f44-4b64-a4ef-9561008a2655
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3587114035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3587114035
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3344426873
Short name T874
Test name
Test status
Simulation time 168304863 ps
CPU time 0.98 seconds
Started Aug 10 07:27:25 PM PDT 24
Finished Aug 10 07:27:26 PM PDT 24
Peak memory 207100 kb
Host smart-e91a71f9-1d85-4b75-87b0-41449de3e559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344426873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3344426873
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1746188332
Short name T658
Test name
Test status
Simulation time 782304360 ps
CPU time 7.2 seconds
Started Aug 10 07:27:24 PM PDT 24
Finished Aug 10 07:27:31 PM PDT 24
Peak memory 216708 kb
Host smart-42721f0d-d377-4152-a7da-7d314fd3b1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746188332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1746188332
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2028309065
Short name T645
Test name
Test status
Simulation time 2619197145 ps
CPU time 8.77 seconds
Started Aug 10 07:27:22 PM PDT 24
Finished Aug 10 07:27:31 PM PDT 24
Peak memory 216700 kb
Host smart-3c911144-69ef-47c3-b09a-fa812455a0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028309065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2028309065
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3163949153
Short name T671
Test name
Test status
Simulation time 32622372 ps
CPU time 0.99 seconds
Started Aug 10 07:27:22 PM PDT 24
Finished Aug 10 07:27:23 PM PDT 24
Peak memory 208180 kb
Host smart-06793b9e-b459-41de-8cb3-c839624764ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163949153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3163949153
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.234899473
Short name T530
Test name
Test status
Simulation time 57149855 ps
CPU time 0.73 seconds
Started Aug 10 07:27:21 PM PDT 24
Finished Aug 10 07:27:22 PM PDT 24
Peak memory 206400 kb
Host smart-a10431aa-67b7-4fd4-a193-e028e59b7b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234899473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.234899473
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.954937251
Short name T498
Test name
Test status
Simulation time 6176860805 ps
CPU time 7.72 seconds
Started Aug 10 07:27:22 PM PDT 24
Finished Aug 10 07:27:30 PM PDT 24
Peak memory 224924 kb
Host smart-16fad430-a09a-4846-97e4-84b924c177dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954937251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.954937251
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2824459516
Short name T760
Test name
Test status
Simulation time 65087176 ps
CPU time 0.72 seconds
Started Aug 10 07:27:32 PM PDT 24
Finished Aug 10 07:27:33 PM PDT 24
Peak memory 206216 kb
Host smart-6d07cdbb-9c99-4ca3-ae62-d41be1174d4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824459516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2824459516
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.640115723
Short name T696
Test name
Test status
Simulation time 1590890676 ps
CPU time 7.54 seconds
Started Aug 10 07:27:30 PM PDT 24
Finished Aug 10 07:27:38 PM PDT 24
Peak memory 233136 kb
Host smart-2ebba4d0-a945-4361-8926-0286bdbe1212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640115723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.640115723
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2557765099
Short name T473
Test name
Test status
Simulation time 40309042 ps
CPU time 0.81 seconds
Started Aug 10 07:27:21 PM PDT 24
Finished Aug 10 07:27:22 PM PDT 24
Peak memory 207344 kb
Host smart-fac8a3c5-a1e4-4da7-8bb4-e97a152f1e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557765099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2557765099
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1206595428
Short name T27
Test name
Test status
Simulation time 1068336555 ps
CPU time 25.86 seconds
Started Aug 10 07:27:32 PM PDT 24
Finished Aug 10 07:27:58 PM PDT 24
Peak memory 250124 kb
Host smart-9913e9ec-7f07-4758-9220-d297d8a188f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206595428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1206595428
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.79397484
Short name T747
Test name
Test status
Simulation time 13066141341 ps
CPU time 89.66 seconds
Started Aug 10 07:27:31 PM PDT 24
Finished Aug 10 07:29:01 PM PDT 24
Peak memory 250584 kb
Host smart-54ced68c-331d-4226-bd1b-69a470bd69bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79397484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.79397484
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3983202017
Short name T280
Test name
Test status
Simulation time 33088023058 ps
CPU time 138.05 seconds
Started Aug 10 07:27:31 PM PDT 24
Finished Aug 10 07:29:49 PM PDT 24
Peak memory 249656 kb
Host smart-a66d1042-c119-4456-85e7-76d6515c1753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983202017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3983202017
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2149001612
Short name T308
Test name
Test status
Simulation time 5742423316 ps
CPU time 7.85 seconds
Started Aug 10 07:27:32 PM PDT 24
Finished Aug 10 07:27:40 PM PDT 24
Peak memory 233492 kb
Host smart-593f5bd3-7b65-494e-a6bb-28585816ceea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149001612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2149001612
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.4032789078
Short name T1000
Test name
Test status
Simulation time 141621066978 ps
CPU time 236.24 seconds
Started Aug 10 07:27:31 PM PDT 24
Finished Aug 10 07:31:28 PM PDT 24
Peak memory 250632 kb
Host smart-0ce38177-5b5a-432f-9597-77e73f190c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032789078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.4032789078
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2377837576
Short name T883
Test name
Test status
Simulation time 10982582773 ps
CPU time 22.6 seconds
Started Aug 10 07:27:32 PM PDT 24
Finished Aug 10 07:27:54 PM PDT 24
Peak memory 224896 kb
Host smart-6bde7572-7f55-4457-87f7-d8361ffa9d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377837576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2377837576
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1096639759
Short name T545
Test name
Test status
Simulation time 364513557 ps
CPU time 8.16 seconds
Started Aug 10 07:27:33 PM PDT 24
Finished Aug 10 07:27:41 PM PDT 24
Peak memory 233144 kb
Host smart-509031b2-9415-40bf-9fb9-1a10fbdfe084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096639759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1096639759
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4235328453
Short name T85
Test name
Test status
Simulation time 2550978386 ps
CPU time 10.35 seconds
Started Aug 10 07:27:31 PM PDT 24
Finished Aug 10 07:27:41 PM PDT 24
Peak memory 233216 kb
Host smart-c01d2d9b-017f-4eb2-80b6-27aa0a6c0581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235328453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4235328453
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2012067005
Short name T611
Test name
Test status
Simulation time 41376964738 ps
CPU time 19.96 seconds
Started Aug 10 07:27:24 PM PDT 24
Finished Aug 10 07:27:44 PM PDT 24
Peak memory 233208 kb
Host smart-39c7d217-07dc-4de2-8d12-a6f192e24199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012067005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2012067005
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.811904331
Short name T414
Test name
Test status
Simulation time 1500059651 ps
CPU time 8.42 seconds
Started Aug 10 07:27:33 PM PDT 24
Finished Aug 10 07:27:41 PM PDT 24
Peak memory 221124 kb
Host smart-5e8e9ce4-f7bd-41f4-bf3b-ec3b4bf126d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=811904331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.811904331
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1711014013
Short name T320
Test name
Test status
Simulation time 6216582868 ps
CPU time 39.4 seconds
Started Aug 10 07:27:22 PM PDT 24
Finished Aug 10 07:28:02 PM PDT 24
Peak memory 220252 kb
Host smart-e30d60fb-a727-441a-9c45-16c2fa4f4c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711014013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1711014013
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4282396626
Short name T655
Test name
Test status
Simulation time 45885062075 ps
CPU time 27.96 seconds
Started Aug 10 07:27:24 PM PDT 24
Finished Aug 10 07:27:52 PM PDT 24
Peak memory 216736 kb
Host smart-d973610d-9280-477b-8fc3-f78c3017e9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282396626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4282396626
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.872599985
Short name T636
Test name
Test status
Simulation time 160903162 ps
CPU time 1.3 seconds
Started Aug 10 07:27:26 PM PDT 24
Finished Aug 10 07:27:27 PM PDT 24
Peak memory 216448 kb
Host smart-b1a231d4-df4e-49ff-9fc6-30183f5f46d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872599985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.872599985
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.841850132
Short name T543
Test name
Test status
Simulation time 177943307 ps
CPU time 0.86 seconds
Started Aug 10 07:27:22 PM PDT 24
Finished Aug 10 07:27:23 PM PDT 24
Peak memory 206380 kb
Host smart-2387fee0-647f-41c7-aa7b-9a4b0640dcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841850132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.841850132
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.303510184
Short name T951
Test name
Test status
Simulation time 10121277342 ps
CPU time 29.59 seconds
Started Aug 10 07:27:31 PM PDT 24
Finished Aug 10 07:28:01 PM PDT 24
Peak memory 240816 kb
Host smart-9172aa0a-bbed-4404-93ab-b5201835da39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303510184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.303510184
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.100281940
Short name T843
Test name
Test status
Simulation time 12644841 ps
CPU time 0.68 seconds
Started Aug 10 07:27:41 PM PDT 24
Finished Aug 10 07:27:41 PM PDT 24
Peak memory 205332 kb
Host smart-8263bc70-b68f-444c-9650-bdbd6d5094a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100281940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.100281940
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2579430674
Short name T553
Test name
Test status
Simulation time 4128310746 ps
CPU time 4.8 seconds
Started Aug 10 07:27:39 PM PDT 24
Finished Aug 10 07:27:44 PM PDT 24
Peak memory 224876 kb
Host smart-6ea8f96b-bc0a-4109-a437-f77f84b9bcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579430674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2579430674
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3179408896
Short name T343
Test name
Test status
Simulation time 65083503 ps
CPU time 0.82 seconds
Started Aug 10 07:27:30 PM PDT 24
Finished Aug 10 07:27:31 PM PDT 24
Peak memory 206900 kb
Host smart-c425d1b4-aa3b-4009-a7ae-ec57f63b004d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179408896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3179408896
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1077815331
Short name T467
Test name
Test status
Simulation time 36415397914 ps
CPU time 70.54 seconds
Started Aug 10 07:27:39 PM PDT 24
Finished Aug 10 07:28:50 PM PDT 24
Peak memory 239224 kb
Host smart-7a204782-3c6a-4680-beed-6dd959c8cbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077815331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1077815331
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2084346499
Short name T756
Test name
Test status
Simulation time 11408371225 ps
CPU time 124.38 seconds
Started Aug 10 07:27:38 PM PDT 24
Finished Aug 10 07:29:42 PM PDT 24
Peak memory 253964 kb
Host smart-7eabd3ea-8b2c-4327-8175-dd319fcdf3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084346499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2084346499
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2140495846
Short name T669
Test name
Test status
Simulation time 90875871592 ps
CPU time 191.96 seconds
Started Aug 10 07:27:40 PM PDT 24
Finished Aug 10 07:30:53 PM PDT 24
Peak memory 252672 kb
Host smart-aec76e45-bbd8-4abc-9137-e76fedca1111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140495846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2140495846
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1046404398
Short name T787
Test name
Test status
Simulation time 154807990 ps
CPU time 3.36 seconds
Started Aug 10 07:27:39 PM PDT 24
Finished Aug 10 07:27:43 PM PDT 24
Peak memory 233076 kb
Host smart-fea22fd6-94f0-4a73-89a5-3356282b1c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046404398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1046404398
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.39933963
Short name T956
Test name
Test status
Simulation time 4480288003 ps
CPU time 23.75 seconds
Started Aug 10 07:27:38 PM PDT 24
Finished Aug 10 07:28:02 PM PDT 24
Peak memory 241368 kb
Host smart-a4d9dc17-5ee3-41cf-a846-876eafdc9ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39933963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.39933963
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.557854217
Short name T218
Test name
Test status
Simulation time 1021737160 ps
CPU time 12.68 seconds
Started Aug 10 07:27:32 PM PDT 24
Finished Aug 10 07:27:45 PM PDT 24
Peak memory 233184 kb
Host smart-9de8db99-a6bc-401f-8ac3-94a4a719e902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557854217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.557854217
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4281604603
Short name T702
Test name
Test status
Simulation time 43449763 ps
CPU time 2.38 seconds
Started Aug 10 07:27:32 PM PDT 24
Finished Aug 10 07:27:35 PM PDT 24
Peak memory 233072 kb
Host smart-974fa1ea-82ba-4a54-a76d-514dcc27cb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281604603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4281604603
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1715813164
Short name T262
Test name
Test status
Simulation time 750822029 ps
CPU time 3.93 seconds
Started Aug 10 07:27:33 PM PDT 24
Finished Aug 10 07:27:37 PM PDT 24
Peak memory 233208 kb
Host smart-9a5d8f62-ae52-4354-b38f-8d29c7c6f9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715813164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1715813164
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1837523349
Short name T599
Test name
Test status
Simulation time 1127108588 ps
CPU time 7.05 seconds
Started Aug 10 07:27:32 PM PDT 24
Finished Aug 10 07:27:39 PM PDT 24
Peak memory 241168 kb
Host smart-53f9483c-8f8b-497e-bd09-baf2f0a04129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837523349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1837523349
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3539087180
Short name T522
Test name
Test status
Simulation time 1601307308 ps
CPU time 4.38 seconds
Started Aug 10 07:27:39 PM PDT 24
Finished Aug 10 07:27:44 PM PDT 24
Peak memory 219928 kb
Host smart-55f92945-3fe6-41d5-8240-07f5cf1cee52
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3539087180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3539087180
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.90215424
Short name T65
Test name
Test status
Simulation time 151760145403 ps
CPU time 380.19 seconds
Started Aug 10 07:27:39 PM PDT 24
Finished Aug 10 07:34:00 PM PDT 24
Peak memory 257292 kb
Host smart-ee7136ac-7573-4627-b96b-8aab51bb11af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90215424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress
_all.90215424
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2343431526
Short name T704
Test name
Test status
Simulation time 6171399207 ps
CPU time 38.44 seconds
Started Aug 10 07:27:32 PM PDT 24
Finished Aug 10 07:28:10 PM PDT 24
Peak memory 216728 kb
Host smart-053eb05f-c361-43ef-bff2-2ee93431a840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343431526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2343431526
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3078920198
Short name T448
Test name
Test status
Simulation time 4090844684 ps
CPU time 7.01 seconds
Started Aug 10 07:27:30 PM PDT 24
Finished Aug 10 07:27:37 PM PDT 24
Peak memory 216720 kb
Host smart-843fd966-d323-4612-9901-8d5fc9f48fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078920198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3078920198
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1633511761
Short name T452
Test name
Test status
Simulation time 117005686 ps
CPU time 1.15 seconds
Started Aug 10 07:27:30 PM PDT 24
Finished Aug 10 07:27:32 PM PDT 24
Peak memory 208440 kb
Host smart-a8f03188-5e28-4bb5-a498-e748609b8f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633511761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1633511761
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3057592851
Short name T712
Test name
Test status
Simulation time 141025279 ps
CPU time 0.87 seconds
Started Aug 10 07:27:31 PM PDT 24
Finished Aug 10 07:27:32 PM PDT 24
Peak memory 206388 kb
Host smart-23fff4cd-636a-454e-8acd-f24a5935f142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057592851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3057592851
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2519524639
Short name T558
Test name
Test status
Simulation time 63977153 ps
CPU time 2.47 seconds
Started Aug 10 07:27:32 PM PDT 24
Finished Aug 10 07:27:34 PM PDT 24
Peak memory 232796 kb
Host smart-b54b7908-25f1-46fe-b410-878665da27ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519524639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2519524639
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3574634554
Short name T959
Test name
Test status
Simulation time 46558427 ps
CPU time 0.73 seconds
Started Aug 10 07:27:42 PM PDT 24
Finished Aug 10 07:27:43 PM PDT 24
Peak memory 205836 kb
Host smart-70887c85-9295-4845-8b88-a6fde81f2123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574634554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3574634554
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.106117796
Short name T909
Test name
Test status
Simulation time 4683312948 ps
CPU time 11.98 seconds
Started Aug 10 07:27:40 PM PDT 24
Finished Aug 10 07:27:52 PM PDT 24
Peak memory 233184 kb
Host smart-a27226c8-2717-40d6-8ad3-793d39cc842a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106117796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.106117796
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1870670252
Short name T666
Test name
Test status
Simulation time 53903156 ps
CPU time 0.75 seconds
Started Aug 10 07:27:40 PM PDT 24
Finished Aug 10 07:27:41 PM PDT 24
Peak memory 206272 kb
Host smart-96803c95-4668-40ab-b0d3-740fe1063f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870670252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1870670252
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3796073453
Short name T405
Test name
Test status
Simulation time 13863935913 ps
CPU time 58.06 seconds
Started Aug 10 07:27:41 PM PDT 24
Finished Aug 10 07:28:39 PM PDT 24
Peak memory 249544 kb
Host smart-e7b9c21c-eec3-432f-aa8a-32ffa716f356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796073453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3796073453
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3393572671
Short name T814
Test name
Test status
Simulation time 1941802424 ps
CPU time 16.78 seconds
Started Aug 10 07:27:41 PM PDT 24
Finished Aug 10 07:27:58 PM PDT 24
Peak memory 217736 kb
Host smart-529d90ea-1397-471a-9179-ee980fd9e5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393572671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3393572671
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4070361591
Short name T997
Test name
Test status
Simulation time 47083736804 ps
CPU time 135.57 seconds
Started Aug 10 07:27:38 PM PDT 24
Finished Aug 10 07:29:53 PM PDT 24
Peak memory 255376 kb
Host smart-a065fce8-ce0f-4ec7-bc04-a95252721a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070361591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4070361591
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.828693613
Short name T409
Test name
Test status
Simulation time 7673090519 ps
CPU time 15.14 seconds
Started Aug 10 07:27:41 PM PDT 24
Finished Aug 10 07:27:56 PM PDT 24
Peak memory 237372 kb
Host smart-7c000231-76f2-4c28-a540-479e7d6c6070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828693613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.828693613
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1676416133
Short name T1001
Test name
Test status
Simulation time 6119261758 ps
CPU time 19.4 seconds
Started Aug 10 07:27:40 PM PDT 24
Finished Aug 10 07:28:00 PM PDT 24
Peak memory 225056 kb
Host smart-a2839d37-b34d-42ea-8d70-3e14e30eacbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676416133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1676416133
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3891417611
Short name T23
Test name
Test status
Simulation time 3267886889 ps
CPU time 31.76 seconds
Started Aug 10 07:27:39 PM PDT 24
Finished Aug 10 07:28:11 PM PDT 24
Peak memory 233168 kb
Host smart-6fc56c1c-25a0-4751-9421-79fe25953a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891417611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3891417611
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1210218481
Short name T483
Test name
Test status
Simulation time 16294162908 ps
CPU time 13.3 seconds
Started Aug 10 07:27:40 PM PDT 24
Finished Aug 10 07:27:53 PM PDT 24
Peak memory 233132 kb
Host smart-26426f30-f88e-4ceb-b2e9-da8f58d63b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210218481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1210218481
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1173451600
Short name T596
Test name
Test status
Simulation time 826476890 ps
CPU time 7.1 seconds
Started Aug 10 07:27:39 PM PDT 24
Finished Aug 10 07:27:46 PM PDT 24
Peak memory 224984 kb
Host smart-1a53e1b9-c4f3-42ab-90d5-0314d5524b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173451600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1173451600
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4270037218
Short name T578
Test name
Test status
Simulation time 366414027 ps
CPU time 4.16 seconds
Started Aug 10 07:27:41 PM PDT 24
Finished Aug 10 07:27:45 PM PDT 24
Peak memory 220896 kb
Host smart-73794a23-efc3-463b-b4bd-f28fa19207dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4270037218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4270037218
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1272960101
Short name T846
Test name
Test status
Simulation time 46148818 ps
CPU time 0.97 seconds
Started Aug 10 07:27:42 PM PDT 24
Finished Aug 10 07:27:43 PM PDT 24
Peak memory 206988 kb
Host smart-592f5ee6-3f67-42e4-bccf-32c4dad4bc04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272960101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1272960101
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3477533805
Short name T314
Test name
Test status
Simulation time 4781546919 ps
CPU time 7.54 seconds
Started Aug 10 07:27:40 PM PDT 24
Finished Aug 10 07:27:48 PM PDT 24
Peak memory 216892 kb
Host smart-b8fc61c8-19f6-4e6a-be19-bf92eb33511e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477533805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3477533805
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1247234242
Short name T380
Test name
Test status
Simulation time 3181050513 ps
CPU time 13.06 seconds
Started Aug 10 07:27:39 PM PDT 24
Finished Aug 10 07:27:52 PM PDT 24
Peak memory 216708 kb
Host smart-605008ba-aa17-4bb9-844b-7ad3d167ac9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247234242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1247234242
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3695208364
Short name T719
Test name
Test status
Simulation time 125186509 ps
CPU time 1.43 seconds
Started Aug 10 07:27:38 PM PDT 24
Finished Aug 10 07:27:39 PM PDT 24
Peak memory 208444 kb
Host smart-8869c9db-771a-4716-ba3f-4f4b9a5d2406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695208364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3695208364
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4035251055
Short name T804
Test name
Test status
Simulation time 198184696 ps
CPU time 0.86 seconds
Started Aug 10 07:27:38 PM PDT 24
Finished Aug 10 07:27:39 PM PDT 24
Peak memory 206340 kb
Host smart-9c5afb9d-e5fb-4c10-b5d8-ec0797be9f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035251055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4035251055
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.881138088
Short name T593
Test name
Test status
Simulation time 11004636094 ps
CPU time 12.51 seconds
Started Aug 10 07:27:41 PM PDT 24
Finished Aug 10 07:27:54 PM PDT 24
Peak memory 233024 kb
Host smart-e84d4e55-637b-4c25-b536-3275cb6d7edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881138088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.881138088
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4181570581
Short name T943
Test name
Test status
Simulation time 33435468 ps
CPU time 0.73 seconds
Started Aug 10 07:27:45 PM PDT 24
Finished Aug 10 07:27:46 PM PDT 24
Peak memory 206228 kb
Host smart-66b2c80e-66e4-4bec-ae72-8210387e6212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181570581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4181570581
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3919151721
Short name T690
Test name
Test status
Simulation time 139986265 ps
CPU time 3.11 seconds
Started Aug 10 07:27:49 PM PDT 24
Finished Aug 10 07:27:52 PM PDT 24
Peak memory 225080 kb
Host smart-9824712b-aaad-47ff-818f-e0c1c756f3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919151721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3919151721
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1897847167
Short name T980
Test name
Test status
Simulation time 77371146 ps
CPU time 0.77 seconds
Started Aug 10 07:27:39 PM PDT 24
Finished Aug 10 07:27:40 PM PDT 24
Peak memory 206936 kb
Host smart-812801f3-afeb-4125-b050-6d7fe67b3ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897847167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1897847167
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3572982997
Short name T856
Test name
Test status
Simulation time 5520387051 ps
CPU time 103.92 seconds
Started Aug 10 07:27:47 PM PDT 24
Finished Aug 10 07:29:31 PM PDT 24
Peak memory 273940 kb
Host smart-03151957-285e-43ab-a103-7179d3708c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572982997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3572982997
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1857553521
Short name T540
Test name
Test status
Simulation time 45429665074 ps
CPU time 96.44 seconds
Started Aug 10 07:27:48 PM PDT 24
Finished Aug 10 07:29:25 PM PDT 24
Peak memory 252488 kb
Host smart-c8f7746c-5921-4e89-aebb-5e36ebc53719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857553521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1857553521
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.649726480
Short name T166
Test name
Test status
Simulation time 18075480719 ps
CPU time 179.5 seconds
Started Aug 10 07:27:48 PM PDT 24
Finished Aug 10 07:30:48 PM PDT 24
Peak memory 264748 kb
Host smart-d2fa3b2f-e5dd-4ae0-be70-2e76b795c0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649726480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.649726480
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.61582625
Short name T643
Test name
Test status
Simulation time 513088811 ps
CPU time 3.48 seconds
Started Aug 10 07:27:51 PM PDT 24
Finished Aug 10 07:27:55 PM PDT 24
Peak memory 224896 kb
Host smart-5bc40345-e443-449f-8cbc-19067e4e089e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61582625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.61582625
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.538429399
Short name T266
Test name
Test status
Simulation time 9030978067 ps
CPU time 28.62 seconds
Started Aug 10 07:27:45 PM PDT 24
Finished Aug 10 07:28:14 PM PDT 24
Peak memory 233200 kb
Host smart-8fa976c5-1bbf-44bb-817e-321c3c76c8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538429399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.538429399
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3888429027
Short name T993
Test name
Test status
Simulation time 3174539456 ps
CPU time 14.81 seconds
Started Aug 10 07:27:45 PM PDT 24
Finished Aug 10 07:28:00 PM PDT 24
Peak memory 233256 kb
Host smart-8c18584a-ed3c-4bb7-9194-d5921f3271b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888429027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3888429027
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1394392282
Short name T276
Test name
Test status
Simulation time 18650144285 ps
CPU time 23.63 seconds
Started Aug 10 07:27:48 PM PDT 24
Finished Aug 10 07:28:12 PM PDT 24
Peak memory 233248 kb
Host smart-6978cc78-24c2-4938-accb-5fe3d46bafff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394392282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1394392282
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2711012240
Short name T778
Test name
Test status
Simulation time 7073930420 ps
CPU time 13.14 seconds
Started Aug 10 07:27:48 PM PDT 24
Finished Aug 10 07:28:02 PM PDT 24
Peak memory 233144 kb
Host smart-2189f1dd-c93c-423c-b689-9f0e73ea2dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711012240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2711012240
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.593803069
Short name T394
Test name
Test status
Simulation time 337097015 ps
CPU time 2.8 seconds
Started Aug 10 07:27:41 PM PDT 24
Finished Aug 10 07:27:44 PM PDT 24
Peak memory 233076 kb
Host smart-4fd5e2d6-4e54-44fc-8a4f-f7cb38d9c721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593803069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.593803069
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2510467737
Short name T415
Test name
Test status
Simulation time 6060278760 ps
CPU time 11.62 seconds
Started Aug 10 07:27:48 PM PDT 24
Finished Aug 10 07:28:00 PM PDT 24
Peak memory 219432 kb
Host smart-ed72f486-5f2f-4c84-bf2b-5245207b20e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2510467737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2510467737
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2457749074
Short name T22
Test name
Test status
Simulation time 8735904909 ps
CPU time 157.63 seconds
Started Aug 10 07:27:49 PM PDT 24
Finished Aug 10 07:30:27 PM PDT 24
Peak memory 268080 kb
Host smart-3aa23683-45a3-4c73-97f3-9d7b1fea5fa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457749074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2457749074
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3455584116
Short name T584
Test name
Test status
Simulation time 6047891514 ps
CPU time 17.6 seconds
Started Aug 10 07:27:39 PM PDT 24
Finished Aug 10 07:27:57 PM PDT 24
Peak memory 216836 kb
Host smart-83c1bf5c-9409-43f8-baa6-8f4c45a6e82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455584116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3455584116
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1588435336
Short name T589
Test name
Test status
Simulation time 286509576 ps
CPU time 1.54 seconds
Started Aug 10 07:27:40 PM PDT 24
Finished Aug 10 07:27:42 PM PDT 24
Peak memory 208260 kb
Host smart-9c9f7c00-d2bb-43b0-afd2-c317f754243e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588435336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1588435336
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1007565783
Short name T759
Test name
Test status
Simulation time 118697131 ps
CPU time 1.22 seconds
Started Aug 10 07:27:43 PM PDT 24
Finished Aug 10 07:27:44 PM PDT 24
Peak memory 207864 kb
Host smart-329c4dff-c018-48ab-9dba-8c95693e0c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007565783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1007565783
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3150028418
Short name T934
Test name
Test status
Simulation time 105146163 ps
CPU time 0.74 seconds
Started Aug 10 07:27:39 PM PDT 24
Finished Aug 10 07:27:40 PM PDT 24
Peak memory 206364 kb
Host smart-98f353b4-b460-45f7-9ec3-e18badbd6b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150028418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3150028418
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.285543203
Short name T766
Test name
Test status
Simulation time 4045681745 ps
CPU time 13.22 seconds
Started Aug 10 07:27:47 PM PDT 24
Finished Aug 10 07:28:00 PM PDT 24
Peak memory 224928 kb
Host smart-1dc452f5-e2f3-4024-b1b8-ef5a4c2fdf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285543203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.285543203
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1545559902
Short name T395
Test name
Test status
Simulation time 43168904 ps
CPU time 0.7 seconds
Started Aug 10 07:27:48 PM PDT 24
Finished Aug 10 07:27:49 PM PDT 24
Peak memory 205880 kb
Host smart-64c84b5e-10f4-4036-9d36-77bbfa67fded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545559902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1545559902
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3675399997
Short name T429
Test name
Test status
Simulation time 1259669125 ps
CPU time 14.86 seconds
Started Aug 10 07:27:49 PM PDT 24
Finished Aug 10 07:28:03 PM PDT 24
Peak memory 233320 kb
Host smart-2e64ef8c-197b-4e70-a5f8-de3fe8843295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675399997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3675399997
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3643416902
Short name T407
Test name
Test status
Simulation time 13315885 ps
CPU time 0.78 seconds
Started Aug 10 07:27:47 PM PDT 24
Finished Aug 10 07:27:48 PM PDT 24
Peak memory 207276 kb
Host smart-d553256f-1963-413c-9c1f-873f3e71f748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643416902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3643416902
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.494038236
Short name T290
Test name
Test status
Simulation time 8568172636 ps
CPU time 98.79 seconds
Started Aug 10 07:27:50 PM PDT 24
Finished Aug 10 07:29:29 PM PDT 24
Peak memory 265996 kb
Host smart-86892d3d-1921-4d0d-9f4e-3fccc5d6ce21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494038236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.494038236
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.738004276
Short name T758
Test name
Test status
Simulation time 23010559 ps
CPU time 0.79 seconds
Started Aug 10 07:27:51 PM PDT 24
Finished Aug 10 07:27:52 PM PDT 24
Peak memory 217700 kb
Host smart-685161f8-0e17-4f94-a336-c1be48fb4837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738004276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.738004276
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2281812334
Short name T64
Test name
Test status
Simulation time 31775931576 ps
CPU time 75.33 seconds
Started Aug 10 07:27:47 PM PDT 24
Finished Aug 10 07:29:03 PM PDT 24
Peak memory 241316 kb
Host smart-9cf0cab0-e9a7-43f1-ab05-039ade8563e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281812334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2281812334
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3739621243
Short name T147
Test name
Test status
Simulation time 10303596162 ps
CPU time 34.43 seconds
Started Aug 10 07:27:50 PM PDT 24
Finished Aug 10 07:28:25 PM PDT 24
Peak memory 249616 kb
Host smart-29ed70da-063a-4d2c-b3e6-7193688cd110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739621243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3739621243
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.4017156291
Short name T642
Test name
Test status
Simulation time 18476678 ps
CPU time 0.75 seconds
Started Aug 10 07:27:48 PM PDT 24
Finished Aug 10 07:27:49 PM PDT 24
Peak memory 216120 kb
Host smart-9fb53e7b-bc06-46f2-bb3c-77fa220e3bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017156291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.4017156291
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2679431355
Short name T236
Test name
Test status
Simulation time 924332956 ps
CPU time 5.3 seconds
Started Aug 10 07:27:50 PM PDT 24
Finished Aug 10 07:27:55 PM PDT 24
Peak memory 224908 kb
Host smart-536cdbd6-3595-40dd-8675-4f0d190b1b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679431355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2679431355
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.591667452
Short name T3
Test name
Test status
Simulation time 235980617 ps
CPU time 4.15 seconds
Started Aug 10 07:27:49 PM PDT 24
Finished Aug 10 07:27:53 PM PDT 24
Peak memory 224856 kb
Host smart-12496e71-2b36-464e-9c90-be1b502f581d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591667452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.591667452
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.751121955
Short name T406
Test name
Test status
Simulation time 5053047948 ps
CPU time 11.83 seconds
Started Aug 10 07:27:46 PM PDT 24
Finished Aug 10 07:27:58 PM PDT 24
Peak memory 224984 kb
Host smart-6d936de7-93af-479d-bc78-fb1dbd3fafd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751121955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.751121955
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1236595711
Short name T87
Test name
Test status
Simulation time 34351183 ps
CPU time 2.42 seconds
Started Aug 10 07:27:48 PM PDT 24
Finished Aug 10 07:27:51 PM PDT 24
Peak memory 232836 kb
Host smart-6d0734a3-34e8-4033-ba27-e296ca7fbb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236595711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1236595711
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3233065489
Short name T527
Test name
Test status
Simulation time 1350977749 ps
CPU time 9.45 seconds
Started Aug 10 07:27:50 PM PDT 24
Finished Aug 10 07:28:00 PM PDT 24
Peak memory 220304 kb
Host smart-838e2b58-433f-493b-a38d-e575a012615c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3233065489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3233065489
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2222709684
Short name T955
Test name
Test status
Simulation time 161280357 ps
CPU time 0.9 seconds
Started Aug 10 07:27:46 PM PDT 24
Finished Aug 10 07:27:47 PM PDT 24
Peak memory 207944 kb
Host smart-90923b4a-f626-4667-a0de-3e0888ded0ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222709684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2222709684
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1796147661
Short name T138
Test name
Test status
Simulation time 1409031697 ps
CPU time 17.31 seconds
Started Aug 10 07:27:52 PM PDT 24
Finished Aug 10 07:28:09 PM PDT 24
Peak memory 216624 kb
Host smart-33ba0e2c-211a-4142-bd74-dc8e75399c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796147661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1796147661
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.4104419933
Short name T542
Test name
Test status
Simulation time 2624708698 ps
CPU time 2.63 seconds
Started Aug 10 07:27:51 PM PDT 24
Finished Aug 10 07:27:54 PM PDT 24
Peak memory 208320 kb
Host smart-1991d748-b908-4707-8eb1-db6e5046c7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104419933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.4104419933
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2124596111
Short name T985
Test name
Test status
Simulation time 170544412 ps
CPU time 2.06 seconds
Started Aug 10 07:27:47 PM PDT 24
Finished Aug 10 07:27:49 PM PDT 24
Peak memory 216716 kb
Host smart-d25c134d-1c2e-44c8-bb56-5d884f590a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124596111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2124596111
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3833674635
Short name T662
Test name
Test status
Simulation time 56093703 ps
CPU time 0.87 seconds
Started Aug 10 07:27:47 PM PDT 24
Finished Aug 10 07:27:48 PM PDT 24
Peak memory 206288 kb
Host smart-54ec0f16-7e3a-4f11-bccc-cf56cef0adb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833674635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3833674635
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3606244678
Short name T764
Test name
Test status
Simulation time 59343289 ps
CPU time 2.31 seconds
Started Aug 10 07:27:47 PM PDT 24
Finished Aug 10 07:27:49 PM PDT 24
Peak memory 232812 kb
Host smart-8b469821-2216-4554-b1c4-e5e4f4f8fa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606244678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3606244678
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2940108678
Short name T556
Test name
Test status
Simulation time 174225360 ps
CPU time 0.68 seconds
Started Aug 10 07:27:56 PM PDT 24
Finished Aug 10 07:27:57 PM PDT 24
Peak memory 205828 kb
Host smart-0b1cbe25-5f56-4494-b2ad-356c933fc098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940108678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2940108678
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4113441412
Short name T801
Test name
Test status
Simulation time 1540024611 ps
CPU time 7.18 seconds
Started Aug 10 07:27:48 PM PDT 24
Finished Aug 10 07:27:56 PM PDT 24
Peak memory 233160 kb
Host smart-265a9e93-f5ef-4c8a-a665-7ae8178688ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113441412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4113441412
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2856708011
Short name T68
Test name
Test status
Simulation time 203754500 ps
CPU time 0.81 seconds
Started Aug 10 07:27:48 PM PDT 24
Finished Aug 10 07:27:49 PM PDT 24
Peak memory 207012 kb
Host smart-5c6ed9ee-0cce-49b9-bc9f-164e80779c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856708011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2856708011
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3334389835
Short name T315
Test name
Test status
Simulation time 63672668980 ps
CPU time 272.03 seconds
Started Aug 10 07:27:56 PM PDT 24
Finished Aug 10 07:32:28 PM PDT 24
Peak memory 265896 kb
Host smart-e0cc0ccd-a67a-47f5-a37b-9ceaa98634f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334389835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3334389835
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3242236085
Short name T897
Test name
Test status
Simulation time 7256298180 ps
CPU time 70.02 seconds
Started Aug 10 07:27:56 PM PDT 24
Finished Aug 10 07:29:06 PM PDT 24
Peak memory 249592 kb
Host smart-8bb55e17-29a3-41a8-a38b-61ebad3ede8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242236085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3242236085
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1584874853
Short name T913
Test name
Test status
Simulation time 14178048539 ps
CPU time 30.51 seconds
Started Aug 10 07:27:56 PM PDT 24
Finished Aug 10 07:28:26 PM PDT 24
Peak memory 239592 kb
Host smart-aba63fdd-56c8-49a2-b5f9-5c313fe9f83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584874853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1584874853
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4055966503
Short name T426
Test name
Test status
Simulation time 5769241558 ps
CPU time 54.18 seconds
Started Aug 10 07:27:57 PM PDT 24
Finished Aug 10 07:28:51 PM PDT 24
Peak memory 257020 kb
Host smart-aa7a8b7c-5a1f-489f-8a7e-be2b376285b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055966503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4055966503
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.566829064
Short name T232
Test name
Test status
Simulation time 13086029505 ps
CPU time 15.09 seconds
Started Aug 10 07:27:47 PM PDT 24
Finished Aug 10 07:28:02 PM PDT 24
Peak memory 224892 kb
Host smart-e5892439-a337-4453-804e-d0327a021935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566829064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.566829064
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1588279432
Short name T251
Test name
Test status
Simulation time 16294029564 ps
CPU time 36.26 seconds
Started Aug 10 07:27:51 PM PDT 24
Finished Aug 10 07:28:28 PM PDT 24
Peak memory 241400 kb
Host smart-2bd832b7-70b8-4a49-a298-9687eedbf625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588279432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1588279432
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1858194860
Short name T514
Test name
Test status
Simulation time 134825146 ps
CPU time 2.46 seconds
Started Aug 10 07:27:46 PM PDT 24
Finished Aug 10 07:27:49 PM PDT 24
Peak memory 233208 kb
Host smart-f597c167-93a5-4ceb-8549-547178b42f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858194860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1858194860
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1965259039
Short name T763
Test name
Test status
Simulation time 3678882608 ps
CPU time 14.45 seconds
Started Aug 10 07:27:46 PM PDT 24
Finished Aug 10 07:28:01 PM PDT 24
Peak memory 233164 kb
Host smart-5d2534bd-7598-4477-a4a2-e3f32a300e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965259039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1965259039
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3937192210
Short name T928
Test name
Test status
Simulation time 4422895966 ps
CPU time 10.65 seconds
Started Aug 10 07:27:58 PM PDT 24
Finished Aug 10 07:28:08 PM PDT 24
Peak memory 221140 kb
Host smart-6ce6ca0c-020b-4b62-b945-04ad1ccd1104
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3937192210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3937192210
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.150474777
Short name T881
Test name
Test status
Simulation time 22102397272 ps
CPU time 194.97 seconds
Started Aug 10 07:27:57 PM PDT 24
Finished Aug 10 07:31:12 PM PDT 24
Peak memory 249676 kb
Host smart-00cb698e-bba7-44b2-987c-a249876b4df4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150474777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.150474777
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.768725671
Short name T319
Test name
Test status
Simulation time 12833027654 ps
CPU time 11.73 seconds
Started Aug 10 07:27:47 PM PDT 24
Finished Aug 10 07:27:59 PM PDT 24
Peak memory 217056 kb
Host smart-820d8792-5ff9-473a-bff3-3695fd7121b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768725671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.768725671
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.225426382
Short name T904
Test name
Test status
Simulation time 21088758 ps
CPU time 0.89 seconds
Started Aug 10 07:27:48 PM PDT 24
Finished Aug 10 07:27:49 PM PDT 24
Peak memory 207364 kb
Host smart-193fe7b7-fbb8-40c0-9457-656a88995bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225426382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.225426382
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2048649093
Short name T782
Test name
Test status
Simulation time 30210127 ps
CPU time 0.85 seconds
Started Aug 10 07:27:47 PM PDT 24
Finished Aug 10 07:27:48 PM PDT 24
Peak memory 206408 kb
Host smart-bc4d4cdc-2a14-4846-acaa-8b065fc74e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048649093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2048649093
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.761552145
Short name T509
Test name
Test status
Simulation time 202542254 ps
CPU time 4.69 seconds
Started Aug 10 07:27:49 PM PDT 24
Finished Aug 10 07:27:54 PM PDT 24
Peak memory 233172 kb
Host smart-13c4543e-e1d5-4541-a482-0f03796f962a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761552145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.761552145
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2185203241
Short name T333
Test name
Test status
Simulation time 45179147 ps
CPU time 0.74 seconds
Started Aug 10 07:28:07 PM PDT 24
Finished Aug 10 07:28:08 PM PDT 24
Peak memory 205312 kb
Host smart-6a3cb422-0677-44d6-8fab-669d1bda2e9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185203241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2185203241
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1483058041
Short name T371
Test name
Test status
Simulation time 409291933 ps
CPU time 7.51 seconds
Started Aug 10 07:27:55 PM PDT 24
Finished Aug 10 07:28:02 PM PDT 24
Peak memory 233120 kb
Host smart-e33c9338-4d78-44ac-b1a6-8f15308c9743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483058041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1483058041
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3201721431
Short name T1002
Test name
Test status
Simulation time 50151961 ps
CPU time 0.79 seconds
Started Aug 10 07:27:56 PM PDT 24
Finished Aug 10 07:27:57 PM PDT 24
Peak memory 206984 kb
Host smart-f16188b2-e750-4f60-9782-8cfca65d52d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201721431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3201721431
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1162061797
Short name T925
Test name
Test status
Simulation time 8364794792 ps
CPU time 28.8 seconds
Started Aug 10 07:27:56 PM PDT 24
Finished Aug 10 07:28:25 PM PDT 24
Peak memory 241288 kb
Host smart-949b973c-d2fb-4874-8e28-a99a5775e9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162061797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1162061797
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.834360490
Short name T919
Test name
Test status
Simulation time 2989120828 ps
CPU time 30.06 seconds
Started Aug 10 07:27:57 PM PDT 24
Finished Aug 10 07:28:27 PM PDT 24
Peak memory 224880 kb
Host smart-cfbc780e-e29d-4d81-b5c6-685ef944b9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834360490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.834360490
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3276208627
Short name T780
Test name
Test status
Simulation time 357257916787 ps
CPU time 410.82 seconds
Started Aug 10 07:28:04 PM PDT 24
Finished Aug 10 07:34:55 PM PDT 24
Peak memory 266184 kb
Host smart-cd92e80e-e19a-434d-aa62-95301b3d31d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276208627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3276208627
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.461935983
Short name T149
Test name
Test status
Simulation time 129459699 ps
CPU time 3.64 seconds
Started Aug 10 07:28:04 PM PDT 24
Finished Aug 10 07:28:07 PM PDT 24
Peak memory 224936 kb
Host smart-f7126470-3900-47c1-93ae-4f5e6f0bf0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461935983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.461935983
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.843564090
Short name T590
Test name
Test status
Simulation time 2046880359 ps
CPU time 19.67 seconds
Started Aug 10 07:27:59 PM PDT 24
Finished Aug 10 07:28:19 PM PDT 24
Peak memory 237616 kb
Host smart-b63512c0-43e4-4ee1-b5ac-6f9da1d628f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843564090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.843564090
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3003723520
Short name T559
Test name
Test status
Simulation time 3855814119 ps
CPU time 11.28 seconds
Started Aug 10 07:27:56 PM PDT 24
Finished Aug 10 07:28:08 PM PDT 24
Peak memory 224932 kb
Host smart-11de6382-2b07-4b45-a1bc-a15c9337efb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003723520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3003723520
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.4167070920
Short name T562
Test name
Test status
Simulation time 123023436 ps
CPU time 2.16 seconds
Started Aug 10 07:27:56 PM PDT 24
Finished Aug 10 07:27:58 PM PDT 24
Peak memory 224804 kb
Host smart-e580ae8c-1931-434b-92af-202acc0df68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167070920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4167070920
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.276153533
Short name T546
Test name
Test status
Simulation time 1113517315 ps
CPU time 3.5 seconds
Started Aug 10 07:27:57 PM PDT 24
Finished Aug 10 07:28:00 PM PDT 24
Peak memory 233096 kb
Host smart-2f43819d-3937-4aab-9d41-46e352a57f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276153533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.276153533
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1144791069
Short name T484
Test name
Test status
Simulation time 1060194626 ps
CPU time 5.4 seconds
Started Aug 10 07:28:00 PM PDT 24
Finished Aug 10 07:28:05 PM PDT 24
Peak memory 233088 kb
Host smart-a42cdd96-e223-4aa2-a182-96a59ef88466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144791069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1144791069
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3789238878
Short name T991
Test name
Test status
Simulation time 312159015 ps
CPU time 6.05 seconds
Started Aug 10 07:28:04 PM PDT 24
Finished Aug 10 07:28:10 PM PDT 24
Peak memory 224056 kb
Host smart-8f626545-14b0-4201-b750-adbabf8350bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3789238878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3789238878
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.26569933
Short name T853
Test name
Test status
Simulation time 32358122320 ps
CPU time 362.78 seconds
Started Aug 10 07:27:57 PM PDT 24
Finished Aug 10 07:33:59 PM PDT 24
Peak memory 268036 kb
Host smart-00f5903e-f82d-4d3e-9c72-bd41ac510b07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26569933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress
_all.26569933
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.514514919
Short name T468
Test name
Test status
Simulation time 25763670501 ps
CPU time 34.42 seconds
Started Aug 10 07:28:02 PM PDT 24
Finished Aug 10 07:28:36 PM PDT 24
Peak memory 216800 kb
Host smart-0941243e-65be-41ec-aacd-bbdcd043298d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514514919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.514514919
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3704597008
Short name T640
Test name
Test status
Simulation time 561832588 ps
CPU time 2.68 seconds
Started Aug 10 07:27:57 PM PDT 24
Finished Aug 10 07:28:00 PM PDT 24
Peak memory 216384 kb
Host smart-b16bba3e-ab51-4913-895e-b0d94edaee47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704597008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3704597008
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.649832320
Short name T972
Test name
Test status
Simulation time 27176553 ps
CPU time 0.73 seconds
Started Aug 10 07:28:00 PM PDT 24
Finished Aug 10 07:28:01 PM PDT 24
Peak memory 206012 kb
Host smart-1c72e4d7-4387-4948-8dfa-4b516c5ce3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649832320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.649832320
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1240312903
Short name T432
Test name
Test status
Simulation time 23568764 ps
CPU time 0.79 seconds
Started Aug 10 07:28:02 PM PDT 24
Finished Aug 10 07:28:03 PM PDT 24
Peak memory 206340 kb
Host smart-378e070e-a397-4a76-913a-1432960696db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240312903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1240312903
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1296663454
Short name T275
Test name
Test status
Simulation time 47870962 ps
CPU time 2.6 seconds
Started Aug 10 07:27:55 PM PDT 24
Finished Aug 10 07:27:58 PM PDT 24
Peak memory 233180 kb
Host smart-81886d07-1e7e-49ab-8ed9-d2dc97ddc008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296663454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1296663454
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3902506191
Short name T834
Test name
Test status
Simulation time 15020533 ps
CPU time 0.79 seconds
Started Aug 10 07:28:05 PM PDT 24
Finished Aug 10 07:28:06 PM PDT 24
Peak memory 205232 kb
Host smart-1378cb21-6d5b-41e1-b14d-7080714a0f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902506191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3902506191
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.271622424
Short name T445
Test name
Test status
Simulation time 91000018 ps
CPU time 3.48 seconds
Started Aug 10 07:28:04 PM PDT 24
Finished Aug 10 07:28:08 PM PDT 24
Peak memory 224872 kb
Host smart-1fad9067-6b38-4064-8b6b-f76ab02adaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271622424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.271622424
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3167228026
Short name T683
Test name
Test status
Simulation time 50487290 ps
CPU time 0.8 seconds
Started Aug 10 07:28:06 PM PDT 24
Finished Aug 10 07:28:07 PM PDT 24
Peak memory 206976 kb
Host smart-69e9eb8c-78c2-412a-ab55-ab29f0478935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167228026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3167228026
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1554307498
Short name T503
Test name
Test status
Simulation time 41674310 ps
CPU time 0.74 seconds
Started Aug 10 07:28:07 PM PDT 24
Finished Aug 10 07:28:08 PM PDT 24
Peak memory 216188 kb
Host smart-b9061a52-6fbe-4b26-997d-555387598d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554307498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1554307498
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3744109938
Short name T164
Test name
Test status
Simulation time 10674796109 ps
CPU time 59.58 seconds
Started Aug 10 07:28:06 PM PDT 24
Finished Aug 10 07:29:06 PM PDT 24
Peak memory 233188 kb
Host smart-a02e1927-f685-447b-8002-a295ccfd57db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744109938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3744109938
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.4245345272
Short name T466
Test name
Test status
Simulation time 1138446400 ps
CPU time 14.62 seconds
Started Aug 10 07:28:07 PM PDT 24
Finished Aug 10 07:28:21 PM PDT 24
Peak memory 224904 kb
Host smart-78cff994-fe91-47e1-a2be-04c9a4546f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245345272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.4245345272
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.100798685
Short name T9
Test name
Test status
Simulation time 119443105060 ps
CPU time 214.08 seconds
Started Aug 10 07:28:05 PM PDT 24
Finished Aug 10 07:31:40 PM PDT 24
Peak memory 271232 kb
Host smart-f629ae60-ae34-417f-9855-49ba100c3261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100798685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.100798685
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.268280869
Short name T6
Test name
Test status
Simulation time 3376406789 ps
CPU time 15.05 seconds
Started Aug 10 07:28:04 PM PDT 24
Finished Aug 10 07:28:19 PM PDT 24
Peak memory 229764 kb
Host smart-b36fdc98-8284-454c-b3c6-dc3f04c3d07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268280869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.268280869
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1841411383
Short name T192
Test name
Test status
Simulation time 7456074787 ps
CPU time 72.15 seconds
Started Aug 10 07:28:06 PM PDT 24
Finished Aug 10 07:29:18 PM PDT 24
Peak memory 233248 kb
Host smart-0bceae5c-177b-437e-8219-9130cc4df791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841411383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1841411383
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2613973340
Short name T613
Test name
Test status
Simulation time 93187427 ps
CPU time 2.21 seconds
Started Aug 10 07:28:05 PM PDT 24
Finished Aug 10 07:28:07 PM PDT 24
Peak memory 224872 kb
Host smart-4cdb7de7-4457-41eb-9d57-b64774eb5cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613973340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2613973340
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.4000755791
Short name T377
Test name
Test status
Simulation time 4186270059 ps
CPU time 11.19 seconds
Started Aug 10 07:28:05 PM PDT 24
Finished Aug 10 07:28:17 PM PDT 24
Peak memory 241436 kb
Host smart-cb71ebfc-c9ef-44c2-8935-f09c27abbe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000755791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.4000755791
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3299080815
Short name T520
Test name
Test status
Simulation time 1397226569 ps
CPU time 13.32 seconds
Started Aug 10 07:28:07 PM PDT 24
Finished Aug 10 07:28:20 PM PDT 24
Peak memory 219488 kb
Host smart-ce435879-a408-412b-817d-0a79df1026dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3299080815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3299080815
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.4262751487
Short name T283
Test name
Test status
Simulation time 103812489436 ps
CPU time 400.4 seconds
Started Aug 10 07:28:04 PM PDT 24
Finished Aug 10 07:34:44 PM PDT 24
Peak memory 268084 kb
Host smart-0b569bb7-5755-4315-941d-98fe296e17e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262751487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.4262751487
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3693016995
Short name T313
Test name
Test status
Simulation time 5656320404 ps
CPU time 11.52 seconds
Started Aug 10 07:28:04 PM PDT 24
Finished Aug 10 07:28:16 PM PDT 24
Peak memory 217104 kb
Host smart-0b2b7f0a-2af9-41c9-b9e5-68fbf62613e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693016995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3693016995
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2043351401
Short name T641
Test name
Test status
Simulation time 9355554474 ps
CPU time 8.12 seconds
Started Aug 10 07:28:06 PM PDT 24
Finished Aug 10 07:28:14 PM PDT 24
Peak memory 216748 kb
Host smart-6edf489a-2ea7-407d-8d52-d575d5644a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043351401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2043351401
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2633328420
Short name T53
Test name
Test status
Simulation time 56991896 ps
CPU time 1.21 seconds
Started Aug 10 07:28:07 PM PDT 24
Finished Aug 10 07:28:08 PM PDT 24
Peak memory 216684 kb
Host smart-672ebe02-6bae-481a-b190-861fd86d3c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633328420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2633328420
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1605356079
Short name T969
Test name
Test status
Simulation time 169666289 ps
CPU time 0.94 seconds
Started Aug 10 07:28:05 PM PDT 24
Finished Aug 10 07:28:06 PM PDT 24
Peak memory 206316 kb
Host smart-d5875255-72b5-4d45-80ec-5c8bc97b6191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605356079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1605356079
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3073924357
Short name T442
Test name
Test status
Simulation time 37582847849 ps
CPU time 24.4 seconds
Started Aug 10 07:28:06 PM PDT 24
Finished Aug 10 07:28:30 PM PDT 24
Peak memory 224820 kb
Host smart-4372730b-f4ba-49fc-8b40-64895bfba8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073924357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3073924357
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2441111659
Short name T569
Test name
Test status
Simulation time 12256841 ps
CPU time 0.74 seconds
Started Aug 10 07:28:13 PM PDT 24
Finished Aug 10 07:28:14 PM PDT 24
Peak memory 205876 kb
Host smart-086aeeff-3882-4b07-a4fc-86ff0623c9be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441111659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2441111659
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3302885823
Short name T706
Test name
Test status
Simulation time 123476814 ps
CPU time 2.34 seconds
Started Aug 10 07:28:05 PM PDT 24
Finished Aug 10 07:28:07 PM PDT 24
Peak memory 224896 kb
Host smart-d66fdef5-ee64-4c3a-b782-5bbbe59ac722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302885823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3302885823
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1228279234
Short name T661
Test name
Test status
Simulation time 12779778 ps
CPU time 0.79 seconds
Started Aug 10 07:28:07 PM PDT 24
Finished Aug 10 07:28:07 PM PDT 24
Peak memory 206972 kb
Host smart-0421e8b2-e694-4f87-9a8e-75227928d009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228279234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1228279234
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1842202391
Short name T184
Test name
Test status
Simulation time 106450538715 ps
CPU time 343.66 seconds
Started Aug 10 07:28:05 PM PDT 24
Finished Aug 10 07:33:49 PM PDT 24
Peak memory 254464 kb
Host smart-e5e452ea-56a2-4773-b014-92b1c3d81e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842202391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1842202391
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2668065766
Short name T231
Test name
Test status
Simulation time 5452417446 ps
CPU time 71.13 seconds
Started Aug 10 07:28:10 PM PDT 24
Finished Aug 10 07:29:22 PM PDT 24
Peak memory 257804 kb
Host smart-559eb6ab-1768-4774-8f08-590f88b87926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668065766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2668065766
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1818516134
Short name T311
Test name
Test status
Simulation time 10717249465 ps
CPU time 73.42 seconds
Started Aug 10 07:28:09 PM PDT 24
Finished Aug 10 07:29:23 PM PDT 24
Peak memory 233176 kb
Host smart-4950a770-7354-42ab-8734-c5069e6d28c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818516134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1818516134
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1261343826
Short name T307
Test name
Test status
Simulation time 4464258833 ps
CPU time 41.56 seconds
Started Aug 10 07:28:07 PM PDT 24
Finished Aug 10 07:28:49 PM PDT 24
Peak memory 233096 kb
Host smart-fce2fcac-456d-4829-a1d2-904b5991d86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261343826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1261343826
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1297695568
Short name T765
Test name
Test status
Simulation time 68020919835 ps
CPU time 118.26 seconds
Started Aug 10 07:28:06 PM PDT 24
Finished Aug 10 07:30:04 PM PDT 24
Peak memory 253724 kb
Host smart-f7f0dd5b-199b-4a92-980a-8c3475bc96df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297695568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1297695568
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3440933187
Short name T700
Test name
Test status
Simulation time 6222231752 ps
CPU time 13.93 seconds
Started Aug 10 07:28:06 PM PDT 24
Finished Aug 10 07:28:20 PM PDT 24
Peak memory 224864 kb
Host smart-34fff223-064f-4f33-bff0-370e698016f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440933187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3440933187
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3418932236
Short name T901
Test name
Test status
Simulation time 82832714 ps
CPU time 3.14 seconds
Started Aug 10 07:28:08 PM PDT 24
Finished Aug 10 07:28:11 PM PDT 24
Peak memory 224888 kb
Host smart-6c1081f0-5c90-4c7a-b3ea-e49e2f77d848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418932236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3418932236
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2593987754
Short name T597
Test name
Test status
Simulation time 1980594370 ps
CPU time 4.06 seconds
Started Aug 10 07:28:09 PM PDT 24
Finished Aug 10 07:28:13 PM PDT 24
Peak memory 233148 kb
Host smart-d4fe44dc-021e-4906-a19b-ed9a94589f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593987754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2593987754
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1573846425
Short name T225
Test name
Test status
Simulation time 23545705048 ps
CPU time 20.09 seconds
Started Aug 10 07:28:06 PM PDT 24
Finished Aug 10 07:28:26 PM PDT 24
Peak memory 229812 kb
Host smart-1f90ecb2-23ba-499b-8a02-ec566953c36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573846425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1573846425
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2200258085
Short name T474
Test name
Test status
Simulation time 175763903 ps
CPU time 4.48 seconds
Started Aug 10 07:28:07 PM PDT 24
Finished Aug 10 07:28:12 PM PDT 24
Peak memory 219780 kb
Host smart-013c4d3e-a818-48f0-8c57-e25171c4f2a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2200258085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2200258085
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.895774118
Short name T261
Test name
Test status
Simulation time 222279864057 ps
CPU time 173.41 seconds
Started Aug 10 07:28:14 PM PDT 24
Finished Aug 10 07:31:08 PM PDT 24
Peak memory 249612 kb
Host smart-cb182165-62ee-45cf-90e7-eece078b6bf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895774118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.895774118
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2072465261
Short name T565
Test name
Test status
Simulation time 24297447161 ps
CPU time 12.43 seconds
Started Aug 10 07:28:05 PM PDT 24
Finished Aug 10 07:28:17 PM PDT 24
Peak memory 216776 kb
Host smart-5c53097a-abab-4838-9063-1e2adfab300a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072465261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2072465261
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3154634714
Short name T726
Test name
Test status
Simulation time 22626258561 ps
CPU time 19.13 seconds
Started Aug 10 07:28:06 PM PDT 24
Finished Aug 10 07:28:25 PM PDT 24
Peak memory 218032 kb
Host smart-5738a8e0-cfba-482e-be67-a745e748510b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154634714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3154634714
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3078309388
Short name T842
Test name
Test status
Simulation time 140610790 ps
CPU time 5.74 seconds
Started Aug 10 07:28:05 PM PDT 24
Finished Aug 10 07:28:11 PM PDT 24
Peak memory 216628 kb
Host smart-60f2e935-0805-417b-a6b2-d2872c80e44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078309388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3078309388
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3846674509
Short name T92
Test name
Test status
Simulation time 32974907 ps
CPU time 0.71 seconds
Started Aug 10 07:28:03 PM PDT 24
Finished Aug 10 07:28:04 PM PDT 24
Peak memory 206292 kb
Host smart-b0ebf675-3f59-4ff4-91b4-7fcb574b3e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846674509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3846674509
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3668651527
Short name T254
Test name
Test status
Simulation time 509782928 ps
CPU time 2.77 seconds
Started Aug 10 07:28:08 PM PDT 24
Finished Aug 10 07:28:11 PM PDT 24
Peak memory 224900 kb
Host smart-f4b179a1-dd8c-4ea5-b782-4f392f5c18b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668651527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3668651527
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3719105222
Short name T724
Test name
Test status
Simulation time 41444616 ps
CPU time 0.72 seconds
Started Aug 10 07:24:55 PM PDT 24
Finished Aug 10 07:24:56 PM PDT 24
Peak memory 205844 kb
Host smart-8e60255a-14c4-4b38-ae6c-d90577ecc233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719105222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
719105222
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3124778781
Short name T48
Test name
Test status
Simulation time 157015944 ps
CPU time 3.99 seconds
Started Aug 10 07:25:01 PM PDT 24
Finished Aug 10 07:25:05 PM PDT 24
Peak memory 233072 kb
Host smart-077ec5a2-d8f2-493b-8240-06285425fbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124778781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3124778781
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3119310955
Short name T976
Test name
Test status
Simulation time 48762795 ps
CPU time 0.79 seconds
Started Aug 10 07:24:46 PM PDT 24
Finished Aug 10 07:24:47 PM PDT 24
Peak memory 207232 kb
Host smart-50a59abd-ad56-4b65-b6b0-3f33eba42a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119310955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3119310955
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1874184156
Short name T289
Test name
Test status
Simulation time 3866627139 ps
CPU time 48.47 seconds
Started Aug 10 07:24:53 PM PDT 24
Finished Aug 10 07:25:42 PM PDT 24
Peak memory 249616 kb
Host smart-3d12ff75-86f2-4a82-bf39-8ad134c11e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874184156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1874184156
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.724093257
Short name T794
Test name
Test status
Simulation time 17816363048 ps
CPU time 92.78 seconds
Started Aug 10 07:24:54 PM PDT 24
Finished Aug 10 07:26:27 PM PDT 24
Peak memory 266328 kb
Host smart-594417e3-1c79-4543-958c-411e0b492f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724093257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.724093257
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.542293085
Short name T477
Test name
Test status
Simulation time 1404478225 ps
CPU time 19.34 seconds
Started Aug 10 07:24:53 PM PDT 24
Finished Aug 10 07:25:13 PM PDT 24
Peak memory 225016 kb
Host smart-500149a0-3224-4937-ac14-48a4c3df667d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542293085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
542293085
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1565928980
Short name T616
Test name
Test status
Simulation time 229357875 ps
CPU time 7.27 seconds
Started Aug 10 07:24:57 PM PDT 24
Finished Aug 10 07:25:05 PM PDT 24
Peak memory 233108 kb
Host smart-ef9d5d23-41d4-4e9e-b07c-944ae6b03c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565928980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1565928980
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1266660689
Short name T206
Test name
Test status
Simulation time 16527815142 ps
CPU time 150.07 seconds
Started Aug 10 07:24:57 PM PDT 24
Finished Aug 10 07:27:27 PM PDT 24
Peak memory 252936 kb
Host smart-f97276cd-1e2d-4ab3-873a-f361522c092d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266660689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1266660689
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.758019709
Short name T890
Test name
Test status
Simulation time 2160549548 ps
CPU time 23.51 seconds
Started Aug 10 07:24:54 PM PDT 24
Finished Aug 10 07:25:18 PM PDT 24
Peak memory 224984 kb
Host smart-d0878561-0fc7-408d-88e9-7e710e5e5167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758019709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.758019709
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.202166567
Short name T848
Test name
Test status
Simulation time 2489291912 ps
CPU time 29.17 seconds
Started Aug 10 07:24:57 PM PDT 24
Finished Aug 10 07:25:26 PM PDT 24
Peak memory 233404 kb
Host smart-42355986-1056-43bb-a76d-208a51a43e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202166567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.202166567
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3136609463
Short name T995
Test name
Test status
Simulation time 5623078155 ps
CPU time 15.25 seconds
Started Aug 10 07:25:01 PM PDT 24
Finished Aug 10 07:25:16 PM PDT 24
Peak memory 224976 kb
Host smart-b66d7784-5dc6-4128-b956-8e214b2d4717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136609463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3136609463
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3752817442
Short name T937
Test name
Test status
Simulation time 33358034526 ps
CPU time 19.54 seconds
Started Aug 10 07:25:01 PM PDT 24
Finished Aug 10 07:25:21 PM PDT 24
Peak memory 233192 kb
Host smart-14b68907-7f07-4f5f-b7dd-95baeaaf54a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752817442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3752817442
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3803673194
Short name T458
Test name
Test status
Simulation time 354316824 ps
CPU time 4.02 seconds
Started Aug 10 07:24:52 PM PDT 24
Finished Aug 10 07:24:56 PM PDT 24
Peak memory 223676 kb
Host smart-82a3e7bd-f623-47fc-bba2-de589257450e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3803673194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3803673194
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3834565672
Short name T431
Test name
Test status
Simulation time 45331473 ps
CPU time 0.96 seconds
Started Aug 10 07:24:54 PM PDT 24
Finished Aug 10 07:24:55 PM PDT 24
Peak memory 207024 kb
Host smart-3975df35-237f-4257-a099-ef5a9a7080eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834565672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3834565672
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.4016392285
Short name T601
Test name
Test status
Simulation time 848410748 ps
CPU time 8.06 seconds
Started Aug 10 07:24:54 PM PDT 24
Finished Aug 10 07:25:02 PM PDT 24
Peak memory 216864 kb
Host smart-4723d22c-87fb-4105-8379-a3b243bb2dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016392285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.4016392285
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3139529211
Short name T978
Test name
Test status
Simulation time 287521457 ps
CPU time 2.75 seconds
Started Aug 10 07:24:54 PM PDT 24
Finished Aug 10 07:24:57 PM PDT 24
Peak memory 216804 kb
Host smart-4eeb8c21-ac5c-4785-a78c-0530bbc88dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139529211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3139529211
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.806782556
Short name T623
Test name
Test status
Simulation time 196848103 ps
CPU time 1.96 seconds
Started Aug 10 07:24:54 PM PDT 24
Finished Aug 10 07:24:57 PM PDT 24
Peak memory 216640 kb
Host smart-b7f0c967-8c52-48bb-96b6-614580581f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806782556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.806782556
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3625607092
Short name T986
Test name
Test status
Simulation time 175374215 ps
CPU time 0.83 seconds
Started Aug 10 07:24:57 PM PDT 24
Finished Aug 10 07:24:58 PM PDT 24
Peak memory 206300 kb
Host smart-66f3bd70-7246-4325-b985-5ab2385f98da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625607092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3625607092
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1915229240
Short name T949
Test name
Test status
Simulation time 2953261029 ps
CPU time 7.34 seconds
Started Aug 10 07:24:56 PM PDT 24
Finished Aug 10 07:25:04 PM PDT 24
Peak memory 233144 kb
Host smart-f0a5a620-2097-4966-920f-181d6b799ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915229240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1915229240
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2690821996
Short name T768
Test name
Test status
Simulation time 34401884 ps
CPU time 0.68 seconds
Started Aug 10 07:25:05 PM PDT 24
Finished Aug 10 07:25:06 PM PDT 24
Peak memory 205248 kb
Host smart-166fcb1f-c996-4b01-87a3-5689a7546279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690821996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
690821996
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3507819504
Short name T97
Test name
Test status
Simulation time 1726163482 ps
CPU time 4.92 seconds
Started Aug 10 07:25:05 PM PDT 24
Finished Aug 10 07:25:10 PM PDT 24
Peak memory 224936 kb
Host smart-5c1b09f6-1fec-4742-8721-25878e2cde83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507819504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3507819504
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1729596669
Short name T58
Test name
Test status
Simulation time 36057790 ps
CPU time 0.82 seconds
Started Aug 10 07:24:57 PM PDT 24
Finished Aug 10 07:24:58 PM PDT 24
Peak memory 206892 kb
Host smart-af41bd22-761e-4240-a2a7-5e836f6f3690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729596669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1729596669
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1955597120
Short name T772
Test name
Test status
Simulation time 76214794183 ps
CPU time 156.34 seconds
Started Aug 10 07:25:02 PM PDT 24
Finished Aug 10 07:27:39 PM PDT 24
Peak memory 250504 kb
Host smart-69fa2cec-aff2-4210-81f6-c1b08553553c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955597120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1955597120
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1675698695
Short name T802
Test name
Test status
Simulation time 19025697000 ps
CPU time 27.99 seconds
Started Aug 10 07:25:02 PM PDT 24
Finished Aug 10 07:25:30 PM PDT 24
Peak memory 224884 kb
Host smart-8cf31176-0c3d-45cd-acf3-68b9bda3b2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675698695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1675698695
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.318586643
Short name T281
Test name
Test status
Simulation time 6125614226 ps
CPU time 79.18 seconds
Started Aug 10 07:25:03 PM PDT 24
Finished Aug 10 07:26:22 PM PDT 24
Peak memory 249640 kb
Host smart-f671ba1e-cb89-4ed8-854c-381404071540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318586643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
318586643
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2804034741
Short name T664
Test name
Test status
Simulation time 547961197 ps
CPU time 5.36 seconds
Started Aug 10 07:25:02 PM PDT 24
Finished Aug 10 07:25:07 PM PDT 24
Peak memory 224888 kb
Host smart-8dbbfae0-a11b-47d9-8dde-877ed8343651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804034741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2804034741
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.676519113
Short name T744
Test name
Test status
Simulation time 4383742705 ps
CPU time 29.43 seconds
Started Aug 10 07:25:12 PM PDT 24
Finished Aug 10 07:25:41 PM PDT 24
Peak memory 225004 kb
Host smart-bd5689e8-63ed-48f4-97ab-55e122bc9695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676519113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
676519113
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1356526851
Short name T354
Test name
Test status
Simulation time 110487494 ps
CPU time 2.48 seconds
Started Aug 10 07:25:06 PM PDT 24
Finished Aug 10 07:25:09 PM PDT 24
Peak memory 224288 kb
Host smart-9997dada-ad86-4b8a-bfc7-b6ac9fd00f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356526851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1356526851
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3714280625
Short name T248
Test name
Test status
Simulation time 10195084576 ps
CPU time 38.93 seconds
Started Aug 10 07:25:00 PM PDT 24
Finished Aug 10 07:25:39 PM PDT 24
Peak memory 233212 kb
Host smart-e4dcd1a4-a1b0-46fd-9157-2bc1dfa39003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714280625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3714280625
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.880348559
Short name T233
Test name
Test status
Simulation time 1925485587 ps
CPU time 2.87 seconds
Started Aug 10 07:25:17 PM PDT 24
Finished Aug 10 07:25:20 PM PDT 24
Peak memory 224804 kb
Host smart-70aebad5-c226-4f92-9e52-b25cd78b24a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880348559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
880348559
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2481407074
Short name T245
Test name
Test status
Simulation time 1752646436 ps
CPU time 4.06 seconds
Started Aug 10 07:24:57 PM PDT 24
Finished Aug 10 07:25:02 PM PDT 24
Peak memory 233056 kb
Host smart-a63dcfba-3528-45ca-8b42-59b8f0f9f172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481407074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2481407074
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3202907804
Short name T151
Test name
Test status
Simulation time 605081711 ps
CPU time 7.78 seconds
Started Aug 10 07:25:05 PM PDT 24
Finished Aug 10 07:25:12 PM PDT 24
Peak memory 223620 kb
Host smart-8731ddc7-33ac-4300-9c37-cba8f82ae55f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3202907804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3202907804
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2985350920
Short name T16
Test name
Test status
Simulation time 8031451682 ps
CPU time 46.38 seconds
Started Aug 10 07:25:06 PM PDT 24
Finished Aug 10 07:25:52 PM PDT 24
Peak memory 249572 kb
Host smart-090c921c-739c-4d64-9ca4-7562ddcc2eef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985350920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2985350920
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2979187830
Short name T730
Test name
Test status
Simulation time 7760543562 ps
CPU time 40.3 seconds
Started Aug 10 07:24:53 PM PDT 24
Finished Aug 10 07:25:33 PM PDT 24
Peak memory 216708 kb
Host smart-8c5e43cc-5487-48da-b3fb-20edef64c419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979187830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2979187830
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3540808540
Short name T31
Test name
Test status
Simulation time 2447779280 ps
CPU time 5.28 seconds
Started Aug 10 07:24:52 PM PDT 24
Finished Aug 10 07:24:57 PM PDT 24
Peak memory 216732 kb
Host smart-4c9165f8-94d0-41f6-931f-fd54b32559d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540808540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3540808540
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2495670028
Short name T867
Test name
Test status
Simulation time 255015096 ps
CPU time 4.42 seconds
Started Aug 10 07:24:54 PM PDT 24
Finished Aug 10 07:24:59 PM PDT 24
Peak memory 216636 kb
Host smart-b9e638b4-e18d-42a0-a394-e3f888d5e0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495670028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2495670028
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3169781976
Short name T581
Test name
Test status
Simulation time 26322460 ps
CPU time 0.77 seconds
Started Aug 10 07:24:54 PM PDT 24
Finished Aug 10 07:24:55 PM PDT 24
Peak memory 206400 kb
Host smart-3d28047a-d94d-4cd9-bfd8-92b38c71f32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169781976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3169781976
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1335740285
Short name T212
Test name
Test status
Simulation time 11967566727 ps
CPU time 5.16 seconds
Started Aug 10 07:25:04 PM PDT 24
Finished Aug 10 07:25:09 PM PDT 24
Peak memory 224948 kb
Host smart-90008717-c5cf-4a37-beee-a22fab8f6c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335740285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1335740285
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2356011695
Short name T471
Test name
Test status
Simulation time 16803599 ps
CPU time 0.73 seconds
Started Aug 10 07:25:03 PM PDT 24
Finished Aug 10 07:25:03 PM PDT 24
Peak memory 205796 kb
Host smart-5848c94f-d61c-4b6d-8815-da69823cd510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356011695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
356011695
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.346113139
Short name T476
Test name
Test status
Simulation time 94621932 ps
CPU time 2.79 seconds
Started Aug 10 07:25:02 PM PDT 24
Finished Aug 10 07:25:05 PM PDT 24
Peak memory 233048 kb
Host smart-a28c072f-16fe-45a3-a973-9db8d316f866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346113139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.346113139
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1081346950
Short name T370
Test name
Test status
Simulation time 13875653 ps
CPU time 0.72 seconds
Started Aug 10 07:25:06 PM PDT 24
Finished Aug 10 07:25:07 PM PDT 24
Peak memory 205896 kb
Host smart-a1b2ca3a-6b14-44ab-b9a5-579337fc7a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081346950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1081346950
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3585804997
Short name T398
Test name
Test status
Simulation time 210351337154 ps
CPU time 113.85 seconds
Started Aug 10 07:25:04 PM PDT 24
Finished Aug 10 07:26:58 PM PDT 24
Peak memory 241348 kb
Host smart-1288dd30-0abf-4c49-95f0-a82a2fba8e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585804997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3585804997
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3477159059
Short name T83
Test name
Test status
Simulation time 31142288430 ps
CPU time 85.38 seconds
Started Aug 10 07:25:03 PM PDT 24
Finished Aug 10 07:26:29 PM PDT 24
Peak memory 268396 kb
Host smart-7531858d-2914-45fc-bd6a-d9e43da1de23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477159059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3477159059
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3085871123
Short name T444
Test name
Test status
Simulation time 32594722288 ps
CPU time 58 seconds
Started Aug 10 07:25:00 PM PDT 24
Finished Aug 10 07:25:58 PM PDT 24
Peak memory 257764 kb
Host smart-ae00e02e-16dc-40e7-8c40-6382f6a0ada5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085871123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3085871123
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3964691990
Short name T838
Test name
Test status
Simulation time 1664776806 ps
CPU time 24.08 seconds
Started Aug 10 07:25:12 PM PDT 24
Finished Aug 10 07:25:37 PM PDT 24
Peak memory 233148 kb
Host smart-13d2670f-81b9-4dff-9bc5-f0178e3c89ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964691990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3964691990
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2110631123
Short name T888
Test name
Test status
Simulation time 78849331401 ps
CPU time 266.74 seconds
Started Aug 10 07:25:02 PM PDT 24
Finished Aug 10 07:29:29 PM PDT 24
Peak memory 251292 kb
Host smart-28abc34e-d556-4266-8736-72070ef9c094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110631123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2110631123
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2528583022
Short name T572
Test name
Test status
Simulation time 205010832 ps
CPU time 5.11 seconds
Started Aug 10 07:25:06 PM PDT 24
Finished Aug 10 07:25:11 PM PDT 24
Peak memory 233184 kb
Host smart-0daa2ce0-3b19-4094-b63b-1088169663c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528583022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2528583022
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.266799698
Short name T751
Test name
Test status
Simulation time 1386845602 ps
CPU time 6.95 seconds
Started Aug 10 07:25:00 PM PDT 24
Finished Aug 10 07:25:07 PM PDT 24
Peak memory 224952 kb
Host smart-7c43d8f3-47aa-496f-ae2a-f94841fef54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266799698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.266799698
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3142540191
Short name T263
Test name
Test status
Simulation time 978817198 ps
CPU time 4.13 seconds
Started Aug 10 07:25:04 PM PDT 24
Finished Aug 10 07:25:09 PM PDT 24
Peak memory 224892 kb
Host smart-49a7463d-54d8-4211-b636-1c0a2726afbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142540191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3142540191
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.434507626
Short name T907
Test name
Test status
Simulation time 1340545372 ps
CPU time 3.14 seconds
Started Aug 10 07:25:00 PM PDT 24
Finished Aug 10 07:25:03 PM PDT 24
Peak memory 224940 kb
Host smart-e8249662-0057-40b2-8251-92ea4f10e9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434507626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.434507626
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1986402486
Short name T863
Test name
Test status
Simulation time 181901340 ps
CPU time 3.81 seconds
Started Aug 10 07:25:13 PM PDT 24
Finished Aug 10 07:25:17 PM PDT 24
Peak memory 220908 kb
Host smart-67d10f89-1f31-45b1-ad71-4b53c8f46120
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1986402486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1986402486
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3692192039
Short name T21
Test name
Test status
Simulation time 8235548044 ps
CPU time 34.67 seconds
Started Aug 10 07:25:01 PM PDT 24
Finished Aug 10 07:25:36 PM PDT 24
Peak memory 225084 kb
Host smart-78efa3d8-1396-4105-be78-da95f5cc6516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692192039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3692192039
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.388393665
Short name T547
Test name
Test status
Simulation time 13009647280 ps
CPU time 30.11 seconds
Started Aug 10 07:25:02 PM PDT 24
Finished Aug 10 07:25:32 PM PDT 24
Peak memory 217136 kb
Host smart-186d1cfb-6bc8-40f3-9eb5-b67a2db034e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388393665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.388393665
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.576251620
Short name T560
Test name
Test status
Simulation time 3656652936 ps
CPU time 6.58 seconds
Started Aug 10 07:25:05 PM PDT 24
Finished Aug 10 07:25:12 PM PDT 24
Peak memory 216644 kb
Host smart-27216d06-813d-470e-815c-7da9ad5b9a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576251620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.576251620
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2673095062
Short name T844
Test name
Test status
Simulation time 22896927 ps
CPU time 0.92 seconds
Started Aug 10 07:25:02 PM PDT 24
Finished Aug 10 07:25:03 PM PDT 24
Peak memory 207528 kb
Host smart-7ca9d2c0-bb17-4683-8985-bb21f6e4100e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673095062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2673095062
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2196918272
Short name T670
Test name
Test status
Simulation time 897848954 ps
CPU time 0.87 seconds
Started Aug 10 07:25:04 PM PDT 24
Finished Aug 10 07:25:05 PM PDT 24
Peak memory 206356 kb
Host smart-b61315ff-f771-4b85-9918-308eb4bbf218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196918272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2196918272
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3879748799
Short name T736
Test name
Test status
Simulation time 801532848 ps
CPU time 8.09 seconds
Started Aug 10 07:25:07 PM PDT 24
Finished Aug 10 07:25:15 PM PDT 24
Peak memory 224884 kb
Host smart-885b6080-d4cd-4b02-afa7-c2f041765982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879748799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3879748799
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1124740279
Short name T541
Test name
Test status
Simulation time 40119157 ps
CPU time 0.75 seconds
Started Aug 10 07:25:03 PM PDT 24
Finished Aug 10 07:25:04 PM PDT 24
Peak memory 205836 kb
Host smart-015b37f8-8f15-4a21-9b71-7088c9a8b21f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124740279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
124740279
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1439133002
Short name T626
Test name
Test status
Simulation time 763852505 ps
CPU time 6.78 seconds
Started Aug 10 07:25:03 PM PDT 24
Finished Aug 10 07:25:10 PM PDT 24
Peak memory 233120 kb
Host smart-ec9eb40a-307c-4240-b99f-751a9db9b1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439133002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1439133002
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.66359813
Short name T490
Test name
Test status
Simulation time 38279397 ps
CPU time 0.75 seconds
Started Aug 10 07:25:03 PM PDT 24
Finished Aug 10 07:25:04 PM PDT 24
Peak memory 206016 kb
Host smart-36d3bd6f-c08c-4321-bf14-e6c75bc61d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66359813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.66359813
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1882794843
Short name T189
Test name
Test status
Simulation time 3424576273 ps
CPU time 54.38 seconds
Started Aug 10 07:25:02 PM PDT 24
Finished Aug 10 07:25:57 PM PDT 24
Peak memory 254548 kb
Host smart-527fc138-0c53-4152-9d9b-65e74faf1234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882794843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1882794843
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2186378011
Short name T717
Test name
Test status
Simulation time 6675348801 ps
CPU time 55 seconds
Started Aug 10 07:25:06 PM PDT 24
Finished Aug 10 07:26:02 PM PDT 24
Peak memory 241444 kb
Host smart-95b13de9-56aa-46fd-99b9-720f48e78374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186378011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2186378011
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2316357082
Short name T439
Test name
Test status
Simulation time 14216558838 ps
CPU time 140.61 seconds
Started Aug 10 07:25:02 PM PDT 24
Finished Aug 10 07:27:22 PM PDT 24
Peak memory 249504 kb
Host smart-bc25b20d-e322-4f9b-9cc5-14b204e020ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316357082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2316357082
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.433865354
Short name T43
Test name
Test status
Simulation time 1981373284 ps
CPU time 11.73 seconds
Started Aug 10 07:25:03 PM PDT 24
Finished Aug 10 07:25:15 PM PDT 24
Peak memory 233176 kb
Host smart-522857b0-1d84-4b3a-a3a0-7e90a01c1c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433865354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.433865354
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3020210280
Short name T201
Test name
Test status
Simulation time 7137370401 ps
CPU time 62.88 seconds
Started Aug 10 07:25:05 PM PDT 24
Finished Aug 10 07:26:08 PM PDT 24
Peak memory 254592 kb
Host smart-6984a18f-c9f9-42f6-bd96-6b8d0074842b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020210280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3020210280
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1976008346
Short name T771
Test name
Test status
Simulation time 9239218209 ps
CPU time 19.03 seconds
Started Aug 10 07:25:02 PM PDT 24
Finished Aug 10 07:25:21 PM PDT 24
Peak memory 224896 kb
Host smart-461552cb-86f1-48bc-b06e-234aac8f9572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976008346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1976008346
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1126981125
Short name T555
Test name
Test status
Simulation time 4050735568 ps
CPU time 47.75 seconds
Started Aug 10 07:25:02 PM PDT 24
Finished Aug 10 07:25:49 PM PDT 24
Peak memory 225052 kb
Host smart-31883943-5cb3-4d72-84cf-425ca317b9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126981125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1126981125
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.34656290
Short name T13
Test name
Test status
Simulation time 6129303663 ps
CPU time 8.9 seconds
Started Aug 10 07:25:06 PM PDT 24
Finished Aug 10 07:25:15 PM PDT 24
Peak memory 233152 kb
Host smart-40396045-2b15-4d5c-8ed6-36c286d62ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34656290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.34656290
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3893948222
Short name T209
Test name
Test status
Simulation time 887934723 ps
CPU time 4.92 seconds
Started Aug 10 07:25:05 PM PDT 24
Finished Aug 10 07:25:10 PM PDT 24
Peak memory 233092 kb
Host smart-54e3439c-64ed-48ef-9e90-0c1c6ea880c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893948222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3893948222
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2517338133
Short name T502
Test name
Test status
Simulation time 148361590 ps
CPU time 4.66 seconds
Started Aug 10 07:25:02 PM PDT 24
Finished Aug 10 07:25:07 PM PDT 24
Peak memory 223592 kb
Host smart-c4d4a31c-41c1-4445-bbdf-574468cf1ae4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2517338133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2517338133
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4157059974
Short name T20
Test name
Test status
Simulation time 22194197876 ps
CPU time 196.96 seconds
Started Aug 10 07:25:06 PM PDT 24
Finished Aug 10 07:28:23 PM PDT 24
Peak memory 256404 kb
Host smart-1a679a2d-8f19-4f4a-b081-7af0c2733afd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157059974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4157059974
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3795600905
Short name T40
Test name
Test status
Simulation time 2731907270 ps
CPU time 7.72 seconds
Started Aug 10 07:25:00 PM PDT 24
Finished Aug 10 07:25:08 PM PDT 24
Peak memory 216748 kb
Host smart-b622756f-b217-48e7-b45c-fcf66a580055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795600905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3795600905
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3362089188
Short name T368
Test name
Test status
Simulation time 632495729 ps
CPU time 4.62 seconds
Started Aug 10 07:25:04 PM PDT 24
Finished Aug 10 07:25:09 PM PDT 24
Peak memory 216568 kb
Host smart-c93b83f9-a568-4975-aec2-eee61c7d87d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362089188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3362089188
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2932388323
Short name T62
Test name
Test status
Simulation time 45747788 ps
CPU time 0.87 seconds
Started Aug 10 07:25:00 PM PDT 24
Finished Aug 10 07:25:01 PM PDT 24
Peak memory 206296 kb
Host smart-b31646c0-0886-4030-a7a0-b0428f424e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932388323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2932388323
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2816650242
Short name T824
Test name
Test status
Simulation time 76316804 ps
CPU time 0.93 seconds
Started Aug 10 07:25:05 PM PDT 24
Finished Aug 10 07:25:06 PM PDT 24
Peak memory 206348 kb
Host smart-461038ab-20fe-4f55-ad98-c3dbf2b69dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816650242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2816650242
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4215610011
Short name T384
Test name
Test status
Simulation time 3894450910 ps
CPU time 14.11 seconds
Started Aug 10 07:25:03 PM PDT 24
Finished Aug 10 07:25:17 PM PDT 24
Peak memory 240040 kb
Host smart-1d251483-191c-4b5c-ba43-0485f3bbe455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215610011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4215610011
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2813609236
Short name T424
Test name
Test status
Simulation time 19683680 ps
CPU time 0.71 seconds
Started Aug 10 07:25:09 PM PDT 24
Finished Aug 10 07:25:09 PM PDT 24
Peak memory 205284 kb
Host smart-aa887c92-a755-456b-bce6-6abefd44f9ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813609236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
813609236
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2620266419
Short name T82
Test name
Test status
Simulation time 1330118235 ps
CPU time 13.18 seconds
Started Aug 10 07:25:13 PM PDT 24
Finished Aug 10 07:25:26 PM PDT 24
Peak memory 233088 kb
Host smart-2a6a4046-bff5-477d-b218-e5bb49e79665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620266419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2620266419
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1899669916
Short name T440
Test name
Test status
Simulation time 61323187 ps
CPU time 0.75 seconds
Started Aug 10 07:25:11 PM PDT 24
Finished Aug 10 07:25:12 PM PDT 24
Peak memory 206984 kb
Host smart-e8a42437-c9b0-41c6-a337-96dd84eceb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899669916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1899669916
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4019132636
Short name T447
Test name
Test status
Simulation time 151596713 ps
CPU time 0.86 seconds
Started Aug 10 07:25:10 PM PDT 24
Finished Aug 10 07:25:11 PM PDT 24
Peak memory 216444 kb
Host smart-0496ff46-36b7-4dbe-94bb-ec7aebeacc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019132636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4019132636
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2027071092
Short name T36
Test name
Test status
Simulation time 85530475999 ps
CPU time 304.45 seconds
Started Aug 10 07:25:11 PM PDT 24
Finished Aug 10 07:30:15 PM PDT 24
Peak memory 257264 kb
Host smart-099a8b49-a2c8-4ce4-8037-cf96a52b0d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027071092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2027071092
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.76305939
Short name T50
Test name
Test status
Simulation time 152952225479 ps
CPU time 378.85 seconds
Started Aug 10 07:25:10 PM PDT 24
Finished Aug 10 07:31:29 PM PDT 24
Peak memory 254064 kb
Host smart-0a4598df-5be9-433b-b91f-7d06d035c730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76305939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.76305939
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1871881
Short name T977
Test name
Test status
Simulation time 66880864 ps
CPU time 2.7 seconds
Started Aug 10 07:25:09 PM PDT 24
Finished Aug 10 07:25:12 PM PDT 24
Peak memory 229532 kb
Host smart-b00dfa79-35cf-44c3-8ce9-c39412c1f0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1871881
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3350283187
Short name T923
Test name
Test status
Simulation time 44131498982 ps
CPU time 144.84 seconds
Started Aug 10 07:25:17 PM PDT 24
Finished Aug 10 07:27:42 PM PDT 24
Peak memory 263196 kb
Host smart-9851ea9b-52a7-483b-9172-74c83f25c7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350283187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3350283187
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1580372110
Short name T917
Test name
Test status
Simulation time 578703421 ps
CPU time 5.1 seconds
Started Aug 10 07:25:10 PM PDT 24
Finished Aug 10 07:25:15 PM PDT 24
Peak memory 233344 kb
Host smart-e5900935-ef59-49a0-855c-ffaf32eef48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580372110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1580372110
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3514496223
Short name T244
Test name
Test status
Simulation time 31866665851 ps
CPU time 36.61 seconds
Started Aug 10 07:25:10 PM PDT 24
Finished Aug 10 07:25:47 PM PDT 24
Peak memory 233348 kb
Host smart-62a87144-77b2-4800-9ce1-fe2d7b8ac88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514496223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3514496223
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1610044214
Short name T132
Test name
Test status
Simulation time 272215210 ps
CPU time 6.2 seconds
Started Aug 10 07:25:12 PM PDT 24
Finished Aug 10 07:25:18 PM PDT 24
Peak memory 224944 kb
Host smart-5278c23c-e33a-4bd9-aba0-abab9f2cb7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610044214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1610044214
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3888549641
Short name T699
Test name
Test status
Simulation time 33327181145 ps
CPU time 26.82 seconds
Started Aug 10 07:25:07 PM PDT 24
Finished Aug 10 07:25:34 PM PDT 24
Peak memory 239692 kb
Host smart-8f6e0e0d-d6b0-424a-a259-95f37774112f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888549641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3888549641
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.840101593
Short name T44
Test name
Test status
Simulation time 2685665789 ps
CPU time 9.59 seconds
Started Aug 10 07:25:10 PM PDT 24
Finished Aug 10 07:25:19 PM PDT 24
Peak memory 219136 kb
Host smart-d915c957-16e6-466e-9b95-5f6d567a217c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=840101593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.840101593
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.36387371
Short name T408
Test name
Test status
Simulation time 193060863 ps
CPU time 1.11 seconds
Started Aug 10 07:25:09 PM PDT 24
Finished Aug 10 07:25:10 PM PDT 24
Peak memory 207388 kb
Host smart-285ae35b-a976-480e-9e05-07abc8447332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36387371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_
all.36387371
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1084876588
Short name T513
Test name
Test status
Simulation time 7845071030 ps
CPU time 36.22 seconds
Started Aug 10 07:25:07 PM PDT 24
Finished Aug 10 07:25:43 PM PDT 24
Peak memory 216632 kb
Host smart-5786ee05-0e97-46bf-93f7-71e926496180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084876588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1084876588
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1322958857
Short name T854
Test name
Test status
Simulation time 2215856831 ps
CPU time 5.53 seconds
Started Aug 10 07:25:07 PM PDT 24
Finished Aug 10 07:25:13 PM PDT 24
Peak memory 216620 kb
Host smart-c41d69a9-cf5f-4876-9a28-6b4491b532c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322958857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1322958857
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1712237843
Short name T411
Test name
Test status
Simulation time 59418490 ps
CPU time 1.12 seconds
Started Aug 10 07:25:05 PM PDT 24
Finished Aug 10 07:25:06 PM PDT 24
Peak memory 216456 kb
Host smart-f9655586-b9d1-4f6f-a929-29471af6186f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712237843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1712237843
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1037222531
Short name T602
Test name
Test status
Simulation time 50751312 ps
CPU time 0.8 seconds
Started Aug 10 07:25:07 PM PDT 24
Finished Aug 10 07:25:08 PM PDT 24
Peak memory 206224 kb
Host smart-64606923-80e6-440c-9395-9c7a66e19bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037222531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1037222531
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.4116608880
Short name T825
Test name
Test status
Simulation time 222545008 ps
CPU time 2.82 seconds
Started Aug 10 07:25:11 PM PDT 24
Finished Aug 10 07:25:14 PM PDT 24
Peak memory 232864 kb
Host smart-6583bfff-d8a3-4391-9ba5-e77a5baf3226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116608880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4116608880
Directory /workspace/9.spi_device_upload/latest
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