Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2365248	1			T2	1		T4	2616		T5	1
all_values[1]	2365248	1			T2	1		T4	2616		T5	1
all_values[2]	2365248	1			T2	1		T4	2616		T5	1
all_values[3]	2365248	1			T2	1		T4	2616		T5	1
all_values[4]	2365248	1			T2	1		T4	2616		T5	1
all_values[5]	2365248	1			T2	1		T4	2616		T5	1
all_values[6]	2365248	1			T2	1		T4	2616		T5	1
all_values[7]	2365248	1			T2	1		T4	2616		T5	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18512545

1

T2

8

T4

20928

T5

8

auto[1]

409439

1

T7

23

T16

13608

T18

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18899837

1

T2

8

T4

20928

T5

8

auto[1]

22147

1

T7

24

T14

195

T16

44

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2244511	1			T2	1		T4	2616		T5	1
all_values[0]	auto[0]	auto[1]	10099	1			T7	4		T14	106		T16	11
all_values[0]	auto[1]	auto[0]	109802	1			T7	3		T16	5		T19	6
all_values[0]	auto[1]	auto[1]	836	1			T7	2		T16	1		T18	2
all_values[1]	auto[0]	auto[0]	2350981	1			T2	1		T4	2616		T5	1
all_values[1]	auto[0]	auto[1]	6761	1			T7	4		T14	74		T16	3
all_values[1]	auto[1]	auto[0]	7310	1			T16	3392		T19	6		T20	2
all_values[1]	auto[1]	auto[1]	196	1			T16	2		T18	1		T19	9
all_values[2]	auto[0]	auto[0]	2318120	1			T2	1		T4	2616		T5	1
all_values[2]	auto[0]	auto[1]	2266	1			T7	1		T14	15		T16	2
all_values[2]	auto[1]	auto[0]	44595	1			T7	1		T16	3392		T18	3
all_values[2]	auto[1]	auto[1]	267	1			T16	2		T18	1		T19	5
all_values[3]	auto[0]	auto[0]	2300263	1			T2	1		T4	2616		T5	1
all_values[3]	auto[0]	auto[1]	181	1			T7	3		T16	1		T19	3
all_values[3]	auto[1]	auto[0]	64635	1			T16	4		T18	2		T19	4
all_values[3]	auto[1]	auto[1]	169	1			T7	1		T16	4		T18	3
all_values[4]	auto[0]	auto[0]	2333034	1			T2	1		T4	2616		T5	1
all_values[4]	auto[0]	auto[1]	185	1			T16	3		T19	2		T20	1
all_values[4]	auto[1]	auto[0]	31857	1			T7	3		T16	3398		T19	9
all_values[4]	auto[1]	auto[1]	172	1			T7	2		T16	1		T19	5
all_values[5]	auto[0]	auto[0]	2262241	1			T2	1		T4	2616		T5	1
all_values[5]	auto[0]	auto[1]	162	1			T16	3		T19	2		T20	5
all_values[5]	auto[1]	auto[0]	102680	1			T7	3		T16	3392		T18	2
all_values[5]	auto[1]	auto[1]	165	1			T7	2		T16	2		T18	3
all_values[6]	auto[0]	auto[0]	2364639	1			T2	1		T4	2616		T5	1
all_values[6]	auto[0]	auto[1]	182	1			T16	3		T18	1		T19	6
all_values[6]	auto[1]	auto[0]	250	1			T7	2		T16	4		T18	1
all_values[6]	auto[1]	auto[1]	177	1			T7	3		T16	2		T18	3
all_values[7]	auto[0]	auto[0]	2318776	1			T2	1		T4	2616		T5	1
all_values[7]	auto[0]	auto[1]	144	1			T7	2		T16	2		T18	3
all_values[7]	auto[1]	auto[0]	46143	1			T7	1		T16	5		T19	14
all_values[7]	auto[1]	auto[1]	185	1			T16	2		T18	1		T19	2