Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34178	1			T2	2		T4	202		T5	20
auto[SpiFlashAddrCfg]	7430	1			T4	25		T7	2		T10	6
auto[SpiFlashAddr3b]	9039	1			T2	4		T4	41		T7	6
auto[SpiFlashAddr4b]	7663	1			T4	39		T7	4		T9	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33786

1

T2

6

T4

212

T5

20

auto[1]

24524

1

T4

95

T7

9

T10

20

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31571

1

T2

4

T4

177

T5

8

auto[1]

26739

1

T2

2

T4

130

T5

12

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38804	1			T4	230		T5	20		T7	13
values[1]	1181	1			T2	2		T4	11		T14	4
values[2]	1458	1			T4	3		T10	1		T14	12
values[3]	1520	1			T2	2		T4	6		T7	1
values[4]	1442	1			T4	4		T10	2		T14	15
values[5]	1443	1			T4	5		T7	3		T10	2
values[6]	1479	1			T4	4		T7	2		T10	1
values[7]	1446	1			T4	2		T9	2		T10	1
values[8]	9537	1			T2	2		T4	42		T7	3

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27124

1

T2

6

T5

20

T9

8

auto[1]

31186

1

T4

307

T7

22

T39

201

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54992

1

T2

6

T4

288

T5

20

write

3318

1

T4

19

T7

2

T10

8

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19298

1

T2

2

T4

80

T7

8

valids[0x1]

39012

1

T2

4

T4

227

T5

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1592	1			T4	5		T5	8		T7	2
internal_process_ops[0x5a]	1540	1			T4	6		T7	1		T10	2
internal_process_ops[0x05]	19777	1			T4	137		T7	3		T10	1
internal_process_ops[0x35]	1607	1			T4	10		T5	4		T7	1
internal_process_ops[0x15]	1662	1			T4	8		T5	8		T10	3
internal_process_ops[0x03]	1013	1			T2	2		T4	4		T10	1
internal_process_ops[0x0b]	979	1			T4	1		T9	2		T10	2
internal_process_ops[0x3b]	1033	1			T4	2		T10	1		T14	7
internal_process_ops[0x6b]	1023	1			T4	2		T10	2		T14	7
internal_process_ops[0xbb]	1000	1			T4	1		T10	1		T14	11
internal_process_ops[0xeb]	1044	1			T4	3		T10	2		T14	12

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56673

1

T2

6

T4

301

T5

20

auto[1]

1637

1

T4

6

T10

5

T14

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55977

1

T2

6

T4

295

T5

20

auto[1]

2333

1

T4

12

T7

2

T10

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9534

1

T2

2

T5

20

T10

7

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4984

1

T10

4

T14

66

T35

63

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1843

1

T10

3

T14

19

T15

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1637

1

T10

2

T14

24

T35

5

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2228

1

T2

4

T9

6

T10

3

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1990

1

T10

5

T14

31

T35

5

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1854

1

T9

2

T10

6

T14

22

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1620

1

T10

2

T14

15

T35

8

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

130

1

T35

1

T30

1

T41

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

70

1

T30

2

T41

1

T42

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

89

1

T10

2

T41

1

T43

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

91

1

T10

1

T14

2

T17

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

102

1

T35

1

T63

2

T43

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

78

1

T10

1

T14

3

T42

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

81

1

T16

4

T42

2

T157

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

100

1

T35

1

T41

1

T42

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

108

1

T63

2

T30

4

T41

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

56

1

T41

1

T42

1

T43

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

70

1

T14

4

T30

2

T36

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

97

1

T10

2

T16

1

T41

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

118

1

T14

5

T40

2

T16

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

79

1

T35

1

T16

1

T30

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

73

1

T10

1

T30

2

T43

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

92

1

T10

1

T36

1

T158

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11260

1

T4

171

T7

9

T39

167

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7527

1

T4

28

T7

1

T39

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1624

1

T4

11

T39

2

T38

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1501

1

T4

11

T7

2

T39

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2002

1

T4

10

T7

4

T39

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2013

1

T4

29

T7

2

T39

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1740

1

T4

6

T39

8

T38

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1635

1

T4

22

T7

2

T39

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

133

1

T4

3

T39

2

T48

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

114

1

T48

3

T159

1

T160

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

121

1

T39

3

T48

2

T17

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

125

1

T48

1

T17

2

T159

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

108

1

T48

2

T49

7

T89

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

136

1

T4

3

T49

3

T47

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

106

1

T48

1

T47

1

T17

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

114

1

T48

2

T17

1

T159

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

119

1

T49

1

T17

1

T159

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

112

1

T4

1

T47

2

T159

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

110

1

T4

1

T48

1

T49

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

134

1

T48

1

T49

3

T17

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

116

1

T4

5

T48

1

T49

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

122

1

T4

2

T49

4

T17

7

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

97

1

T4

4

T7

2

T49

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

117

1

T48

1

T49

1

T47

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3475	1			T10	3		T14	46		T15	4
auto[0]	values[0]	valids[0x1]	13612	1			T5	20		T9	4		T10	19
auto[0]	values[1]	valids[0x1]	563	1			T2	2		T14	4		T35	3
auto[0]	values[2]	valids[0x0]	534	1			T10	1		T14	11		T16	6
auto[0]	values[2]	valids[0x1]	246	1			T14	1		T35	1		T16	3
auto[0]	values[3]	valids[0x0]	513	1			T14	5		T35	1		T63	2
auto[0]	values[3]	valids[0x1]	274	1			T2	2		T14	4		T23	2
auto[0]	values[4]	valids[0x0]	515	1			T10	2		T14	12		T15	4
auto[0]	values[4]	valids[0x1]	209	1			T14	3		T16	2		T30	4
auto[0]	values[5]	valids[0x0]	395	1			T10	2		T14	10		T35	1
auto[0]	values[5]	valids[0x1]	292	1			T14	5		T35	1		T16	2
auto[0]	values[6]	valids[0x0]	532	1			T10	1		T14	3		T35	2
auto[0]	values[6]	valids[0x1]	247	1			T14	4		T15	2		T30	4
auto[0]	values[7]	valids[0x0]	489	1			T10	1		T14	9		T40	2
auto[0]	values[7]	valids[0x1]	268	1			T9	2		T14	2		T35	1
auto[0]	values[8]	valids[0x0]	3122	1			T2	2		T9	2		T10	6
auto[0]	values[8]	valids[0x1]	1838	1			T10	5		T14	12		T15	2
auto[1]	values[0]	valids[0x0]	4501	1			T4	37		T7	4		T39	11
auto[1]	values[0]	valids[0x1]	17216	1			T4	193		T7	9		T39	174
auto[1]	values[1]	valids[0x1]	618	1			T4	11		T48	7		T49	7
auto[1]	values[2]	valids[0x0]	391	1			T4	1		T48	3		T49	1
auto[1]	values[2]	valids[0x1]	287	1			T4	2		T39	1		T38	2
auto[1]	values[3]	valids[0x0]	433	1			T4	6		T48	9		T49	5
auto[1]	values[3]	valids[0x1]	300	1			T7	1		T39	2		T48	1
auto[1]	values[4]	valids[0x0]	422	1			T4	2		T39	1		T38	2
auto[1]	values[4]	valids[0x1]	296	1			T4	2		T48	1		T49	3
auto[1]	values[5]	valids[0x0]	469	1			T4	3		T7	1		T49	7
auto[1]	values[5]	valids[0x1]	287	1			T4	2		T7	2		T38	2
auto[1]	values[6]	valids[0x0]	434	1			T4	3		T7	1		T48	9
auto[1]	values[6]	valids[0x1]	266	1			T4	1		T7	1		T39	1
auto[1]	values[7]	valids[0x0]	390	1			T4	1		T39	2		T48	1
auto[1]	values[7]	valids[0x1]	299	1			T4	1		T48	1		T49	4
auto[1]	values[8]	valids[0x0]	2683	1			T4	27		T7	2		T39	4
auto[1]	values[8]	valids[0x1]	1894	1			T4	15		T7	1		T39	5