Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3479394

1

T2

1

T4

12265

T5

43909

auto[1]

28342

1

T4

127

T7

2

T10

23

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1083458

1

T2

1

T4

59

T5

37893

auto[1]

2424278

1

T4

12333

T5

6016

T7

257

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	684945	1			T2	1		T4	521		T5	6027
auto[524288:1048575]	394503	1			T4	3241		T5	1546		T10	4
auto[1048576:1572863]	424034	1			T4	652		T5	1359		T7	258
auto[1572864:2097151]	349099	1			T4	258		T5	13383		T10	10
auto[2097152:2621439]	440252	1			T4	3849		T5	10875		T7	5
auto[2621440:3145727]	405063	1			T4	2935		T5	10513		T10	138
auto[3145728:3670015]	385449	1			T4	934		T5	205		T10	5
auto[3670016:4194303]	424391	1			T4	2		T5	1		T10	300

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2462244

1

T2

1

T4

12380

T5

6060

auto[1]

1045492

1

T4

12

T5

37849

T10

5

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3104998

1

T2

1

T4

6916

T5

43909

auto[1]

402738

1

T4

5476

T7

6

T10

18

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	197582	1			T2	1		T4	6		T5	5384
auto[0]	auto[0]	auto[0:524287]	auto[1]	406662	1			T4	500		T5	643		T10	3
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	129684	1			T4	10		T5	1544		T10	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	207115	1			T4	442		T5	2		T14	848
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	118434	1			T4	3		T5	1357		T7	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	253239	1			T4	641		T5	2		T7	254
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	116890	1			T4	2		T5	11795		T10	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	197374	1			T4	256		T5	1588		T14	339
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	130917	1			T4	3		T5	7744		T7	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	263373	1			T4	1083		T5	3131		T7	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	127195	1			T4	6		T5	9867		T10	10
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	225237	1			T4	2923		T5	646		T10	128
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	111725	1			T4	4		T5	201		T10	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	226131	1			T4	917		T5	4		T14	640
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	135126	1			T5	1		T10	25		T14	5
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	234377	1			T10	256		T14	1		T39	2
auto[0]	auto[1]	auto[0:524287]	auto[0]	2993	1			T4	2		T7	3		T14	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	73315	1			T39	1		T30	3068		T17	2
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2493	1			T4	5		T14	1		T30	6
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	50736	1			T4	2736		T14	5		T39	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	488	1			T7	1		T48	2		T49	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	48593	1			T7	1		T49	2		T41	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	507	1			T10	2		T14	2		T39	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	30136	1			T39	1		T35	2		T47	259
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1246	1			T4	4		T14	1		T16	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	41886	1			T4	2720		T16	2198		T30	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2357	1			T14	12		T35	2		T48	17
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	47037	1			T14	2773		T49	642		T42	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	811	1			T14	3		T48	42		T49	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	44024	1			T14	2692		T48	4		T49	910
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	727	1			T4	2		T10	7		T14	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	50984	1			T14	3820		T39	1		T48	569
auto[1]	auto[0]	auto[0:524287]	auto[0]	613	1			T4	2		T10	3		T35	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3321	1			T4	11		T35	22		T49	56
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	394	1			T4	3		T10	2		T39	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3362	1			T4	44		T39	17		T49	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	522	1			T4	1		T14	2		T16	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2219	1			T4	7		T14	3		T16	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	480	1			T10	2		T14	2		T30	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3132	1			T14	29		T30	7		T49	57
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	400	1			T4	2		T7	1		T14	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1635	1			T4	31		T14	10		T16	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	446	1			T4	1		T30	1		T48	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2392	1			T4	5		T30	5		T49	7
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	395	1			T4	1		T16	1		T49	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1855	1			T4	12		T16	2		T49	17
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	323	1			T10	7		T14	1		T39	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2448	1			T14	1		T39	76		T35	46
auto[1]	auto[1]	auto[0:524287]	auto[0]	109	1			T39	1		T30	1		T17	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	350	1			T17	6		T171	5		T225	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	87	1			T4	1		T30	2		T48	19
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	632	1			T30	8		T48	16		T49	82
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	83	1			T7	1		T49	2		T41	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	456	1			T49	23		T41	2		T47	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	74	1			T10	4		T39	1		T35	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	506	1			T39	57		T35	5		T47	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	90	1			T4	1		T16	1		T30	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	705	1			T4	5		T16	5		T30	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	81	1			T14	3		T49	2		T42	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	318	1			T14	2		T49	17		T42	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	108	1			T48	5		T49	1		T42	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	400	1			T49	4		T42	1		T47	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	78	1			T10	5		T39	1		T41	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	328	1			T39	5		T41	15		T159	7

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2042587	1			T2	1		T4	6790		T5	6060
auto[0]	auto[0]	auto[1]	1038474	1			T4	6		T5	37849		T14	2
auto[0]	auto[1]	auto[0]	392026	1			T4	5468		T7	5		T10	9
auto[0]	auto[1]	auto[1]	6307	1			T4	1		T39	3		T35	1
auto[1]	auto[0]	auto[0]	23341	1			T4	115		T7	1		T10	11
auto[1]	auto[0]	auto[1]	596	1			T4	5		T10	3		T14	1
auto[1]	auto[1]	auto[0]	4290	1			T4	7		T7	1		T10	7
auto[1]	auto[1]	auto[1]	115	1			T10	2		T14	1		T48	4