Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2365248	1			T2	1		T4	2616		T5	1
all_pins[1]	2365248	1			T2	1		T4	2616		T5	1
all_pins[2]	2365248	1			T2	1		T4	2616		T5	1
all_pins[3]	2365248	1			T2	1		T4	2616		T5	1
all_pins[4]	2365248	1			T2	1		T4	2616		T5	1
all_pins[5]	2365248	1			T2	1		T4	2616		T5	1
all_pins[6]	2365248	1			T2	1		T4	2616		T5	1
all_pins[7]	2365248	1			T2	1		T4	2616		T5	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18917232	1			T2	8		T4	20928		T5	8
values[0x1]	4752	1			T7	10		T16	637		T18	14
transitions[0x0=>0x1]	4365	1			T7	8		T16	631		T18	8
transitions[0x1=>0x0]	4376	1			T7	8		T16	631		T18	8

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2364342	1			T2	1		T4	2616		T5	1
all_pins[0]	values[0x1]	906	1			T7	2		T16	1		T18	2
all_pins[0]	transitions[0x0=>0x1]	837	1			T7	2		T16	1		T18	1
all_pins[0]	transitions[0x1=>0x0]	132	1			T16	5		T19	7		T20	4
all_pins[1]	values[0x0]	2365047	1			T2	1		T4	2616		T5	1
all_pins[1]	values[0x1]	201	1			T16	5		T18	1		T19	9
all_pins[1]	transitions[0x0=>0x1]	139	1			T16	1		T19	7		T20	2
all_pins[1]	transitions[0x1=>0x0]	218	1			T19	3		T20	1		T31	49
all_pins[2]	values[0x0]	2364968	1			T2	1		T4	2616		T5	1
all_pins[2]	values[0x1]	280	1			T16	4		T18	1		T19	5
all_pins[2]	transitions[0x0=>0x1]	246	1			T16	4		T19	5		T20	3
all_pins[2]	transitions[0x1=>0x0]	135	1			T7	1		T16	4		T18	2
all_pins[3]	values[0x0]	2365079	1			T2	1		T4	2616		T5	1
all_pins[3]	values[0x1]	169	1			T7	1		T16	4		T18	3
all_pins[3]	transitions[0x0=>0x1]	121	1			T7	1		T16	3		T18	3
all_pins[3]	transitions[0x1=>0x0]	124	1			T7	2		T19	4		T20	3
all_pins[4]	values[0x0]	2365076	1			T2	1		T4	2616		T5	1
all_pins[4]	values[0x1]	172	1			T7	2		T16	1		T19	5
all_pins[4]	transitions[0x0=>0x1]	144	1			T7	1		T19	4		T20	7
all_pins[4]	transitions[0x1=>0x0]	2634	1			T7	1		T16	617		T18	3
all_pins[5]	values[0x0]	2362586	1			T2	1		T4	2616		T5	1
all_pins[5]	values[0x1]	2662	1			T7	2		T16	618		T18	3
all_pins[5]	transitions[0x0=>0x1]	2626	1			T7	1		T16	618		T18	1
all_pins[5]	transitions[0x1=>0x0]	141	1			T7	2		T16	2		T18	1
all_pins[6]	values[0x0]	2365071	1			T2	1		T4	2616		T5	1
all_pins[6]	values[0x1]	177	1			T7	3		T16	2		T18	3
all_pins[6]	transitions[0x0=>0x1]	127	1			T7	3		T16	2		T18	2
all_pins[6]	transitions[0x1=>0x0]	135	1			T16	2		T19	2		T20	3
all_pins[7]	values[0x0]	2365063	1			T2	1		T4	2616		T5	1
all_pins[7]	values[0x1]	185	1			T16	2		T18	1		T19	2
all_pins[7]	transitions[0x0=>0x1]	125	1			T16	2		T18	1		T19	2
all_pins[7]	transitions[0x1=>0x0]	857	1			T7	2		T16	1		T18	2