Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16200

1

T2

6

T5

20

T9

8

auto[1]

10924

1

T10

20

T14

142

T35

82

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3095	1			T14	20		T46	10		T16	46
values[1]	4202	1			T14	51		T15	16		T35	43
values[2]	3362	1			T2	6		T14	22		T16	49
values[3]	3265	1			T14	51		T35	43		T30	95
values[4]	3736	1			T9	8		T14	40		T35	53
values[5]	3760	1			T5	20		T10	40		T14	20
values[6]	3159	1			T14	70		T30	20		T42	48
values[7]	2545	1			T23	4		T40	14		T16	24

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3222	1			T10	20		T14	31		T15	16
values[1]	3268	1			T10	20		T14	60		T30	94
values[2]	3506	1			T23	4		T16	49		T30	60
values[3]	3413	1			T35	43		T16	45		T30	49
values[4]	3478	1			T2	6		T5	20		T9	8
values[5]	3357	1			T14	87		T30	20		T204	10
values[6]	3243	1			T14	51		T40	14		T16	26
values[7]	3637	1			T35	43		T30	41		T96	4

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	177	1			T30	12		T180	13		T170	16
auto[0]	values[0]	values[1]	315	1			T14	13		T191	14		T187	68
auto[0]	values[0]	values[2]	282	1			T87	14		T181	13		T226	14
auto[0]	values[0]	values[3]	169	1			T30	10		T41	13		T157	9
auto[0]	values[0]	values[4]	225	1			T46	10		T16	10		T83	12
auto[0]	values[0]	values[5]	98	1			T182	9		T227	6		T228	22
auto[0]	values[0]	values[6]	213	1			T16	15		T30	6		T41	12
auto[0]	values[0]	values[7]	342	1			T22	17		T229	18		T192	8
auto[0]	values[1]	values[0]	307	1			T14	10		T15	16		T41	14
auto[0]	values[1]	values[1]	164	1			T36	14		T37	9		T230	16
auto[0]	values[1]	values[2]	362	1			T76	18		T192	17		T87	11
auto[0]	values[1]	values[3]	251	1			T17	15		T180	13		T59	15
auto[0]	values[1]	values[4]	366	1			T180	13		T172	12		T76	8
auto[0]	values[1]	values[5]	396	1			T14	15		T204	10		T43	26
auto[0]	values[1]	values[6]	426	1			T30	10		T209	16		T192	10
auto[0]	values[1]	values[7]	345	1			T35	10		T41	32		T36	14
auto[0]	values[2]	values[0]	205	1			T30	10		T43	9		T36	33
auto[0]	values[2]	values[1]	304	1			T203	22		T192	7		T181	12
auto[0]	values[2]	values[2]	247	1			T16	21		T42	16		T231	2
auto[0]	values[2]	values[3]	166	1			T170	8		T232	24		T87	6
auto[0]	values[2]	values[4]	201	1			T2	6		T43	16		T233	4
auto[0]	values[2]	values[5]	323	1			T14	15		T37	56		T180	11
auto[0]	values[2]	values[6]	224	1			T43	14		T170	3		T120	9
auto[0]	values[2]	values[7]	322	1			T96	4		T157	8		T181	29
auto[0]	values[3]	values[0]	401	1			T42	10		T216	12		T180	54
auto[0]	values[3]	values[1]	235	1			T30	22		T180	13		T234	16
auto[0]	values[3]	values[2]	157	1			T30	9		T42	11		T17	8
auto[0]	values[3]	values[3]	169	1			T35	37		T235	6		T120	11
auto[0]	values[3]	values[4]	219	1			T236	20		T182	40		T214	15
auto[0]	values[3]	values[5]	317	1			T41	15		T37	56		T220	6
auto[0]	values[3]	values[6]	174	1			T14	6		T36	25		T195	11
auto[0]	values[3]	values[7]	164	1			T30	15		T157	12		T17	13
auto[0]	values[4]	values[0]	182	1			T63	20		T170	13		T195	12
auto[0]	values[4]	values[1]	249	1			T30	20		T17	11		T170	12
auto[0]	values[4]	values[2]	188	1			T157	10		T120	10		T87	23
auto[0]	values[4]	values[3]	399	1			T30	12		T41	8		T37	56
auto[0]	values[4]	values[4]	394	1			T9	8		T14	14		T35	10
auto[0]	values[4]	values[5]	344	1			T14	13		T180	12		T76	9
auto[0]	values[4]	values[6]	199	1			T41	14		T158	13		T237	2
auto[0]	values[4]	values[7]	385	1			T158	8		T182	13		T207	13
auto[0]	values[5]	values[0]	428	1			T10	11		T37	12		T203	30
auto[0]	values[5]	values[1]	366	1			T10	9		T14	15		T30	24
auto[0]	values[5]	values[2]	204	1			T30	8		T238	12		T172	14
auto[0]	values[5]	values[3]	288	1			T16	10		T42	12		T120	16
auto[0]	values[5]	values[4]	136	1			T5	20		T170	4		T21	9
auto[0]	values[5]	values[5]	251	1			T43	9		T180	13		T192	16
auto[0]	values[5]	values[6]	195	1			T186	11		T239	8		T240	12
auto[0]	values[5]	values[7]	426	1			T21	14		T198	78		T207	18
auto[0]	values[6]	values[0]	164	1			T172	13		T182	10		T241	39
auto[0]	values[6]	values[1]	234	1			T14	11		T190	9		T191	75
auto[0]	values[6]	values[2]	365	1			T17	13		T43	15		T199	16
auto[0]	values[6]	values[3]	213	1			T43	12		T179	4		T191	30
auto[0]	values[6]	values[4]	193	1			T14	10		T178	12		T242	18
auto[0]	values[6]	values[5]	191	1			T14	10		T30	9		T42	12
auto[0]	values[6]	values[6]	190	1			T43	11		T243	20		T22	14
auto[0]	values[6]	values[7]	226	1			T172	12		T21	11		T120	10
auto[0]	values[7]	values[0]	111	1			T43	12		T37	10		T170	12
auto[0]	values[7]	values[1]	117	1			T182	12		T207	12		T188	9
auto[0]	values[7]	values[2]	150	1			T23	4		T76	13		T202	45
auto[0]	values[7]	values[3]	333	1			T16	6		T170	15		T172	5
auto[0]	values[7]	values[4]	275	1			T193	12		T76	14		T203	9
auto[0]	values[7]	values[5]	139	1			T186	13		T244	20		T245	12
auto[0]	values[7]	values[6]	316	1			T40	14		T21	15		T120	8
auto[0]	values[7]	values[7]	83	1			T30	11		T246	6		T196	6
auto[1]	values[0]	values[0]	89	1			T30	8		T180	12		T170	4
auto[1]	values[0]	values[1]	154	1			T14	7		T191	6		T187	5
auto[1]	values[0]	values[2]	146	1			T87	6		T181	10		T221	8
auto[1]	values[0]	values[3]	133	1			T30	11		T41	7		T157	11
auto[1]	values[0]	values[4]	153	1			T16	10		T172	10		T222	9
auto[1]	values[0]	values[5]	233	1			T182	20		T228	91		T247	30
auto[1]	values[0]	values[6]	197	1			T16	11		T30	14		T41	25
auto[1]	values[0]	values[7]	169	1			T22	4		T192	12		T87	12
auto[1]	values[1]	values[0]	181	1			T14	21		T41	23		T37	10
auto[1]	values[1]	values[1]	135	1			T36	6		T37	55		T218	6
auto[1]	values[1]	values[2]	186	1			T76	7		T192	3		T87	9
auto[1]	values[1]	values[3]	119	1			T17	7		T180	7		T59	8
auto[1]	values[1]	values[4]	156	1			T180	7		T172	8		T76	12
auto[1]	values[1]	values[5]	196	1			T14	5		T43	5		T37	8
auto[1]	values[1]	values[6]	314	1			T30	10		T192	10		T191	10
auto[1]	values[1]	values[7]	298	1			T35	33		T41	6		T36	6
auto[1]	values[2]	values[0]	200	1			T30	10		T43	14		T36	22
auto[1]	values[2]	values[1]	187	1			T203	18		T192	13		T181	8
auto[1]	values[2]	values[2]	230	1			T16	28		T42	25		T180	20
auto[1]	values[2]	values[3]	133	1			T170	12		T87	14		T221	11
auto[1]	values[2]	values[4]	172	1			T43	5		T172	9		T181	27
auto[1]	values[2]	values[5]	204	1			T14	7		T37	11		T180	9
auto[1]	values[2]	values[6]	140	1			T43	9		T170	17		T120	11
auto[1]	values[2]	values[7]	104	1			T157	12		T181	5		T182	4
auto[1]	values[3]	values[0]	257	1			T42	21		T180	9		T172	5
auto[1]	values[3]	values[1]	179	1			T30	13		T180	14		T87	10
auto[1]	values[3]	values[2]	167	1			T30	30		T42	17		T17	14
auto[1]	values[3]	values[3]	206	1			T35	6		T120	9		T87	11
auto[1]	values[3]	values[4]	188	1			T182	7		T214	5		T128	20
auto[1]	values[3]	values[5]	149	1			T41	5		T37	9		T76	10
auto[1]	values[3]	values[6]	138	1			T14	45		T36	19		T195	9
auto[1]	values[3]	values[7]	145	1			T30	6		T157	8		T17	7
auto[1]	values[4]	values[0]	129	1			T205	6		T170	7		T195	18
auto[1]	values[4]	values[1]	148	1			T30	5		T17	9		T170	8
auto[1]	values[4]	values[2]	147	1			T157	10		T120	14		T87	17
auto[1]	values[4]	values[3]	179	1			T30	16		T41	22		T37	4
auto[1]	values[4]	values[4]	371	1			T14	6		T35	43		T21	12
auto[1]	values[4]	values[5]	150	1			T14	7		T180	43		T76	11
auto[1]	values[4]	values[6]	132	1			T41	12		T158	10		T180	3
auto[1]	values[4]	values[7]	140	1			T158	12		T182	8		T207	7
auto[1]	values[5]	values[0]	182	1			T10	9		T37	8		T203	10
auto[1]	values[5]	values[1]	149	1			T10	11		T14	5		T30	10
auto[1]	values[5]	values[2]	292	1			T30	13		T172	6		T192	8
auto[1]	values[5]	values[3]	221	1			T16	11		T42	75		T120	4
auto[1]	values[5]	values[4]	70	1			T170	16		T21	11		T221	6
auto[1]	values[5]	values[5]	137	1			T43	18		T180	7		T192	4
auto[1]	values[5]	values[6]	207	1			T186	9		T239	12		T248	9
auto[1]	values[5]	values[7]	208	1			T21	18		T249	4		T207	53
auto[1]	values[6]	values[0]	120	1			T44	16		T172	7		T250	4
auto[1]	values[6]	values[1]	180	1			T14	9		T190	16		T191	13
auto[1]	values[6]	values[2]	283	1			T17	8		T43	5		T76	19
auto[1]	values[6]	values[3]	270	1			T43	13		T191	8		T202	15
auto[1]	values[6]	values[4]	108	1			T14	15		T192	8		T214	11
auto[1]	values[6]	values[5]	161	1			T14	15		T30	11		T42	36
auto[1]	values[6]	values[6]	55	1			T43	18		T22	7		T128	4
auto[1]	values[6]	values[7]	206	1			T172	8		T21	10		T120	11
auto[1]	values[7]	values[0]	89	1			T43	8		T37	10		T170	8
auto[1]	values[7]	values[1]	152	1			T182	8		T207	20		T188	91
auto[1]	values[7]	values[2]	100	1			T76	8		T202	19		T251	11
auto[1]	values[7]	values[3]	164	1			T16	18		T170	5		T172	15
auto[1]	values[7]	values[4]	251	1			T76	6		T203	11		T191	7
auto[1]	values[7]	values[5]	68	1			T186	7		T244	7		T252	7
auto[1]	values[7]	values[6]	123	1			T21	5		T120	17		T253	4
auto[1]	values[7]	values[7]	74	1			T30	9		T254	16		T196	14