Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	377	1			T10	3		T14	4		T46	2
auto[ReadAddrCrossIntoMailbox]	208	1			T14	4		T16	4		T30	1
auto[ReadAddrCrossOutOfMailbox]	252	1			T14	1		T46	4		T16	2
auto[ReadAddrCrossAllMailbox]	180	1			T14	2		T46	4		T16	1
auto[ReadAddrOutsideMailbox]	3317	1			T2	2		T9	2		T10	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2124

1

T2

1

T9

1

T10

4

auto[1]

2210

1

T2

1

T9

1

T10

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	673	1			T2	2		T10	1		T14	10
read_ops[0x0b]	702	1			T9	2		T10	2		T14	7
read_ops[0x3b]	740	1			T10	1		T14	7		T40	2
read_ops[0x6b]	733	1			T10	2		T14	7		T46	4
read_ops[0xbb]	723	1			T10	1		T14	11		T35	4
read_ops[0xeb]	763	1			T10	2		T14	12		T46	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T16	1		T41	1		T43	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T36	1		T125	1		T220	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T37	1		T172	1		T76	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T14	2		T157	2		T180	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T16	1		T42	1		T37	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T172	1		T203	1		T181	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T157	1		T36	1		T192	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T172	2		T22	1		T203	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	232	1			T2	1		T14	5		T35	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	288	1			T2	1		T10	1		T14	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T10	1		T83	3		T43	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T10	1		T157	1		T83	3
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	12	1			T14	1		T180	1		T182	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	13	1			T16	1		T192	2		T186	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T43	1		T180	1		T172	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T14	1		T16	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T16	1		T42	1		T172	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T180	1		T125	3		T196	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	281	1			T9	1		T14	3		T35	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	267	1			T9	1		T14	2		T16	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T157	1		T76	1		T191	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T42	1		T172	2		T203	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T43	1		T125	1		T192	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T16	2		T43	1		T180	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T36	1		T172	1		T192	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T30	1		T42	1		T17	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T17	1		T43	1		T216	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T216	1		T180	1		T191	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	277	1			T10	1		T14	2		T40	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	299	1			T14	5		T40	1		T35	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T46	1		T30	2		T42	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T14	1		T46	1		T16	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	12	1			T36	1		T180	1		T172	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T37	1		T172	1		T120	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	13	1			T216	1		T76	1		T255	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T30	1		T37	1		T216	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T46	1		T17	2		T37	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T46	1		T30	1		T41	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	290	1			T14	2		T16	1		T30	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	280	1			T10	2		T14	4		T16	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T14	2		T83	1		T43	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T83	1		T37	1		T216	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T14	1		T30	1		T43	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T180	1		T172	1		T21	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T36	1		T216	1		T190	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T17	1		T216	1		T180	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T37	1		T172	1		T220	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T42	1		T36	1		T37	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	267	1			T14	4		T63	3		T30	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	262	1			T10	1		T14	4		T35	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T10	1		T14	1		T43	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T30	2		T36	1		T237	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T41	1		T191	1		T214	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T16	1		T37	1		T172	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T46	2		T180	1		T246	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T46	2		T180	1		T170	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T14	2		T46	1		T43	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T46	1		T42	1		T43	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	288	1			T10	1		T14	3		T35	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	286	1			T14	6		T35	2		T63	1