Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3264	1			T2	6		T5	20		T30	20
values[1]	2978	1			T16	24		T30	39		T41	26
values[2]	3410	1			T14	25		T15	16		T41	20
values[3]	3771	1			T9	8		T14	76		T63	20
values[4]	3383	1			T14	100		T35	43		T16	29
values[5]	3332	1			T10	40		T14	31		T23	4
values[6]	3799	1			T35	43		T16	67		T30	55
values[7]	3187	1			T14	42		T40	14		T46	10

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3233	1			T5	20		T14	20		T15	16
values[1]	3099	1			T10	20		T14	31		T16	49
values[2]	3579	1			T14	51		T16	67		T30	75
values[3]	3088	1			T14	45		T30	20		T204	10
values[4]	3539	1			T10	20		T14	22		T16	24
values[5]	3302	1			T14	80		T40	14		T63	20
values[6]	3618	1			T9	8		T30	55		T36	20
values[7]	3666	1			T2	6		T14	25		T46	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26461

1

T2

6

T5

20

T9

8

auto[1]

663

1

T10

5

T14

5

T35

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	412	1			T5	20		T30	20		T43	22
auto[0]	values[0]	values[1]	427	1			T235	6		T22	21		T203	20
auto[0]	values[0]	values[2]	445	1			T179	4		T192	20		T191	115
auto[0]	values[0]	values[3]	213	1			T192	20		T214	20		T256	2
auto[0]	values[0]	values[4]	366	1			T180	68		T226	14		T257	20
auto[0]	values[0]	values[5]	483	1			T21	20		T258	12		T186	17
auto[0]	values[0]	values[6]	489	1			T180	20		T259	6		T260	10
auto[0]	values[0]	values[7]	340	1			T2	6		T17	19		T232	24
auto[0]	values[1]	values[0]	251	1			T41	26		T236	20		T246	6
auto[0]	values[1]	values[1]	398	1			T43	20		T170	16		T22	21
auto[0]	values[1]	values[2]	319	1			T45	2		T37	20		T21	20
auto[0]	values[1]	values[3]	314	1			T42	46		T190	24		T76	21
auto[0]	values[1]	values[4]	532	1			T16	23		T30	39		T170	19
auto[0]	values[1]	values[5]	297	1			T60	63		T241	39		T261	4
auto[0]	values[1]	values[6]	567	1			T36	20		T158	21		T233	4
auto[0]	values[1]	values[7]	230	1			T231	2		T170	18		T172	39
auto[0]	values[2]	values[0]	510	1			T15	16		T216	12		T120	42
auto[0]	values[2]	values[1]	342	1			T43	30		T125	14		T192	38
auto[0]	values[2]	values[2]	352	1			T83	12		T262	4		T120	24
auto[0]	values[2]	values[3]	326	1			T14	25		T157	20		T17	20
auto[0]	values[2]	values[4]	503	1			T237	2		T21	20		T203	18
auto[0]	values[2]	values[5]	342	1			T37	57		T191	20		T182	20
auto[0]	values[2]	values[6]	418	1			T158	20		T180	59		T263	6
auto[0]	values[2]	values[7]	514	1			T41	19		T120	20		T249	2
auto[0]	values[3]	values[0]	421	1			T180	20		T191	38		T221	84
auto[0]	values[3]	values[1]	316	1			T30	27		T90	12		T42	40
auto[0]	values[3]	values[2]	407	1			T14	49		T16	20		T264	22
auto[0]	values[3]	values[3]	460	1			T180	27		T87	20		T181	42
auto[0]	values[3]	values[4]	488	1			T254	16		T76	20		T182	117
auto[0]	values[3]	values[5]	465	1			T63	20		T43	20		T193	12
auto[0]	values[3]	values[6]	656	1			T9	8		T37	63		T181	27
auto[0]	values[3]	values[7]	468	1			T14	25		T30	20		T43	21
auto[0]	values[4]	values[0]	483	1			T14	19		T96	4		T36	30
auto[0]	values[4]	values[1]	230	1			T16	28		T17	20		T242	18
auto[0]	values[4]	values[2]	705	1			T30	21		T41	19		T42	114
auto[0]	values[4]	values[3]	496	1			T14	20		T76	20		T192	17
auto[0]	values[4]	values[4]	402	1			T41	29		T43	28		T91	6
auto[0]	values[4]	values[5]	430	1			T14	60		T30	25		T17	21
auto[0]	values[4]	values[6]	313	1			T30	20		T220	6		T76	21
auto[0]	values[4]	values[7]	257	1			T35	43		T180	20		T265	8
auto[0]	values[5]	values[0]	440	1			T23	4		T30	20		T37	65
auto[0]	values[5]	values[1]	444	1			T10	18		T14	29		T41	38
auto[0]	values[5]	values[2]	301	1			T30	20		T157	40		T170	18
auto[0]	values[5]	values[3]	628	1			T30	20		T173	20		T158	22
auto[0]	values[5]	values[4]	356	1			T10	17		T180	20		T172	20
auto[0]	values[5]	values[5]	318	1			T36	22		T180	25		T170	18
auto[0]	values[5]	values[6]	348	1			T30	35		T172	19		T76	25
auto[0]	values[5]	values[7]	396	1			T35	51		T30	19		T17	20
auto[0]	values[6]	values[0]	329	1			T35	43		T172	20		T120	20
auto[0]	values[6]	values[1]	450	1			T16	20		T37	20		T201	19
auto[0]	values[6]	values[2]	434	1			T16	47		T30	32		T207	20
auto[0]	values[6]	values[3]	220	1			T204	10		T37	41		T206	6
auto[0]	values[6]	values[4]	634	1			T30	21		T42	29		T36	24
auto[0]	values[6]	values[5]	541	1			T203	20		T196	20		T214	20
auto[0]	values[6]	values[6]	386	1			T37	63		T180	17		T76	21
auto[0]	values[6]	values[7]	728	1			T43	20		T170	20		T76	25
auto[0]	values[7]	values[0]	307	1			T36	20		T180	53		T192	20
auto[0]	values[7]	values[1]	422	1			T43	49		T37	20		T180	20
auto[0]	values[7]	values[2]	538	1			T41	37		T203	20		T186	19
auto[0]	values[7]	values[3]	350	1			T192	20		T87	19		T32	27
auto[0]	values[7]	values[4]	177	1			T14	22		T37	20		T203	20
auto[0]	values[7]	values[5]	365	1			T14	20		T40	14		T181	27
auto[0]	values[7]	values[6]	321	1			T234	16		T198	78		T266	8
auto[0]	values[7]	values[7]	641	1			T46	10		T41	35		T43	21
auto[1]	values[0]	values[0]	18	1			T43	5		T36	1		T207	2
auto[1]	values[0]	values[1]	8	1			T196	2		T267	1		T268	3
auto[1]	values[0]	values[2]	15	1			T191	2		T257	1		T188	1
auto[1]	values[0]	values[3]	4	1			T251	3		T269	1		-	-
auto[1]	values[0]	values[4]	7	1			T180	1		T188	1		T270	2
auto[1]	values[0]	values[5]	5	1			T186	3		T128	1		T197	1
auto[1]	values[0]	values[6]	23	1			T187	4		T271	3		T272	1
auto[1]	values[0]	values[7]	9	1			T17	2		T192	2		T197	2
auto[1]	values[1]	values[0]	3	1			T257	1		T251	2		-	-
auto[1]	values[1]	values[1]	12	1			T170	4		T87	3		T191	1
auto[1]	values[1]	values[2]	7	1			T45	2		T273	1		T272	2
auto[1]	values[1]	values[3]	14	1			T42	2		T190	1		T221	4
auto[1]	values[1]	values[4]	4	1			T16	1		T170	1		T32	1
auto[1]	values[1]	values[5]	5	1			T60	1		T274	1		T275	2
auto[1]	values[1]	values[6]	18	1			T158	1		T192	2		T60	1
auto[1]	values[1]	values[7]	7	1			T170	2		T172	1		T214	1
auto[1]	values[2]	values[0]	13	1			T120	4		T207	1		T60	1
auto[1]	values[2]	values[1]	10	1			T43	1		T192	2		T221	2
auto[1]	values[2]	values[2]	5	1			T201	1		T202	1		T276	3
auto[1]	values[2]	values[3]	7	1			T17	2		T21	2		T277	2
auto[1]	values[2]	values[4]	18	1			T203	2		T87	4		T214	1
auto[1]	values[2]	values[5]	10	1			T37	3		T128	3		T278	2
auto[1]	values[2]	values[6]	20	1			T180	4		T263	2		T182	3
auto[1]	values[2]	values[7]	20	1			T41	1		T249	2		T87	2
auto[1]	values[3]	values[0]	12	1			T248	1		T275	1		T279	2
auto[1]	values[3]	values[1]	3	1			T30	1		T42	1		T157	1
auto[1]	values[3]	values[2]	14	1			T14	2		T128	4		T272	1
auto[1]	values[3]	values[3]	6	1			T181	2		T257	1		T280	1
auto[1]	values[3]	values[4]	8	1			T182	1		T281	2		T280	2
auto[1]	values[3]	values[5]	13	1			T172	1		T59	2		T248	2
auto[1]	values[3]	values[6]	20	1			T37	1		T207	1		T187	2
auto[1]	values[3]	values[7]	14	1			T44	4		T282	2		T283	2
auto[1]	values[4]	values[0]	13	1			T14	1		T36	1		T275	3
auto[1]	values[4]	values[1]	3	1			T16	1		T284	2		-	-
auto[1]	values[4]	values[2]	14	1			T41	1		T42	1		T195	3
auto[1]	values[4]	values[3]	10	1			T192	3		T248	1		T188	2
auto[1]	values[4]	values[4]	14	1			T41	1		T43	1		T203	1
auto[1]	values[4]	values[5]	5	1			T17	1		T190	1		T172	2
auto[1]	values[4]	values[6]	4	1			T76	2		T281	1		T285	1
auto[1]	values[4]	values[7]	4	1			T180	1		T252	1		T251	2
auto[1]	values[5]	values[0]	8	1			T286	1		T281	3		T287	4
auto[1]	values[5]	values[1]	15	1			T10	2		T14	2		T288	6
auto[1]	values[5]	values[2]	13	1			T170	2		T87	2		T181	1
auto[1]	values[5]	values[3]	25	1			T158	1		T170	1		T76	1
auto[1]	values[5]	values[4]	9	1			T10	3		T192	1		T181	1
auto[1]	values[5]	values[5]	5	1			T36	2		T170	2		T289	1
auto[1]	values[5]	values[6]	16	1			T172	1		T76	3		T248	6
auto[1]	values[5]	values[7]	10	1			T35	2		T30	2		T36	2
auto[1]	values[6]	values[0]	8	1			T186	3		T252	1		T290	2
auto[1]	values[6]	values[1]	10	1			T201	1		T272	2		T291	1
auto[1]	values[6]	values[2]	4	1			T30	2		T282	2		-	-
auto[1]	values[6]	values[3]	5	1			T37	1		T292	3		T289	1
auto[1]	values[6]	values[4]	20	1			T42	2		T181	2		T293	6
auto[1]	values[6]	values[5]	12	1			T228	1		T275	4		T197	1
auto[1]	values[6]	values[6]	10	1			T37	4		T180	3		T182	2
auto[1]	values[6]	values[7]	8	1			T43	1		T247	2		T153	1
auto[1]	values[7]	values[0]	5	1			T180	2		T207	1		T271	1
auto[1]	values[7]	values[1]	9	1			T43	2		T252	3		T294	1
auto[1]	values[7]	values[2]	6	1			T186	1		T252	2		T295	1
auto[1]	values[7]	values[3]	10	1			T87	1		T32	1		T60	2
auto[1]	values[7]	values[4]	1	1			T192	1		-	-		-	-
auto[1]	values[7]	values[5]	6	1			T181	2		T186	1		T188	1
auto[1]	values[7]	values[6]	9	1			T266	4		T291	3		T197	1
auto[1]	values[7]	values[7]	20	1			T41	2		T43	2		T21	1