Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	745	1			T7	4		T16	14		T18	4
all_values[1]	745	1			T7	4		T16	14		T18	4
all_values[2]	745	1			T7	4		T16	14		T18	4
all_values[3]	745	1			T7	4		T16	14		T18	4
all_values[4]	745	1			T7	4		T16	14		T18	4
all_values[5]	745	1			T7	4		T16	14		T18	4
all_values[6]	745	1			T7	4		T16	14		T18	4
all_values[7]	745	1			T7	4		T16	14		T18	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3153

1

T7

16

T16

61

T18

21

auto[1]

2807

1

T7

16

T16

51

T18

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2425

1

T7

11

T16

52

T18

8

auto[1]

3535

1

T7

21

T16

60

T18

24

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3433

1

T7

16

T16

69

T18

17

auto[1]

2527

1

T7

16

T16

43

T18

15

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	163	1			T16	2		T19	5		T20	1
all_values[0]	auto[0]	auto[0]	auto[1]	69	1			T16	1		T18	1		T19	1
all_values[0]	auto[0]	auto[1]	auto[0]	103	1			T16	4		T19	1		T20	8
all_values[0]	auto[0]	auto[1]	auto[1]	84	1			T7	1		T18	1		T19	3
all_values[0]	auto[1]	auto[0]	auto[1]	172	1			T7	2		T16	4		T18	2
all_values[0]	auto[1]	auto[1]	auto[1]	154	1			T7	1		T16	3		T19	3
all_values[1]	auto[0]	auto[0]	auto[0]	168	1			T7	3		T16	2		T19	3
all_values[1]	auto[0]	auto[0]	auto[1]	61	1			T16	2		T18	2		T20	2
all_values[1]	auto[0]	auto[1]	auto[0]	129	1			T16	4		T19	4		T20	2
all_values[1]	auto[0]	auto[1]	auto[1]	74	1			T19	3		T21	1		T22	1
all_values[1]	auto[1]	auto[0]	auto[1]	151	1			T7	1		T16	4		T18	2
all_values[1]	auto[1]	auto[1]	auto[1]	162	1			T16	2		T19	5		T20	5
all_values[2]	auto[0]	auto[0]	auto[0]	154	1			T7	2		T16	5		T19	4
all_values[2]	auto[0]	auto[0]	auto[1]	76	1			T16	2		T19	1		T20	1
all_values[2]	auto[0]	auto[1]	auto[0]	137	1			T7	1		T16	3		T18	2
all_values[2]	auto[0]	auto[1]	auto[1]	72	1			T19	3		T31	4		T150	2
all_values[2]	auto[1]	auto[0]	auto[1]	168	1			T16	3		T18	2		T19	6
all_values[2]	auto[1]	auto[1]	auto[1]	138	1			T7	1		T16	1		T19	2
all_values[3]	auto[0]	auto[0]	auto[0]	157	1			T16	1		T19	5		T20	1
all_values[3]	auto[0]	auto[0]	auto[1]	61	1			T7	1		T20	1		T21	2
all_values[3]	auto[0]	auto[1]	auto[0]	134	1			T16	3		T18	1		T19	2
all_values[3]	auto[0]	auto[1]	auto[1]	69	1			T16	3		T18	1		T19	3
all_values[3]	auto[1]	auto[0]	auto[1]	174	1			T7	1		T16	4		T18	1
all_values[3]	auto[1]	auto[1]	auto[1]	150	1			T7	2		T16	3		T18	1
all_values[4]	auto[0]	auto[0]	auto[0]	147	1			T16	2		T18	4		T19	5
all_values[4]	auto[0]	auto[0]	auto[1]	81	1			T16	2		T19	1		T20	1
all_values[4]	auto[0]	auto[1]	auto[0]	138	1			T7	2		T16	4		T19	5
all_values[4]	auto[0]	auto[1]	auto[1]	79	1			T7	1		T16	1		T19	3
all_values[4]	auto[1]	auto[0]	auto[1]	175	1			T7	1		T16	2		T20	2
all_values[4]	auto[1]	auto[1]	auto[1]	125	1			T16	3		T19	4		T20	3
all_values[5]	auto[0]	auto[0]	auto[0]	218	1			T7	1		T16	7		T19	4
all_values[5]	auto[0]	auto[1]	auto[0]	200	1			T7	1		T16	2		T18	1
all_values[5]	auto[1]	auto[0]	auto[1]	175	1			T7	1		T16	2		T18	1
all_values[5]	auto[1]	auto[1]	auto[1]	152	1			T7	1		T16	3		T18	2
all_values[6]	auto[0]	auto[0]	auto[0]	146	1			T16	4		T19	6		T21	2
all_values[6]	auto[0]	auto[0]	auto[1]	79	1			T16	2		T19	3		T20	1
all_values[6]	auto[0]	auto[1]	auto[0]	123	1			T16	2		T19	1		T20	7
all_values[6]	auto[0]	auto[1]	auto[1]	62	1			T7	1		T16	1		T18	2
all_values[6]	auto[1]	auto[0]	auto[1]	186	1			T7	1		T16	3		T18	2
all_values[6]	auto[1]	auto[1]	auto[1]	149	1			T7	2		T16	2		T19	2
all_values[7]	auto[0]	auto[0]	auto[0]	165	1			T16	5		T19	4		T20	3
all_values[7]	auto[0]	auto[0]	auto[1]	54	1			T7	1		T18	2		T20	2
all_values[7]	auto[0]	auto[1]	auto[0]	143	1			T7	1		T16	2		T19	8
all_values[7]	auto[0]	auto[1]	auto[1]	87	1			T16	3		T19	2		T20	1
all_values[7]	auto[1]	auto[0]	auto[1]	153	1			T7	1		T16	2		T18	2
all_values[7]	auto[1]	auto[1]	auto[1]	143	1			T7	1		T16	2		T19	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal