Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1739

1

T6

10

T7

3

T14

7

auto[1]

1771

1

T6

17

T7

5

T14

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1929

1

T7

6

T14

7

T24

6

auto[1]

1581

1

T6

27

T7

2

T14

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2772

1

T6

27

T7

3

T14

6

auto[1]

738

1

T7

5

T14

4

T24

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	722	1			T6	6		T7	1		T14	1
valid[1]	645	1			T6	3		T24	1		T25	1
valid[2]	717	1			T6	6		T7	6		T14	4
valid[3]	723	1			T6	8		T14	2		T24	2
valid[4]	703	1			T6	4		T7	1		T14	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	123	1			T14	1		T24	1		T25	1
auto[0]	auto[0]	valid[0]	auto[1]	153	1			T6	3		T26	2		T27	1
auto[0]	auto[0]	valid[1]	auto[0]	105	1			T28	1		T16	2		T30	1
auto[0]	auto[0]	valid[1]	auto[1]	159	1			T6	2		T26	2		T29	2
auto[0]	auto[0]	valid[2]	auto[0]	120	1			T14	2		T16	2		T30	1
auto[0]	auto[0]	valid[2]	auto[1]	164	1			T6	2		T81	1		T82	4
auto[0]	auto[0]	valid[3]	auto[0]	107	1			T28	2		T16	1		T30	1
auto[0]	auto[0]	valid[3]	auto[1]	153	1			T26	2		T28	1		T81	1
auto[0]	auto[0]	valid[4]	auto[0]	118	1			T28	1		T16	5		T30	1
auto[0]	auto[0]	valid[4]	auto[1]	168	1			T6	3		T7	1		T14	2
auto[0]	auto[1]	valid[0]	auto[0]	131	1			T16	2		T30	2		T47	1
auto[0]	auto[1]	valid[0]	auto[1]	158	1			T6	3		T26	1		T29	1
auto[0]	auto[1]	valid[1]	auto[0]	108	1			T25	1		T17	3		T159	1
auto[0]	auto[1]	valid[1]	auto[1]	138	1			T6	1		T29	1		T82	7
auto[0]	auto[1]	valid[2]	auto[0]	130	1			T7	1		T30	1		T41	1
auto[0]	auto[1]	valid[2]	auto[1]	163	1			T6	4		T7	1		T14	1
auto[0]	auto[1]	valid[3]	auto[0]	136	1			T24	1		T16	1		T30	1
auto[0]	auto[1]	valid[3]	auto[1]	167	1			T6	8		T26	1		T29	1
auto[0]	auto[1]	valid[4]	auto[0]	113	1			T24	2		T28	1		T16	1
auto[0]	auto[1]	valid[4]	auto[1]	158	1			T6	1		T26	1		T29	1
auto[1]	auto[0]	valid[0]	auto[0]	81	1			T7	1		T16	1		T47	1
auto[1]	auto[0]	valid[1]	auto[0]	65	1			T30	1		T17	1		T18	1
auto[1]	auto[0]	valid[2]	auto[0]	75	1			T7	1		T14	1		T16	1
auto[1]	auto[0]	valid[3]	auto[0]	84	1			T28	1		T16	2		T30	1
auto[1]	auto[0]	valid[4]	auto[0]	64	1			T14	1		T25	1		T28	1
auto[1]	auto[1]	valid[0]	auto[0]	76	1			T16	1		T30	1		T47	1
auto[1]	auto[1]	valid[1]	auto[0]	70	1			T24	1		T28	1		T17	1
auto[1]	auto[1]	valid[2]	auto[0]	65	1			T7	3		T16	1		T30	1
auto[1]	auto[1]	valid[3]	auto[0]	76	1			T14	2		T24	1		T159	1
auto[1]	auto[1]	valid[4]	auto[0]	82	1			T25	1		T16	1		T30	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal