Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47168

1

T7

133

T8

1

T14

121

auto[1]

17281

1

T6

349

T7

52

T14

17

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47214

1

T6

349

T7

119

T8

1

auto[1]

17235

1

T7

66

T14

46

T24

68

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33017	1			T6	169		T7	96		T14	65
others[1]	5329	1			T6	33		T7	14		T14	16
others[2]	5554	1			T6	33		T7	13		T8	1
others[3]	6142	1			T6	36		T7	18		T14	10
interest[1]	3587	1			T6	18		T7	10		T14	10
interest[4]	21504	1			T6	111		T7	64		T14	43
interest[64]	10820	1			T6	60		T7	34		T14	30

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15270	1			T7	34		T14	36		T24	67
auto[0]	auto[0]	others[1]	2477	1			T7	7		T14	8		T24	17
auto[0]	auto[0]	others[2]	2583	1			T7	8		T8	1		T14	4
auto[0]	auto[0]	others[3]	2868	1			T7	5		T14	6		T24	15
auto[0]	auto[0]	interest[1]	1652	1			T7	2		T14	6		T24	9
auto[0]	auto[0]	interest[4]	9935	1			T7	22		T14	23		T24	40
auto[0]	auto[0]	interest[64]	5083	1			T7	11		T14	15		T24	25
auto[0]	auto[1]	others[0]	8932	1			T6	169		T7	25		T14	11
auto[0]	auto[1]	others[1]	1392	1			T6	33		T7	3		T14	1
auto[0]	auto[1]	others[2]	1514	1			T6	33		T7	3		T25	1
auto[0]	auto[1]	others[3]	1633	1			T6	36		T7	6		T14	1
auto[0]	auto[1]	interest[1]	996	1			T6	18		T7	6		T14	1
auto[0]	auto[1]	interest[4]	5854	1			T6	111		T7	14		T14	9
auto[0]	auto[1]	interest[64]	2814	1			T6	60		T7	9		T14	3
auto[1]	auto[0]	others[0]	8815	1			T7	37		T14	18		T24	42
auto[1]	auto[0]	others[1]	1460	1			T7	4		T14	7		T24	3
auto[1]	auto[0]	others[2]	1457	1			T7	2		T14	3		T24	8
auto[1]	auto[0]	others[3]	1641	1			T7	7		T14	3		T24	3
auto[1]	auto[0]	interest[1]	939	1			T7	2		T14	3		T24	2
auto[1]	auto[0]	interest[4]	5715	1			T7	28		T14	11		T24	23
auto[1]	auto[0]	interest[64]	2923	1			T7	14		T14	12		T24	10

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal