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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
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T77 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1810817733 Aug 11 04:57:45 PM PDT 24 Aug 11 04:57:46 PM PDT 24 69670213 ps
T1032 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3532596718 Aug 11 04:57:56 PM PDT 24 Aug 11 04:57:57 PM PDT 24 20361472 ps
T113 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3477611956 Aug 11 04:57:47 PM PDT 24 Aug 11 04:58:10 PM PDT 24 310993023 ps
T114 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4071431618 Aug 11 04:57:44 PM PDT 24 Aug 11 04:58:00 PM PDT 24 229940679 ps
T1033 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4212566124 Aug 11 04:57:50 PM PDT 24 Aug 11 04:57:52 PM PDT 24 341738099 ps
T1034 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4129177101 Aug 11 04:57:49 PM PDT 24 Aug 11 04:57:57 PM PDT 24 269756320 ps
T78 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2889059744 Aug 11 04:57:48 PM PDT 24 Aug 11 04:57:49 PM PDT 24 14499917 ps
T1035 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.951894596 Aug 11 04:57:46 PM PDT 24 Aug 11 04:57:50 PM PDT 24 687125136 ps
T1036 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1744602581 Aug 11 04:58:06 PM PDT 24 Aug 11 04:58:09 PM PDT 24 44850087 ps
T141 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1270303233 Aug 11 04:57:48 PM PDT 24 Aug 11 04:58:04 PM PDT 24 2839448428 ps
T1037 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1457945324 Aug 11 04:58:00 PM PDT 24 Aug 11 04:58:01 PM PDT 24 13740135 ps
T1038 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2804025625 Aug 11 04:58:04 PM PDT 24 Aug 11 04:58:05 PM PDT 24 13789052 ps
T115 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3720365805 Aug 11 04:57:49 PM PDT 24 Aug 11 04:57:50 PM PDT 24 119868910 ps
T147 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.157270182 Aug 11 04:57:56 PM PDT 24 Aug 11 04:57:59 PM PDT 24 198111906 ps
T104 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3867183295 Aug 11 04:57:35 PM PDT 24 Aug 11 04:57:38 PM PDT 24 55551040 ps
T142 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3532334346 Aug 11 04:57:58 PM PDT 24 Aug 11 04:58:01 PM PDT 24 280093615 ps
T99 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3531494225 Aug 11 04:57:36 PM PDT 24 Aug 11 04:57:39 PM PDT 24 93355772 ps
T117 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.58506104 Aug 11 04:57:47 PM PDT 24 Aug 11 04:57:49 PM PDT 24 32460296 ps
T79 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3678456582 Aug 11 04:57:40 PM PDT 24 Aug 11 04:57:41 PM PDT 24 167405122 ps
T118 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4125701656 Aug 11 04:57:58 PM PDT 24 Aug 11 04:58:01 PM PDT 24 104575603 ps
T1039 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3497031400 Aug 11 04:58:01 PM PDT 24 Aug 11 04:58:02 PM PDT 24 12792941 ps
T1040 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1770125967 Aug 11 04:57:42 PM PDT 24 Aug 11 04:57:43 PM PDT 24 39555000 ps
T1041 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.369376335 Aug 11 04:57:56 PM PDT 24 Aug 11 04:57:58 PM PDT 24 127973045 ps
T143 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.128432259 Aug 11 04:58:05 PM PDT 24 Aug 11 04:58:09 PM PDT 24 543736620 ps
T144 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2788159090 Aug 11 04:57:49 PM PDT 24 Aug 11 04:57:52 PM PDT 24 103133912 ps
T1042 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1052331237 Aug 11 04:58:00 PM PDT 24 Aug 11 04:58:01 PM PDT 24 23894154 ps
T1043 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3201985138 Aug 11 04:57:56 PM PDT 24 Aug 11 04:57:59 PM PDT 24 121791473 ps
T1044 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3038956458 Aug 11 04:57:42 PM PDT 24 Aug 11 04:57:43 PM PDT 24 13203660 ps
T1045 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4149459467 Aug 11 04:58:03 PM PDT 24 Aug 11 04:58:05 PM PDT 24 34087844 ps
T145 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3360251455 Aug 11 04:57:50 PM PDT 24 Aug 11 04:57:52 PM PDT 24 287949067 ps
T1046 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2146778599 Aug 11 04:58:08 PM PDT 24 Aug 11 04:58:09 PM PDT 24 14664474 ps
T1047 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1648734368 Aug 11 04:57:56 PM PDT 24 Aug 11 04:57:59 PM PDT 24 154975698 ps
T146 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1220780553 Aug 11 04:57:55 PM PDT 24 Aug 11 04:58:05 PM PDT 24 1457379768 ps
T1048 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3674791831 Aug 11 04:57:56 PM PDT 24 Aug 11 04:57:58 PM PDT 24 53164298 ps
T1049 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1008811589 Aug 11 04:57:49 PM PDT 24 Aug 11 04:57:50 PM PDT 24 55483479 ps
T1050 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4287209673 Aug 11 04:57:50 PM PDT 24 Aug 11 04:57:51 PM PDT 24 12894113 ps
T148 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2400414348 Aug 11 04:57:53 PM PDT 24 Aug 11 04:57:56 PM PDT 24 104766210 ps
T1051 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3209864981 Aug 11 04:58:01 PM PDT 24 Aug 11 04:58:02 PM PDT 24 14166871 ps
T1052 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.970287825 Aug 11 04:57:41 PM PDT 24 Aug 11 04:57:44 PM PDT 24 30720907 ps
T149 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1277475053 Aug 11 04:58:06 PM PDT 24 Aug 11 04:58:08 PM PDT 24 322855569 ps
T1053 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3835106106 Aug 11 04:57:58 PM PDT 24 Aug 11 04:58:00 PM PDT 24 183609945 ps
T1054 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2439768861 Aug 11 04:58:00 PM PDT 24 Aug 11 04:58:01 PM PDT 24 15703511 ps
T1055 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.317690822 Aug 11 04:57:42 PM PDT 24 Aug 11 04:57:43 PM PDT 24 92182696 ps
T1056 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1076778300 Aug 11 04:57:45 PM PDT 24 Aug 11 04:57:46 PM PDT 24 152323826 ps
T1057 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.533937650 Aug 11 04:57:50 PM PDT 24 Aug 11 04:57:52 PM PDT 24 170923899 ps
T165 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3619030035 Aug 11 04:58:03 PM PDT 24 Aug 11 04:58:10 PM PDT 24 342438493 ps
T1058 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2966415196 Aug 11 04:58:06 PM PDT 24 Aug 11 04:58:07 PM PDT 24 41456921 ps
T98 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.274528740 Aug 11 04:57:46 PM PDT 24 Aug 11 04:57:49 PM PDT 24 52755300 ps
T1059 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2562820886 Aug 11 04:58:08 PM PDT 24 Aug 11 04:58:09 PM PDT 24 14618300 ps
T1060 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3532041112 Aug 11 04:57:49 PM PDT 24 Aug 11 04:57:51 PM PDT 24 53609641 ps
T1061 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3024520951 Aug 11 04:57:56 PM PDT 24 Aug 11 04:57:57 PM PDT 24 191420104 ps
T161 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4281270636 Aug 11 04:57:55 PM PDT 24 Aug 11 04:57:58 PM PDT 24 43110353 ps
T1062 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2733514279 Aug 11 04:57:56 PM PDT 24 Aug 11 04:57:59 PM PDT 24 41654915 ps
T1063 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.267622276 Aug 11 04:58:03 PM PDT 24 Aug 11 04:58:04 PM PDT 24 39269159 ps
T1064 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2743014574 Aug 11 04:57:45 PM PDT 24 Aug 11 04:57:47 PM PDT 24 56220674 ps
T80 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2217461824 Aug 11 04:57:43 PM PDT 24 Aug 11 04:57:45 PM PDT 24 70893871 ps
T102 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4076677936 Aug 11 04:57:48 PM PDT 24 Aug 11 04:57:52 PM PDT 24 749814660 ps
T1065 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3492618633 Aug 11 04:58:06 PM PDT 24 Aug 11 04:58:07 PM PDT 24 29217358 ps
T1066 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1306104335 Aug 11 04:57:50 PM PDT 24 Aug 11 04:58:12 PM PDT 24 1946334381 ps
T1067 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4073941735 Aug 11 04:58:07 PM PDT 24 Aug 11 04:58:08 PM PDT 24 13205756 ps
T1068 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4213192353 Aug 11 04:57:57 PM PDT 24 Aug 11 04:57:59 PM PDT 24 80722736 ps
T1069 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3557270435 Aug 11 04:57:56 PM PDT 24 Aug 11 04:58:02 PM PDT 24 194529364 ps
T168 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2697425498 Aug 11 04:57:42 PM PDT 24 Aug 11 04:58:03 PM PDT 24 1590248409 ps
T1070 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1066567374 Aug 11 04:57:49 PM PDT 24 Aug 11 04:57:52 PM PDT 24 483193072 ps
T1071 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3931004213 Aug 11 04:58:09 PM PDT 24 Aug 11 04:58:10 PM PDT 24 31965510 ps
T1072 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3221541815 Aug 11 04:57:43 PM PDT 24 Aug 11 04:57:46 PM PDT 24 678524620 ps
T1073 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.915430918 Aug 11 04:57:54 PM PDT 24 Aug 11 04:57:58 PM PDT 24 559717833 ps
T167 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.27575799 Aug 11 04:57:59 PM PDT 24 Aug 11 04:58:12 PM PDT 24 769796796 ps
T1074 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2788974393 Aug 11 04:57:43 PM PDT 24 Aug 11 04:57:45 PM PDT 24 27166547 ps
T1075 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1707795531 Aug 11 04:57:51 PM PDT 24 Aug 11 04:58:07 PM PDT 24 880015078 ps
T1076 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2722789190 Aug 11 04:57:44 PM PDT 24 Aug 11 04:57:47 PM PDT 24 36100296 ps
T1077 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3296050917 Aug 11 04:57:55 PM PDT 24 Aug 11 04:57:56 PM PDT 24 143548265 ps
T1078 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1698647429 Aug 11 04:57:55 PM PDT 24 Aug 11 04:57:57 PM PDT 24 53851339 ps
T1079 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.260611759 Aug 11 04:57:47 PM PDT 24 Aug 11 04:57:50 PM PDT 24 352042224 ps
T1080 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3665990430 Aug 11 04:57:44 PM PDT 24 Aug 11 04:57:45 PM PDT 24 16837571 ps
T1081 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.594346292 Aug 11 04:58:01 PM PDT 24 Aug 11 04:58:06 PM PDT 24 194155317 ps
T1082 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3736250939 Aug 11 04:57:59 PM PDT 24 Aug 11 04:58:02 PM PDT 24 321882861 ps
T1083 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.795834416 Aug 11 04:58:07 PM PDT 24 Aug 11 04:58:09 PM PDT 24 71700475 ps
T1084 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2388275801 Aug 11 04:57:56 PM PDT 24 Aug 11 04:57:57 PM PDT 24 15752576 ps
T1085 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2920421203 Aug 11 04:58:03 PM PDT 24 Aug 11 04:58:04 PM PDT 24 34693755 ps
T1086 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.466663117 Aug 11 04:57:50 PM PDT 24 Aug 11 04:57:53 PM PDT 24 198705150 ps
T1087 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.924172341 Aug 11 04:57:57 PM PDT 24 Aug 11 04:57:58 PM PDT 24 24775510 ps
T1088 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2452463016 Aug 11 04:57:44 PM PDT 24 Aug 11 04:57:45 PM PDT 24 29935662 ps
T1089 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2208205261 Aug 11 04:58:02 PM PDT 24 Aug 11 04:58:03 PM PDT 24 16628680 ps
T1090 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.618467030 Aug 11 04:57:43 PM PDT 24 Aug 11 04:57:45 PM PDT 24 89465402 ps
T1091 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.538770691 Aug 11 04:57:43 PM PDT 24 Aug 11 04:57:44 PM PDT 24 177946308 ps
T166 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4230610417 Aug 11 04:57:57 PM PDT 24 Aug 11 04:58:05 PM PDT 24 109642486 ps
T1092 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.70385729 Aug 11 04:57:37 PM PDT 24 Aug 11 04:57:39 PM PDT 24 25481631 ps
T1093 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2976687579 Aug 11 04:57:50 PM PDT 24 Aug 11 04:57:52 PM PDT 24 102084215 ps
T1094 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.835923528 Aug 11 04:57:56 PM PDT 24 Aug 11 04:57:59 PM PDT 24 57890591 ps
T1095 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2461156060 Aug 11 04:57:44 PM PDT 24 Aug 11 04:57:45 PM PDT 24 15628986 ps
T1096 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.95727152 Aug 11 04:57:58 PM PDT 24 Aug 11 04:57:59 PM PDT 24 41481773 ps
T1097 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2913286431 Aug 11 04:57:51 PM PDT 24 Aug 11 04:57:52 PM PDT 24 14041883 ps
T1098 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.847689466 Aug 11 04:57:56 PM PDT 24 Aug 11 04:57:59 PM PDT 24 142257921 ps
T162 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.659835231 Aug 11 04:57:56 PM PDT 24 Aug 11 04:58:10 PM PDT 24 392163791 ps
T1099 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2114606285 Aug 11 04:57:40 PM PDT 24 Aug 11 04:57:42 PM PDT 24 64824695 ps
T1100 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.743292777 Aug 11 04:58:07 PM PDT 24 Aug 11 04:58:10 PM PDT 24 64361175 ps
T1101 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1803610345 Aug 11 04:57:54 PM PDT 24 Aug 11 04:57:55 PM PDT 24 13181333 ps
T1102 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3189363385 Aug 11 04:58:06 PM PDT 24 Aug 11 04:58:09 PM PDT 24 46015987 ps
T1103 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2254252158 Aug 11 04:57:50 PM PDT 24 Aug 11 04:57:51 PM PDT 24 89832923 ps
T1104 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1206072755 Aug 11 04:58:00 PM PDT 24 Aug 11 04:58:01 PM PDT 24 12021496 ps
T1105 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.677000895 Aug 11 04:57:56 PM PDT 24 Aug 11 04:57:57 PM PDT 24 43291489 ps
T163 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4257644043 Aug 11 04:57:59 PM PDT 24 Aug 11 04:58:09 PM PDT 24 1542222009 ps
T1106 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1445486711 Aug 11 04:57:48 PM PDT 24 Aug 11 04:57:51 PM PDT 24 120923211 ps
T1107 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.603744667 Aug 11 04:57:50 PM PDT 24 Aug 11 04:57:55 PM PDT 24 82332666 ps
T1108 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.586776970 Aug 11 04:57:54 PM PDT 24 Aug 11 04:57:55 PM PDT 24 51909367 ps
T1109 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2414901689 Aug 11 04:57:58 PM PDT 24 Aug 11 04:58:03 PM PDT 24 994754633 ps
T1110 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.673713577 Aug 11 04:57:51 PM PDT 24 Aug 11 04:57:53 PM PDT 24 62576487 ps
T1111 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3961881338 Aug 11 04:58:04 PM PDT 24 Aug 11 04:58:05 PM PDT 24 45700185 ps
T1112 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.602923567 Aug 11 04:57:43 PM PDT 24 Aug 11 04:57:44 PM PDT 24 32757141 ps
T1113 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2306001443 Aug 11 04:57:56 PM PDT 24 Aug 11 04:57:59 PM PDT 24 62175708 ps
T1114 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.446732241 Aug 11 04:57:54 PM PDT 24 Aug 11 04:57:58 PM PDT 24 228056605 ps
T164 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.102046564 Aug 11 04:57:46 PM PDT 24 Aug 11 04:57:59 PM PDT 24 2577838571 ps
T1115 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1554274852 Aug 11 04:57:58 PM PDT 24 Aug 11 04:58:00 PM PDT 24 247461891 ps
T1116 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1819494046 Aug 11 04:57:58 PM PDT 24 Aug 11 04:58:24 PM PDT 24 2103284034 ps
T1117 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2411379520 Aug 11 04:57:56 PM PDT 24 Aug 11 04:57:56 PM PDT 24 128684114 ps
T1118 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.121651233 Aug 11 04:57:40 PM PDT 24 Aug 11 04:57:49 PM PDT 24 712233431 ps
T1119 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1033210337 Aug 11 04:57:56 PM PDT 24 Aug 11 04:58:04 PM PDT 24 1642209533 ps
T1120 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3663031683 Aug 11 04:57:37 PM PDT 24 Aug 11 04:58:12 PM PDT 24 551773787 ps
T169 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1912559293 Aug 11 04:57:59 PM PDT 24 Aug 11 04:58:19 PM PDT 24 1022315627 ps
T1121 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3652060106 Aug 11 04:57:58 PM PDT 24 Aug 11 04:58:03 PM PDT 24 156869120 ps
T1122 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3936891950 Aug 11 04:57:40 PM PDT 24 Aug 11 04:57:41 PM PDT 24 75613233 ps
T1123 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2321826102 Aug 11 04:57:57 PM PDT 24 Aug 11 04:58:06 PM PDT 24 294823357 ps
T1124 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4211310703 Aug 11 04:58:01 PM PDT 24 Aug 11 04:58:04 PM PDT 24 377824427 ps
T1125 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.187481163 Aug 11 04:57:56 PM PDT 24 Aug 11 04:57:58 PM PDT 24 84271543 ps
T1126 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4094289126 Aug 11 04:57:56 PM PDT 24 Aug 11 04:58:02 PM PDT 24 491701864 ps
T1127 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1052653192 Aug 11 04:57:48 PM PDT 24 Aug 11 04:57:51 PM PDT 24 41772606 ps
T1128 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.121481596 Aug 11 04:57:43 PM PDT 24 Aug 11 04:57:52 PM PDT 24 614615131 ps
T1129 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2458530147 Aug 11 04:57:59 PM PDT 24 Aug 11 04:58:04 PM PDT 24 786806767 ps
T1130 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3736205061 Aug 11 04:58:02 PM PDT 24 Aug 11 04:58:03 PM PDT 24 14652648 ps
T1131 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1750255827 Aug 11 04:57:48 PM PDT 24 Aug 11 04:57:49 PM PDT 24 16833168 ps

Test location /workspace/coverage/default/23.spi_device_stress_all.445791325
Short name T7
Test name
Test status
Simulation time 33701232470 ps
CPU time 60.22 seconds
Started Aug 11 05:21:31 PM PDT 24
Finished Aug 11 05:22:32 PM PDT 24
Peak memory 241360 kb
Host smart-5c364414-48b7-408f-b24c-c9c0a39bc068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445791325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.445791325
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3390545533
Short name T14
Test name
Test status
Simulation time 1177062437864 ps
CPU time 524.02 seconds
Started Aug 11 05:22:32 PM PDT 24
Finished Aug 11 05:31:16 PM PDT 24
Peak memory 273512 kb
Host smart-ba0e5c2a-e203-408d-9ea5-b80477a9a9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390545533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3390545533
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2108274714
Short name T16
Test name
Test status
Simulation time 17672251854 ps
CPU time 95 seconds
Started Aug 11 05:22:08 PM PDT 24
Finished Aug 11 05:23:44 PM PDT 24
Peak memory 263256 kb
Host smart-d0d05ba9-f00d-4b1b-ad48-255a5d507270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108274714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2108274714
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1270303233
Short name T141
Test name
Test status
Simulation time 2839448428 ps
CPU time 15.68 seconds
Started Aug 11 04:57:48 PM PDT 24
Finished Aug 11 04:58:04 PM PDT 24
Peak memory 215360 kb
Host smart-8c891b11-9179-4f66-b8ca-3ccca2594b55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270303233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1270303233
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.4107495788
Short name T17
Test name
Test status
Simulation time 721134693131 ps
CPU time 427.39 seconds
Started Aug 11 05:22:31 PM PDT 24
Finished Aug 11 05:29:38 PM PDT 24
Peak memory 257800 kb
Host smart-93f32011-eb17-4a07-9f49-9b8b0b685ac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107495788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.4107495788
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.540256717
Short name T70
Test name
Test status
Simulation time 15263947 ps
CPU time 0.75 seconds
Started Aug 11 05:17:57 PM PDT 24
Finished Aug 11 05:17:58 PM PDT 24
Peak memory 216276 kb
Host smart-263014d0-8932-4b3d-9042-cd8aeb2b994d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540256717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.540256717
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3390514974
Short name T97
Test name
Test status
Simulation time 208335821 ps
CPU time 4 seconds
Started Aug 11 04:57:55 PM PDT 24
Finished Aug 11 04:57:59 PM PDT 24
Peak memory 218400 kb
Host smart-c978eea9-76cf-46d2-a96b-a30cfce4491d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390514974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3390514974
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.5334674
Short name T76
Test name
Test status
Simulation time 355262710913 ps
CPU time 947.42 seconds
Started Aug 11 05:24:33 PM PDT 24
Finished Aug 11 05:40:20 PM PDT 24
Peak memory 274100 kb
Host smart-8b971509-2496-4676-b26c-0fe74ff1d375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5334674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_
all.5334674
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3389062058
Short name T43
Test name
Test status
Simulation time 454949031252 ps
CPU time 279.42 seconds
Started Aug 11 05:23:59 PM PDT 24
Finished Aug 11 05:28:38 PM PDT 24
Peak memory 265788 kb
Host smart-1315af3c-db49-45e0-a64c-2d1464977a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389062058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3389062058
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1845041234
Short name T224
Test name
Test status
Simulation time 26606197630 ps
CPU time 276.46 seconds
Started Aug 11 05:19:01 PM PDT 24
Finished Aug 11 05:23:37 PM PDT 24
Peak memory 262740 kb
Host smart-84726479-327b-4ad0-8215-0c301cec8d9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845041234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1845041234
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.99285425
Short name T13
Test name
Test status
Simulation time 124323720 ps
CPU time 0.95 seconds
Started Aug 11 05:18:03 PM PDT 24
Finished Aug 11 05:18:04 PM PDT 24
Peak memory 236788 kb
Host smart-bfcbfc20-cb45-4e93-976f-6001dc90b3c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99285425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.99285425
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3793587664
Short name T180
Test name
Test status
Simulation time 35816177369 ps
CPU time 293.16 seconds
Started Aug 11 05:21:00 PM PDT 24
Finished Aug 11 05:25:54 PM PDT 24
Peak memory 249432 kb
Host smart-c4f48e17-9e6f-4edc-b6a3-db45e7ba7809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793587664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3793587664
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.612865778
Short name T181
Test name
Test status
Simulation time 46718352878 ps
CPU time 203.19 seconds
Started Aug 11 05:23:25 PM PDT 24
Finished Aug 11 05:26:48 PM PDT 24
Peak memory 250564 kb
Host smart-0a50d587-21c7-4d22-9b81-f42bf1353c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612865778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.612865778
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2843728162
Short name T38
Test name
Test status
Simulation time 9839942366 ps
CPU time 39.5 seconds
Started Aug 11 05:23:52 PM PDT 24
Finished Aug 11 05:24:32 PM PDT 24
Peak memory 241292 kb
Host smart-c0516908-5850-4f89-92b2-d7bcdd0d60d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843728162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2843728162
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.209454107
Short name T197
Test name
Test status
Simulation time 26026969091 ps
CPU time 400.96 seconds
Started Aug 11 05:21:39 PM PDT 24
Finished Aug 11 05:28:20 PM PDT 24
Peak memory 282292 kb
Host smart-e1566257-f86f-447e-ba77-ac1acc646c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209454107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.209454107
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3684120810
Short name T182
Test name
Test status
Simulation time 80486985876 ps
CPU time 183.53 seconds
Started Aug 11 05:18:32 PM PDT 24
Finished Aug 11 05:21:35 PM PDT 24
Peak memory 266012 kb
Host smart-c0e45a4c-3223-4889-8d4d-b70a72e1716d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684120810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3684120810
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2904114916
Short name T186
Test name
Test status
Simulation time 13350122753 ps
CPU time 75.88 seconds
Started Aug 11 05:20:00 PM PDT 24
Finished Aug 11 05:21:16 PM PDT 24
Peak memory 257624 kb
Host smart-a05f53ce-d8ce-4224-9827-2e62d5218967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904114916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2904114916
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2187804353
Short name T202
Test name
Test status
Simulation time 48449026239 ps
CPU time 466.46 seconds
Started Aug 11 05:22:39 PM PDT 24
Finished Aug 11 05:30:26 PM PDT 24
Peak memory 265740 kb
Host smart-bcdc792a-66d1-47f0-9853-c0a54c2ba802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187804353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2187804353
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2357355989
Short name T110
Test name
Test status
Simulation time 430782181 ps
CPU time 15.44 seconds
Started Aug 11 04:57:44 PM PDT 24
Finished Aug 11 04:57:59 PM PDT 24
Peak memory 206840 kb
Host smart-01523f53-85a9-4af7-8155-bfd764088d7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357355989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2357355989
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2330298058
Short name T184
Test name
Test status
Simulation time 4985760688 ps
CPU time 46.3 seconds
Started Aug 11 05:23:58 PM PDT 24
Finished Aug 11 05:24:44 PM PDT 24
Peak memory 249884 kb
Host smart-13b056be-04a9-4716-b93e-7045a049ebf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330298058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2330298058
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2286505603
Short name T172
Test name
Test status
Simulation time 14526949856 ps
CPU time 146.69 seconds
Started Aug 11 05:23:16 PM PDT 24
Finished Aug 11 05:25:43 PM PDT 24
Peak memory 265624 kb
Host smart-c0d0314a-a343-4989-9a29-a2fd90f21322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286505603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2286505603
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1168474668
Short name T187
Test name
Test status
Simulation time 12308248013 ps
CPU time 78.94 seconds
Started Aug 11 05:19:05 PM PDT 24
Finished Aug 11 05:20:24 PM PDT 24
Peak memory 265948 kb
Host smart-808cf7a4-1521-41be-8c86-1db05efbab32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168474668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1168474668
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.944299322
Short name T37
Test name
Test status
Simulation time 19663182281 ps
CPU time 189.18 seconds
Started Aug 11 05:21:13 PM PDT 24
Finished Aug 11 05:24:23 PM PDT 24
Peak memory 264824 kb
Host smart-697e32e0-63f2-4d46-ad43-8c8bb4385d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944299322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.944299322
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1158310250
Short name T188
Test name
Test status
Simulation time 277166363457 ps
CPU time 348.74 seconds
Started Aug 11 05:18:30 PM PDT 24
Finished Aug 11 05:24:19 PM PDT 24
Peak memory 265880 kb
Host smart-3b32381f-a2ab-41c5-b837-788ae28fbfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158310250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1158310250
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.298444321
Short name T3
Test name
Test status
Simulation time 133824596 ps
CPU time 0.72 seconds
Started Aug 11 05:23:54 PM PDT 24
Finished Aug 11 05:23:54 PM PDT 24
Peak memory 205208 kb
Host smart-d728282f-cdec-4399-9916-5ad9fc21d41e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298444321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.298444321
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1190465577
Short name T327
Test name
Test status
Simulation time 8863664281 ps
CPU time 13.32 seconds
Started Aug 11 05:22:10 PM PDT 24
Finished Aug 11 05:22:24 PM PDT 24
Peak memory 216568 kb
Host smart-ee26df37-d10e-41c9-809f-21cf8e41ccfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190465577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1190465577
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1858500521
Short name T275
Test name
Test status
Simulation time 185068179240 ps
CPU time 493.17 seconds
Started Aug 11 05:22:09 PM PDT 24
Finished Aug 11 05:30:22 PM PDT 24
Peak memory 272928 kb
Host smart-18ef73f4-775a-46f4-be48-98fa6b25819a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858500521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1858500521
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1951151952
Short name T33
Test name
Test status
Simulation time 51165176845 ps
CPU time 271.47 seconds
Started Aug 11 05:22:16 PM PDT 24
Finished Aug 11 05:26:47 PM PDT 24
Peak memory 252584 kb
Host smart-61be2f48-a7a7-43b5-9331-2134cd9685e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951151952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1951151952
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2949239151
Short name T195
Test name
Test status
Simulation time 9483002403 ps
CPU time 53.67 seconds
Started Aug 11 05:23:03 PM PDT 24
Finished Aug 11 05:23:57 PM PDT 24
Peak memory 241020 kb
Host smart-1c4357a7-8d71-4b1a-8d36-be904a1fbfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949239151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2949239151
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1551038852
Short name T5
Test name
Test status
Simulation time 10645709972 ps
CPU time 91.87 seconds
Started Aug 11 05:20:25 PM PDT 24
Finished Aug 11 05:21:57 PM PDT 24
Peak memory 241012 kb
Host smart-245c6421-bd97-4086-8e81-1ecb621d723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551038852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1551038852
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3683126860
Short name T214
Test name
Test status
Simulation time 289562430863 ps
CPU time 509.73 seconds
Started Aug 11 05:20:39 PM PDT 24
Finished Aug 11 05:29:09 PM PDT 24
Peak memory 254624 kb
Host smart-0fe50e44-bffe-4fd5-b92c-e1c99f8678ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683126860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3683126860
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1097166778
Short name T171
Test name
Test status
Simulation time 5592770328 ps
CPU time 58.21 seconds
Started Aug 11 05:18:35 PM PDT 24
Finished Aug 11 05:19:33 PM PDT 24
Peak memory 250520 kb
Host smart-63c004bb-fdfc-45fc-bf84-76bcf527a453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097166778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1097166778
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.263333414
Short name T128
Test name
Test status
Simulation time 35313220673 ps
CPU time 354.39 seconds
Started Aug 11 05:22:05 PM PDT 24
Finished Aug 11 05:28:00 PM PDT 24
Peak memory 269068 kb
Host smart-f6ac70e3-0edf-4f9d-b96d-dda3bffc0d4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263333414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.263333414
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.274528740
Short name T98
Test name
Test status
Simulation time 52755300 ps
CPU time 3.28 seconds
Started Aug 11 04:57:46 PM PDT 24
Finished Aug 11 04:57:49 PM PDT 24
Peak memory 215184 kb
Host smart-d2154da5-683e-415d-846b-19edaff382a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274528740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.274528740
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.102046564
Short name T164
Test name
Test status
Simulation time 2577838571 ps
CPU time 12.67 seconds
Started Aug 11 04:57:46 PM PDT 24
Finished Aug 11 04:57:59 PM PDT 24
Peak memory 215336 kb
Host smart-fd87f6d3-dc23-4f49-a7d7-5b3c1e670d56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102046564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.102046564
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3807953424
Short name T282
Test name
Test status
Simulation time 13608897855 ps
CPU time 185.22 seconds
Started Aug 11 05:19:43 PM PDT 24
Finished Aug 11 05:22:49 PM PDT 24
Peak memory 265500 kb
Host smart-51a82dbb-baf9-4de2-8bd4-37828e01d1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807953424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3807953424
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.4053856723
Short name T301
Test name
Test status
Simulation time 479299885 ps
CPU time 8.1 seconds
Started Aug 11 05:19:38 PM PDT 24
Finished Aug 11 05:19:46 PM PDT 24
Peak memory 224880 kb
Host smart-63f62618-a5c5-47a3-9cd6-4f5811e2cc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053856723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.4053856723
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2341576333
Short name T291
Test name
Test status
Simulation time 55344627742 ps
CPU time 270.1 seconds
Started Aug 11 05:19:49 PM PDT 24
Finished Aug 11 05:24:19 PM PDT 24
Peak memory 256124 kb
Host smart-5777e3a9-f54d-4abf-8c9c-d0312a93a7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341576333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2341576333
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3191187588
Short name T251
Test name
Test status
Simulation time 86416171457 ps
CPU time 341.9 seconds
Started Aug 11 05:21:00 PM PDT 24
Finished Aug 11 05:26:42 PM PDT 24
Peak memory 254716 kb
Host smart-bf7b7adc-c14f-43f4-80d8-3e0af3e5e027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191187588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3191187588
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1912559293
Short name T169
Test name
Test status
Simulation time 1022315627 ps
CPU time 19.35 seconds
Started Aug 11 04:57:59 PM PDT 24
Finished Aug 11 04:58:19 PM PDT 24
Peak memory 215604 kb
Host smart-2268eb51-a9c6-4ef2-a87d-f4121c5ed92a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912559293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1912559293
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4257644043
Short name T163
Test name
Test status
Simulation time 1542222009 ps
CPU time 10.35 seconds
Started Aug 11 04:57:59 PM PDT 24
Finished Aug 11 04:58:09 PM PDT 24
Peak memory 215044 kb
Host smart-7bcb09ac-38bc-4d23-893c-6e48cbf0f5b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257644043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.4257644043
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1536116994
Short name T196
Test name
Test status
Simulation time 81988779794 ps
CPU time 192.46 seconds
Started Aug 11 05:18:06 PM PDT 24
Finished Aug 11 05:21:19 PM PDT 24
Peak memory 249548 kb
Host smart-a6eba3ce-314d-4099-a58f-df817f011394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536116994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1536116994
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1850819826
Short name T538
Test name
Test status
Simulation time 41005581137 ps
CPU time 182.84 seconds
Started Aug 11 05:18:04 PM PDT 24
Finished Aug 11 05:21:07 PM PDT 24
Peak memory 264836 kb
Host smart-7e5344e8-2180-47cf-95ca-f44b99d0c00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850819826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1850819826
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1620388467
Short name T138
Test name
Test status
Simulation time 573050287 ps
CPU time 6.58 seconds
Started Aug 11 05:19:42 PM PDT 24
Finished Aug 11 05:19:49 PM PDT 24
Peak memory 224916 kb
Host smart-ad4ea910-7bb1-456e-91a3-82cdff324988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620388467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1620388467
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1112783030
Short name T286
Test name
Test status
Simulation time 17370919889 ps
CPU time 109.81 seconds
Started Aug 11 05:19:48 PM PDT 24
Finished Aug 11 05:21:38 PM PDT 24
Peak memory 256472 kb
Host smart-a10fa9c1-132e-43e3-8ae6-09f8a9e01f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112783030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1112783030
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3496982000
Short name T289
Test name
Test status
Simulation time 27464503192 ps
CPU time 130.74 seconds
Started Aug 11 05:19:54 PM PDT 24
Finished Aug 11 05:22:05 PM PDT 24
Peak memory 268128 kb
Host smart-c869f491-82cb-4f23-8fc9-84754af0140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496982000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3496982000
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1745746540
Short name T300
Test name
Test status
Simulation time 3317653858 ps
CPU time 18.38 seconds
Started Aug 11 05:20:38 PM PDT 24
Finished Aug 11 05:20:56 PM PDT 24
Peak memory 224812 kb
Host smart-dcfaa16d-ae80-4e07-807a-12e6b821bb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745746540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1745746540
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3610927931
Short name T157
Test name
Test status
Simulation time 69915019388 ps
CPU time 113.21 seconds
Started Aug 11 05:18:23 PM PDT 24
Finished Aug 11 05:20:17 PM PDT 24
Peak memory 238920 kb
Host smart-efe76dcc-d29b-4af5-b539-03c453236c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610927931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3610927931
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3810712603
Short name T45
Test name
Test status
Simulation time 104158348 ps
CPU time 2.91 seconds
Started Aug 11 05:21:07 PM PDT 24
Finished Aug 11 05:21:10 PM PDT 24
Peak memory 224864 kb
Host smart-e8bfb1ec-4f81-412d-bc9f-21f59d0755cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810712603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3810712603
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2777676898
Short name T308
Test name
Test status
Simulation time 35058071888 ps
CPU time 45.76 seconds
Started Aug 11 05:21:08 PM PDT 24
Finished Aug 11 05:21:53 PM PDT 24
Peak memory 216576 kb
Host smart-22d72ee5-907c-4b28-8c3f-45afeafc5d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777676898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2777676898
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1709543241
Short name T175
Test name
Test status
Simulation time 486530202 ps
CPU time 4.1 seconds
Started Aug 11 05:22:14 PM PDT 24
Finished Aug 11 05:22:19 PM PDT 24
Peak memory 233044 kb
Host smart-fd08fec7-6700-4aa0-8c18-0b22d4a724c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709543241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1709543241
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3962891791
Short name T192
Test name
Test status
Simulation time 203215485960 ps
CPU time 512.39 seconds
Started Aug 11 05:24:35 PM PDT 24
Finished Aug 11 05:33:08 PM PDT 24
Peak memory 267348 kb
Host smart-5e9fd98e-4b50-46f8-b3c4-9628d9081084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962891791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3962891791
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1762741862
Short name T91
Test name
Test status
Simulation time 2923960789 ps
CPU time 6.15 seconds
Started Aug 11 05:19:53 PM PDT 24
Finished Aug 11 05:20:00 PM PDT 24
Peak memory 232996 kb
Host smart-4318e498-e32c-471b-a754-ec33598b7db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762741862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1762741862
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3678456582
Short name T79
Test name
Test status
Simulation time 167405122 ps
CPU time 1.19 seconds
Started Aug 11 04:57:40 PM PDT 24
Finished Aug 11 04:57:41 PM PDT 24
Peak memory 206804 kb
Host smart-0f590889-1ef1-4728-947b-3bb15c08bc95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678456582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3678456582
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1409781273
Short name T93
Test name
Test status
Simulation time 378841622 ps
CPU time 5.96 seconds
Started Aug 11 04:57:47 PM PDT 24
Finished Aug 11 04:57:53 PM PDT 24
Peak memory 216176 kb
Host smart-ca17433f-513c-4af3-961f-cbdb45788cd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409781273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
409781273
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.121651233
Short name T1118
Test name
Test status
Simulation time 712233431 ps
CPU time 8.69 seconds
Started Aug 11 04:57:40 PM PDT 24
Finished Aug 11 04:57:49 PM PDT 24
Peak memory 215048 kb
Host smart-8d4809f6-8788-4956-9c24-e9dba56103ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121651233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.121651233
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3663031683
Short name T1120
Test name
Test status
Simulation time 551773787 ps
CPU time 34.69 seconds
Started Aug 11 04:57:37 PM PDT 24
Finished Aug 11 04:58:12 PM PDT 24
Peak memory 206852 kb
Host smart-494e3e7f-7f94-45ad-92ff-6a429f883fa9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663031683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3663031683
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3867183295
Short name T104
Test name
Test status
Simulation time 55551040 ps
CPU time 2.02 seconds
Started Aug 11 04:57:35 PM PDT 24
Finished Aug 11 04:57:38 PM PDT 24
Peak memory 215120 kb
Host smart-fe404363-448f-4c6b-a1c4-853bde682984
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867183295 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3867183295
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2114606285
Short name T1099
Test name
Test status
Simulation time 64824695 ps
CPU time 2.36 seconds
Started Aug 11 04:57:40 PM PDT 24
Finished Aug 11 04:57:42 PM PDT 24
Peak memory 215012 kb
Host smart-ca730c6e-cad8-4b4d-b2a9-4b6809a984cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114606285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
114606285
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2788974393
Short name T1074
Test name
Test status
Simulation time 27166547 ps
CPU time 0.76 seconds
Started Aug 11 04:57:43 PM PDT 24
Finished Aug 11 04:57:45 PM PDT 24
Peak memory 203588 kb
Host smart-7dbace8c-9ff3-49eb-942f-c0c7719f2b8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788974393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
788974393
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.70385729
Short name T1092
Test name
Test status
Simulation time 25481631 ps
CPU time 1.77 seconds
Started Aug 11 04:57:37 PM PDT 24
Finished Aug 11 04:57:39 PM PDT 24
Peak memory 214936 kb
Host smart-391812ec-a7e1-4c7b-a3bf-9f7c84ae80d9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70385729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_d
evice_mem_partial_access.70385729
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3936891950
Short name T1122
Test name
Test status
Simulation time 75613233 ps
CPU time 0.67 seconds
Started Aug 11 04:57:40 PM PDT 24
Finished Aug 11 04:57:41 PM PDT 24
Peak memory 203468 kb
Host smart-e3cb3fd5-4f9d-49ee-89e6-252759fb2218
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936891950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3936891950
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.22713657
Short name T1027
Test name
Test status
Simulation time 29869701 ps
CPU time 1.89 seconds
Started Aug 11 04:57:39 PM PDT 24
Finished Aug 11 04:57:41 PM PDT 24
Peak memory 215064 kb
Host smart-ddc5f4d8-403d-426e-9dd9-73d6ca8feda7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22713657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_same_csr_outstanding.22713657
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3531494225
Short name T99
Test name
Test status
Simulation time 93355772 ps
CPU time 2.4 seconds
Started Aug 11 04:57:36 PM PDT 24
Finished Aug 11 04:57:39 PM PDT 24
Peak memory 216128 kb
Host smart-1e938b49-2354-499c-b268-7afc3d471293
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531494225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
531494225
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3131440639
Short name T106
Test name
Test status
Simulation time 274760866 ps
CPU time 7.71 seconds
Started Aug 11 04:57:40 PM PDT 24
Finished Aug 11 04:57:48 PM PDT 24
Peak memory 215020 kb
Host smart-73cbcc15-17a1-4115-8047-eed389fc67c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131440639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3131440639
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1092925091
Short name T1029
Test name
Test status
Simulation time 3504113177 ps
CPU time 22.32 seconds
Started Aug 11 04:57:42 PM PDT 24
Finished Aug 11 04:58:04 PM PDT 24
Peak memory 206868 kb
Host smart-b5877bdf-db79-4e7e-a3c8-0b4ffbf2a0b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092925091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1092925091
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3665990430
Short name T1080
Test name
Test status
Simulation time 16837571 ps
CPU time 0.95 seconds
Started Aug 11 04:57:44 PM PDT 24
Finished Aug 11 04:57:45 PM PDT 24
Peak memory 206588 kb
Host smart-cd9b8c6c-2fb1-4741-9dd4-6cb2fecd765c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665990430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3665990430
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.827781394
Short name T101
Test name
Test status
Simulation time 259884811 ps
CPU time 4.67 seconds
Started Aug 11 04:57:41 PM PDT 24
Finished Aug 11 04:57:46 PM PDT 24
Peak memory 217452 kb
Host smart-1132b587-21a5-410a-9a9c-124b367a2725
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827781394 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.827781394
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.58506104
Short name T117
Test name
Test status
Simulation time 32460296 ps
CPU time 1.91 seconds
Started Aug 11 04:57:47 PM PDT 24
Finished Aug 11 04:57:49 PM PDT 24
Peak memory 215096 kb
Host smart-ec7dc3a5-7d44-49c9-a2a0-fac7e5c1edaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58506104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.58506104
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1770125967
Short name T1040
Test name
Test status
Simulation time 39555000 ps
CPU time 0.81 seconds
Started Aug 11 04:57:42 PM PDT 24
Finished Aug 11 04:57:43 PM PDT 24
Peak memory 203808 kb
Host smart-1f969eab-0a97-4b68-a421-6ba3e2c462fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770125967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
770125967
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3080902250
Short name T108
Test name
Test status
Simulation time 207270812 ps
CPU time 1.75 seconds
Started Aug 11 04:57:44 PM PDT 24
Finished Aug 11 04:57:46 PM PDT 24
Peak memory 214984 kb
Host smart-3638ea75-a62c-4048-9dfe-b3b745451ac4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080902250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3080902250
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2461156060
Short name T1095
Test name
Test status
Simulation time 15628986 ps
CPU time 0.72 seconds
Started Aug 11 04:57:44 PM PDT 24
Finished Aug 11 04:57:45 PM PDT 24
Peak memory 203456 kb
Host smart-27f2252a-084a-4bc0-9372-2ee69ca612a6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461156060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2461156060
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3221541815
Short name T1072
Test name
Test status
Simulation time 678524620 ps
CPU time 2.89 seconds
Started Aug 11 04:57:43 PM PDT 24
Finished Aug 11 04:57:46 PM PDT 24
Peak memory 215012 kb
Host smart-09a5774b-4013-4627-bad3-1a47fa55946b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221541815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3221541815
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2733514279
Short name T1062
Test name
Test status
Simulation time 41654915 ps
CPU time 2.87 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:59 PM PDT 24
Peak memory 215388 kb
Host smart-cd1be9e1-4a5f-4957-9293-dac53619b0cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733514279 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2733514279
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1277475053
Short name T149
Test name
Test status
Simulation time 322855569 ps
CPU time 2.19 seconds
Started Aug 11 04:58:06 PM PDT 24
Finished Aug 11 04:58:08 PM PDT 24
Peak memory 215080 kb
Host smart-359022c5-3430-4a4d-ba07-5bb6ae7e4586
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277475053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1277475053
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3124305116
Short name T1018
Test name
Test status
Simulation time 18316027 ps
CPU time 0.8 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:57 PM PDT 24
Peak memory 203468 kb
Host smart-43bdbf96-2ee0-4907-ac8c-ca33a7c0695f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124305116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3124305116
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2461666671
Short name T130
Test name
Test status
Simulation time 177578560 ps
CPU time 2.65 seconds
Started Aug 11 04:57:59 PM PDT 24
Finished Aug 11 04:58:02 PM PDT 24
Peak memory 215020 kb
Host smart-d1d1c004-d22d-42fc-a888-5641c3049e07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461666671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2461666671
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4094289126
Short name T1126
Test name
Test status
Simulation time 491701864 ps
CPU time 5.83 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:58:02 PM PDT 24
Peak memory 215180 kb
Host smart-6943c381-db74-49a1-897c-7a846534d38e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094289126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4094289126
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4230610417
Short name T166
Test name
Test status
Simulation time 109642486 ps
CPU time 7.53 seconds
Started Aug 11 04:57:57 PM PDT 24
Finished Aug 11 04:58:05 PM PDT 24
Peak memory 215044 kb
Host smart-92794071-b1a0-4dc5-9053-bc321114af12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230610417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4230610417
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.847689466
Short name T1098
Test name
Test status
Simulation time 142257921 ps
CPU time 2.72 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:59 PM PDT 24
Peak memory 217108 kb
Host smart-1262537c-1e26-4078-9f6a-94c41e1e6f57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847689466 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.847689466
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3296050917
Short name T1077
Test name
Test status
Simulation time 143548265 ps
CPU time 1.25 seconds
Started Aug 11 04:57:55 PM PDT 24
Finished Aug 11 04:57:56 PM PDT 24
Peak memory 206956 kb
Host smart-f0df90bf-97da-4621-abf3-126922fe4a00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296050917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3296050917
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.95727152
Short name T1096
Test name
Test status
Simulation time 41481773 ps
CPU time 0.66 seconds
Started Aug 11 04:57:58 PM PDT 24
Finished Aug 11 04:57:59 PM PDT 24
Peak memory 203512 kb
Host smart-b32b723f-3d6e-4046-a1e5-d789a45be7c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95727152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.95727152
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3189363385
Short name T1102
Test name
Test status
Simulation time 46015987 ps
CPU time 3.04 seconds
Started Aug 11 04:58:06 PM PDT 24
Finished Aug 11 04:58:09 PM PDT 24
Peak memory 215012 kb
Host smart-3df812c1-1792-42a0-84df-6f5bd6ba768c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189363385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3189363385
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4154843754
Short name T100
Test name
Test status
Simulation time 285939895 ps
CPU time 5.11 seconds
Started Aug 11 04:57:57 PM PDT 24
Finished Aug 11 04:58:02 PM PDT 24
Peak memory 215128 kb
Host smart-0f632d0a-91d8-4559-ad81-6fd57e3b8c34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154843754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
4154843754
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.27575799
Short name T167
Test name
Test status
Simulation time 769796796 ps
CPU time 12.52 seconds
Started Aug 11 04:57:59 PM PDT 24
Finished Aug 11 04:58:12 PM PDT 24
Peak memory 215032 kb
Host smart-d7821b37-ab6b-45a6-a9f1-f25b41c2c5ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27575799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_
tl_intg_err.27575799
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3201985138
Short name T1043
Test name
Test status
Simulation time 121791473 ps
CPU time 3.8 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:59 PM PDT 24
Peak memory 217780 kb
Host smart-937c78f5-8df2-40fb-bd8c-37402f50b531
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201985138 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3201985138
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1698647429
Short name T1078
Test name
Test status
Simulation time 53851339 ps
CPU time 1.76 seconds
Started Aug 11 04:57:55 PM PDT 24
Finished Aug 11 04:57:57 PM PDT 24
Peak memory 214996 kb
Host smart-1c6fc9ac-9399-474c-b4de-fc69b83bd5d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698647429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1698647429
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.924172341
Short name T1087
Test name
Test status
Simulation time 24775510 ps
CPU time 0.7 seconds
Started Aug 11 04:57:57 PM PDT 24
Finished Aug 11 04:57:58 PM PDT 24
Peak memory 203500 kb
Host smart-4914e036-b351-45a5-bff1-e5c3b127b7b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924172341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.924172341
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1047135837
Short name T129
Test name
Test status
Simulation time 40887245 ps
CPU time 2.86 seconds
Started Aug 11 04:57:59 PM PDT 24
Finished Aug 11 04:58:02 PM PDT 24
Peak memory 214992 kb
Host smart-8d4ec8c5-66fa-451e-ba19-a96cf50e81e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047135837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1047135837
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.886104434
Short name T68
Test name
Test status
Simulation time 260797786 ps
CPU time 5.99 seconds
Started Aug 11 04:57:57 PM PDT 24
Finished Aug 11 04:58:03 PM PDT 24
Peak memory 216128 kb
Host smart-c945bb61-203e-411b-b1ec-4f9ef831239f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886104434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.886104434
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1819494046
Short name T1116
Test name
Test status
Simulation time 2103284034 ps
CPU time 25.9 seconds
Started Aug 11 04:57:58 PM PDT 24
Finished Aug 11 04:58:24 PM PDT 24
Peak memory 216324 kb
Host smart-d045bc05-9adc-4503-9ff2-c0fb963bf168
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819494046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1819494046
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.157270182
Short name T147
Test name
Test status
Simulation time 198111906 ps
CPU time 2.81 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:59 PM PDT 24
Peak memory 216448 kb
Host smart-5f52ddf5-e506-4a3a-ab41-ed9ec7e8c474
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157270182 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.157270182
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2306001443
Short name T1113
Test name
Test status
Simulation time 62175708 ps
CPU time 2.16 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:59 PM PDT 24
Peak memory 215012 kb
Host smart-c017f53b-099a-40bf-9738-0830750431d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306001443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2306001443
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3532596718
Short name T1032
Test name
Test status
Simulation time 20361472 ps
CPU time 0.76 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:57 PM PDT 24
Peak memory 203824 kb
Host smart-41db67e2-5bce-40ec-bb22-f251e73e9cd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532596718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3532596718
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2414901689
Short name T1109
Test name
Test status
Simulation time 994754633 ps
CPU time 4.35 seconds
Started Aug 11 04:57:58 PM PDT 24
Finished Aug 11 04:58:03 PM PDT 24
Peak memory 215044 kb
Host smart-d3ca066a-bd3a-49b7-9361-684a9999fae8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414901689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2414901689
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2458530147
Short name T1129
Test name
Test status
Simulation time 786806767 ps
CPU time 4.6 seconds
Started Aug 11 04:57:59 PM PDT 24
Finished Aug 11 04:58:04 PM PDT 24
Peak memory 215288 kb
Host smart-daab7c00-cd07-4ed0-939a-36e610d023e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458530147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2458530147
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1220780553
Short name T146
Test name
Test status
Simulation time 1457379768 ps
CPU time 9.87 seconds
Started Aug 11 04:57:55 PM PDT 24
Finished Aug 11 04:58:05 PM PDT 24
Peak memory 215044 kb
Host smart-c1a09f17-1e10-4063-93ee-3f47ac3363fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220780553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1220780553
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3532334346
Short name T142
Test name
Test status
Simulation time 280093615 ps
CPU time 3.34 seconds
Started Aug 11 04:57:58 PM PDT 24
Finished Aug 11 04:58:01 PM PDT 24
Peak memory 217300 kb
Host smart-6a03ba55-fc9e-41b0-814a-a0ee5b7e102f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532334346 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3532334346
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3835106106
Short name T1053
Test name
Test status
Simulation time 183609945 ps
CPU time 1.47 seconds
Started Aug 11 04:57:58 PM PDT 24
Finished Aug 11 04:58:00 PM PDT 24
Peak memory 206768 kb
Host smart-9210ba05-bf0f-4a07-88a8-5029b5fd55fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835106106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3835106106
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2966415196
Short name T1058
Test name
Test status
Simulation time 41456921 ps
CPU time 0.73 seconds
Started Aug 11 04:58:06 PM PDT 24
Finished Aug 11 04:58:07 PM PDT 24
Peak memory 203844 kb
Host smart-cec8c402-ed01-4e29-a47c-07aea3a84441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966415196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2966415196
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.436009123
Short name T140
Test name
Test status
Simulation time 132940069 ps
CPU time 2.23 seconds
Started Aug 11 04:57:57 PM PDT 24
Finished Aug 11 04:57:59 PM PDT 24
Peak memory 206784 kb
Host smart-029c8340-b43d-4df9-8c2d-572ff76229ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436009123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.436009123
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4281270636
Short name T161
Test name
Test status
Simulation time 43110353 ps
CPU time 2.69 seconds
Started Aug 11 04:57:55 PM PDT 24
Finished Aug 11 04:57:58 PM PDT 24
Peak memory 215088 kb
Host smart-bc4a8ceb-426f-4ffa-ad98-37e68c74cc9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281270636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
4281270636
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3736250939
Short name T1082
Test name
Test status
Simulation time 321882861 ps
CPU time 2.8 seconds
Started Aug 11 04:57:59 PM PDT 24
Finished Aug 11 04:58:02 PM PDT 24
Peak memory 216696 kb
Host smart-81c3ea12-0260-443a-8259-a752c86ea05c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736250939 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3736250939
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.795834416
Short name T1083
Test name
Test status
Simulation time 71700475 ps
CPU time 2.15 seconds
Started Aug 11 04:58:07 PM PDT 24
Finished Aug 11 04:58:09 PM PDT 24
Peak memory 215108 kb
Host smart-c9c6f795-d142-4527-b0eb-e0509ae7b757
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795834416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.795834416
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3024520951
Short name T1061
Test name
Test status
Simulation time 191420104 ps
CPU time 0.77 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:57 PM PDT 24
Peak memory 203488 kb
Host smart-119b61c1-8b6f-4074-8270-16866823738c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024520951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3024520951
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4213192353
Short name T1068
Test name
Test status
Simulation time 80722736 ps
CPU time 1.92 seconds
Started Aug 11 04:57:57 PM PDT 24
Finished Aug 11 04:57:59 PM PDT 24
Peak memory 206832 kb
Host smart-50d0be54-e7b1-497d-b707-43af5f3471a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213192353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4213192353
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3557270435
Short name T1069
Test name
Test status
Simulation time 194529364 ps
CPU time 4.96 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:58:02 PM PDT 24
Peak memory 219508 kb
Host smart-37257e97-e68b-41ac-886d-a99d0ac830c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557270435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3557270435
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1033210337
Short name T1119
Test name
Test status
Simulation time 1642209533 ps
CPU time 7.23 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:58:04 PM PDT 24
Peak memory 215212 kb
Host smart-730c2916-31f7-4e11-920d-4206ceaf7120
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033210337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1033210337
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3970177195
Short name T103
Test name
Test status
Simulation time 144302193 ps
CPU time 2.75 seconds
Started Aug 11 04:58:07 PM PDT 24
Finished Aug 11 04:58:10 PM PDT 24
Peak memory 216688 kb
Host smart-35e1f6e3-54e6-413a-9472-fd64b621be01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970177195 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3970177195
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4125701656
Short name T118
Test name
Test status
Simulation time 104575603 ps
CPU time 2.79 seconds
Started Aug 11 04:57:58 PM PDT 24
Finished Aug 11 04:58:01 PM PDT 24
Peak memory 206716 kb
Host smart-a4640601-f887-47d8-9105-c1a60293b3d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125701656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4125701656
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2388275801
Short name T1084
Test name
Test status
Simulation time 15752576 ps
CPU time 0.74 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:57 PM PDT 24
Peak memory 203864 kb
Host smart-81eb5fa8-34f8-43e8-8618-6211de70b80a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388275801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2388275801
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.743292777
Short name T1100
Test name
Test status
Simulation time 64361175 ps
CPU time 2.69 seconds
Started Aug 11 04:58:07 PM PDT 24
Finished Aug 11 04:58:10 PM PDT 24
Peak memory 215016 kb
Host smart-239fa7fa-c669-4083-aff7-cdb0ae025d47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743292777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.743292777
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2321826102
Short name T1123
Test name
Test status
Simulation time 294823357 ps
CPU time 8.93 seconds
Started Aug 11 04:57:57 PM PDT 24
Finished Aug 11 04:58:06 PM PDT 24
Peak memory 215100 kb
Host smart-e14fc376-16ed-4e8f-bcc8-bc170e0a3ffc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321826102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2321826102
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.835923528
Short name T1094
Test name
Test status
Simulation time 57890591 ps
CPU time 2.52 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:59 PM PDT 24
Peak memory 216688 kb
Host smart-aa49f700-4e64-4fcc-9313-0abb2fb4a0b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835923528 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.835923528
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.369376335
Short name T1041
Test name
Test status
Simulation time 127973045 ps
CPU time 2.51 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:58 PM PDT 24
Peak memory 214980 kb
Host smart-43b04653-906c-4594-9ad2-54011ed380df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369376335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.369376335
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2411379520
Short name T1117
Test name
Test status
Simulation time 128684114 ps
CPU time 0.74 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:56 PM PDT 24
Peak memory 203888 kb
Host smart-08844a73-ca2d-423c-9244-f5d1d98cd073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411379520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2411379520
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2385266954
Short name T1026
Test name
Test status
Simulation time 51309664 ps
CPU time 1.95 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:58 PM PDT 24
Peak memory 215060 kb
Host smart-9d810e9d-b9fb-410a-8103-6b42eb82ef61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385266954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2385266954
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2579974277
Short name T67
Test name
Test status
Simulation time 766034373 ps
CPU time 5.17 seconds
Started Aug 11 04:57:59 PM PDT 24
Finished Aug 11 04:58:04 PM PDT 24
Peak memory 215096 kb
Host smart-fe6f9d77-8e9a-4d05-aebe-3939b414870d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579974277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2579974277
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1744602581
Short name T1036
Test name
Test status
Simulation time 44850087 ps
CPU time 2.95 seconds
Started Aug 11 04:58:06 PM PDT 24
Finished Aug 11 04:58:09 PM PDT 24
Peak memory 217644 kb
Host smart-853827ac-06b6-4a02-8098-32925ae4c8be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744602581 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1744602581
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.375782271
Short name T132
Test name
Test status
Simulation time 66487515 ps
CPU time 2 seconds
Started Aug 11 04:58:05 PM PDT 24
Finished Aug 11 04:58:07 PM PDT 24
Peak memory 215032 kb
Host smart-60960bb3-0030-4d6e-b7ce-7f91eeb2ddb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375782271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.375782271
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3709467612
Short name T1030
Test name
Test status
Simulation time 11514253 ps
CPU time 0.71 seconds
Started Aug 11 04:57:57 PM PDT 24
Finished Aug 11 04:57:58 PM PDT 24
Peak memory 203508 kb
Host smart-01750841-9083-4107-a3ce-fae8bb4770c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709467612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3709467612
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1554274852
Short name T1115
Test name
Test status
Simulation time 247461891 ps
CPU time 2.04 seconds
Started Aug 11 04:57:58 PM PDT 24
Finished Aug 11 04:58:00 PM PDT 24
Peak memory 215012 kb
Host smart-99ac73ce-f252-4639-a8ce-ecab441d825f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554274852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1554274852
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3652060106
Short name T1121
Test name
Test status
Simulation time 156869120 ps
CPU time 4.64 seconds
Started Aug 11 04:57:58 PM PDT 24
Finished Aug 11 04:58:03 PM PDT 24
Peak memory 215072 kb
Host smart-4d0fce7b-8867-435f-8823-f0f6d032af03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652060106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3652060106
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.659835231
Short name T162
Test name
Test status
Simulation time 392163791 ps
CPU time 13.52 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:58:10 PM PDT 24
Peak memory 214992 kb
Host smart-1b9b6d9a-6615-40ce-8c66-e42a2e5241ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659835231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.659835231
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4211310703
Short name T1124
Test name
Test status
Simulation time 377824427 ps
CPU time 2.74 seconds
Started Aug 11 04:58:01 PM PDT 24
Finished Aug 11 04:58:04 PM PDT 24
Peak memory 216792 kb
Host smart-990c41fd-95eb-4936-9420-98b7da047130
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211310703 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.4211310703
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2610991682
Short name T131
Test name
Test status
Simulation time 58024489 ps
CPU time 1.84 seconds
Started Aug 11 04:58:06 PM PDT 24
Finished Aug 11 04:58:08 PM PDT 24
Peak memory 206724 kb
Host smart-4f93ea1c-a0bb-4939-b79c-bc348b2e5434
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610991682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2610991682
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.730417303
Short name T1014
Test name
Test status
Simulation time 15138903 ps
CPU time 0.76 seconds
Started Aug 11 04:58:02 PM PDT 24
Finished Aug 11 04:58:03 PM PDT 24
Peak memory 203544 kb
Host smart-a1dff889-5242-43ae-82e7-841e94a19e53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730417303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.730417303
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.128432259
Short name T143
Test name
Test status
Simulation time 543736620 ps
CPU time 3.12 seconds
Started Aug 11 04:58:05 PM PDT 24
Finished Aug 11 04:58:09 PM PDT 24
Peak memory 214944 kb
Host smart-fc0f802c-369a-43cc-89d5-711aed727756
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128432259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.128432259
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.594346292
Short name T1081
Test name
Test status
Simulation time 194155317 ps
CPU time 4.87 seconds
Started Aug 11 04:58:01 PM PDT 24
Finished Aug 11 04:58:06 PM PDT 24
Peak memory 216220 kb
Host smart-060258ac-0574-40f6-9ce0-cdbd8623468c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594346292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.594346292
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3619030035
Short name T165
Test name
Test status
Simulation time 342438493 ps
CPU time 7.7 seconds
Started Aug 11 04:58:03 PM PDT 24
Finished Aug 11 04:58:10 PM PDT 24
Peak memory 215332 kb
Host smart-daa53a17-0ed2-42fd-9424-5f0939bf280d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619030035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3619030035
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4071431618
Short name T114
Test name
Test status
Simulation time 229940679 ps
CPU time 15.26 seconds
Started Aug 11 04:57:44 PM PDT 24
Finished Aug 11 04:58:00 PM PDT 24
Peak memory 215024 kb
Host smart-6796d6da-0c45-493b-8a26-eff9ee973486
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071431618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.4071431618
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1602397441
Short name T116
Test name
Test status
Simulation time 543316824 ps
CPU time 34.66 seconds
Started Aug 11 04:57:46 PM PDT 24
Finished Aug 11 04:58:20 PM PDT 24
Peak memory 214996 kb
Host smart-75d67b4c-1a2c-4f62-b8f8-6082ac151beb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602397441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1602397441
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1810817733
Short name T77
Test name
Test status
Simulation time 69670213 ps
CPU time 0.97 seconds
Started Aug 11 04:57:45 PM PDT 24
Finished Aug 11 04:57:46 PM PDT 24
Peak memory 206548 kb
Host smart-ac639437-2af0-47cd-8762-a590490ad5df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810817733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1810817733
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.618467030
Short name T1090
Test name
Test status
Simulation time 89465402 ps
CPU time 1.77 seconds
Started Aug 11 04:57:43 PM PDT 24
Finished Aug 11 04:57:45 PM PDT 24
Peak memory 216148 kb
Host smart-4f5b450e-8acb-44fe-8264-56de59fd749d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618467030 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.618467030
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.970287825
Short name T1052
Test name
Test status
Simulation time 30720907 ps
CPU time 1.99 seconds
Started Aug 11 04:57:41 PM PDT 24
Finished Aug 11 04:57:44 PM PDT 24
Peak memory 206824 kb
Host smart-51c09704-7340-471d-ba68-bc09505eca69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970287825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.970287825
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.538770691
Short name T1091
Test name
Test status
Simulation time 177946308 ps
CPU time 0.75 seconds
Started Aug 11 04:57:43 PM PDT 24
Finished Aug 11 04:57:44 PM PDT 24
Peak memory 203848 kb
Host smart-5ca84ea5-dcf0-4341-b3fb-238d9363bd98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538770691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.538770691
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.602923567
Short name T1112
Test name
Test status
Simulation time 32757141 ps
CPU time 1.21 seconds
Started Aug 11 04:57:43 PM PDT 24
Finished Aug 11 04:57:44 PM PDT 24
Peak memory 214968 kb
Host smart-4bbc9cdd-e77f-4241-b942-1ec932f2eacf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602923567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.602923567
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3038956458
Short name T1044
Test name
Test status
Simulation time 13203660 ps
CPU time 0.69 seconds
Started Aug 11 04:57:42 PM PDT 24
Finished Aug 11 04:57:43 PM PDT 24
Peak memory 203464 kb
Host smart-4ad8132d-78bf-489a-afa5-cd427ce65ca8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038956458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3038956458
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.951894596
Short name T1035
Test name
Test status
Simulation time 687125136 ps
CPU time 3.21 seconds
Started Aug 11 04:57:46 PM PDT 24
Finished Aug 11 04:57:50 PM PDT 24
Peak memory 214888 kb
Host smart-174130e2-3943-4931-a6ae-27282cb1ea1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951894596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.951894596
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2697425498
Short name T168
Test name
Test status
Simulation time 1590248409 ps
CPU time 20.72 seconds
Started Aug 11 04:57:42 PM PDT 24
Finished Aug 11 04:58:03 PM PDT 24
Peak memory 215340 kb
Host smart-fbd712d2-bf56-4fe5-86e0-220240b1775a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697425498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2697425498
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1282542772
Short name T1015
Test name
Test status
Simulation time 12263066 ps
CPU time 0.74 seconds
Started Aug 11 04:58:00 PM PDT 24
Finished Aug 11 04:58:01 PM PDT 24
Peak memory 203516 kb
Host smart-9d01fb4b-6635-4b82-b64b-874c679b0bac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282542772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1282542772
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2399160663
Short name T1013
Test name
Test status
Simulation time 12206035 ps
CPU time 0.76 seconds
Started Aug 11 04:58:01 PM PDT 24
Finished Aug 11 04:58:02 PM PDT 24
Peak memory 203816 kb
Host smart-2e5ab367-6e3c-441a-9e28-506952756b24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399160663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2399160663
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3497031400
Short name T1039
Test name
Test status
Simulation time 12792941 ps
CPU time 0.75 seconds
Started Aug 11 04:58:01 PM PDT 24
Finished Aug 11 04:58:02 PM PDT 24
Peak memory 203912 kb
Host smart-1eb8735c-be0b-47d8-ad40-1717be650ebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497031400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3497031400
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2208205261
Short name T1089
Test name
Test status
Simulation time 16628680 ps
CPU time 0.8 seconds
Started Aug 11 04:58:02 PM PDT 24
Finished Aug 11 04:58:03 PM PDT 24
Peak memory 203612 kb
Host smart-3c42704a-b592-4dfb-8897-f6219239b810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208205261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2208205261
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1206072755
Short name T1104
Test name
Test status
Simulation time 12021496 ps
CPU time 0.72 seconds
Started Aug 11 04:58:00 PM PDT 24
Finished Aug 11 04:58:01 PM PDT 24
Peak memory 203516 kb
Host smart-7d6b7bc1-f42f-42d7-a461-707ce3a9db77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206072755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1206072755
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2713250974
Short name T1019
Test name
Test status
Simulation time 29086250 ps
CPU time 0.76 seconds
Started Aug 11 04:58:03 PM PDT 24
Finished Aug 11 04:58:04 PM PDT 24
Peak memory 203824 kb
Host smart-615d0d64-3abf-4e5d-beca-d84552b9a7c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713250974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2713250974
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2920421203
Short name T1085
Test name
Test status
Simulation time 34693755 ps
CPU time 0.8 seconds
Started Aug 11 04:58:03 PM PDT 24
Finished Aug 11 04:58:04 PM PDT 24
Peak memory 203628 kb
Host smart-fdbcf919-2813-46d2-be59-0d4c27c54d5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920421203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2920421203
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1052331237
Short name T1042
Test name
Test status
Simulation time 23894154 ps
CPU time 0.72 seconds
Started Aug 11 04:58:00 PM PDT 24
Finished Aug 11 04:58:01 PM PDT 24
Peak memory 203520 kb
Host smart-bb4ce59d-d99d-4f6e-b1ec-50f2a1ceb84f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052331237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1052331237
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1457945324
Short name T1037
Test name
Test status
Simulation time 13740135 ps
CPU time 0.74 seconds
Started Aug 11 04:58:00 PM PDT 24
Finished Aug 11 04:58:01 PM PDT 24
Peak memory 203540 kb
Host smart-9c7cd445-f58f-4502-849e-58da18bcc81c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457945324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1457945324
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3736205061
Short name T1130
Test name
Test status
Simulation time 14652648 ps
CPU time 0.73 seconds
Started Aug 11 04:58:02 PM PDT 24
Finished Aug 11 04:58:03 PM PDT 24
Peak memory 203492 kb
Host smart-c60c7efa-c87b-40a5-b2a7-e28753477c0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736205061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3736205061
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3477611956
Short name T113
Test name
Test status
Simulation time 310993023 ps
CPU time 22.26 seconds
Started Aug 11 04:57:47 PM PDT 24
Finished Aug 11 04:58:10 PM PDT 24
Peak memory 206848 kb
Host smart-afb022b6-6f6a-40e0-97e7-a984744c3b16
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477611956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3477611956
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1083708121
Short name T112
Test name
Test status
Simulation time 3456674000 ps
CPU time 27.25 seconds
Started Aug 11 04:57:45 PM PDT 24
Finished Aug 11 04:58:12 PM PDT 24
Peak memory 215036 kb
Host smart-6e6be4ae-4ff9-4a0a-b2ee-f442d5c05b02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083708121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1083708121
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2217461824
Short name T80
Test name
Test status
Simulation time 70893871 ps
CPU time 1.15 seconds
Started Aug 11 04:57:43 PM PDT 24
Finished Aug 11 04:57:45 PM PDT 24
Peak memory 216020 kb
Host smart-b2975fb0-7939-470c-9d47-9272b330e639
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217461824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2217461824
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1445486711
Short name T1106
Test name
Test status
Simulation time 120923211 ps
CPU time 3.34 seconds
Started Aug 11 04:57:48 PM PDT 24
Finished Aug 11 04:57:51 PM PDT 24
Peak memory 217568 kb
Host smart-90c35b2d-27fb-40cb-bf3f-f32272874e31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445486711 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1445486711
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1740658283
Short name T109
Test name
Test status
Simulation time 59380688 ps
CPU time 2.15 seconds
Started Aug 11 04:57:44 PM PDT 24
Finished Aug 11 04:57:46 PM PDT 24
Peak memory 206816 kb
Host smart-a8a87272-2417-43aa-8b71-fed6518ac05e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740658283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
740658283
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2452463016
Short name T1088
Test name
Test status
Simulation time 29935662 ps
CPU time 0.75 seconds
Started Aug 11 04:57:44 PM PDT 24
Finished Aug 11 04:57:45 PM PDT 24
Peak memory 203520 kb
Host smart-c16b7220-de5d-42ad-9130-04894d5ee5e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452463016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
452463016
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.165469928
Short name T111
Test name
Test status
Simulation time 60153388 ps
CPU time 1.31 seconds
Started Aug 11 04:57:46 PM PDT 24
Finished Aug 11 04:57:48 PM PDT 24
Peak memory 214896 kb
Host smart-c8f3cbb9-c396-43e3-bfcd-e847de18a295
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165469928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.165469928
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1076778300
Short name T1056
Test name
Test status
Simulation time 152323826 ps
CPU time 0.7 seconds
Started Aug 11 04:57:45 PM PDT 24
Finished Aug 11 04:57:46 PM PDT 24
Peak memory 203552 kb
Host smart-1ab8a6d1-cd62-4752-a621-2c0296d21db1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076778300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1076778300
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2743014574
Short name T1064
Test name
Test status
Simulation time 56220674 ps
CPU time 1.77 seconds
Started Aug 11 04:57:45 PM PDT 24
Finished Aug 11 04:57:47 PM PDT 24
Peak memory 215140 kb
Host smart-31def8ec-0217-4a29-b9a2-936a1b45d80a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743014574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2743014574
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4114782201
Short name T69
Test name
Test status
Simulation time 186684670 ps
CPU time 2.98 seconds
Started Aug 11 04:57:43 PM PDT 24
Finished Aug 11 04:57:46 PM PDT 24
Peak memory 215220 kb
Host smart-d44c442f-c822-4470-8759-0aca48a059f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114782201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.4
114782201
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.121481596
Short name T1128
Test name
Test status
Simulation time 614615131 ps
CPU time 8.75 seconds
Started Aug 11 04:57:43 PM PDT 24
Finished Aug 11 04:57:52 PM PDT 24
Peak memory 215024 kb
Host smart-7659c565-cc08-4aed-b2ca-972e83701590
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121481596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.121481596
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.602029954
Short name T1028
Test name
Test status
Simulation time 17372841 ps
CPU time 0.74 seconds
Started Aug 11 04:58:00 PM PDT 24
Finished Aug 11 04:58:01 PM PDT 24
Peak memory 203860 kb
Host smart-132e56db-44d1-4b5d-ad84-556bcfbe92b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602029954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.602029954
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.949040788
Short name T1022
Test name
Test status
Simulation time 34528476 ps
CPU time 0.79 seconds
Started Aug 11 04:58:03 PM PDT 24
Finished Aug 11 04:58:04 PM PDT 24
Peak memory 203488 kb
Host smart-a9da5ad2-4647-42ce-b561-94e12a35be17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949040788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.949040788
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4149459467
Short name T1045
Test name
Test status
Simulation time 34087844 ps
CPU time 0.77 seconds
Started Aug 11 04:58:03 PM PDT 24
Finished Aug 11 04:58:05 PM PDT 24
Peak memory 203512 kb
Host smart-4273c13e-9d2b-4f44-a410-f8ddbf948136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149459467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
4149459467
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3492618633
Short name T1065
Test name
Test status
Simulation time 29217358 ps
CPU time 0.77 seconds
Started Aug 11 04:58:06 PM PDT 24
Finished Aug 11 04:58:07 PM PDT 24
Peak memory 203464 kb
Host smart-6e8b7a78-0c0c-45d0-bd77-25f769df7a76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492618633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3492618633
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3961881338
Short name T1111
Test name
Test status
Simulation time 45700185 ps
CPU time 0.91 seconds
Started Aug 11 04:58:04 PM PDT 24
Finished Aug 11 04:58:05 PM PDT 24
Peak memory 203828 kb
Host smart-7a15009e-029f-4e9a-9fa1-e3cf3585673d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961881338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3961881338
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.678211731
Short name T1031
Test name
Test status
Simulation time 42453075 ps
CPU time 0.73 seconds
Started Aug 11 04:58:03 PM PDT 24
Finished Aug 11 04:58:04 PM PDT 24
Peak memory 203528 kb
Host smart-e0faa225-138b-4cb4-833a-a592c705e5e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678211731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.678211731
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4199634103
Short name T1016
Test name
Test status
Simulation time 11448722 ps
CPU time 0.76 seconds
Started Aug 11 04:58:02 PM PDT 24
Finished Aug 11 04:58:02 PM PDT 24
Peak memory 203512 kb
Host smart-5f4b07cf-85cd-4e75-a67b-4127779d1261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199634103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
4199634103
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.267622276
Short name T1063
Test name
Test status
Simulation time 39269159 ps
CPU time 0.75 seconds
Started Aug 11 04:58:03 PM PDT 24
Finished Aug 11 04:58:04 PM PDT 24
Peak memory 203504 kb
Host smart-80e33fbe-b3ab-4b66-9634-289da2b2d127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267622276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.267622276
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1252616389
Short name T1017
Test name
Test status
Simulation time 12111766 ps
CPU time 0.75 seconds
Started Aug 11 04:58:01 PM PDT 24
Finished Aug 11 04:58:02 PM PDT 24
Peak memory 203808 kb
Host smart-747d3f46-914d-4eef-9500-eecafe204b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252616389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1252616389
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2439768861
Short name T1054
Test name
Test status
Simulation time 15703511 ps
CPU time 0.79 seconds
Started Aug 11 04:58:00 PM PDT 24
Finished Aug 11 04:58:01 PM PDT 24
Peak memory 203508 kb
Host smart-eafd93b7-201c-4830-9ecf-7a981e7b539d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439768861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2439768861
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1707795531
Short name T1075
Test name
Test status
Simulation time 880015078 ps
CPU time 15.26 seconds
Started Aug 11 04:57:51 PM PDT 24
Finished Aug 11 04:58:07 PM PDT 24
Peak memory 206820 kb
Host smart-f07162b0-70e4-4216-88a0-e3df9fe3e4c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707795531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1707795531
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1306104335
Short name T1066
Test name
Test status
Simulation time 1946334381 ps
CPU time 22.09 seconds
Started Aug 11 04:57:50 PM PDT 24
Finished Aug 11 04:58:12 PM PDT 24
Peak memory 206784 kb
Host smart-af5b1673-76a2-4624-866c-111f90ebbe75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306104335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1306104335
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2889059744
Short name T78
Test name
Test status
Simulation time 14499917 ps
CPU time 0.98 seconds
Started Aug 11 04:57:48 PM PDT 24
Finished Aug 11 04:57:49 PM PDT 24
Peak memory 206572 kb
Host smart-18aca461-4dc6-489f-b8d0-e7d131a915ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889059744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2889059744
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.260611759
Short name T1079
Test name
Test status
Simulation time 352042224 ps
CPU time 2.86 seconds
Started Aug 11 04:57:47 PM PDT 24
Finished Aug 11 04:57:50 PM PDT 24
Peak memory 217836 kb
Host smart-f19284de-2769-4f35-ace9-8c10b29f8d45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260611759 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.260611759
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2788159090
Short name T144
Test name
Test status
Simulation time 103133912 ps
CPU time 2.8 seconds
Started Aug 11 04:57:49 PM PDT 24
Finished Aug 11 04:57:52 PM PDT 24
Peak memory 215052 kb
Host smart-b96e4e11-379b-488e-ae21-335d10c9e0e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788159090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
788159090
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.317690822
Short name T1055
Test name
Test status
Simulation time 92182696 ps
CPU time 0.76 seconds
Started Aug 11 04:57:42 PM PDT 24
Finished Aug 11 04:57:43 PM PDT 24
Peak memory 203568 kb
Host smart-0d3169bb-58e8-4d7b-899b-e7ff56bc2c68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317690822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.317690822
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3720365805
Short name T115
Test name
Test status
Simulation time 119868910 ps
CPU time 1.34 seconds
Started Aug 11 04:57:49 PM PDT 24
Finished Aug 11 04:57:50 PM PDT 24
Peak memory 215056 kb
Host smart-be3bf0da-5a2f-4cdd-82c7-d180ca67e9fa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720365805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3720365805
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4287209673
Short name T1050
Test name
Test status
Simulation time 12894113 ps
CPU time 0.66 seconds
Started Aug 11 04:57:50 PM PDT 24
Finished Aug 11 04:57:51 PM PDT 24
Peak memory 203804 kb
Host smart-d00dcf9f-aca5-48af-95db-bd791707fe8b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287209673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4287209673
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.673713577
Short name T1110
Test name
Test status
Simulation time 62576487 ps
CPU time 1.59 seconds
Started Aug 11 04:57:51 PM PDT 24
Finished Aug 11 04:57:53 PM PDT 24
Peak memory 215032 kb
Host smart-6b451b7b-237d-46e5-9f2b-54c063e59e33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673713577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.673713577
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2722789190
Short name T1076
Test name
Test status
Simulation time 36100296 ps
CPU time 2.24 seconds
Started Aug 11 04:57:44 PM PDT 24
Finished Aug 11 04:57:47 PM PDT 24
Peak memory 215148 kb
Host smart-93c0a4dc-40ce-469d-92d7-678e801d1784
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722789190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
722789190
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3620096276
Short name T95
Test name
Test status
Simulation time 794364421 ps
CPU time 7.6 seconds
Started Aug 11 04:57:48 PM PDT 24
Finished Aug 11 04:57:55 PM PDT 24
Peak memory 215088 kb
Host smart-426052b3-6b68-4cd8-9a06-179108a55be1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620096276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3620096276
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3209864981
Short name T1051
Test name
Test status
Simulation time 14166871 ps
CPU time 0.81 seconds
Started Aug 11 04:58:01 PM PDT 24
Finished Aug 11 04:58:02 PM PDT 24
Peak memory 203520 kb
Host smart-7f2451a0-464e-42de-bc13-98f733c79838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209864981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3209864981
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4168222396
Short name T1025
Test name
Test status
Simulation time 34631359 ps
CPU time 0.75 seconds
Started Aug 11 04:58:04 PM PDT 24
Finished Aug 11 04:58:04 PM PDT 24
Peak memory 203524 kb
Host smart-27edd756-ec57-49df-9b6e-88d72402d601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168222396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
4168222396
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2804025625
Short name T1038
Test name
Test status
Simulation time 13789052 ps
CPU time 0.73 seconds
Started Aug 11 04:58:04 PM PDT 24
Finished Aug 11 04:58:05 PM PDT 24
Peak memory 203520 kb
Host smart-90690148-4357-41e5-8ae0-3b309663332a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804025625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2804025625
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2146778599
Short name T1046
Test name
Test status
Simulation time 14664474 ps
CPU time 0.72 seconds
Started Aug 11 04:58:08 PM PDT 24
Finished Aug 11 04:58:09 PM PDT 24
Peak memory 203508 kb
Host smart-cf89cb63-493d-4e06-ae1b-2130ab883053
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146778599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2146778599
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4073941735
Short name T1067
Test name
Test status
Simulation time 13205756 ps
CPU time 0.79 seconds
Started Aug 11 04:58:07 PM PDT 24
Finished Aug 11 04:58:08 PM PDT 24
Peak memory 203500 kb
Host smart-4e677b38-b715-46aa-a50a-d9ef9aa776e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073941735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
4073941735
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3931004213
Short name T1071
Test name
Test status
Simulation time 31965510 ps
CPU time 0.78 seconds
Started Aug 11 04:58:09 PM PDT 24
Finished Aug 11 04:58:10 PM PDT 24
Peak memory 203544 kb
Host smart-2ea881d9-7cf5-42fa-a9da-61c2da12b1a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931004213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3931004213
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2562820886
Short name T1059
Test name
Test status
Simulation time 14618300 ps
CPU time 0.75 seconds
Started Aug 11 04:58:08 PM PDT 24
Finished Aug 11 04:58:09 PM PDT 24
Peak memory 203540 kb
Host smart-0bb4166f-90b8-4cf5-90ef-dfdfb07dc846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562820886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2562820886
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1662135803
Short name T1021
Test name
Test status
Simulation time 22161324 ps
CPU time 0.74 seconds
Started Aug 11 04:58:08 PM PDT 24
Finished Aug 11 04:58:08 PM PDT 24
Peak memory 203500 kb
Host smart-f873694e-90dd-4717-8466-aa1d9a8911bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662135803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1662135803
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3927174282
Short name T1023
Test name
Test status
Simulation time 15523355 ps
CPU time 0.78 seconds
Started Aug 11 04:58:08 PM PDT 24
Finished Aug 11 04:58:09 PM PDT 24
Peak memory 203584 kb
Host smart-2bab49a6-f81e-431e-9f24-39236a69d411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927174282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3927174282
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2174189412
Short name T1020
Test name
Test status
Simulation time 145068034 ps
CPU time 0.77 seconds
Started Aug 11 04:58:09 PM PDT 24
Finished Aug 11 04:58:10 PM PDT 24
Peak memory 203532 kb
Host smart-692eaf1e-c007-46aa-8c3d-d7c0d19180d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174189412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2174189412
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2400414348
Short name T148
Test name
Test status
Simulation time 104766210 ps
CPU time 2.78 seconds
Started Aug 11 04:57:53 PM PDT 24
Finished Aug 11 04:57:56 PM PDT 24
Peak memory 217620 kb
Host smart-b101e2e6-4fd0-4cc0-9f6b-a50cbe82aad4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400414348 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2400414348
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2254252158
Short name T1103
Test name
Test status
Simulation time 89832923 ps
CPU time 1.34 seconds
Started Aug 11 04:57:50 PM PDT 24
Finished Aug 11 04:57:51 PM PDT 24
Peak memory 206788 kb
Host smart-a9dfcf94-050a-4f2a-87d6-3ea709ff454b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254252158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
254252158
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1008811589
Short name T1049
Test name
Test status
Simulation time 55483479 ps
CPU time 0.76 seconds
Started Aug 11 04:57:49 PM PDT 24
Finished Aug 11 04:57:50 PM PDT 24
Peak memory 203872 kb
Host smart-91f4c3e5-722d-4010-82f8-38c6b39f49aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008811589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
008811589
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1094060558
Short name T1024
Test name
Test status
Simulation time 150400051 ps
CPU time 4.19 seconds
Started Aug 11 04:57:51 PM PDT 24
Finished Aug 11 04:57:55 PM PDT 24
Peak memory 214992 kb
Host smart-53977897-5e1b-4ecc-b868-32c6c0f036ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094060558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1094060558
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.915430918
Short name T1073
Test name
Test status
Simulation time 559717833 ps
CPU time 3.95 seconds
Started Aug 11 04:57:54 PM PDT 24
Finished Aug 11 04:57:58 PM PDT 24
Peak memory 215212 kb
Host smart-f24c0940-c21f-4f7f-9992-aa75742d208c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915430918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.915430918
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3671158673
Short name T107
Test name
Test status
Simulation time 331292173 ps
CPU time 19.7 seconds
Started Aug 11 04:57:51 PM PDT 24
Finished Aug 11 04:58:11 PM PDT 24
Peak memory 215008 kb
Host smart-776e8d86-0403-4366-8c39-5d0b537766da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671158673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3671158673
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.466663117
Short name T1086
Test name
Test status
Simulation time 198705150 ps
CPU time 3.46 seconds
Started Aug 11 04:57:50 PM PDT 24
Finished Aug 11 04:57:53 PM PDT 24
Peak memory 218064 kb
Host smart-ec245191-a52e-4484-b6c8-22f7f6daa9b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466663117 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.466663117
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1052653192
Short name T1127
Test name
Test status
Simulation time 41772606 ps
CPU time 2.81 seconds
Started Aug 11 04:57:48 PM PDT 24
Finished Aug 11 04:57:51 PM PDT 24
Peak memory 215024 kb
Host smart-991cd861-887b-432b-b546-d2c8cdd6daf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052653192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
052653192
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1750255827
Short name T1131
Test name
Test status
Simulation time 16833168 ps
CPU time 0.77 seconds
Started Aug 11 04:57:48 PM PDT 24
Finished Aug 11 04:57:49 PM PDT 24
Peak memory 203820 kb
Host smart-bc97e3c6-8a73-4793-a44b-eff66c1f6651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750255827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
750255827
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.533937650
Short name T1057
Test name
Test status
Simulation time 170923899 ps
CPU time 1.79 seconds
Started Aug 11 04:57:50 PM PDT 24
Finished Aug 11 04:57:52 PM PDT 24
Peak memory 215072 kb
Host smart-725e3222-ee26-4683-b288-4ba282e1e363
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533937650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.533937650
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4076677936
Short name T102
Test name
Test status
Simulation time 749814660 ps
CPU time 3.79 seconds
Started Aug 11 04:57:48 PM PDT 24
Finished Aug 11 04:57:52 PM PDT 24
Peak memory 215236 kb
Host smart-4e1dd0ad-0ca9-4ead-acc3-a624a462e521
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076677936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
076677936
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3532041112
Short name T1060
Test name
Test status
Simulation time 53609641 ps
CPU time 1.76 seconds
Started Aug 11 04:57:49 PM PDT 24
Finished Aug 11 04:57:51 PM PDT 24
Peak memory 216104 kb
Host smart-5b238d9a-c089-4d93-99dc-6d5262c0dc45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532041112 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3532041112
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3674791831
Short name T1048
Test name
Test status
Simulation time 53164298 ps
CPU time 1.81 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:58 PM PDT 24
Peak memory 206800 kb
Host smart-330dad1a-e19c-4e5b-95f4-df35e2b17b41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674791831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
674791831
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.586776970
Short name T1108
Test name
Test status
Simulation time 51909367 ps
CPU time 0.73 seconds
Started Aug 11 04:57:54 PM PDT 24
Finished Aug 11 04:57:55 PM PDT 24
Peak memory 203820 kb
Host smart-663882b0-fcab-4d34-87a3-15968157a244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586776970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.586776970
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.446732241
Short name T1114
Test name
Test status
Simulation time 228056605 ps
CPU time 4.45 seconds
Started Aug 11 04:57:54 PM PDT 24
Finished Aug 11 04:57:58 PM PDT 24
Peak memory 215052 kb
Host smart-11380649-ca21-4a0b-86b9-0adef9b2ddc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446732241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.446732241
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2932495093
Short name T105
Test name
Test status
Simulation time 138991822 ps
CPU time 2.24 seconds
Started Aug 11 04:57:48 PM PDT 24
Finished Aug 11 04:57:50 PM PDT 24
Peak memory 215132 kb
Host smart-35fc156e-fb02-4f75-893d-ff7b83e6c785
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932495093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
932495093
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1044787668
Short name T94
Test name
Test status
Simulation time 118364167 ps
CPU time 7.24 seconds
Started Aug 11 04:57:48 PM PDT 24
Finished Aug 11 04:57:55 PM PDT 24
Peak memory 214980 kb
Host smart-1c38e145-e334-4d9b-80bd-f92df9d8deb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044787668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1044787668
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4212566124
Short name T1033
Test name
Test status
Simulation time 341738099 ps
CPU time 2.55 seconds
Started Aug 11 04:57:50 PM PDT 24
Finished Aug 11 04:57:52 PM PDT 24
Peak memory 217912 kb
Host smart-8a368bfe-99ff-476e-9d3b-0de6432fadd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212566124 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.4212566124
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3360251455
Short name T145
Test name
Test status
Simulation time 287949067 ps
CPU time 1.54 seconds
Started Aug 11 04:57:50 PM PDT 24
Finished Aug 11 04:57:52 PM PDT 24
Peak memory 206788 kb
Host smart-72f58d8b-48fe-41f1-bf17-8d2a65d60faf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360251455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
360251455
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2913286431
Short name T1097
Test name
Test status
Simulation time 14041883 ps
CPU time 0.74 seconds
Started Aug 11 04:57:51 PM PDT 24
Finished Aug 11 04:57:52 PM PDT 24
Peak memory 203540 kb
Host smart-a554e58f-5426-43b6-a099-7b6b22d0681b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913286431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
913286431
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2976687579
Short name T1093
Test name
Test status
Simulation time 102084215 ps
CPU time 1.88 seconds
Started Aug 11 04:57:50 PM PDT 24
Finished Aug 11 04:57:52 PM PDT 24
Peak memory 214960 kb
Host smart-c3136a8e-04b1-43d8-bdb1-1cd078397a14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976687579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2976687579
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.603744667
Short name T1107
Test name
Test status
Simulation time 82332666 ps
CPU time 5.11 seconds
Started Aug 11 04:57:50 PM PDT 24
Finished Aug 11 04:57:55 PM PDT 24
Peak memory 215080 kb
Host smart-5688bcd8-f532-44ba-a4a8-1d6b3826ac06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603744667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.603744667
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1126974147
Short name T92
Test name
Test status
Simulation time 1180785272 ps
CPU time 8.22 seconds
Started Aug 11 04:57:51 PM PDT 24
Finished Aug 11 04:57:59 PM PDT 24
Peak memory 215064 kb
Host smart-faea0712-7fec-409f-995f-a7c54507118f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126974147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1126974147
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.187481163
Short name T1125
Test name
Test status
Simulation time 84271543 ps
CPU time 2.76 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:58 PM PDT 24
Peak memory 217144 kb
Host smart-05ef3eda-2576-4ab0-b647-c7f5ad6f6018
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187481163 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.187481163
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.677000895
Short name T1105
Test name
Test status
Simulation time 43291489 ps
CPU time 1.39 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:57 PM PDT 24
Peak memory 215096 kb
Host smart-82181344-b92d-40c3-9844-9ac6aa68ff6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677000895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.677000895
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1803610345
Short name T1101
Test name
Test status
Simulation time 13181333 ps
CPU time 0.78 seconds
Started Aug 11 04:57:54 PM PDT 24
Finished Aug 11 04:57:55 PM PDT 24
Peak memory 203504 kb
Host smart-134d3167-993e-4a69-bfce-3ef696457000
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803610345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
803610345
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1648734368
Short name T1047
Test name
Test status
Simulation time 154975698 ps
CPU time 2.6 seconds
Started Aug 11 04:57:56 PM PDT 24
Finished Aug 11 04:57:59 PM PDT 24
Peak memory 214960 kb
Host smart-3a8d7e26-6687-4b56-8483-25b425e893f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648734368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1648734368
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1066567374
Short name T1070
Test name
Test status
Simulation time 483193072 ps
CPU time 2.49 seconds
Started Aug 11 04:57:49 PM PDT 24
Finished Aug 11 04:57:52 PM PDT 24
Peak memory 216136 kb
Host smart-4ba6ec26-06f9-4c19-83cb-6f8ea830e2f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066567374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
066567374
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4129177101
Short name T1034
Test name
Test status
Simulation time 269756320 ps
CPU time 8.09 seconds
Started Aug 11 04:57:49 PM PDT 24
Finished Aug 11 04:57:57 PM PDT 24
Peak memory 223148 kb
Host smart-66b26b96-5843-4f74-b0e9-64fc931f391c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129177101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.4129177101
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1059427823
Short name T65
Test name
Test status
Simulation time 21281676 ps
CPU time 0.75 seconds
Started Aug 11 05:18:04 PM PDT 24
Finished Aug 11 05:18:05 PM PDT 24
Peak memory 206044 kb
Host smart-c5bd04d0-9bde-417c-af26-e17f35d05780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059427823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
059427823
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.4090636163
Short name T716
Test name
Test status
Simulation time 2456540161 ps
CPU time 3.46 seconds
Started Aug 11 05:18:03 PM PDT 24
Finished Aug 11 05:18:07 PM PDT 24
Peak memory 224768 kb
Host smart-ea85aae6-4ee5-4f72-a4d3-d12c61ba1cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090636163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.4090636163
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2517438736
Short name T373
Test name
Test status
Simulation time 157012102 ps
CPU time 0.79 seconds
Started Aug 11 05:17:59 PM PDT 24
Finished Aug 11 05:17:59 PM PDT 24
Peak memory 206812 kb
Host smart-1f0b1d51-48da-4365-9478-f18d07390a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517438736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2517438736
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.125992613
Short name T744
Test name
Test status
Simulation time 2578993658 ps
CPU time 12.38 seconds
Started Aug 11 05:18:06 PM PDT 24
Finished Aug 11 05:18:19 PM PDT 24
Peak memory 234320 kb
Host smart-e9cdeea0-9253-4c90-9239-fb0ecbbe4c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125992613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.125992613
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3105360984
Short name T618
Test name
Test status
Simulation time 928431374 ps
CPU time 6.74 seconds
Started Aug 11 05:18:05 PM PDT 24
Finished Aug 11 05:18:12 PM PDT 24
Peak memory 224904 kb
Host smart-2b7da395-4531-4583-9c21-b0f30ecad005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105360984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3105360984
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.4131216385
Short name T915
Test name
Test status
Simulation time 5805484735 ps
CPU time 84.84 seconds
Started Aug 11 05:18:11 PM PDT 24
Finished Aug 11 05:19:36 PM PDT 24
Peak memory 265940 kb
Host smart-cf19c598-8547-4af8-8dd7-4d8d70cde654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131216385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.4131216385
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1514670594
Short name T854
Test name
Test status
Simulation time 3617988419 ps
CPU time 7.82 seconds
Started Aug 11 05:18:11 PM PDT 24
Finished Aug 11 05:18:19 PM PDT 24
Peak memory 233164 kb
Host smart-2a951570-7523-4485-90ce-3742f55dcb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514670594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1514670594
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.776137188
Short name T680
Test name
Test status
Simulation time 9704829244 ps
CPU time 34.97 seconds
Started Aug 11 05:18:04 PM PDT 24
Finished Aug 11 05:18:39 PM PDT 24
Peak memory 241184 kb
Host smart-f1267f4e-e472-4ad1-a1e8-26ea326ec0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776137188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.776137188
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3995237458
Short name T807
Test name
Test status
Simulation time 4145349862 ps
CPU time 8.18 seconds
Started Aug 11 05:18:03 PM PDT 24
Finished Aug 11 05:18:12 PM PDT 24
Peak memory 233032 kb
Host smart-97ee06db-86a7-47c2-9c13-9233e5de6a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995237458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3995237458
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.179656678
Short name T569
Test name
Test status
Simulation time 696042913 ps
CPU time 8.68 seconds
Started Aug 11 05:17:59 PM PDT 24
Finished Aug 11 05:18:08 PM PDT 24
Peak memory 224764 kb
Host smart-dfd8d4b1-2c5d-45f5-b6df-e42b78c3e462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179656678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.179656678
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.4103369186
Short name T1008
Test name
Test status
Simulation time 3608541385 ps
CPU time 10.95 seconds
Started Aug 11 05:18:04 PM PDT 24
Finished Aug 11 05:18:15 PM PDT 24
Peak memory 222476 kb
Host smart-2674a94a-8bec-4c61-a6b6-e5d50f7f7700
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4103369186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.4103369186
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.514309382
Short name T271
Test name
Test status
Simulation time 41381989103 ps
CPU time 223.56 seconds
Started Aug 11 05:18:11 PM PDT 24
Finished Aug 11 05:21:54 PM PDT 24
Peak memory 257376 kb
Host smart-0a982e02-87e0-4914-b78c-c5423311fb55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514309382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.514309382
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1230583257
Short name T673
Test name
Test status
Simulation time 8425653902 ps
CPU time 25.19 seconds
Started Aug 11 05:17:58 PM PDT 24
Finished Aug 11 05:18:23 PM PDT 24
Peak memory 216560 kb
Host smart-6d8cc5bf-9c03-480f-82c9-9f28ef41de0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230583257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1230583257
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.974779106
Short name T533
Test name
Test status
Simulation time 1103554242 ps
CPU time 1.73 seconds
Started Aug 11 05:17:55 PM PDT 24
Finished Aug 11 05:17:57 PM PDT 24
Peak memory 208176 kb
Host smart-0af7ef58-7eea-42b7-be52-24f0144d40f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974779106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.974779106
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.244232851
Short name T769
Test name
Test status
Simulation time 233186713 ps
CPU time 8.36 seconds
Started Aug 11 05:17:56 PM PDT 24
Finished Aug 11 05:18:05 PM PDT 24
Peak memory 216532 kb
Host smart-a7b56e15-a1dd-4b8d-8fe6-4006bed25d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244232851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.244232851
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3507197113
Short name T606
Test name
Test status
Simulation time 142920293 ps
CPU time 0.93 seconds
Started Aug 11 05:17:58 PM PDT 24
Finished Aug 11 05:17:59 PM PDT 24
Peak memory 206332 kb
Host smart-261552b8-c377-4e37-84d4-4d8e22166923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507197113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3507197113
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3613578415
Short name T436
Test name
Test status
Simulation time 2713767272 ps
CPU time 7.1 seconds
Started Aug 11 05:18:04 PM PDT 24
Finished Aug 11 05:18:11 PM PDT 24
Peak memory 234816 kb
Host smart-2aefccbb-c09d-4615-bf96-721768da8258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613578415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3613578415
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2044604456
Short name T492
Test name
Test status
Simulation time 11895388 ps
CPU time 0.71 seconds
Started Aug 11 05:18:25 PM PDT 24
Finished Aug 11 05:18:26 PM PDT 24
Peak memory 206128 kb
Host smart-ca1b946a-3bf7-498c-bceb-ceea38377af4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044604456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
044604456
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3466744768
Short name T360
Test name
Test status
Simulation time 363600768 ps
CPU time 5.57 seconds
Started Aug 11 05:18:11 PM PDT 24
Finished Aug 11 05:18:17 PM PDT 24
Peak memory 224756 kb
Host smart-47ef2102-614f-469f-9c2c-7d8e6507a461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466744768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3466744768
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3875935368
Short name T902
Test name
Test status
Simulation time 14274715 ps
CPU time 0.82 seconds
Started Aug 11 05:18:05 PM PDT 24
Finished Aug 11 05:18:06 PM PDT 24
Peak memory 206952 kb
Host smart-74a862a3-6900-4d42-986c-114b2b3a6fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875935368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3875935368
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3241454027
Short name T938
Test name
Test status
Simulation time 40587626842 ps
CPU time 88.88 seconds
Started Aug 11 05:18:17 PM PDT 24
Finished Aug 11 05:19:46 PM PDT 24
Peak memory 239376 kb
Host smart-b11c1b53-e5d3-44f0-a39f-f7e4558d6b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241454027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3241454027
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3392464028
Short name T631
Test name
Test status
Simulation time 5348883261 ps
CPU time 17.67 seconds
Started Aug 11 05:18:17 PM PDT 24
Finished Aug 11 05:18:35 PM PDT 24
Peak memory 224888 kb
Host smart-a44c508d-282c-4cd8-b1e7-bf35cdd8a6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392464028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3392464028
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3118430902
Short name T363
Test name
Test status
Simulation time 4652991086 ps
CPU time 83.1 seconds
Started Aug 11 05:18:17 PM PDT 24
Finished Aug 11 05:19:40 PM PDT 24
Peak memory 256992 kb
Host smart-2cad3708-33cf-4b4e-b012-7215a9797d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118430902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3118430902
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2776341615
Short name T124
Test name
Test status
Simulation time 3011742812 ps
CPU time 12.65 seconds
Started Aug 11 05:18:10 PM PDT 24
Finished Aug 11 05:18:23 PM PDT 24
Peak memory 234444 kb
Host smart-b2de263b-c252-475a-a705-6e3dae52c3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776341615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2776341615
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2251721464
Short name T203
Test name
Test status
Simulation time 62432616968 ps
CPU time 417.61 seconds
Started Aug 11 05:18:10 PM PDT 24
Finished Aug 11 05:25:08 PM PDT 24
Peak memory 257672 kb
Host smart-2a42c5c0-11ba-4787-ac49-25003f949e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251721464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2251721464
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2853427901
Short name T532
Test name
Test status
Simulation time 2108452820 ps
CPU time 10.94 seconds
Started Aug 11 05:18:12 PM PDT 24
Finished Aug 11 05:18:23 PM PDT 24
Peak memory 233032 kb
Host smart-9c6b99bf-af90-43f0-9abf-2b96187dcb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853427901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2853427901
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.234594102
Short name T610
Test name
Test status
Simulation time 859031183 ps
CPU time 3.03 seconds
Started Aug 11 05:18:11 PM PDT 24
Finished Aug 11 05:18:14 PM PDT 24
Peak memory 224804 kb
Host smart-f87ada3c-b495-4443-bc15-cf8105a9d6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234594102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.234594102
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1489623685
Short name T853
Test name
Test status
Simulation time 5811578908 ps
CPU time 7.26 seconds
Started Aug 11 05:18:09 PM PDT 24
Finished Aug 11 05:18:17 PM PDT 24
Peak memory 233060 kb
Host smart-b77af00e-f553-4c4f-9fa7-055f535eb10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489623685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1489623685
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4015837757
Short name T371
Test name
Test status
Simulation time 6672705272 ps
CPU time 6.4 seconds
Started Aug 11 05:18:10 PM PDT 24
Finished Aug 11 05:18:17 PM PDT 24
Peak memory 224920 kb
Host smart-d268b346-25d5-46e9-a455-38e6654ac079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015837757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4015837757
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1871909354
Short name T528
Test name
Test status
Simulation time 2764182684 ps
CPU time 6.7 seconds
Started Aug 11 05:18:11 PM PDT 24
Finished Aug 11 05:18:18 PM PDT 24
Peak memory 220956 kb
Host smart-aa13dafa-8d26-4667-bbeb-81bc14fa5d3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1871909354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1871909354
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2234574067
Short name T73
Test name
Test status
Simulation time 181943773 ps
CPU time 1.08 seconds
Started Aug 11 05:18:16 PM PDT 24
Finished Aug 11 05:18:18 PM PDT 24
Peak memory 236736 kb
Host smart-d78f4920-2f1e-4eba-a0db-2b8ac93f6210
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234574067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2234574067
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.4211975032
Short name T153
Test name
Test status
Simulation time 191228022687 ps
CPU time 974.66 seconds
Started Aug 11 05:18:17 PM PDT 24
Finished Aug 11 05:34:32 PM PDT 24
Peak memory 288452 kb
Host smart-082c6704-1800-407e-bf04-dbeb444468f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211975032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.4211975032
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3833942199
Short name T724
Test name
Test status
Simulation time 807423008 ps
CPU time 11.31 seconds
Started Aug 11 05:18:04 PM PDT 24
Finished Aug 11 05:18:16 PM PDT 24
Peak memory 216476 kb
Host smart-c02df09a-390f-4fd0-9c7e-53ce6f1c28e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833942199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3833942199
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1343850325
Short name T353
Test name
Test status
Simulation time 14984687649 ps
CPU time 14.1 seconds
Started Aug 11 05:18:05 PM PDT 24
Finished Aug 11 05:18:19 PM PDT 24
Peak memory 216624 kb
Host smart-2d5fb725-9f5e-470f-afef-3345175cfbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343850325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1343850325
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1051928282
Short name T892
Test name
Test status
Simulation time 383305826 ps
CPU time 1.12 seconds
Started Aug 11 05:18:10 PM PDT 24
Finished Aug 11 05:18:12 PM PDT 24
Peak memory 207816 kb
Host smart-7fe92457-10df-4a58-b741-96dd0ec4fe20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051928282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1051928282
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1804288157
Short name T423
Test name
Test status
Simulation time 57418458 ps
CPU time 0.74 seconds
Started Aug 11 05:18:04 PM PDT 24
Finished Aug 11 05:18:05 PM PDT 24
Peak memory 206272 kb
Host smart-c9aa77a8-ac57-4b88-9b70-16450f8b6cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804288157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1804288157
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1409050283
Short name T565
Test name
Test status
Simulation time 8251847548 ps
CPU time 27.95 seconds
Started Aug 11 05:18:11 PM PDT 24
Finished Aug 11 05:18:39 PM PDT 24
Peak memory 251960 kb
Host smart-f49c0c8c-d60d-4a0a-8a1b-1afa43f79d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409050283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1409050283
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.194402904
Short name T816
Test name
Test status
Simulation time 150141709 ps
CPU time 0.69 seconds
Started Aug 11 05:19:41 PM PDT 24
Finished Aug 11 05:19:42 PM PDT 24
Peak memory 205720 kb
Host smart-607d9e6c-2cee-4077-9385-4e12e10a003f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194402904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.194402904
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1293593622
Short name T401
Test name
Test status
Simulation time 16057147507 ps
CPU time 7.43 seconds
Started Aug 11 05:19:37 PM PDT 24
Finished Aug 11 05:19:44 PM PDT 24
Peak memory 232960 kb
Host smart-fc2c1f54-92d5-4b9d-9317-0c6e9d83bcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293593622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1293593622
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.218253942
Short name T586
Test name
Test status
Simulation time 95692388 ps
CPU time 0.79 seconds
Started Aug 11 05:19:29 PM PDT 24
Finished Aug 11 05:19:29 PM PDT 24
Peak memory 207208 kb
Host smart-a9015bc0-0e23-4bc2-a48f-778f6de61687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218253942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.218253942
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2962418091
Short name T207
Test name
Test status
Simulation time 3622004590 ps
CPU time 48.46 seconds
Started Aug 11 05:19:41 PM PDT 24
Finished Aug 11 05:20:29 PM PDT 24
Peak memory 256124 kb
Host smart-5e323be0-ce72-4c5d-83d9-2a2df072f197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962418091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2962418091
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1532941493
Short name T968
Test name
Test status
Simulation time 2118936260 ps
CPU time 49.85 seconds
Started Aug 11 05:19:43 PM PDT 24
Finished Aug 11 05:20:33 PM PDT 24
Peak memory 256956 kb
Host smart-b8d0e7d9-3545-474e-bbb4-ceb20046e269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532941493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1532941493
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.4133800948
Short name T750
Test name
Test status
Simulation time 15090969069 ps
CPU time 119.89 seconds
Started Aug 11 05:19:36 PM PDT 24
Finished Aug 11 05:21:36 PM PDT 24
Peak memory 252788 kb
Host smart-34ba8cd9-4ec1-45ae-8b77-d448065dff97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133800948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.4133800948
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3542168293
Short name T640
Test name
Test status
Simulation time 870307108 ps
CPU time 4.62 seconds
Started Aug 11 05:19:36 PM PDT 24
Finished Aug 11 05:19:41 PM PDT 24
Peak memory 224676 kb
Host smart-a9df9895-7518-4504-9639-3474dc6b7749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542168293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3542168293
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3708983232
Short name T995
Test name
Test status
Simulation time 9358463558 ps
CPU time 51.1 seconds
Started Aug 11 05:19:36 PM PDT 24
Finished Aug 11 05:20:27 PM PDT 24
Peak memory 233120 kb
Host smart-237fe017-325e-41ce-ac9a-9c0e1ac68c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708983232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3708983232
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2761193020
Short name T671
Test name
Test status
Simulation time 2941293113 ps
CPU time 10.52 seconds
Started Aug 11 05:19:36 PM PDT 24
Finished Aug 11 05:19:47 PM PDT 24
Peak memory 233052 kb
Host smart-5245c762-6e4b-4168-8447-4367246fc84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761193020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2761193020
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1004940198
Short name T741
Test name
Test status
Simulation time 39822886191 ps
CPU time 24.6 seconds
Started Aug 11 05:19:37 PM PDT 24
Finished Aug 11 05:20:02 PM PDT 24
Peak memory 233104 kb
Host smart-b6d723bd-55ab-4820-b8f1-01c007b75a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004940198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1004940198
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.990745363
Short name T1003
Test name
Test status
Simulation time 301114779 ps
CPU time 4.55 seconds
Started Aug 11 05:19:36 PM PDT 24
Finished Aug 11 05:19:41 PM PDT 24
Peak memory 223416 kb
Host smart-6184fdcd-4642-44a2-bfa1-728eb0433d0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=990745363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.990745363
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.4009987152
Short name T592
Test name
Test status
Simulation time 72051122 ps
CPU time 0.99 seconds
Started Aug 11 05:19:40 PM PDT 24
Finished Aug 11 05:19:41 PM PDT 24
Peak memory 207104 kb
Host smart-556da21f-6694-4ce7-af75-323e459b738f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009987152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.4009987152
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3669906360
Short name T976
Test name
Test status
Simulation time 7102984823 ps
CPU time 25.42 seconds
Started Aug 11 05:19:35 PM PDT 24
Finished Aug 11 05:20:01 PM PDT 24
Peak memory 220632 kb
Host smart-2facf5ce-b9b0-43a5-bc38-de2b34d18362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669906360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3669906360
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3369665637
Short name T356
Test name
Test status
Simulation time 825289277 ps
CPU time 3.01 seconds
Started Aug 11 05:19:36 PM PDT 24
Finished Aug 11 05:19:39 PM PDT 24
Peak memory 216612 kb
Host smart-629d41c9-f18e-435e-a9a4-e352bbc0a680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369665637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3369665637
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3287854465
Short name T977
Test name
Test status
Simulation time 57869773 ps
CPU time 0.95 seconds
Started Aug 11 05:19:36 PM PDT 24
Finished Aug 11 05:19:37 PM PDT 24
Peak memory 207304 kb
Host smart-a8392886-85df-434f-b04c-53e27c936230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287854465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3287854465
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3181760027
Short name T970
Test name
Test status
Simulation time 48338954 ps
CPU time 0.74 seconds
Started Aug 11 05:19:38 PM PDT 24
Finished Aug 11 05:19:39 PM PDT 24
Peak memory 206224 kb
Host smart-3c9fc233-488c-4e9b-bd0d-61f9a7e1e2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181760027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3181760027
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2940754704
Short name T240
Test name
Test status
Simulation time 6485071295 ps
CPU time 12.21 seconds
Started Aug 11 05:19:35 PM PDT 24
Finished Aug 11 05:19:48 PM PDT 24
Peak memory 224900 kb
Host smart-7931917c-87ac-40f9-82b0-af927fb385ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940754704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2940754704
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.960824948
Short name T679
Test name
Test status
Simulation time 27830153 ps
CPU time 0.68 seconds
Started Aug 11 05:19:47 PM PDT 24
Finished Aug 11 05:19:48 PM PDT 24
Peak memory 205184 kb
Host smart-1eb66160-6fe9-4dd5-b820-bfaa0b4cdb70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960824948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.960824948
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1340096624
Short name T245
Test name
Test status
Simulation time 2943470888 ps
CPU time 3.87 seconds
Started Aug 11 05:19:41 PM PDT 24
Finished Aug 11 05:19:45 PM PDT 24
Peak memory 232972 kb
Host smart-df4ee50b-d7b3-42c1-a5cc-13bb109efcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340096624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1340096624
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.155059620
Short name T522
Test name
Test status
Simulation time 22275656 ps
CPU time 0.74 seconds
Started Aug 11 05:19:44 PM PDT 24
Finished Aug 11 05:19:45 PM PDT 24
Peak memory 206228 kb
Host smart-48fae756-3527-4e7e-83c4-dd927245d9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155059620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.155059620
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1900873531
Short name T284
Test name
Test status
Simulation time 25888596559 ps
CPU time 117.18 seconds
Started Aug 11 05:19:50 PM PDT 24
Finished Aug 11 05:21:48 PM PDT 24
Peak memory 265240 kb
Host smart-8247625c-dbbe-4f01-b321-ebf32cc034e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900873531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1900873531
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1232780999
Short name T835
Test name
Test status
Simulation time 124094051417 ps
CPU time 248 seconds
Started Aug 11 05:19:48 PM PDT 24
Finished Aug 11 05:23:56 PM PDT 24
Peak memory 256884 kb
Host smart-0c4ca3dd-8222-484e-b96a-1389372ec3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232780999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1232780999
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1350663383
Short name T821
Test name
Test status
Simulation time 133969049 ps
CPU time 4.68 seconds
Started Aug 11 05:19:42 PM PDT 24
Finished Aug 11 05:19:47 PM PDT 24
Peak memory 225196 kb
Host smart-9dba0586-baf9-4ce0-b650-b4548296829e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350663383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1350663383
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.4000666601
Short name T1009
Test name
Test status
Simulation time 43878171045 ps
CPU time 85.36 seconds
Started Aug 11 05:19:49 PM PDT 24
Finished Aug 11 05:21:15 PM PDT 24
Peak memory 249280 kb
Host smart-33cdb3c8-2441-4dad-8b3d-5789209f0eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000666601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4000666601
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.845858226
Short name T460
Test name
Test status
Simulation time 2369781144 ps
CPU time 12.24 seconds
Started Aug 11 05:19:40 PM PDT 24
Finished Aug 11 05:19:52 PM PDT 24
Peak memory 233052 kb
Host smart-85a0d0e1-2d06-4b12-a88c-dd07ebaacb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845858226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.845858226
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2327560811
Short name T686
Test name
Test status
Simulation time 125734608 ps
CPU time 2.35 seconds
Started Aug 11 05:19:40 PM PDT 24
Finished Aug 11 05:19:42 PM PDT 24
Peak memory 232696 kb
Host smart-31088d3e-a23b-43aa-959c-e78ba76f7cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327560811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2327560811
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1884113780
Short name T966
Test name
Test status
Simulation time 543388360 ps
CPU time 3.47 seconds
Started Aug 11 05:19:48 PM PDT 24
Finished Aug 11 05:19:51 PM PDT 24
Peak memory 219208 kb
Host smart-b47dd848-acee-4189-a034-51366b03b121
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1884113780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1884113780
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1980096161
Short name T155
Test name
Test status
Simulation time 35701018051 ps
CPU time 230.59 seconds
Started Aug 11 05:19:50 PM PDT 24
Finished Aug 11 05:23:41 PM PDT 24
Peak memory 268432 kb
Host smart-6c75669e-6b10-43b5-9f41-ea939090abee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980096161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1980096161
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.4096083823
Short name T485
Test name
Test status
Simulation time 1843813367 ps
CPU time 26.91 seconds
Started Aug 11 05:19:49 PM PDT 24
Finished Aug 11 05:20:16 PM PDT 24
Peak memory 216584 kb
Host smart-e7676719-d9c2-4d57-92d8-23935b85d0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096083823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.4096083823
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3517961220
Short name T944
Test name
Test status
Simulation time 712378239 ps
CPU time 3.31 seconds
Started Aug 11 05:19:42 PM PDT 24
Finished Aug 11 05:19:45 PM PDT 24
Peak memory 216420 kb
Host smart-31bfb882-87f3-4bf4-9f21-0186ebcb5db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517961220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3517961220
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4166335486
Short name T378
Test name
Test status
Simulation time 70885709 ps
CPU time 1.36 seconds
Started Aug 11 05:19:41 PM PDT 24
Finished Aug 11 05:19:43 PM PDT 24
Peak memory 216580 kb
Host smart-ca278978-37cd-4d9e-92ce-bd60ac9655bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166335486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4166335486
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3398313412
Short name T805
Test name
Test status
Simulation time 113020257 ps
CPU time 0.78 seconds
Started Aug 11 05:19:41 PM PDT 24
Finished Aug 11 05:19:42 PM PDT 24
Peak memory 206136 kb
Host smart-e5ae901f-a952-45fb-b3eb-bb616d480213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398313412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3398313412
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1886398627
Short name T241
Test name
Test status
Simulation time 10267926699 ps
CPU time 19.82 seconds
Started Aug 11 05:19:49 PM PDT 24
Finished Aug 11 05:20:09 PM PDT 24
Peak memory 234764 kb
Host smart-af417f37-2b19-402e-9bf7-9c2042c33961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886398627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1886398627
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.511348244
Short name T458
Test name
Test status
Simulation time 13499884 ps
CPU time 0.69 seconds
Started Aug 11 05:19:53 PM PDT 24
Finished Aug 11 05:19:54 PM PDT 24
Peak memory 205244 kb
Host smart-2420607d-a45e-4fda-9783-23b806d1e6cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511348244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.511348244
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.770393546
Short name T720
Test name
Test status
Simulation time 344543287 ps
CPU time 4.99 seconds
Started Aug 11 05:19:55 PM PDT 24
Finished Aug 11 05:20:00 PM PDT 24
Peak memory 224860 kb
Host smart-7de7abd4-1087-4e3e-9011-b418db1d3e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770393546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.770393546
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.418955010
Short name T316
Test name
Test status
Simulation time 21371969 ps
CPU time 0.8 seconds
Started Aug 11 05:19:50 PM PDT 24
Finished Aug 11 05:19:50 PM PDT 24
Peak memory 206856 kb
Host smart-8fefc11c-ed28-49cc-82c7-13d153ecd4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418955010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.418955010
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3981764000
Short name T774
Test name
Test status
Simulation time 10378587027 ps
CPU time 89.37 seconds
Started Aug 11 05:19:56 PM PDT 24
Finished Aug 11 05:21:25 PM PDT 24
Peak memory 249568 kb
Host smart-cba7ddce-7335-4dd8-93c7-bb9f37329c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981764000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3981764000
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1747459930
Short name T120
Test name
Test status
Simulation time 225361294840 ps
CPU time 433.38 seconds
Started Aug 11 05:19:55 PM PDT 24
Finished Aug 11 05:27:08 PM PDT 24
Peak memory 257764 kb
Host smart-f8b198d0-53c9-4a77-8856-ab5f42702e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747459930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1747459930
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1090816280
Short name T139
Test name
Test status
Simulation time 298480821 ps
CPU time 5.02 seconds
Started Aug 11 05:19:56 PM PDT 24
Finished Aug 11 05:20:01 PM PDT 24
Peak memory 224852 kb
Host smart-889e8cf6-f06f-4209-a4d3-009e5556d813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090816280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1090816280
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1718166023
Short name T451
Test name
Test status
Simulation time 5890188974 ps
CPU time 19.12 seconds
Started Aug 11 05:19:53 PM PDT 24
Finished Aug 11 05:20:12 PM PDT 24
Peak memory 224808 kb
Host smart-29217dc0-262e-405e-aae2-1525d5f0ac0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718166023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1718166023
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3639356105
Short name T444
Test name
Test status
Simulation time 7012674562 ps
CPU time 40.04 seconds
Started Aug 11 05:19:54 PM PDT 24
Finished Aug 11 05:20:34 PM PDT 24
Peak memory 224828 kb
Host smart-6f28a457-f30f-451a-bf57-f86320dceb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639356105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3639356105
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3675733684
Short name T290
Test name
Test status
Simulation time 293895725 ps
CPU time 2.84 seconds
Started Aug 11 05:19:49 PM PDT 24
Finished Aug 11 05:19:52 PM PDT 24
Peak memory 224712 kb
Host smart-74be1ac6-c6dc-4416-8e25-908b271da75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675733684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3675733684
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.87982321
Short name T706
Test name
Test status
Simulation time 1402370509 ps
CPU time 11.73 seconds
Started Aug 11 05:19:48 PM PDT 24
Finished Aug 11 05:19:59 PM PDT 24
Peak memory 240520 kb
Host smart-224c5557-bcd1-4932-b8e9-6172d38927a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87982321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.87982321
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.998370264
Short name T869
Test name
Test status
Simulation time 1778104752 ps
CPU time 5.91 seconds
Started Aug 11 05:19:55 PM PDT 24
Finished Aug 11 05:20:01 PM PDT 24
Peak memory 219408 kb
Host smart-1c6c1cf5-1b47-4aad-8217-620a9f21bc71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=998370264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.998370264
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3447812500
Short name T382
Test name
Test status
Simulation time 41089445 ps
CPU time 1.03 seconds
Started Aug 11 05:19:56 PM PDT 24
Finished Aug 11 05:19:57 PM PDT 24
Peak memory 207832 kb
Host smart-7978154f-c2e4-4d01-834e-9435b3e68807
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447812500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3447812500
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3083320682
Short name T311
Test name
Test status
Simulation time 1325789505 ps
CPU time 5.48 seconds
Started Aug 11 05:19:47 PM PDT 24
Finished Aug 11 05:19:53 PM PDT 24
Peak memory 216536 kb
Host smart-e49a4d52-1090-4ac1-831b-1903a13ed5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083320682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3083320682
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2328039812
Short name T950
Test name
Test status
Simulation time 31767428 ps
CPU time 0.7 seconds
Started Aug 11 05:19:47 PM PDT 24
Finished Aug 11 05:19:48 PM PDT 24
Peak memory 206008 kb
Host smart-dbcc357d-7dd7-4b63-8804-388cf2d619fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328039812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2328039812
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1326625141
Short name T462
Test name
Test status
Simulation time 75822574 ps
CPU time 1.32 seconds
Started Aug 11 05:19:49 PM PDT 24
Finished Aug 11 05:19:50 PM PDT 24
Peak memory 216912 kb
Host smart-3cc5eae5-2790-4602-8a32-734f72f370df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326625141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1326625141
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2079641666
Short name T27
Test name
Test status
Simulation time 119522132 ps
CPU time 0.72 seconds
Started Aug 11 05:19:47 PM PDT 24
Finished Aug 11 05:19:48 PM PDT 24
Peak memory 206224 kb
Host smart-91773e5d-ce08-45ac-be77-0e80910b9d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079641666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2079641666
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1607395386
Short name T677
Test name
Test status
Simulation time 697576420 ps
CPU time 3.52 seconds
Started Aug 11 05:19:54 PM PDT 24
Finished Aug 11 05:19:57 PM PDT 24
Peak memory 224804 kb
Host smart-dd9889b1-c102-4c35-9347-3a5123c81198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607395386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1607395386
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3591127284
Short name T433
Test name
Test status
Simulation time 28348291 ps
CPU time 0.76 seconds
Started Aug 11 05:20:09 PM PDT 24
Finished Aug 11 05:20:10 PM PDT 24
Peak memory 205804 kb
Host smart-33abf292-493d-4cc5-a47f-996ac6578e46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591127284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3591127284
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2677041786
Short name T236
Test name
Test status
Simulation time 158747067 ps
CPU time 3.18 seconds
Started Aug 11 05:20:02 PM PDT 24
Finished Aug 11 05:20:05 PM PDT 24
Peak memory 224756 kb
Host smart-5ca5a00f-d616-4586-9c40-978139d4caa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677041786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2677041786
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3905793769
Short name T1011
Test name
Test status
Simulation time 19567734 ps
CPU time 0.81 seconds
Started Aug 11 05:19:55 PM PDT 24
Finished Aug 11 05:19:56 PM PDT 24
Peak memory 206880 kb
Host smart-c04599b1-6204-4254-88a2-fb82f8e6bbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905793769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3905793769
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1353736721
Short name T334
Test name
Test status
Simulation time 94392420 ps
CPU time 0.74 seconds
Started Aug 11 05:19:59 PM PDT 24
Finished Aug 11 05:20:00 PM PDT 24
Peak memory 215988 kb
Host smart-a55d2cae-0f4b-48e4-9aa2-be918259d78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353736721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1353736721
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3234069216
Short name T469
Test name
Test status
Simulation time 2069247543 ps
CPU time 14.05 seconds
Started Aug 11 05:20:10 PM PDT 24
Finished Aug 11 05:20:24 PM PDT 24
Peak memory 224904 kb
Host smart-06c21847-5b11-47e5-8f29-5d59f028a383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234069216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3234069216
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.4070405254
Short name T159
Test name
Test status
Simulation time 2893907121 ps
CPU time 45.78 seconds
Started Aug 11 05:20:07 PM PDT 24
Finished Aug 11 05:20:53 PM PDT 24
Peak memory 254336 kb
Host smart-96134f9f-17f3-43b9-a51a-935e7c7cf632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070405254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.4070405254
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.563592618
Short name T705
Test name
Test status
Simulation time 2979962943 ps
CPU time 12.92 seconds
Started Aug 11 05:20:01 PM PDT 24
Finished Aug 11 05:20:14 PM PDT 24
Peak memory 225184 kb
Host smart-cfbba5cd-12aa-47d1-b608-7e351fac45a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563592618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.563592618
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.226955678
Short name T557
Test name
Test status
Simulation time 6320208111 ps
CPU time 24.08 seconds
Started Aug 11 05:20:00 PM PDT 24
Finished Aug 11 05:20:24 PM PDT 24
Peak memory 233096 kb
Host smart-583067c7-7c97-4c6e-ac45-94622472a5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226955678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.226955678
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.806745273
Short name T255
Test name
Test status
Simulation time 1511815039 ps
CPU time 15.86 seconds
Started Aug 11 05:20:02 PM PDT 24
Finished Aug 11 05:20:18 PM PDT 24
Peak memory 232956 kb
Host smart-1d8c9147-bdea-413e-ad0a-fcc33636bbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806745273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.806745273
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2071124307
Short name T975
Test name
Test status
Simulation time 6219772159 ps
CPU time 5.79 seconds
Started Aug 11 05:20:01 PM PDT 24
Finished Aug 11 05:20:07 PM PDT 24
Peak memory 233024 kb
Host smart-f5cba8a9-2283-4528-9dbc-ee02ed2f6707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071124307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2071124307
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3624879715
Short name T264
Test name
Test status
Simulation time 30664225696 ps
CPU time 27.88 seconds
Started Aug 11 05:19:59 PM PDT 24
Finished Aug 11 05:20:27 PM PDT 24
Peak memory 224896 kb
Host smart-7d58cd2d-1d6b-459f-a86a-6bf44f47dd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624879715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3624879715
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2658082007
Short name T732
Test name
Test status
Simulation time 2863937235 ps
CPU time 5.86 seconds
Started Aug 11 05:19:59 PM PDT 24
Finished Aug 11 05:20:05 PM PDT 24
Peak memory 223392 kb
Host smart-ecd7108e-02d6-432e-b7a9-425f3485bc14
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2658082007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2658082007
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.762617776
Short name T31
Test name
Test status
Simulation time 4083560243 ps
CPU time 95.81 seconds
Started Aug 11 05:20:06 PM PDT 24
Finished Aug 11 05:21:42 PM PDT 24
Peak memory 255836 kb
Host smart-4ca828f6-dddb-40dc-ba09-3ba972ac170e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762617776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.762617776
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2325334476
Short name T718
Test name
Test status
Simulation time 26103724 ps
CPU time 0.76 seconds
Started Aug 11 05:20:01 PM PDT 24
Finished Aug 11 05:20:02 PM PDT 24
Peak memory 206068 kb
Host smart-47391a4c-584b-4c15-8fe4-2eef5a2d4e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325334476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2325334476
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2611951761
Short name T339
Test name
Test status
Simulation time 1766768876 ps
CPU time 2.99 seconds
Started Aug 11 05:19:54 PM PDT 24
Finished Aug 11 05:19:57 PM PDT 24
Peak memory 216560 kb
Host smart-7b65a958-a790-4823-9214-6e7fa66f18fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611951761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2611951761
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1546565883
Short name T502
Test name
Test status
Simulation time 13058591 ps
CPU time 0.67 seconds
Started Aug 11 05:20:01 PM PDT 24
Finished Aug 11 05:20:01 PM PDT 24
Peak memory 205872 kb
Host smart-9be81f14-879b-4fe3-bde0-62c3d5b67b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546565883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1546565883
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3688321077
Short name T682
Test name
Test status
Simulation time 236224064 ps
CPU time 0.88 seconds
Started Aug 11 05:20:00 PM PDT 24
Finished Aug 11 05:20:01 PM PDT 24
Peak memory 206312 kb
Host smart-8dc80d5f-3f8d-4c77-8f08-74b43d65a3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688321077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3688321077
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1901548346
Short name T231
Test name
Test status
Simulation time 3058920836 ps
CPU time 2.91 seconds
Started Aug 11 05:20:02 PM PDT 24
Finished Aug 11 05:20:05 PM PDT 24
Peak memory 224944 kb
Host smart-0cb81470-8451-4c0a-857a-13e2b0d1e065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901548346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1901548346
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.4144980637
Short name T403
Test name
Test status
Simulation time 19421573 ps
CPU time 0.73 seconds
Started Aug 11 05:20:12 PM PDT 24
Finished Aug 11 05:20:13 PM PDT 24
Peak memory 205184 kb
Host smart-ad887570-cbee-4bef-a982-1ae3ba6b3569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144980637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
4144980637
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.4113862760
Short name T551
Test name
Test status
Simulation time 44181349742 ps
CPU time 22.8 seconds
Started Aug 11 05:20:09 PM PDT 24
Finished Aug 11 05:20:32 PM PDT 24
Peak memory 224920 kb
Host smart-1829a1c8-1446-45d9-beae-4b63461855aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113862760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4113862760
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2850571508
Short name T350
Test name
Test status
Simulation time 20643572 ps
CPU time 0.75 seconds
Started Aug 11 05:20:09 PM PDT 24
Finished Aug 11 05:20:10 PM PDT 24
Peak memory 206980 kb
Host smart-61c987cc-760e-4838-b08e-f54b7a1c0172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850571508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2850571508
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.454418375
Short name T660
Test name
Test status
Simulation time 10411493640 ps
CPU time 105.56 seconds
Started Aug 11 05:20:18 PM PDT 24
Finished Aug 11 05:22:04 PM PDT 24
Peak memory 253364 kb
Host smart-34334495-c58e-42f9-bc8e-b2c7eae0df08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454418375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.454418375
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.4019714710
Short name T281
Test name
Test status
Simulation time 37220651394 ps
CPU time 379.31 seconds
Started Aug 11 05:20:18 PM PDT 24
Finished Aug 11 05:26:37 PM PDT 24
Peak memory 249576 kb
Host smart-27472380-2cfc-46d2-96c7-2488403478f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019714710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4019714710
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3153960287
Short name T41
Test name
Test status
Simulation time 9532619767 ps
CPU time 66.26 seconds
Started Aug 11 05:20:18 PM PDT 24
Finished Aug 11 05:21:24 PM PDT 24
Peak memory 257772 kb
Host smart-9a206b6d-bc34-4942-aab2-4406fc282933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153960287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3153960287
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1367816694
Short name T534
Test name
Test status
Simulation time 83834485 ps
CPU time 3.55 seconds
Started Aug 11 05:20:16 PM PDT 24
Finished Aug 11 05:20:20 PM PDT 24
Peak memory 224868 kb
Host smart-74e03c07-5b36-4868-909f-8dc0790709d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367816694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1367816694
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3950746366
Short name T645
Test name
Test status
Simulation time 18701767716 ps
CPU time 10.26 seconds
Started Aug 11 05:20:14 PM PDT 24
Finished Aug 11 05:20:24 PM PDT 24
Peak memory 235056 kb
Host smart-64dca562-2b2f-4b34-8aff-4141e2c4870f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950746366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3950746366
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.740091461
Short name T212
Test name
Test status
Simulation time 2083876177 ps
CPU time 19.79 seconds
Started Aug 11 05:20:07 PM PDT 24
Finished Aug 11 05:20:27 PM PDT 24
Peak memory 233036 kb
Host smart-136d323e-7e76-4df4-8090-a34fb5d248ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740091461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.740091461
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1228705297
Short name T521
Test name
Test status
Simulation time 8342076252 ps
CPU time 34.97 seconds
Started Aug 11 05:20:09 PM PDT 24
Finished Aug 11 05:20:44 PM PDT 24
Peak memory 250912 kb
Host smart-0517466c-5eb0-43d7-922b-3d42e3e81c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228705297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1228705297
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1687239398
Short name T288
Test name
Test status
Simulation time 14828861228 ps
CPU time 23.92 seconds
Started Aug 11 05:20:07 PM PDT 24
Finished Aug 11 05:20:31 PM PDT 24
Peak memory 241292 kb
Host smart-4e39f597-5d57-4f72-a799-a474b0c9626f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687239398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1687239398
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2344707612
Short name T471
Test name
Test status
Simulation time 614349247 ps
CPU time 9.4 seconds
Started Aug 11 05:20:07 PM PDT 24
Finished Aug 11 05:20:16 PM PDT 24
Peak memory 241056 kb
Host smart-9c1e990c-ab99-4f45-8f07-7ca9b39b5948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344707612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2344707612
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3066197011
Short name T630
Test name
Test status
Simulation time 853400976 ps
CPU time 7.1 seconds
Started Aug 11 05:20:14 PM PDT 24
Finished Aug 11 05:20:21 PM PDT 24
Peak memory 220704 kb
Host smart-18186032-1928-407d-9735-2142661de72c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3066197011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3066197011
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2902770137
Short name T817
Test name
Test status
Simulation time 36160099795 ps
CPU time 423.77 seconds
Started Aug 11 05:20:17 PM PDT 24
Finished Aug 11 05:27:21 PM PDT 24
Peak memory 285924 kb
Host smart-f7988ca9-ed93-4b63-9296-fc92aeabaf3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902770137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2902770137
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.575108891
Short name T550
Test name
Test status
Simulation time 914606536 ps
CPU time 14.55 seconds
Started Aug 11 05:20:11 PM PDT 24
Finished Aug 11 05:20:26 PM PDT 24
Peak memory 216732 kb
Host smart-347ddfe3-fbc6-46af-bcc0-42adbab64ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575108891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.575108891
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3907182028
Short name T595
Test name
Test status
Simulation time 369712052 ps
CPU time 2.31 seconds
Started Aug 11 05:20:09 PM PDT 24
Finished Aug 11 05:20:11 PM PDT 24
Peak memory 216536 kb
Host smart-4e44484b-693e-41d6-a184-f2a7cd4e75ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907182028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3907182028
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1350738813
Short name T579
Test name
Test status
Simulation time 131473834 ps
CPU time 1.69 seconds
Started Aug 11 05:20:09 PM PDT 24
Finished Aug 11 05:20:11 PM PDT 24
Peak memory 216432 kb
Host smart-8bd8bce6-a613-4cb4-9975-0bd140edda6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350738813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1350738813
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3677835585
Short name T330
Test name
Test status
Simulation time 37657546 ps
CPU time 0.72 seconds
Started Aug 11 05:20:11 PM PDT 24
Finished Aug 11 05:20:12 PM PDT 24
Peak memory 206256 kb
Host smart-f95c93fa-1a83-488e-954b-e21ec78b1fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677835585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3677835585
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.483629080
Short name T1002
Test name
Test status
Simulation time 1392520656 ps
CPU time 5.92 seconds
Started Aug 11 05:20:07 PM PDT 24
Finished Aug 11 05:20:13 PM PDT 24
Peak memory 224856 kb
Host smart-36d985f0-e9fa-4f83-b4f8-7921923ef41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483629080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.483629080
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.457078269
Short name T526
Test name
Test status
Simulation time 22411219 ps
CPU time 0.74 seconds
Started Aug 11 05:20:23 PM PDT 24
Finished Aug 11 05:20:24 PM PDT 24
Peak memory 205832 kb
Host smart-bbc8853d-48ff-48d1-97ef-d67044223055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457078269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.457078269
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2080516685
Short name T607
Test name
Test status
Simulation time 240136802 ps
CPU time 3.38 seconds
Started Aug 11 05:20:20 PM PDT 24
Finished Aug 11 05:20:24 PM PDT 24
Peak memory 224816 kb
Host smart-16dcaa29-643c-4f64-80a2-3b7c551a3b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080516685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2080516685
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1072320279
Short name T703
Test name
Test status
Simulation time 19807054 ps
CPU time 0.81 seconds
Started Aug 11 05:20:21 PM PDT 24
Finished Aug 11 05:20:22 PM PDT 24
Peak memory 206916 kb
Host smart-2d91041b-4d92-4bc1-96fb-24cd7d5178d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072320279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1072320279
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.428061714
Short name T965
Test name
Test status
Simulation time 48540426627 ps
CPU time 136.17 seconds
Started Aug 11 05:20:19 PM PDT 24
Finished Aug 11 05:22:35 PM PDT 24
Peak memory 249456 kb
Host smart-3551ddb3-bcb4-498d-b49d-4500735d0a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428061714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.428061714
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.4264596499
Short name T280
Test name
Test status
Simulation time 4613802288 ps
CPU time 125.48 seconds
Started Aug 11 05:20:22 PM PDT 24
Finished Aug 11 05:22:28 PM PDT 24
Peak memory 265964 kb
Host smart-acab22d6-2db6-4b3e-8085-3927ca461bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264596499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.4264596499
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.71498551
Short name T836
Test name
Test status
Simulation time 58741949626 ps
CPU time 508.57 seconds
Started Aug 11 05:20:23 PM PDT 24
Finished Aug 11 05:28:51 PM PDT 24
Peak memory 257780 kb
Host smart-6db4313e-e959-46fb-af90-a0672e63bff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71498551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.71498551
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3420825298
Short name T531
Test name
Test status
Simulation time 141662748 ps
CPU time 4.21 seconds
Started Aug 11 05:20:20 PM PDT 24
Finished Aug 11 05:20:25 PM PDT 24
Peak memory 241280 kb
Host smart-1a5cd596-7f8a-4be4-8d53-d58580337c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420825298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3420825298
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1476518945
Short name T549
Test name
Test status
Simulation time 30162421773 ps
CPU time 192.1 seconds
Started Aug 11 05:20:21 PM PDT 24
Finished Aug 11 05:23:33 PM PDT 24
Peak memory 253916 kb
Host smart-aebef9b4-cebf-42eb-9ba3-c277bc9344c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476518945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1476518945
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.361669658
Short name T217
Test name
Test status
Simulation time 1723272305 ps
CPU time 17.79 seconds
Started Aug 11 05:20:19 PM PDT 24
Finished Aug 11 05:20:37 PM PDT 24
Peak memory 232968 kb
Host smart-28977a4f-bdef-47e7-a6c9-357e4bdec2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361669658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.361669658
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2166519721
Short name T259
Test name
Test status
Simulation time 12328365637 ps
CPU time 34.65 seconds
Started Aug 11 05:20:20 PM PDT 24
Finished Aug 11 05:20:55 PM PDT 24
Peak memory 224720 kb
Host smart-0cc1d7bb-3766-4427-b800-be9e88e49f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166519721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2166519721
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3078804661
Short name T477
Test name
Test status
Simulation time 1369382641 ps
CPU time 3.21 seconds
Started Aug 11 05:20:23 PM PDT 24
Finished Aug 11 05:20:27 PM PDT 24
Peak memory 233048 kb
Host smart-4693c836-04cb-4264-a6a2-405c17c2ec22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078804661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3078804661
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3756953490
Short name T852
Test name
Test status
Simulation time 30611445 ps
CPU time 2.16 seconds
Started Aug 11 05:20:18 PM PDT 24
Finished Aug 11 05:20:20 PM PDT 24
Peak memory 232732 kb
Host smart-04ac8342-0e1b-4a24-9651-38f2243b4be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756953490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3756953490
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.797597062
Short name T639
Test name
Test status
Simulation time 1802174251 ps
CPU time 12.21 seconds
Started Aug 11 05:20:20 PM PDT 24
Finished Aug 11 05:20:33 PM PDT 24
Peak memory 220680 kb
Host smart-4243b068-0d4c-4e44-93a2-5e7a6844d5b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=797597062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.797597062
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.105779094
Short name T937
Test name
Test status
Simulation time 86773235397 ps
CPU time 273.76 seconds
Started Aug 11 05:20:20 PM PDT 24
Finished Aug 11 05:24:54 PM PDT 24
Peak memory 290356 kb
Host smart-72a117b7-7fdb-4a5b-b95e-1cc6010bc6e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105779094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.105779094
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1836931043
Short name T425
Test name
Test status
Simulation time 1565362148 ps
CPU time 7.46 seconds
Started Aug 11 05:20:22 PM PDT 24
Finished Aug 11 05:20:30 PM PDT 24
Peak memory 216684 kb
Host smart-b90c749d-6e7d-49a0-aa6a-af08d663195f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836931043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1836931043
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3756352011
Short name T121
Test name
Test status
Simulation time 5408574753 ps
CPU time 12.22 seconds
Started Aug 11 05:20:21 PM PDT 24
Finished Aug 11 05:20:34 PM PDT 24
Peak memory 216680 kb
Host smart-bb3a72b4-dc4e-4d4f-afae-dcfa3de6c1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756352011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3756352011
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.267709452
Short name T762
Test name
Test status
Simulation time 110383147 ps
CPU time 0.74 seconds
Started Aug 11 05:20:20 PM PDT 24
Finished Aug 11 05:20:21 PM PDT 24
Peak memory 206232 kb
Host smart-47602505-62e2-4f3c-a18f-cfa747bb7d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267709452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.267709452
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3604990277
Short name T484
Test name
Test status
Simulation time 97983961 ps
CPU time 0.99 seconds
Started Aug 11 05:20:21 PM PDT 24
Finished Aug 11 05:20:22 PM PDT 24
Peak memory 206284 kb
Host smart-97fcc63b-ea43-454e-8aa1-bf1365b0942d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604990277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3604990277
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.4098995491
Short name T358
Test name
Test status
Simulation time 9023357132 ps
CPU time 9.98 seconds
Started Aug 11 05:20:19 PM PDT 24
Finished Aug 11 05:20:29 PM PDT 24
Peak memory 224952 kb
Host smart-7a649f00-8bf2-4dcc-8763-d3868e5c8651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098995491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4098995491
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1563687710
Short name T863
Test name
Test status
Simulation time 27295422 ps
CPU time 0.73 seconds
Started Aug 11 05:20:33 PM PDT 24
Finished Aug 11 05:20:34 PM PDT 24
Peak memory 205792 kb
Host smart-f2eb220b-4f63-4fca-8e06-e508efa111b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563687710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1563687710
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2285946115
Short name T504
Test name
Test status
Simulation time 2255624347 ps
CPU time 9.07 seconds
Started Aug 11 05:20:26 PM PDT 24
Finished Aug 11 05:20:35 PM PDT 24
Peak memory 232972 kb
Host smart-0150e253-4b21-430a-86ae-c76b797828ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285946115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2285946115
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3228151804
Short name T742
Test name
Test status
Simulation time 37465241 ps
CPU time 0.83 seconds
Started Aug 11 05:20:26 PM PDT 24
Finished Aug 11 05:20:27 PM PDT 24
Peak memory 206848 kb
Host smart-1c72b9de-37b4-4fe2-ba6c-3ea84964c0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228151804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3228151804
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3888498344
Short name T191
Test name
Test status
Simulation time 12575785953 ps
CPU time 107.12 seconds
Started Aug 11 05:20:25 PM PDT 24
Finished Aug 11 05:22:12 PM PDT 24
Peak memory 257700 kb
Host smart-63033b93-0acd-4dec-bc4a-998efe52b907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888498344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3888498344
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3103209760
Short name T252
Test name
Test status
Simulation time 4194808222 ps
CPU time 80.67 seconds
Started Aug 11 05:20:30 PM PDT 24
Finished Aug 11 05:21:50 PM PDT 24
Peak memory 255284 kb
Host smart-defdb254-7255-44c5-82dd-24b51eb0e223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103209760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3103209760
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.940062563
Short name T726
Test name
Test status
Simulation time 7412456504 ps
CPU time 69.09 seconds
Started Aug 11 05:20:28 PM PDT 24
Finished Aug 11 05:21:37 PM PDT 24
Peak memory 257076 kb
Host smart-16c7b6e0-492a-4926-90ca-665b232f20a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940062563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.940062563
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2441375369
Short name T84
Test name
Test status
Simulation time 355627985 ps
CPU time 5.86 seconds
Started Aug 11 05:20:30 PM PDT 24
Finished Aug 11 05:20:36 PM PDT 24
Peak memory 224880 kb
Host smart-bbb09f26-03f8-45c7-838a-687d291eb9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441375369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2441375369
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.924935675
Short name T170
Test name
Test status
Simulation time 184431291950 ps
CPU time 296.24 seconds
Started Aug 11 05:20:26 PM PDT 24
Finished Aug 11 05:25:22 PM PDT 24
Peak memory 258000 kb
Host smart-1fe23599-7b5b-46c3-9882-ecd51a466bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924935675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.924935675
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2298294599
Short name T870
Test name
Test status
Simulation time 430664245 ps
CPU time 5.53 seconds
Started Aug 11 05:20:27 PM PDT 24
Finished Aug 11 05:20:32 PM PDT 24
Peak memory 233092 kb
Host smart-cfaf385e-13cf-4c09-b4fe-acef0602bbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298294599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2298294599
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4053263565
Short name T959
Test name
Test status
Simulation time 139454525 ps
CPU time 3.82 seconds
Started Aug 11 05:20:27 PM PDT 24
Finished Aug 11 05:20:31 PM PDT 24
Peak memory 233036 kb
Host smart-c815f26a-d5f7-46d6-857a-acdddb12d736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053263565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4053263565
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2042763344
Short name T707
Test name
Test status
Simulation time 6725784418 ps
CPU time 6.55 seconds
Started Aug 11 05:20:29 PM PDT 24
Finished Aug 11 05:20:36 PM PDT 24
Peak memory 224832 kb
Host smart-029da5fc-2c50-44f4-a8a2-6f0dda488444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042763344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2042763344
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1092589532
Short name T476
Test name
Test status
Simulation time 7146162050 ps
CPU time 18.6 seconds
Started Aug 11 05:20:25 PM PDT 24
Finished Aug 11 05:20:44 PM PDT 24
Peak memory 222944 kb
Host smart-d775faeb-b48f-471e-bf3b-930f98dd9487
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1092589532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1092589532
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2907601440
Short name T151
Test name
Test status
Simulation time 3228360976 ps
CPU time 27.17 seconds
Started Aug 11 05:20:33 PM PDT 24
Finished Aug 11 05:21:01 PM PDT 24
Peak memory 249504 kb
Host smart-cf65e7ea-4dc0-4ce9-9b25-dfd6f8bc2810
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907601440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2907601440
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.788230105
Short name T861
Test name
Test status
Simulation time 3109458316 ps
CPU time 18.87 seconds
Started Aug 11 05:20:28 PM PDT 24
Finished Aug 11 05:20:47 PM PDT 24
Peak memory 216712 kb
Host smart-a9a16b17-543b-4af0-a08c-05c1e6464539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788230105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.788230105
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3151765534
Short name T694
Test name
Test status
Simulation time 978220088 ps
CPU time 6.68 seconds
Started Aug 11 05:20:25 PM PDT 24
Finished Aug 11 05:20:32 PM PDT 24
Peak memory 216576 kb
Host smart-084b6115-a5fd-4189-bc1f-7b0d06f39de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151765534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3151765534
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3053275033
Short name T953
Test name
Test status
Simulation time 10819991 ps
CPU time 0.72 seconds
Started Aug 11 05:20:25 PM PDT 24
Finished Aug 11 05:20:26 PM PDT 24
Peak memory 205948 kb
Host smart-a6ec76ed-b8bc-4db0-b1c2-dd38a9e1982c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053275033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3053275033
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2065262025
Short name T487
Test name
Test status
Simulation time 154998881 ps
CPU time 0.97 seconds
Started Aug 11 05:20:26 PM PDT 24
Finished Aug 11 05:20:27 PM PDT 24
Peak memory 206236 kb
Host smart-ed116dca-5a44-4794-9dc8-a64737601cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065262025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2065262025
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.173595536
Short name T204
Test name
Test status
Simulation time 5645940823 ps
CPU time 8.39 seconds
Started Aug 11 05:20:25 PM PDT 24
Finished Aug 11 05:20:34 PM PDT 24
Peak memory 233040 kb
Host smart-278dedfc-302e-49fb-a25c-a1bf6ab36cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173595536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.173595536
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3312404237
Short name T408
Test name
Test status
Simulation time 30144155 ps
CPU time 0.69 seconds
Started Aug 11 05:20:38 PM PDT 24
Finished Aug 11 05:20:39 PM PDT 24
Peak memory 205148 kb
Host smart-d6abf576-54ac-463c-9b51-7342567d1ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312404237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3312404237
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.533159807
Short name T880
Test name
Test status
Simulation time 83456388 ps
CPU time 3 seconds
Started Aug 11 05:20:39 PM PDT 24
Finished Aug 11 05:20:42 PM PDT 24
Peak memory 233008 kb
Host smart-351cb37d-54df-4132-9dde-08af44a4200e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533159807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.533159807
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2901279288
Short name T380
Test name
Test status
Simulation time 35006530 ps
CPU time 0.8 seconds
Started Aug 11 05:20:32 PM PDT 24
Finished Aug 11 05:20:32 PM PDT 24
Peak memory 206752 kb
Host smart-242ee6fd-afff-4f9c-98ab-340d1ad0d4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901279288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2901279288
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1312652492
Short name T899
Test name
Test status
Simulation time 18450473 ps
CPU time 0.72 seconds
Started Aug 11 05:20:38 PM PDT 24
Finished Aug 11 05:20:39 PM PDT 24
Peak memory 216084 kb
Host smart-c694f641-8470-480c-b3d8-e722b57807b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312652492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1312652492
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3335896541
Short name T981
Test name
Test status
Simulation time 34126581182 ps
CPU time 340.31 seconds
Started Aug 11 05:20:38 PM PDT 24
Finished Aug 11 05:26:19 PM PDT 24
Peak memory 255036 kb
Host smart-474983e9-f532-42c8-85b5-d4ad45931551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335896541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3335896541
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.4145364182
Short name T312
Test name
Test status
Simulation time 2287743327 ps
CPU time 30.91 seconds
Started Aug 11 05:20:38 PM PDT 24
Finished Aug 11 05:21:09 PM PDT 24
Peak memory 239896 kb
Host smart-ba6c5e2e-67c4-4c54-9a25-30dbb9fa3eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145364182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.4145364182
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_intercept.494193261
Short name T512
Test name
Test status
Simulation time 1537433941 ps
CPU time 6.34 seconds
Started Aug 11 05:20:38 PM PDT 24
Finished Aug 11 05:20:45 PM PDT 24
Peak memory 233396 kb
Host smart-c5fab3f6-941c-450d-af1d-1d638e0a1cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494193261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.494193261
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2433834472
Short name T603
Test name
Test status
Simulation time 28173355 ps
CPU time 2.11 seconds
Started Aug 11 05:20:37 PM PDT 24
Finished Aug 11 05:20:39 PM PDT 24
Peak memory 224536 kb
Host smart-85430b52-9346-4629-a82b-bf81a69be9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433834472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2433834472
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.289119083
Short name T818
Test name
Test status
Simulation time 1807889253 ps
CPU time 10.83 seconds
Started Aug 11 05:20:38 PM PDT 24
Finished Aug 11 05:20:49 PM PDT 24
Peak memory 233036 kb
Host smart-10157af9-ca6a-430e-bc51-1928862c35db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289119083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.289119083
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.4034678225
Short name T736
Test name
Test status
Simulation time 34733824 ps
CPU time 2.78 seconds
Started Aug 11 05:20:32 PM PDT 24
Finished Aug 11 05:20:35 PM PDT 24
Peak memory 233028 kb
Host smart-455ec078-42ce-4920-931d-b79d2c39435d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034678225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.4034678225
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1022234240
Short name T133
Test name
Test status
Simulation time 1020443481 ps
CPU time 10.8 seconds
Started Aug 11 05:20:39 PM PDT 24
Finished Aug 11 05:20:50 PM PDT 24
Peak memory 223388 kb
Host smart-8a89f525-1c29-4d67-8fce-a671f11b4fa4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1022234240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1022234240
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2073805978
Short name T685
Test name
Test status
Simulation time 2266403348 ps
CPU time 22.78 seconds
Started Aug 11 05:20:41 PM PDT 24
Finished Aug 11 05:21:04 PM PDT 24
Peak memory 225024 kb
Host smart-1e0ea97b-5a2b-4254-a60d-d3106b92ee0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073805978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2073805978
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.345910393
Short name T453
Test name
Test status
Simulation time 2614901626 ps
CPU time 18.96 seconds
Started Aug 11 05:20:32 PM PDT 24
Finished Aug 11 05:20:51 PM PDT 24
Peak memory 220332 kb
Host smart-e3157ca4-f970-4e7d-887c-bb4b93b68004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345910393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.345910393
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.916905323
Short name T548
Test name
Test status
Simulation time 17550433664 ps
CPU time 14.45 seconds
Started Aug 11 05:20:31 PM PDT 24
Finished Aug 11 05:20:46 PM PDT 24
Peak memory 216948 kb
Host smart-99674203-ba6c-452c-aa17-0908161c5120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916905323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.916905323
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2656502863
Short name T728
Test name
Test status
Simulation time 422584464 ps
CPU time 1.74 seconds
Started Aug 11 05:20:32 PM PDT 24
Finished Aug 11 05:20:34 PM PDT 24
Peak memory 208388 kb
Host smart-7ef1f2eb-b753-474e-9fb6-3cf6bce94759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656502863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2656502863
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2422978017
Short name T837
Test name
Test status
Simulation time 104073550 ps
CPU time 0.74 seconds
Started Aug 11 05:20:31 PM PDT 24
Finished Aug 11 05:20:32 PM PDT 24
Peak memory 206272 kb
Host smart-21b2970c-8caa-466b-b619-d54717093c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422978017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2422978017
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.985501859
Short name T230
Test name
Test status
Simulation time 1808900570 ps
CPU time 7.35 seconds
Started Aug 11 05:20:39 PM PDT 24
Finished Aug 11 05:20:46 PM PDT 24
Peak memory 224808 kb
Host smart-adfbcfe6-3e37-496c-bfa6-ed7219a920fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985501859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.985501859
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.744075659
Short name T495
Test name
Test status
Simulation time 16725242 ps
CPU time 0.73 seconds
Started Aug 11 05:20:53 PM PDT 24
Finished Aug 11 05:20:54 PM PDT 24
Peak memory 205468 kb
Host smart-89aec676-6897-4071-98ff-cd48ef158625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744075659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.744075659
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3005996912
Short name T708
Test name
Test status
Simulation time 930224647 ps
CPU time 10.39 seconds
Started Aug 11 05:20:50 PM PDT 24
Finished Aug 11 05:21:00 PM PDT 24
Peak memory 224888 kb
Host smart-da290af4-edcd-4b84-a363-003bf186d359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005996912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3005996912
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2013073372
Short name T318
Test name
Test status
Simulation time 40538353 ps
CPU time 0.82 seconds
Started Aug 11 05:20:46 PM PDT 24
Finished Aug 11 05:20:47 PM PDT 24
Peak memory 206948 kb
Host smart-5e5a7ddb-080b-48a1-baf2-c43a103043e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013073372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2013073372
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1398018774
Short name T641
Test name
Test status
Simulation time 2276615594 ps
CPU time 30.2 seconds
Started Aug 11 05:20:44 PM PDT 24
Finished Aug 11 05:21:14 PM PDT 24
Peak memory 238600 kb
Host smart-a39289ae-4b16-4e06-8f98-ef2b502eb412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398018774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1398018774
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2882284149
Short name T919
Test name
Test status
Simulation time 4597889043 ps
CPU time 79.89 seconds
Started Aug 11 05:20:53 PM PDT 24
Finished Aug 11 05:22:13 PM PDT 24
Peak memory 265276 kb
Host smart-4b9130dd-c306-4732-8831-519ff38c92ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882284149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2882284149
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.162220867
Short name T790
Test name
Test status
Simulation time 23533019247 ps
CPU time 95.59 seconds
Started Aug 11 05:20:51 PM PDT 24
Finished Aug 11 05:22:27 PM PDT 24
Peak memory 249496 kb
Host smart-d3ef6b26-1d16-43cb-a893-0be5efd5a6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162220867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.162220867
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3607335184
Short name T413
Test name
Test status
Simulation time 165916107 ps
CPU time 4.94 seconds
Started Aug 11 05:20:47 PM PDT 24
Finished Aug 11 05:20:53 PM PDT 24
Peak memory 224904 kb
Host smart-e8d31c44-ebb0-46f6-a9ad-4418e12e006c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607335184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3607335184
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.366606423
Short name T814
Test name
Test status
Simulation time 1238012895 ps
CPU time 28.21 seconds
Started Aug 11 05:20:44 PM PDT 24
Finished Aug 11 05:21:12 PM PDT 24
Peak memory 249512 kb
Host smart-acddaa8e-be6e-47d9-ad64-d358e1453905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366606423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.366606423
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2621676809
Short name T675
Test name
Test status
Simulation time 284537172 ps
CPU time 2.45 seconds
Started Aug 11 05:20:46 PM PDT 24
Finished Aug 11 05:20:49 PM PDT 24
Peak memory 233080 kb
Host smart-cdcb307c-3878-43aa-9d3a-2a8593744142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621676809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2621676809
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1033499494
Short name T926
Test name
Test status
Simulation time 2333720777 ps
CPU time 9.86 seconds
Started Aug 11 05:20:47 PM PDT 24
Finished Aug 11 05:20:57 PM PDT 24
Peak memory 224820 kb
Host smart-478084e8-2470-459c-b347-75eff7d36403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033499494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1033499494
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3284128457
Short name T648
Test name
Test status
Simulation time 4138820315 ps
CPU time 7.83 seconds
Started Aug 11 05:20:46 PM PDT 24
Finished Aug 11 05:20:54 PM PDT 24
Peak memory 233120 kb
Host smart-5ced7f81-9888-4f8d-a257-a3615490e357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284128457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3284128457
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3696391261
Short name T242
Test name
Test status
Simulation time 7201701048 ps
CPU time 27.66 seconds
Started Aug 11 05:20:47 PM PDT 24
Finished Aug 11 05:21:15 PM PDT 24
Peak memory 249548 kb
Host smart-407154ea-b345-4d6f-a3e1-ffe76d65b755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696391261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3696391261
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2369504099
Short name T806
Test name
Test status
Simulation time 8754214273 ps
CPU time 24.01 seconds
Started Aug 11 05:20:47 PM PDT 24
Finished Aug 11 05:21:11 PM PDT 24
Peak memory 220484 kb
Host smart-5e56b259-f1ba-4664-890c-1d21e789ea0c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2369504099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2369504099
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3902280158
Short name T20
Test name
Test status
Simulation time 48244095 ps
CPU time 1.15 seconds
Started Aug 11 05:20:54 PM PDT 24
Finished Aug 11 05:20:55 PM PDT 24
Peak memory 207396 kb
Host smart-a9af4ba4-ee3d-4396-b5e4-6519e7b3c8f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902280158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3902280158
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.916664451
Short name T678
Test name
Test status
Simulation time 11303047796 ps
CPU time 21.96 seconds
Started Aug 11 05:20:46 PM PDT 24
Finished Aug 11 05:21:08 PM PDT 24
Peak memory 216732 kb
Host smart-65d43adb-d9c4-48a9-82d5-0df9fc36b4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916664451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.916664451
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1741343436
Short name T960
Test name
Test status
Simulation time 5201869809 ps
CPU time 12.47 seconds
Started Aug 11 05:20:46 PM PDT 24
Finished Aug 11 05:20:59 PM PDT 24
Peak memory 216596 kb
Host smart-173702ab-36a9-4bdc-bb32-dc393d3a33c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741343436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1741343436
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2103751091
Short name T555
Test name
Test status
Simulation time 572822584 ps
CPU time 4.33 seconds
Started Aug 11 05:20:47 PM PDT 24
Finished Aug 11 05:20:52 PM PDT 24
Peak memory 216568 kb
Host smart-9ed30911-a8c1-4d86-9e26-9bcce34c708a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103751091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2103751091
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.662679481
Short name T331
Test name
Test status
Simulation time 62501744 ps
CPU time 0.79 seconds
Started Aug 11 05:20:44 PM PDT 24
Finished Aug 11 05:20:45 PM PDT 24
Peak memory 206164 kb
Host smart-cd4df84e-f532-498c-80d0-e4ae427fea33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662679481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.662679481
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1529645591
Short name T345
Test name
Test status
Simulation time 159729449 ps
CPU time 2.42 seconds
Started Aug 11 05:20:45 PM PDT 24
Finished Aug 11 05:20:48 PM PDT 24
Peak memory 224412 kb
Host smart-b5506f73-fbf2-4d3f-a9d8-3864143ba2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529645591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1529645591
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1673934269
Short name T841
Test name
Test status
Simulation time 38928675 ps
CPU time 0.69 seconds
Started Aug 11 05:21:01 PM PDT 24
Finished Aug 11 05:21:02 PM PDT 24
Peak memory 205752 kb
Host smart-fa241bda-9d99-4568-9704-e5c13be3d3e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673934269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1673934269
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2105048056
Short name T910
Test name
Test status
Simulation time 121119784 ps
CPU time 2.79 seconds
Started Aug 11 05:21:00 PM PDT 24
Finished Aug 11 05:21:03 PM PDT 24
Peak memory 232960 kb
Host smart-2aa70cec-98fe-40c8-97e3-cb3e8fb61486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105048056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2105048056
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2001055378
Short name T729
Test name
Test status
Simulation time 34203251 ps
CPU time 0.8 seconds
Started Aug 11 05:20:53 PM PDT 24
Finished Aug 11 05:20:54 PM PDT 24
Peak memory 207196 kb
Host smart-64d1d654-fc9c-4683-85c0-8a41fd0b9700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001055378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2001055378
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.760511455
Short name T878
Test name
Test status
Simulation time 1702897192 ps
CPU time 24.9 seconds
Started Aug 11 05:20:58 PM PDT 24
Finished Aug 11 05:21:23 PM PDT 24
Peak memory 249436 kb
Host smart-1bc9bf06-7aa1-42ff-84a7-1b9679276e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760511455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.760511455
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1463195554
Short name T274
Test name
Test status
Simulation time 2148576926 ps
CPU time 31.15 seconds
Started Aug 11 05:20:58 PM PDT 24
Finished Aug 11 05:21:29 PM PDT 24
Peak memory 233208 kb
Host smart-581c8ea1-625b-48c0-8eb5-aab1df5b6c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463195554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1463195554
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3893558271
Short name T422
Test name
Test status
Simulation time 4249740190 ps
CPU time 15.61 seconds
Started Aug 11 05:20:59 PM PDT 24
Finished Aug 11 05:21:15 PM PDT 24
Peak memory 224820 kb
Host smart-4ff47840-93d5-4feb-9fda-d781d7b669e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893558271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3893558271
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3707946516
Short name T473
Test name
Test status
Simulation time 193495947 ps
CPU time 3.63 seconds
Started Aug 11 05:21:00 PM PDT 24
Finished Aug 11 05:21:04 PM PDT 24
Peak memory 224852 kb
Host smart-b7355e7c-f805-4b55-b1a1-5fe69ea0e63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707946516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3707946516
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.4158027983
Short name T929
Test name
Test status
Simulation time 827816441 ps
CPU time 7.07 seconds
Started Aug 11 05:20:58 PM PDT 24
Finished Aug 11 05:21:05 PM PDT 24
Peak memory 233036 kb
Host smart-a9df4322-cd7d-4fa2-984f-21e6d13c880b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158027983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.4158027983
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.4138329872
Short name T261
Test name
Test status
Simulation time 314418874 ps
CPU time 2.41 seconds
Started Aug 11 05:20:59 PM PDT 24
Finished Aug 11 05:21:01 PM PDT 24
Peak memory 232928 kb
Host smart-7a45011f-98cf-4a4b-b8f9-94e54e7e0779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138329872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.4138329872
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.423835034
Short name T894
Test name
Test status
Simulation time 1866465284 ps
CPU time 4.84 seconds
Started Aug 11 05:20:52 PM PDT 24
Finished Aug 11 05:20:57 PM PDT 24
Peak memory 224856 kb
Host smart-a385619d-7ba8-4770-a151-a14f90e04949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423835034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.423835034
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2022545897
Short name T383
Test name
Test status
Simulation time 2033092874 ps
CPU time 7.16 seconds
Started Aug 11 05:21:00 PM PDT 24
Finished Aug 11 05:21:07 PM PDT 24
Peak memory 224412 kb
Host smart-341fc33e-0703-431a-a313-c2c8319631b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2022545897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2022545897
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3996826158
Short name T239
Test name
Test status
Simulation time 74174063420 ps
CPU time 185.76 seconds
Started Aug 11 05:20:59 PM PDT 24
Finished Aug 11 05:24:05 PM PDT 24
Peak memory 233204 kb
Host smart-366eb06b-03e6-43dd-80e3-20d0c17ce67b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996826158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3996826158
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3202809849
Short name T572
Test name
Test status
Simulation time 4895543349 ps
CPU time 18.46 seconds
Started Aug 11 05:20:51 PM PDT 24
Finished Aug 11 05:21:09 PM PDT 24
Peak memory 216636 kb
Host smart-392d0a6d-edaf-4a97-8450-8231072d378e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202809849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3202809849
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1546371059
Short name T626
Test name
Test status
Simulation time 3610591586 ps
CPU time 3.99 seconds
Started Aug 11 05:20:57 PM PDT 24
Finished Aug 11 05:21:01 PM PDT 24
Peak memory 216616 kb
Host smart-2051a5da-6e25-4222-8492-3d46af16d0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546371059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1546371059
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1321572203
Short name T625
Test name
Test status
Simulation time 258559917 ps
CPU time 2.27 seconds
Started Aug 11 05:20:54 PM PDT 24
Finished Aug 11 05:20:56 PM PDT 24
Peak memory 216552 kb
Host smart-efde1a1f-b0e2-4d4a-aef1-17707dfa9357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321572203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1321572203
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3359078865
Short name T372
Test name
Test status
Simulation time 98426603 ps
CPU time 0.81 seconds
Started Aug 11 05:20:52 PM PDT 24
Finished Aug 11 05:20:52 PM PDT 24
Peak memory 206256 kb
Host smart-61fa1c77-5321-4cc5-976b-79a19116172c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359078865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3359078865
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.4063263527
Short name T633
Test name
Test status
Simulation time 295878459 ps
CPU time 3.09 seconds
Started Aug 11 05:20:58 PM PDT 24
Finished Aug 11 05:21:01 PM PDT 24
Peak memory 241192 kb
Host smart-9f5616ef-ea4d-43bd-b7a5-412880f53e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063263527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.4063263527
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1758297609
Short name T881
Test name
Test status
Simulation time 11826831 ps
CPU time 0.71 seconds
Started Aug 11 05:18:24 PM PDT 24
Finished Aug 11 05:18:25 PM PDT 24
Peak memory 205100 kb
Host smart-48563c67-594f-464d-a0b4-0f5cfa2c3b45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758297609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
758297609
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.960229538
Short name T613
Test name
Test status
Simulation time 825643874 ps
CPU time 7.3 seconds
Started Aug 11 05:18:17 PM PDT 24
Finished Aug 11 05:18:24 PM PDT 24
Peak memory 224804 kb
Host smart-cd1d22ac-855d-4a54-9914-04806ae65387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960229538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.960229538
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.298815278
Short name T319
Test name
Test status
Simulation time 44146015 ps
CPU time 0.8 seconds
Started Aug 11 05:18:18 PM PDT 24
Finished Aug 11 05:18:19 PM PDT 24
Peak memory 206888 kb
Host smart-f1647cc0-72f0-4971-895f-1d86c9700eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298815278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.298815278
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2476792893
Short name T431
Test name
Test status
Simulation time 39113380 ps
CPU time 0.75 seconds
Started Aug 11 05:18:26 PM PDT 24
Finished Aug 11 05:18:27 PM PDT 24
Peak memory 216036 kb
Host smart-77e57bbe-9395-41ac-9ae0-d090fce8dc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476792893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2476792893
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.491522201
Short name T32
Test name
Test status
Simulation time 12021028852 ps
CPU time 62.11 seconds
Started Aug 11 05:18:24 PM PDT 24
Finished Aug 11 05:19:26 PM PDT 24
Peak memory 235264 kb
Host smart-420225f0-1228-4fcd-b364-edf6228991fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491522201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.491522201
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1366502545
Short name T225
Test name
Test status
Simulation time 9371010418 ps
CPU time 99.53 seconds
Started Aug 11 05:18:26 PM PDT 24
Finished Aug 11 05:20:05 PM PDT 24
Peak memory 252496 kb
Host smart-0003f648-fd00-4783-b9c3-f03f443bb692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366502545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1366502545
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3411729689
Short name T297
Test name
Test status
Simulation time 1971648692 ps
CPU time 27.39 seconds
Started Aug 11 05:18:19 PM PDT 24
Finished Aug 11 05:18:46 PM PDT 24
Peak memory 231980 kb
Host smart-f5b9a324-60e4-4f1b-83fc-bf96648374fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411729689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3411729689
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1462509302
Short name T655
Test name
Test status
Simulation time 4416087381 ps
CPU time 9.33 seconds
Started Aug 11 05:18:20 PM PDT 24
Finished Aug 11 05:18:29 PM PDT 24
Peak memory 232024 kb
Host smart-4f559696-bb90-4d91-b104-70f1b2cddc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462509302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1462509302
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.549215558
Short name T539
Test name
Test status
Simulation time 1499155644 ps
CPU time 7.43 seconds
Started Aug 11 05:18:17 PM PDT 24
Finished Aug 11 05:18:24 PM PDT 24
Peak memory 233012 kb
Host smart-fb52ce78-d275-40ba-9c6e-7b2970bb3e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549215558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.549215558
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3843705257
Short name T529
Test name
Test status
Simulation time 380414636 ps
CPU time 3.17 seconds
Started Aug 11 05:18:16 PM PDT 24
Finished Aug 11 05:18:20 PM PDT 24
Peak memory 233104 kb
Host smart-33fbc781-b480-42f2-8e2a-899073040a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843705257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3843705257
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4034331881
Short name T397
Test name
Test status
Simulation time 1061037736 ps
CPU time 5.56 seconds
Started Aug 11 05:18:16 PM PDT 24
Finished Aug 11 05:18:22 PM PDT 24
Peak memory 233032 kb
Host smart-39a4fc86-46db-46e5-bac2-2e3883ae674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034331881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4034331881
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1307686797
Short name T593
Test name
Test status
Simulation time 609940810 ps
CPU time 6.17 seconds
Started Aug 11 05:18:26 PM PDT 24
Finished Aug 11 05:18:33 PM PDT 24
Peak memory 223536 kb
Host smart-c730655d-5d0b-4fb0-9511-112296b0109f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1307686797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1307686797
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2008933769
Short name T72
Test name
Test status
Simulation time 84592307 ps
CPU time 1.18 seconds
Started Aug 11 05:18:26 PM PDT 24
Finished Aug 11 05:18:27 PM PDT 24
Peak memory 236780 kb
Host smart-350c85d2-6fe6-4bae-a941-2797da51c4f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008933769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2008933769
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1941779553
Short name T21
Test name
Test status
Simulation time 20204224199 ps
CPU time 213.63 seconds
Started Aug 11 05:18:24 PM PDT 24
Finished Aug 11 05:21:58 PM PDT 24
Peak memory 249488 kb
Host smart-ea838a10-d664-4a48-8405-8fadced15e7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941779553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1941779553
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3286152626
Short name T986
Test name
Test status
Simulation time 2323025943 ps
CPU time 14.9 seconds
Started Aug 11 05:18:20 PM PDT 24
Finished Aug 11 05:18:34 PM PDT 24
Peak memory 215592 kb
Host smart-c946e562-d156-487d-8750-d82da938094c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286152626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3286152626
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2400948196
Short name T336
Test name
Test status
Simulation time 1594889008 ps
CPU time 6.61 seconds
Started Aug 11 05:18:17 PM PDT 24
Finished Aug 11 05:18:24 PM PDT 24
Peak memory 216520 kb
Host smart-b31bf54d-965e-4c03-a2ef-efc9dffade6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400948196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2400948196
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2864390975
Short name T1006
Test name
Test status
Simulation time 144777185 ps
CPU time 2.81 seconds
Started Aug 11 05:18:26 PM PDT 24
Finished Aug 11 05:18:29 PM PDT 24
Peak memory 216636 kb
Host smart-5dfb6f4f-42e6-4e42-8525-e4b9bd9e11cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864390975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2864390975
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3876109835
Short name T53
Test name
Test status
Simulation time 76543774 ps
CPU time 0.78 seconds
Started Aug 11 05:18:17 PM PDT 24
Finished Aug 11 05:18:18 PM PDT 24
Peak memory 206260 kb
Host smart-1605ce94-7e98-44d8-a133-8f40181269fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876109835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3876109835
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2595864061
Short name T781
Test name
Test status
Simulation time 1088030234 ps
CPU time 3.74 seconds
Started Aug 11 05:18:18 PM PDT 24
Finished Aug 11 05:18:22 PM PDT 24
Peak memory 224768 kb
Host smart-aa9251bb-5e36-403e-9f31-041c0e5632af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595864061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2595864061
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.139103979
Short name T849
Test name
Test status
Simulation time 12639690 ps
CPU time 0.71 seconds
Started Aug 11 05:21:07 PM PDT 24
Finished Aug 11 05:21:08 PM PDT 24
Peak memory 205764 kb
Host smart-e4440b92-21b0-4d35-8334-762e06ca43ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139103979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.139103979
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3123725605
Short name T496
Test name
Test status
Simulation time 33313420 ps
CPU time 2.43 seconds
Started Aug 11 05:21:05 PM PDT 24
Finished Aug 11 05:21:07 PM PDT 24
Peak memory 232748 kb
Host smart-44931b03-5156-4814-8ab1-8a74d14d861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123725605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3123725605
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.547871724
Short name T674
Test name
Test status
Simulation time 61072566 ps
CPU time 0.76 seconds
Started Aug 11 05:21:02 PM PDT 24
Finished Aug 11 05:21:03 PM PDT 24
Peak memory 205840 kb
Host smart-05513c25-6ee6-4619-8f55-9203538f8822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547871724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.547871724
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.730455610
Short name T390
Test name
Test status
Simulation time 41270326827 ps
CPU time 102.6 seconds
Started Aug 11 05:21:06 PM PDT 24
Finished Aug 11 05:22:49 PM PDT 24
Peak memory 249468 kb
Host smart-caaa96e1-0f64-40c2-b3c7-55d76962bfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730455610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.730455610
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1152024176
Short name T244
Test name
Test status
Simulation time 39528230422 ps
CPU time 130.71 seconds
Started Aug 11 05:21:05 PM PDT 24
Finished Aug 11 05:23:16 PM PDT 24
Peak memory 251416 kb
Host smart-858f7901-74e1-42f4-8b6b-0408a12ffe72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152024176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1152024176
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2697442414
Short name T268
Test name
Test status
Simulation time 9632210453 ps
CPU time 123 seconds
Started Aug 11 05:21:05 PM PDT 24
Finished Aug 11 05:23:08 PM PDT 24
Peak memory 255264 kb
Host smart-7311d481-4587-40af-81c9-4687896a2e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697442414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2697442414
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3006446960
Short name T619
Test name
Test status
Simulation time 753148724 ps
CPU time 4.15 seconds
Started Aug 11 05:21:11 PM PDT 24
Finished Aug 11 05:21:15 PM PDT 24
Peak memory 224900 kb
Host smart-71c9d2d0-c7eb-425a-9124-76ea68f7649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006446960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3006446960
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2684866918
Short name T903
Test name
Test status
Simulation time 11019476994 ps
CPU time 97.38 seconds
Started Aug 11 05:21:11 PM PDT 24
Finished Aug 11 05:22:48 PM PDT 24
Peak memory 251944 kb
Host smart-56a04984-66f8-4332-8810-5d561927c41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684866918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2684866918
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1642841098
Short name T489
Test name
Test status
Simulation time 352115339 ps
CPU time 2.19 seconds
Started Aug 11 05:21:09 PM PDT 24
Finished Aug 11 05:21:11 PM PDT 24
Peak memory 224160 kb
Host smart-08ec1409-e7fa-4303-8691-c9b024ca6efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642841098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1642841098
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1631462151
Short name T215
Test name
Test status
Simulation time 2615500545 ps
CPU time 27.68 seconds
Started Aug 11 05:21:06 PM PDT 24
Finished Aug 11 05:21:34 PM PDT 24
Peak memory 241248 kb
Host smart-e6a435c0-c052-4dc3-a52e-279b63ca89c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631462151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1631462151
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2368093750
Short name T552
Test name
Test status
Simulation time 1143689590 ps
CPU time 3.55 seconds
Started Aug 11 05:21:09 PM PDT 24
Finished Aug 11 05:21:13 PM PDT 24
Peak memory 233104 kb
Host smart-73663e2d-9685-4ba2-aac1-9cd13e575ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368093750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2368093750
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3571911111
Short name T951
Test name
Test status
Simulation time 2331043222 ps
CPU time 9.44 seconds
Started Aug 11 05:21:07 PM PDT 24
Finished Aug 11 05:21:17 PM PDT 24
Peak memory 219832 kb
Host smart-e37b04cb-fb86-4d3b-a998-6189759334f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3571911111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3571911111
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1034238810
Short name T954
Test name
Test status
Simulation time 35238609817 ps
CPU time 234.29 seconds
Started Aug 11 05:21:10 PM PDT 24
Finished Aug 11 05:25:04 PM PDT 24
Peak memory 249684 kb
Host smart-a3e91e04-d6c5-4652-8da2-51f75c5f69e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034238810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1034238810
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2948058928
Short name T558
Test name
Test status
Simulation time 1727224313 ps
CPU time 27.32 seconds
Started Aug 11 05:20:59 PM PDT 24
Finished Aug 11 05:21:26 PM PDT 24
Peak memory 216652 kb
Host smart-2f617fcd-eb99-4901-a037-e7f3e2a91c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948058928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2948058928
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3157931361
Short name T361
Test name
Test status
Simulation time 12463116380 ps
CPU time 9.83 seconds
Started Aug 11 05:20:59 PM PDT 24
Finished Aug 11 05:21:09 PM PDT 24
Peak memory 216736 kb
Host smart-4f228519-a057-422f-980c-3b7393fbe83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157931361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3157931361
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.605737746
Short name T466
Test name
Test status
Simulation time 347793885 ps
CPU time 2.05 seconds
Started Aug 11 05:21:02 PM PDT 24
Finished Aug 11 05:21:04 PM PDT 24
Peak memory 216596 kb
Host smart-8b9ee1ce-290a-4bf1-bbba-e865a154c818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605737746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.605737746
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3797548698
Short name T827
Test name
Test status
Simulation time 44326477 ps
CPU time 0.76 seconds
Started Aug 11 05:20:59 PM PDT 24
Finished Aug 11 05:21:00 PM PDT 24
Peak memory 206144 kb
Host smart-fdc6cd73-9606-42a7-90bc-6b18bae5401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797548698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3797548698
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.4064710850
Short name T559
Test name
Test status
Simulation time 2353761658 ps
CPU time 13.96 seconds
Started Aug 11 05:21:10 PM PDT 24
Finished Aug 11 05:21:24 PM PDT 24
Peak memory 234348 kb
Host smart-bc0399f5-a5f3-4550-9d3b-3e4b367a40c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064710850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4064710850
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.405736337
Short name T66
Test name
Test status
Simulation time 12262772 ps
CPU time 0.76 seconds
Started Aug 11 05:21:13 PM PDT 24
Finished Aug 11 05:21:14 PM PDT 24
Peak memory 205672 kb
Host smart-b727c5e6-6c71-43d1-a559-ee963a630fb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405736337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.405736337
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.766141192
Short name T839
Test name
Test status
Simulation time 160117567 ps
CPU time 2.6 seconds
Started Aug 11 05:21:12 PM PDT 24
Finished Aug 11 05:21:14 PM PDT 24
Peak memory 233040 kb
Host smart-72fac712-28d5-45a8-9ca0-c0bbf74054b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766141192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.766141192
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.337808878
Short name T391
Test name
Test status
Simulation time 87390126 ps
CPU time 0.83 seconds
Started Aug 11 05:21:07 PM PDT 24
Finished Aug 11 05:21:08 PM PDT 24
Peak memory 206880 kb
Host smart-dc474164-adb5-423a-9486-05f17e24a834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337808878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.337808878
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.649130540
Short name T652
Test name
Test status
Simulation time 59198744414 ps
CPU time 183.25 seconds
Started Aug 11 05:21:12 PM PDT 24
Finished Aug 11 05:24:15 PM PDT 24
Peak memory 250176 kb
Host smart-89c7ebca-7d02-41c5-85e6-be7e567e556d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649130540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.649130540
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2234815410
Short name T697
Test name
Test status
Simulation time 54071058464 ps
CPU time 361.2 seconds
Started Aug 11 05:21:12 PM PDT 24
Finished Aug 11 05:27:14 PM PDT 24
Peak memory 265920 kb
Host smart-704b992b-cd0e-44cb-9cbc-1f24e9bcc8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234815410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2234815410
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.418916022
Short name T302
Test name
Test status
Simulation time 8919587992 ps
CPU time 30.58 seconds
Started Aug 11 05:21:11 PM PDT 24
Finished Aug 11 05:21:41 PM PDT 24
Peak memory 249532 kb
Host smart-ea5efc78-2d1e-40e5-adde-4c2385d55eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418916022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.418916022
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.940656279
Short name T213
Test name
Test status
Simulation time 15229916067 ps
CPU time 17.54 seconds
Started Aug 11 05:21:15 PM PDT 24
Finished Aug 11 05:21:33 PM PDT 24
Peak memory 234376 kb
Host smart-e7ba6b2f-98b8-443d-80b2-b16f85f35d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940656279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.940656279
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.143289829
Short name T893
Test name
Test status
Simulation time 186486195 ps
CPU time 4.37 seconds
Started Aug 11 05:21:08 PM PDT 24
Finished Aug 11 05:21:12 PM PDT 24
Peak memory 224672 kb
Host smart-8ce68435-fac5-4479-be79-6982812cce27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143289829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.143289829
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1371976705
Short name T914
Test name
Test status
Simulation time 545330057 ps
CPU time 13.29 seconds
Started Aug 11 05:21:06 PM PDT 24
Finished Aug 11 05:21:19 PM PDT 24
Peak memory 233016 kb
Host smart-1f7f8cec-0cb5-4276-a5de-2f2af8e4b10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371976705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1371976705
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2574196361
Short name T263
Test name
Test status
Simulation time 4484685971 ps
CPU time 15.22 seconds
Started Aug 11 05:21:08 PM PDT 24
Finished Aug 11 05:21:23 PM PDT 24
Peak memory 224800 kb
Host smart-6fc1e376-9ccb-48fe-8342-f3553335e560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574196361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2574196361
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1857030245
Short name T368
Test name
Test status
Simulation time 2059175768 ps
CPU time 7.46 seconds
Started Aug 11 05:21:08 PM PDT 24
Finished Aug 11 05:21:16 PM PDT 24
Peak memory 233024 kb
Host smart-0b0087c2-6d9d-47cf-b396-7f9c52f169b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857030245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1857030245
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1564111480
Short name T338
Test name
Test status
Simulation time 705385643 ps
CPU time 7.05 seconds
Started Aug 11 05:21:11 PM PDT 24
Finished Aug 11 05:21:19 PM PDT 24
Peak memory 219256 kb
Host smart-78f3383f-7f27-4816-85f5-16d079e9f324
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1564111480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1564111480
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2858064498
Short name T930
Test name
Test status
Simulation time 135405082074 ps
CPU time 693.32 seconds
Started Aug 11 05:21:13 PM PDT 24
Finished Aug 11 05:32:47 PM PDT 24
Peak memory 270908 kb
Host smart-121aac10-6a3e-46c3-9af2-2ae91064f08c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858064498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2858064498
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1442889596
Short name T6
Test name
Test status
Simulation time 1290069170 ps
CPU time 5.01 seconds
Started Aug 11 05:21:06 PM PDT 24
Finished Aug 11 05:21:11 PM PDT 24
Peak memory 216536 kb
Host smart-9678b184-ab2b-4110-b3b7-0b182164380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442889596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1442889596
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.938675212
Short name T933
Test name
Test status
Simulation time 106710736 ps
CPU time 1.37 seconds
Started Aug 11 05:21:07 PM PDT 24
Finished Aug 11 05:21:08 PM PDT 24
Peak memory 216672 kb
Host smart-743e2f1a-ca75-49bd-b443-8b684dba3393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938675212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.938675212
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1217659796
Short name T783
Test name
Test status
Simulation time 146763995 ps
CPU time 0.85 seconds
Started Aug 11 05:21:10 PM PDT 24
Finished Aug 11 05:21:11 PM PDT 24
Peak memory 206344 kb
Host smart-6c40daa1-0561-450a-9e74-584c07980138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217659796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1217659796
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3801970442
Short name T459
Test name
Test status
Simulation time 1317911227 ps
CPU time 10.1 seconds
Started Aug 11 05:21:13 PM PDT 24
Finished Aug 11 05:21:24 PM PDT 24
Peak memory 238264 kb
Host smart-f74a165d-d4d2-4cae-b97b-d29e4f97ee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801970442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3801970442
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3401163550
Short name T375
Test name
Test status
Simulation time 22142332 ps
CPU time 0.69 seconds
Started Aug 11 05:21:22 PM PDT 24
Finished Aug 11 05:21:23 PM PDT 24
Peak memory 205748 kb
Host smart-79894b32-afba-4c83-95c3-dbe4e6a88916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401163550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3401163550
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1554119455
Short name T352
Test name
Test status
Simulation time 103398792 ps
CPU time 2.06 seconds
Started Aug 11 05:21:19 PM PDT 24
Finished Aug 11 05:21:21 PM PDT 24
Peak memory 224896 kb
Host smart-c8dccb82-baa1-4c40-a692-6398c4709526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554119455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1554119455
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1535621194
Short name T889
Test name
Test status
Simulation time 62453351 ps
CPU time 0.85 seconds
Started Aug 11 05:21:12 PM PDT 24
Finished Aug 11 05:21:13 PM PDT 24
Peak memory 206892 kb
Host smart-5a1b30b8-5a2f-4e8e-bf34-3e85b11b193d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535621194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1535621194
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3956629600
Short name T799
Test name
Test status
Simulation time 103937006315 ps
CPU time 171.72 seconds
Started Aug 11 05:21:17 PM PDT 24
Finished Aug 11 05:24:09 PM PDT 24
Peak memory 249560 kb
Host smart-7aa40e1f-0109-4064-90b2-dc798fa82262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956629600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3956629600
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2699502383
Short name T949
Test name
Test status
Simulation time 37158400246 ps
CPU time 233.85 seconds
Started Aug 11 05:21:22 PM PDT 24
Finished Aug 11 05:25:16 PM PDT 24
Peak memory 254632 kb
Host smart-bdd9d1a1-975a-4ee4-a422-0b84b0e9652a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699502383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2699502383
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3958448108
Short name T362
Test name
Test status
Simulation time 7541288942 ps
CPU time 92.83 seconds
Started Aug 11 05:21:20 PM PDT 24
Finished Aug 11 05:22:53 PM PDT 24
Peak memory 255064 kb
Host smart-ca1ec397-ad23-4d87-b2ca-58bee5f8123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958448108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3958448108
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.373028993
Short name T455
Test name
Test status
Simulation time 2623726141 ps
CPU time 14.03 seconds
Started Aug 11 05:21:17 PM PDT 24
Finished Aug 11 05:21:31 PM PDT 24
Peak memory 224776 kb
Host smart-458f6d00-b69b-4c1d-bc4f-dc448defbf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373028993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.373028993
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1319561674
Short name T449
Test name
Test status
Simulation time 11712882579 ps
CPU time 85.32 seconds
Started Aug 11 05:21:22 PM PDT 24
Finished Aug 11 05:22:48 PM PDT 24
Peak memory 257688 kb
Host smart-8957c467-3aa3-4f96-b767-b1d627a71d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319561674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1319561674
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.4018954861
Short name T793
Test name
Test status
Simulation time 36514682 ps
CPU time 2.51 seconds
Started Aug 11 05:21:20 PM PDT 24
Finished Aug 11 05:21:23 PM PDT 24
Peak memory 232664 kb
Host smart-db6955fa-27ee-4c86-b658-cd57f604c90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018954861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4018954861
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1879323624
Short name T763
Test name
Test status
Simulation time 10183644894 ps
CPU time 93.1 seconds
Started Aug 11 05:21:20 PM PDT 24
Finished Aug 11 05:22:53 PM PDT 24
Peak memory 233148 kb
Host smart-cbc67d78-9ca5-4811-ac3d-2d5de7370524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879323624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1879323624
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3274604543
Short name T967
Test name
Test status
Simulation time 24137407954 ps
CPU time 19.08 seconds
Started Aug 11 05:21:19 PM PDT 24
Finished Aug 11 05:21:38 PM PDT 24
Peak memory 233048 kb
Host smart-df006f5c-873c-4a88-9fc2-bb9a1b0f950d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274604543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3274604543
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2864672520
Short name T243
Test name
Test status
Simulation time 22371624149 ps
CPU time 31.26 seconds
Started Aug 11 05:21:19 PM PDT 24
Finished Aug 11 05:21:50 PM PDT 24
Peak memory 224836 kb
Host smart-ee1da2b7-ffb7-418b-a4c7-7a9346f5d2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864672520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2864672520
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2025406356
Short name T624
Test name
Test status
Simulation time 3330510189 ps
CPU time 15.5 seconds
Started Aug 11 05:21:19 PM PDT 24
Finished Aug 11 05:21:35 PM PDT 24
Peak memory 223028 kb
Host smart-2dffbe89-e92e-4ed5-844c-c927e107d92e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2025406356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2025406356
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3627888594
Short name T154
Test name
Test status
Simulation time 16458996913 ps
CPU time 96.36 seconds
Started Aug 11 05:21:18 PM PDT 24
Finished Aug 11 05:22:54 PM PDT 24
Peak memory 267864 kb
Host smart-b345b7f7-fc4f-4d44-a402-49f5f2153284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627888594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3627888594
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4154673767
Short name T614
Test name
Test status
Simulation time 7280629883 ps
CPU time 38.11 seconds
Started Aug 11 05:21:11 PM PDT 24
Finished Aug 11 05:21:49 PM PDT 24
Peak memory 216596 kb
Host smart-ab1a50a1-9fa3-4f3b-9057-98e366e90f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154673767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4154673767
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.309342099
Short name T771
Test name
Test status
Simulation time 31554131578 ps
CPU time 23.52 seconds
Started Aug 11 05:21:14 PM PDT 24
Finished Aug 11 05:21:38 PM PDT 24
Peak memory 217984 kb
Host smart-0754e03d-35d3-4e4c-8559-565d24bade6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309342099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.309342099
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1092016677
Short name T324
Test name
Test status
Simulation time 160603030 ps
CPU time 1.12 seconds
Started Aug 11 05:21:17 PM PDT 24
Finished Aug 11 05:21:18 PM PDT 24
Peak memory 208176 kb
Host smart-fc659fae-4683-49c2-9438-c38df69aab83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092016677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1092016677
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2162700620
Short name T344
Test name
Test status
Simulation time 129208775 ps
CPU time 0.78 seconds
Started Aug 11 05:21:13 PM PDT 24
Finished Aug 11 05:21:14 PM PDT 24
Peak memory 206136 kb
Host smart-8b99913c-14b3-4c10-84cc-75d37d939ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162700620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2162700620
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2681453134
Short name T513
Test name
Test status
Simulation time 3308883710 ps
CPU time 12.83 seconds
Started Aug 11 05:21:18 PM PDT 24
Finished Aug 11 05:21:31 PM PDT 24
Peak memory 233040 kb
Host smart-66227e6e-7b30-47e7-bdee-be2b9fe7b81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681453134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2681453134
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.450968074
Short name T688
Test name
Test status
Simulation time 32643625 ps
CPU time 0.8 seconds
Started Aug 11 05:21:34 PM PDT 24
Finished Aug 11 05:21:34 PM PDT 24
Peak memory 205776 kb
Host smart-429809d2-d2d4-4049-a5db-64069d88b510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450968074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.450968074
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2873275562
Short name T591
Test name
Test status
Simulation time 294334866 ps
CPU time 3.1 seconds
Started Aug 11 05:21:24 PM PDT 24
Finished Aug 11 05:21:28 PM PDT 24
Peak memory 233364 kb
Host smart-b042bd63-e2c3-496b-9207-4e246987feba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873275562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2873275562
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2448699707
Short name T600
Test name
Test status
Simulation time 20904297 ps
CPU time 0.75 seconds
Started Aug 11 05:21:26 PM PDT 24
Finished Aug 11 05:21:26 PM PDT 24
Peak memory 206844 kb
Host smart-653f89f9-82d5-4379-8e2b-2f1ea40c6fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448699707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2448699707
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1724007356
Short name T687
Test name
Test status
Simulation time 43401043554 ps
CPU time 87.24 seconds
Started Aug 11 05:21:31 PM PDT 24
Finished Aug 11 05:22:58 PM PDT 24
Peak memory 257176 kb
Host smart-535146e6-3788-45ac-849a-0bb9b6fdec51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724007356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1724007356
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1780122500
Short name T314
Test name
Test status
Simulation time 10623259143 ps
CPU time 60.87 seconds
Started Aug 11 05:21:32 PM PDT 24
Finished Aug 11 05:22:33 PM PDT 24
Peak memory 249548 kb
Host smart-52100819-607d-4c7f-88ec-0bc538364d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780122500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1780122500
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.767129385
Short name T158
Test name
Test status
Simulation time 21815012868 ps
CPU time 169.76 seconds
Started Aug 11 05:21:33 PM PDT 24
Finished Aug 11 05:24:23 PM PDT 24
Peak memory 241420 kb
Host smart-32987394-f6e2-4cab-84c7-1c11d0bd1949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767129385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.767129385
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3437884475
Short name T325
Test name
Test status
Simulation time 111864788 ps
CPU time 2.79 seconds
Started Aug 11 05:21:30 PM PDT 24
Finished Aug 11 05:21:32 PM PDT 24
Peak memory 233116 kb
Host smart-7cc9f96e-5bcc-431a-8c12-aa459c562195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437884475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3437884475
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1827915482
Short name T879
Test name
Test status
Simulation time 47468043797 ps
CPU time 334.51 seconds
Started Aug 11 05:21:31 PM PDT 24
Finished Aug 11 05:27:06 PM PDT 24
Peak memory 250548 kb
Host smart-4c5f5a16-f9df-4f32-bb24-7075b2d0ed06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827915482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1827915482
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1258165214
Short name T193
Test name
Test status
Simulation time 15116630934 ps
CPU time 31.86 seconds
Started Aug 11 05:21:24 PM PDT 24
Finished Aug 11 05:21:56 PM PDT 24
Peak memory 224832 kb
Host smart-52aca9cc-0b8a-4173-ad18-35b9030b9ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258165214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1258165214
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.10451880
Short name T46
Test name
Test status
Simulation time 694645976 ps
CPU time 9.47 seconds
Started Aug 11 05:21:25 PM PDT 24
Finished Aug 11 05:21:35 PM PDT 24
Peak memory 233088 kb
Host smart-4646cbc6-32ca-4f14-b2f6-aa7dd8328504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10451880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.10451880
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.4166841550
Short name T249
Test name
Test status
Simulation time 256251226 ps
CPU time 6.77 seconds
Started Aug 11 05:21:25 PM PDT 24
Finished Aug 11 05:21:31 PM PDT 24
Peak memory 249440 kb
Host smart-61b9b381-3fce-45d8-b114-ee7c4deace39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166841550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.4166841550
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4236242140
Short name T2
Test name
Test status
Simulation time 27126465398 ps
CPU time 7.04 seconds
Started Aug 11 05:21:25 PM PDT 24
Finished Aug 11 05:21:32 PM PDT 24
Peak memory 224948 kb
Host smart-46f5f9af-3b6b-4606-8441-7793978ffa7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236242140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4236242140
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3729448395
Short name T567
Test name
Test status
Simulation time 6574480486 ps
CPU time 9.62 seconds
Started Aug 11 05:21:33 PM PDT 24
Finished Aug 11 05:21:43 PM PDT 24
Peak memory 221296 kb
Host smart-74029c3c-f795-43e0-85bb-53d61b4788ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3729448395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3729448395
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1539166998
Short name T746
Test name
Test status
Simulation time 14418413683 ps
CPU time 21.25 seconds
Started Aug 11 05:21:25 PM PDT 24
Finished Aug 11 05:21:46 PM PDT 24
Peak memory 216796 kb
Host smart-284d4fd6-a502-461f-9c10-4563f2adbbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539166998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1539166998
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3989998440
Short name T683
Test name
Test status
Simulation time 5363309527 ps
CPU time 5.4 seconds
Started Aug 11 05:21:25 PM PDT 24
Finished Aug 11 05:21:31 PM PDT 24
Peak memory 216692 kb
Host smart-4f7c9739-44f9-4701-8238-cd832a067b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989998440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3989998440
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2801744421
Short name T662
Test name
Test status
Simulation time 31613367 ps
CPU time 0.69 seconds
Started Aug 11 05:21:24 PM PDT 24
Finished Aug 11 05:21:24 PM PDT 24
Peak memory 205920 kb
Host smart-1e9b90ac-4432-40d2-82a4-1e9a987f90d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801744421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2801744421
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3154966304
Short name T329
Test name
Test status
Simulation time 44784287 ps
CPU time 0.78 seconds
Started Aug 11 05:21:25 PM PDT 24
Finished Aug 11 05:21:26 PM PDT 24
Peak memory 206292 kb
Host smart-2c3f693b-1b4f-4311-8514-cf892e58dcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154966304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3154966304
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.690162416
Short name T15
Test name
Test status
Simulation time 974240478 ps
CPU time 7.67 seconds
Started Aug 11 05:21:25 PM PDT 24
Finished Aug 11 05:21:32 PM PDT 24
Peak memory 233052 kb
Host smart-1ee07f9b-631d-42f7-a76f-51be38f8907b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690162416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.690162416
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2330927804
Short name T936
Test name
Test status
Simulation time 21251255 ps
CPU time 0.72 seconds
Started Aug 11 05:21:37 PM PDT 24
Finished Aug 11 05:21:38 PM PDT 24
Peak memory 205176 kb
Host smart-cd3c3393-f72f-49c9-b23f-692f2530b9d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330927804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2330927804
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.114304495
Short name T396
Test name
Test status
Simulation time 898751188 ps
CPU time 6.72 seconds
Started Aug 11 05:21:39 PM PDT 24
Finished Aug 11 05:21:46 PM PDT 24
Peak memory 233116 kb
Host smart-702c8c13-890f-4297-82f3-b739a12626c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114304495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.114304495
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.442213052
Short name T427
Test name
Test status
Simulation time 74044883 ps
CPU time 0.76 seconds
Started Aug 11 05:21:30 PM PDT 24
Finished Aug 11 05:21:31 PM PDT 24
Peak memory 207136 kb
Host smart-eca0f59d-777a-4a6a-95eb-60065d0ea5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442213052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.442213052
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.4018196813
Short name T636
Test name
Test status
Simulation time 4708821078 ps
CPU time 20.62 seconds
Started Aug 11 05:21:36 PM PDT 24
Finished Aug 11 05:21:57 PM PDT 24
Peak memory 241172 kb
Host smart-6ea29571-c8de-41d5-aa7c-7198cc480e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018196813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.4018196813
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.78128975
Short name T612
Test name
Test status
Simulation time 24058547746 ps
CPU time 68.58 seconds
Started Aug 11 05:21:36 PM PDT 24
Finished Aug 11 05:22:45 PM PDT 24
Peak memory 249604 kb
Host smart-3f1fb051-47c6-459d-b8a5-4a97c471f013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78128975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.78128975
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3100267830
Short name T979
Test name
Test status
Simulation time 22679743059 ps
CPU time 68.49 seconds
Started Aug 11 05:21:36 PM PDT 24
Finished Aug 11 05:22:45 PM PDT 24
Peak memory 254040 kb
Host smart-e3a1919f-175f-40ec-8b18-fac76550c09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100267830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3100267830
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.914074058
Short name T794
Test name
Test status
Simulation time 7365675652 ps
CPU time 6.97 seconds
Started Aug 11 05:21:44 PM PDT 24
Finished Aug 11 05:21:51 PM PDT 24
Peak memory 224812 kb
Host smart-27be3398-30e1-47f8-ba8d-a6aa4d098aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914074058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.914074058
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3224932826
Short name T364
Test name
Test status
Simulation time 16856247116 ps
CPU time 62.54 seconds
Started Aug 11 05:21:36 PM PDT 24
Finished Aug 11 05:22:38 PM PDT 24
Peak memory 255012 kb
Host smart-d924130a-1188-43cb-bcca-fa1368573f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224932826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3224932826
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.532866578
Short name T366
Test name
Test status
Simulation time 193290408 ps
CPU time 4.88 seconds
Started Aug 11 05:21:31 PM PDT 24
Finished Aug 11 05:21:36 PM PDT 24
Peak memory 224828 kb
Host smart-203d3e24-0bf1-4b23-8ead-56da9bc6e21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532866578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.532866578
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2076488279
Short name T189
Test name
Test status
Simulation time 3861556883 ps
CPU time 25.57 seconds
Started Aug 11 05:21:36 PM PDT 24
Finished Aug 11 05:22:02 PM PDT 24
Peak memory 233316 kb
Host smart-90175cf3-10cf-4a7a-a5c3-42cec2d8dc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076488279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2076488279
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3217330822
Short name T797
Test name
Test status
Simulation time 30107782218 ps
CPU time 22.81 seconds
Started Aug 11 05:21:31 PM PDT 24
Finished Aug 11 05:21:54 PM PDT 24
Peak memory 233160 kb
Host smart-34e98641-5c22-4407-99e0-0fde63d19cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217330822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3217330822
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1959752221
Short name T258
Test name
Test status
Simulation time 2297838264 ps
CPU time 8.35 seconds
Started Aug 11 05:21:29 PM PDT 24
Finished Aug 11 05:21:38 PM PDT 24
Peak memory 233112 kb
Host smart-429301a6-00dd-4c95-827e-fbc30f83550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959752221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1959752221
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.275450180
Short name T855
Test name
Test status
Simulation time 1093920749 ps
CPU time 8.43 seconds
Started Aug 11 05:21:38 PM PDT 24
Finished Aug 11 05:21:47 PM PDT 24
Peak memory 219328 kb
Host smart-cb4a342d-255b-4638-8a47-e7479de9afcd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=275450180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.275450180
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1196259509
Short name T24
Test name
Test status
Simulation time 1936481408 ps
CPU time 13.29 seconds
Started Aug 11 05:21:31 PM PDT 24
Finished Aug 11 05:21:44 PM PDT 24
Peak memory 216564 kb
Host smart-d39e0da7-fc65-499e-a71e-f3a582e70d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196259509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1196259509
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3051644228
Short name T482
Test name
Test status
Simulation time 709795014 ps
CPU time 2.32 seconds
Started Aug 11 05:21:31 PM PDT 24
Finished Aug 11 05:21:33 PM PDT 24
Peak memory 216440 kb
Host smart-42ec2927-e993-42d1-ab15-1a4dc23ea83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051644228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3051644228
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1935154930
Short name T788
Test name
Test status
Simulation time 72046320 ps
CPU time 1 seconds
Started Aug 11 05:21:31 PM PDT 24
Finished Aug 11 05:21:32 PM PDT 24
Peak memory 208164 kb
Host smart-2a5d776e-0eca-473d-95fd-8d2517046f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935154930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1935154930
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1270516835
Short name T428
Test name
Test status
Simulation time 30362310 ps
CPU time 0.82 seconds
Started Aug 11 05:21:33 PM PDT 24
Finished Aug 11 05:21:34 PM PDT 24
Peak memory 206216 kb
Host smart-b243db25-d821-45a7-9094-5bc341932d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270516835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1270516835
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1525232651
Short name T627
Test name
Test status
Simulation time 1185861747 ps
CPU time 9.38 seconds
Started Aug 11 05:21:36 PM PDT 24
Finished Aug 11 05:21:46 PM PDT 24
Peak memory 232984 kb
Host smart-cc2b74f5-33de-4e07-939a-a110555af785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525232651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1525232651
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4148785218
Short name T379
Test name
Test status
Simulation time 44658147 ps
CPU time 0.69 seconds
Started Aug 11 05:21:44 PM PDT 24
Finished Aug 11 05:21:45 PM PDT 24
Peak memory 205744 kb
Host smart-e7b67ffc-cb74-482d-bbe2-cd70400187a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148785218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4148785218
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1275868256
Short name T653
Test name
Test status
Simulation time 1587128050 ps
CPU time 6.94 seconds
Started Aug 11 05:21:46 PM PDT 24
Finished Aug 11 05:21:53 PM PDT 24
Peak memory 224864 kb
Host smart-3e20a7c9-1e38-442f-af0d-c13fa78c1f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275868256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1275868256
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.67224166
Short name T787
Test name
Test status
Simulation time 15863003 ps
CPU time 0.78 seconds
Started Aug 11 05:21:38 PM PDT 24
Finished Aug 11 05:21:39 PM PDT 24
Peak memory 206796 kb
Host smart-6011301b-5f94-4d5a-8f32-07ea852b0294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67224166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.67224166
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.50214017
Short name T35
Test name
Test status
Simulation time 5219554762 ps
CPU time 55.74 seconds
Started Aug 11 05:21:44 PM PDT 24
Finished Aug 11 05:22:40 PM PDT 24
Peak memory 255944 kb
Host smart-fff22449-734c-4eb8-9e78-40d0e2f92a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50214017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.50214017
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3701705882
Short name T829
Test name
Test status
Simulation time 7083177715 ps
CPU time 128.48 seconds
Started Aug 11 05:21:45 PM PDT 24
Finished Aug 11 05:23:54 PM PDT 24
Peak memory 257716 kb
Host smart-da2ac4b6-024c-4094-9002-91c1961a08f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701705882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3701705882
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.312962370
Short name T34
Test name
Test status
Simulation time 4621380919 ps
CPU time 64.42 seconds
Started Aug 11 05:21:46 PM PDT 24
Finished Aug 11 05:22:51 PM PDT 24
Peak memory 250688 kb
Host smart-b1c8b7b1-e573-4e94-bad0-9dfea0ce6bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312962370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.312962370
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3452825624
Short name T303
Test name
Test status
Simulation time 471785271 ps
CPU time 5.55 seconds
Started Aug 11 05:21:45 PM PDT 24
Finished Aug 11 05:21:51 PM PDT 24
Peak memory 233416 kb
Host smart-793289ea-99c0-4edc-a27f-f0127289185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452825624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3452825624
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2749054155
Short name T940
Test name
Test status
Simulation time 51952256328 ps
CPU time 101.46 seconds
Started Aug 11 05:21:45 PM PDT 24
Finished Aug 11 05:23:27 PM PDT 24
Peak memory 250756 kb
Host smart-9ef25d0a-f230-4286-a556-c356a68ba0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749054155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2749054155
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3998496034
Short name T768
Test name
Test status
Simulation time 717599286 ps
CPU time 9.73 seconds
Started Aug 11 05:21:43 PM PDT 24
Finished Aug 11 05:21:53 PM PDT 24
Peak memory 224928 kb
Host smart-3e93e5ed-d138-4c46-b272-f7243d8c7d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998496034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3998496034
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1158430061
Short name T871
Test name
Test status
Simulation time 1858480242 ps
CPU time 18.61 seconds
Started Aug 11 05:21:43 PM PDT 24
Finished Aug 11 05:22:02 PM PDT 24
Peak memory 232964 kb
Host smart-6e89db3a-5640-45ed-8a3d-968d6abecc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158430061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1158430061
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.513374056
Short name T44
Test name
Test status
Simulation time 10626705597 ps
CPU time 13.51 seconds
Started Aug 11 05:21:42 PM PDT 24
Finished Aug 11 05:21:56 PM PDT 24
Peak memory 233172 kb
Host smart-0e16abea-3fd4-44ce-a2cc-5388d84e1297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513374056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.513374056
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3042417714
Short name T63
Test name
Test status
Simulation time 29744937606 ps
CPU time 17.73 seconds
Started Aug 11 05:21:45 PM PDT 24
Finished Aug 11 05:22:03 PM PDT 24
Peak memory 234172 kb
Host smart-be280718-b838-46f8-ae5b-ca13bd266af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042417714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3042417714
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1079583820
Short name T711
Test name
Test status
Simulation time 254261509 ps
CPU time 5.22 seconds
Started Aug 11 05:21:47 PM PDT 24
Finished Aug 11 05:21:53 PM PDT 24
Peak memory 220792 kb
Host smart-36f0a05d-625e-4cd2-8556-a178a303a4cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1079583820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1079583820
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1935869631
Short name T22
Test name
Test status
Simulation time 67138443902 ps
CPU time 169.02 seconds
Started Aug 11 05:21:43 PM PDT 24
Finished Aug 11 05:24:33 PM PDT 24
Peak memory 241308 kb
Host smart-7981fa1b-6f81-47c7-ac22-2eae32ab5124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935869631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1935869631
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1342128977
Short name T654
Test name
Test status
Simulation time 29144313 ps
CPU time 0.74 seconds
Started Aug 11 05:21:39 PM PDT 24
Finished Aug 11 05:21:39 PM PDT 24
Peak memory 206008 kb
Host smart-35a50af7-e345-40e0-ae42-5dc3330ff5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342128977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1342128977
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2143737851
Short name T527
Test name
Test status
Simulation time 9135860929 ps
CPU time 14.11 seconds
Started Aug 11 05:21:35 PM PDT 24
Finished Aug 11 05:21:49 PM PDT 24
Peak memory 216620 kb
Host smart-0b8f6d2c-6e53-4185-86ba-75899173048b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143737851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2143737851
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2100302833
Short name T367
Test name
Test status
Simulation time 27834597 ps
CPU time 1.71 seconds
Started Aug 11 05:21:38 PM PDT 24
Finished Aug 11 05:21:40 PM PDT 24
Peak memory 216492 kb
Host smart-47f00843-0e0c-44ab-93ad-9eb4d60672ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100302833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2100302833
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1117495466
Short name T335
Test name
Test status
Simulation time 278374194 ps
CPU time 0.87 seconds
Started Aug 11 05:21:37 PM PDT 24
Finished Aug 11 05:21:38 PM PDT 24
Peak memory 206252 kb
Host smart-9a9e0918-caf6-409e-87ef-08495d5aecac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117495466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1117495466
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3595908398
Short name T503
Test name
Test status
Simulation time 1862238874 ps
CPU time 11.92 seconds
Started Aug 11 05:21:46 PM PDT 24
Finished Aug 11 05:21:58 PM PDT 24
Peak memory 232968 kb
Host smart-92f85e1d-4a98-44ca-bc4e-e1d670582f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595908398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3595908398
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2676118505
Short name T441
Test name
Test status
Simulation time 18739796 ps
CPU time 0.73 seconds
Started Aug 11 05:21:48 PM PDT 24
Finished Aug 11 05:21:49 PM PDT 24
Peak memory 205804 kb
Host smart-1f96f2dd-ee5d-4ccf-b090-6487a118471e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676118505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2676118505
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2234688177
Short name T392
Test name
Test status
Simulation time 1345325797 ps
CPU time 17.1 seconds
Started Aug 11 05:21:59 PM PDT 24
Finished Aug 11 05:22:16 PM PDT 24
Peak memory 233076 kb
Host smart-b2a37dd2-ab45-489f-b0a5-03a03de213c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234688177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2234688177
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3544211774
Short name T604
Test name
Test status
Simulation time 20355301 ps
CPU time 0.73 seconds
Started Aug 11 05:21:44 PM PDT 24
Finished Aug 11 05:21:45 PM PDT 24
Peak memory 205876 kb
Host smart-3f422445-62c0-4d8e-a6a3-146477973d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544211774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3544211774
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.294330687
Short name T39
Test name
Test status
Simulation time 2442866635 ps
CPU time 10.72 seconds
Started Aug 11 05:21:57 PM PDT 24
Finished Aug 11 05:22:08 PM PDT 24
Peak memory 224968 kb
Host smart-3b13125e-66cc-44f8-815b-0219a0e4b8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294330687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.294330687
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1757056101
Short name T59
Test name
Test status
Simulation time 5762753162 ps
CPU time 53.26 seconds
Started Aug 11 05:21:51 PM PDT 24
Finished Aug 11 05:22:45 PM PDT 24
Peak memory 239464 kb
Host smart-5be0bf99-777d-4df6-9f3b-3a40db4f513f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757056101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1757056101
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3438867401
Short name T219
Test name
Test status
Simulation time 94024093085 ps
CPU time 242.12 seconds
Started Aug 11 05:21:57 PM PDT 24
Finished Aug 11 05:25:59 PM PDT 24
Peak memory 265956 kb
Host smart-a4ca140d-7cad-4aa7-8831-43581b78e50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438867401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3438867401
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1120748935
Short name T414
Test name
Test status
Simulation time 8593089038 ps
CPU time 18.34 seconds
Started Aug 11 05:21:50 PM PDT 24
Finished Aug 11 05:22:08 PM PDT 24
Peak memory 233188 kb
Host smart-37dd4bad-50c2-448a-bdb1-83ff84e0baf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120748935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1120748935
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.325501800
Short name T850
Test name
Test status
Simulation time 133505238422 ps
CPU time 215.22 seconds
Started Aug 11 05:21:49 PM PDT 24
Finished Aug 11 05:25:25 PM PDT 24
Peak memory 249472 kb
Host smart-c6541df7-53f0-498a-b079-6650e11875e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325501800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.325501800
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.18364392
Short name T715
Test name
Test status
Simulation time 481123376 ps
CPU time 2.52 seconds
Started Aug 11 05:21:52 PM PDT 24
Finished Aug 11 05:21:55 PM PDT 24
Peak memory 224792 kb
Host smart-bed5e7dc-9fcb-46ab-a9f3-b427622196aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18364392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.18364392
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2386670901
Short name T602
Test name
Test status
Simulation time 41507709464 ps
CPU time 93.87 seconds
Started Aug 11 05:21:56 PM PDT 24
Finished Aug 11 05:23:30 PM PDT 24
Peak memory 233048 kb
Host smart-fe8d69ab-acb5-49b6-a6ae-002220aab4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386670901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2386670901
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3322956876
Short name T885
Test name
Test status
Simulation time 1469508927 ps
CPU time 5.88 seconds
Started Aug 11 05:21:49 PM PDT 24
Finished Aug 11 05:21:55 PM PDT 24
Peak memory 233032 kb
Host smart-c8849778-0d8d-4829-b6ef-3ef5a7186277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322956876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3322956876
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1776961021
Short name T456
Test name
Test status
Simulation time 32179574 ps
CPU time 2.39 seconds
Started Aug 11 05:21:50 PM PDT 24
Finished Aug 11 05:21:53 PM PDT 24
Peak memory 232708 kb
Host smart-e0f6923b-655b-4ba2-8840-53dbe16a7fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776961021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1776961021
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2670696855
Short name T911
Test name
Test status
Simulation time 248519716 ps
CPU time 3.15 seconds
Started Aug 11 05:21:51 PM PDT 24
Finished Aug 11 05:21:55 PM PDT 24
Peak memory 220296 kb
Host smart-80412b96-0df8-402b-bf9e-483242a2380f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2670696855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2670696855
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2780096624
Short name T285
Test name
Test status
Simulation time 1730190724 ps
CPU time 29.73 seconds
Started Aug 11 05:21:58 PM PDT 24
Finished Aug 11 05:22:28 PM PDT 24
Peak memory 234948 kb
Host smart-6230aa27-fda2-48fb-aff7-babaf533a9fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780096624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2780096624
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2994844209
Short name T309
Test name
Test status
Simulation time 2504739842 ps
CPU time 3.77 seconds
Started Aug 11 05:21:50 PM PDT 24
Finished Aug 11 05:21:54 PM PDT 24
Peak memory 218340 kb
Host smart-edd7a6f7-011e-4cdb-9da4-20f7dbd57df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994844209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2994844209
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3961951142
Short name T789
Test name
Test status
Simulation time 1631932733 ps
CPU time 3.04 seconds
Started Aug 11 05:21:51 PM PDT 24
Finished Aug 11 05:21:54 PM PDT 24
Peak memory 216348 kb
Host smart-dee870c9-9a11-4943-807c-d12a86cfa09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961951142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3961951142
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2088107215
Short name T786
Test name
Test status
Simulation time 760771955 ps
CPU time 2.43 seconds
Started Aug 11 05:21:49 PM PDT 24
Finished Aug 11 05:21:51 PM PDT 24
Peak memory 216564 kb
Host smart-eec38664-e1b6-46d6-bc08-7c938e62654a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088107215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2088107215
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2314404411
Short name T684
Test name
Test status
Simulation time 169740808 ps
CPU time 0.8 seconds
Started Aug 11 05:21:59 PM PDT 24
Finished Aug 11 05:22:00 PM PDT 24
Peak memory 206216 kb
Host smart-f97c4ee1-78c1-4c89-bcac-13b7378b73a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314404411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2314404411
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1935056673
Short name T517
Test name
Test status
Simulation time 8379686391 ps
CPU time 18.95 seconds
Started Aug 11 05:21:51 PM PDT 24
Finished Aug 11 05:22:10 PM PDT 24
Peak memory 240336 kb
Host smart-e3e1120c-13a3-4e98-99f0-505b3d4a4200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935056673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1935056673
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.914896815
Short name T745
Test name
Test status
Simulation time 124418433 ps
CPU time 0.71 seconds
Started Aug 11 05:22:04 PM PDT 24
Finished Aug 11 05:22:04 PM PDT 24
Peak memory 205740 kb
Host smart-607eb6dd-001e-4ddc-94a6-c6a0464d3e0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914896815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.914896815
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2344370471
Short name T435
Test name
Test status
Simulation time 81249290 ps
CPU time 2.65 seconds
Started Aug 11 05:21:58 PM PDT 24
Finished Aug 11 05:22:01 PM PDT 24
Peak memory 224768 kb
Host smart-e585e340-0c3f-4c84-b145-5d4bade256ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344370471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2344370471
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2169898309
Short name T405
Test name
Test status
Simulation time 110822346 ps
CPU time 0.79 seconds
Started Aug 11 05:22:01 PM PDT 24
Finished Aug 11 05:22:02 PM PDT 24
Peak memory 206916 kb
Host smart-79ba6753-5a99-4489-8a38-f4398f1e5a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169898309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2169898309
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2663786312
Short name T810
Test name
Test status
Simulation time 91391733830 ps
CPU time 324.34 seconds
Started Aug 11 05:22:04 PM PDT 24
Finished Aug 11 05:27:28 PM PDT 24
Peak memory 265936 kb
Host smart-422b4315-b548-4a85-a8d7-9e642415a1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663786312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2663786312
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2467897809
Short name T868
Test name
Test status
Simulation time 8294938056 ps
CPU time 68.48 seconds
Started Aug 11 05:22:03 PM PDT 24
Finished Aug 11 05:23:11 PM PDT 24
Peak memory 249576 kb
Host smart-cd571e0d-64d5-4996-a9a9-734857e2622c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467897809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2467897809
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3210142176
Short name T815
Test name
Test status
Simulation time 16209785219 ps
CPU time 184.33 seconds
Started Aug 11 05:22:04 PM PDT 24
Finished Aug 11 05:25:09 PM PDT 24
Peak memory 264856 kb
Host smart-7a536bb7-4dc6-40d5-a083-6834765c294a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210142176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3210142176
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.31658278
Short name T589
Test name
Test status
Simulation time 2209083127 ps
CPU time 16.85 seconds
Started Aug 11 05:21:59 PM PDT 24
Finished Aug 11 05:22:16 PM PDT 24
Peak memory 224864 kb
Host smart-97ca5b6d-410a-4db2-ba0c-63fe83f18c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31658278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.31658278
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1040691644
Short name T952
Test name
Test status
Simulation time 20766156240 ps
CPU time 71.94 seconds
Started Aug 11 05:22:01 PM PDT 24
Finished Aug 11 05:23:13 PM PDT 24
Peak memory 249576 kb
Host smart-5bc82284-56eb-46a0-ad0d-e4a151e08b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040691644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1040691644
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1694394552
Short name T823
Test name
Test status
Simulation time 8053948807 ps
CPU time 9.05 seconds
Started Aug 11 05:21:58 PM PDT 24
Finished Aug 11 05:22:07 PM PDT 24
Peak memory 224916 kb
Host smart-4183a16c-d51c-4665-be36-a1c06fd3cb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694394552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1694394552
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1777829281
Short name T216
Test name
Test status
Simulation time 2404538605 ps
CPU time 12.65 seconds
Started Aug 11 05:21:56 PM PDT 24
Finished Aug 11 05:22:09 PM PDT 24
Peak memory 233140 kb
Host smart-67a2e9f3-0b2c-4eaf-a35b-d8cf7e6a3635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777829281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1777829281
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1829070563
Short name T205
Test name
Test status
Simulation time 919925078 ps
CPU time 4.59 seconds
Started Aug 11 05:21:56 PM PDT 24
Finished Aug 11 05:22:01 PM PDT 24
Peak memory 233028 kb
Host smart-b64a798f-7cdc-4850-83ef-18ed1bae2ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829070563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1829070563
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3209417393
Short name T798
Test name
Test status
Simulation time 13859599725 ps
CPU time 20.98 seconds
Started Aug 11 05:21:52 PM PDT 24
Finished Aug 11 05:22:13 PM PDT 24
Peak memory 233064 kb
Host smart-5578d306-e560-4d83-9dcf-360afdc99e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209417393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3209417393
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.427587724
Short name T972
Test name
Test status
Simulation time 2189281781 ps
CPU time 9.34 seconds
Started Aug 11 05:21:57 PM PDT 24
Finished Aug 11 05:22:07 PM PDT 24
Peak memory 220556 kb
Host smart-fec7c5b8-739c-40ad-a3a4-2fe977f52b6e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=427587724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.427587724
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2782932042
Short name T307
Test name
Test status
Simulation time 1491807262 ps
CPU time 8.66 seconds
Started Aug 11 05:21:48 PM PDT 24
Finished Aug 11 05:21:57 PM PDT 24
Peak memory 216588 kb
Host smart-14997283-aad1-43af-aeda-c1eebc5c414d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782932042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2782932042
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2427846553
Short name T973
Test name
Test status
Simulation time 60856712245 ps
CPU time 13.13 seconds
Started Aug 11 05:21:51 PM PDT 24
Finished Aug 11 05:22:04 PM PDT 24
Peak memory 216892 kb
Host smart-61deccde-a0f8-4a8e-b6f3-146b31fff585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427846553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2427846553
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4052872914
Short name T767
Test name
Test status
Simulation time 219582883 ps
CPU time 1.3 seconds
Started Aug 11 05:21:49 PM PDT 24
Finished Aug 11 05:21:51 PM PDT 24
Peak memory 208100 kb
Host smart-30c41c8e-f8ff-4bb7-aa00-31d4bbabd33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052872914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4052872914
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.11038402
Short name T637
Test name
Test status
Simulation time 107952044 ps
CPU time 0.87 seconds
Started Aug 11 05:21:59 PM PDT 24
Finished Aug 11 05:22:00 PM PDT 24
Peak memory 206264 kb
Host smart-f93a7053-c0ea-4e13-95f2-64fd200a0a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11038402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.11038402
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2460330290
Short name T546
Test name
Test status
Simulation time 205242625 ps
CPU time 2.66 seconds
Started Aug 11 05:21:59 PM PDT 24
Finished Aug 11 05:22:02 PM PDT 24
Peak memory 233068 kb
Host smart-74973df9-807a-4c5f-bf82-388d62fa9208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460330290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2460330290
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2599588703
Short name T795
Test name
Test status
Simulation time 39063546 ps
CPU time 0.73 seconds
Started Aug 11 05:22:08 PM PDT 24
Finished Aug 11 05:22:09 PM PDT 24
Peak memory 205664 kb
Host smart-95159332-3947-4996-907a-e7fdf8bd03ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599588703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2599588703
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2711653086
Short name T701
Test name
Test status
Simulation time 204075026 ps
CPU time 4.83 seconds
Started Aug 11 05:22:01 PM PDT 24
Finished Aug 11 05:22:06 PM PDT 24
Peak memory 224832 kb
Host smart-637e27e5-5af1-43b6-87d6-0ef95b831344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711653086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2711653086
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1238838834
Short name T800
Test name
Test status
Simulation time 74914869 ps
CPU time 0.8 seconds
Started Aug 11 05:22:01 PM PDT 24
Finished Aug 11 05:22:02 PM PDT 24
Peak memory 206836 kb
Host smart-3a9560d1-1eee-4799-a583-547cb9becf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238838834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1238838834
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.93755419
Short name T721
Test name
Test status
Simulation time 14679502789 ps
CPU time 36.82 seconds
Started Aug 11 05:22:12 PM PDT 24
Finished Aug 11 05:22:49 PM PDT 24
Peak memory 237788 kb
Host smart-4be7daa8-dfab-49ab-99d0-0ca39b79ff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93755419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.93755419
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.931056819
Short name T590
Test name
Test status
Simulation time 71750054260 ps
CPU time 166.7 seconds
Started Aug 11 05:22:09 PM PDT 24
Finished Aug 11 05:24:56 PM PDT 24
Peak memory 249436 kb
Host smart-132bcce2-6276-401a-8c0f-013156ac8667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931056819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.931056819
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1758812934
Short name T223
Test name
Test status
Simulation time 8073727745 ps
CPU time 102.87 seconds
Started Aug 11 05:22:12 PM PDT 24
Finished Aug 11 05:23:55 PM PDT 24
Peak memory 254056 kb
Host smart-619dd57d-8967-43a5-bd1c-a6582d41cef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758812934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1758812934
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1854644849
Short name T298
Test name
Test status
Simulation time 5134223193 ps
CPU time 75.34 seconds
Started Aug 11 05:22:08 PM PDT 24
Finished Aug 11 05:23:23 PM PDT 24
Peak memory 252412 kb
Host smart-7c9925a8-4489-44a1-874c-84c1e9cd87c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854644849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1854644849
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.149975194
Short name T824
Test name
Test status
Simulation time 1637832654 ps
CPU time 11.14 seconds
Started Aug 11 05:22:04 PM PDT 24
Finished Aug 11 05:22:15 PM PDT 24
Peak memory 232936 kb
Host smart-9352510d-0c38-4396-ba98-8ebd53b6ab8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149975194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.149975194
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2138228572
Short name T1004
Test name
Test status
Simulation time 132513508 ps
CPU time 3.26 seconds
Started Aug 11 05:22:02 PM PDT 24
Finished Aug 11 05:22:05 PM PDT 24
Peak memory 228156 kb
Host smart-af5aa7c8-121a-4269-a38e-7ef7727ace6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138228572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2138228572
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1785836283
Short name T253
Test name
Test status
Simulation time 109891353 ps
CPU time 2.38 seconds
Started Aug 11 05:22:04 PM PDT 24
Finished Aug 11 05:22:06 PM PDT 24
Peak memory 224708 kb
Host smart-a4d80ef2-3082-4d61-904e-1e35cd9999ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785836283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1785836283
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3974520184
Short name T578
Test name
Test status
Simulation time 4959671757 ps
CPU time 8.7 seconds
Started Aug 11 05:22:02 PM PDT 24
Finished Aug 11 05:22:11 PM PDT 24
Peak memory 224832 kb
Host smart-b2e329d6-6257-4ca3-8f7d-56fc93138593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974520184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3974520184
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.721402416
Short name T553
Test name
Test status
Simulation time 568003615 ps
CPU time 5.89 seconds
Started Aug 11 05:22:12 PM PDT 24
Finished Aug 11 05:22:18 PM PDT 24
Peak memory 219412 kb
Host smart-c90e54c2-b9a6-4c11-b70b-285ce18adade
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=721402416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.721402416
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.576356705
Short name T562
Test name
Test status
Simulation time 1366874374 ps
CPU time 9.02 seconds
Started Aug 11 05:22:03 PM PDT 24
Finished Aug 11 05:22:13 PM PDT 24
Peak memory 216668 kb
Host smart-c177e8b8-0b6f-4f23-ab86-a220c37d2763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576356705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.576356705
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3243585963
Short name T323
Test name
Test status
Simulation time 594816291 ps
CPU time 2.56 seconds
Started Aug 11 05:22:02 PM PDT 24
Finished Aug 11 05:22:04 PM PDT 24
Peak memory 216592 kb
Host smart-93c5f88d-2085-4cf3-b404-404b94d862f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243585963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3243585963
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4286192835
Short name T563
Test name
Test status
Simulation time 32914436 ps
CPU time 0.7 seconds
Started Aug 11 05:22:04 PM PDT 24
Finished Aug 11 05:22:04 PM PDT 24
Peak memory 205924 kb
Host smart-eb05aabe-cd5a-41c6-8832-f55d6ae49d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286192835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4286192835
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1892778901
Short name T991
Test name
Test status
Simulation time 91417194 ps
CPU time 0.8 seconds
Started Aug 11 05:22:03 PM PDT 24
Finished Aug 11 05:22:04 PM PDT 24
Peak memory 206204 kb
Host smart-9a931a91-e1fa-4542-b39f-3a0dbdec0a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892778901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1892778901
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3150533027
Short name T916
Test name
Test status
Simulation time 42487608 ps
CPU time 2.22 seconds
Started Aug 11 05:22:03 PM PDT 24
Finished Aug 11 05:22:06 PM PDT 24
Peak memory 224880 kb
Host smart-64d1466b-6850-4452-a017-fb9602fac374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150533027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3150533027
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.212619389
Short name T514
Test name
Test status
Simulation time 17285785 ps
CPU time 0.77 seconds
Started Aug 11 05:22:17 PM PDT 24
Finished Aug 11 05:22:18 PM PDT 24
Peak memory 206076 kb
Host smart-5b77876e-378d-42dc-8bc7-90d838ad357e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212619389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.212619389
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1338335538
Short name T756
Test name
Test status
Simulation time 36208344 ps
CPU time 0.82 seconds
Started Aug 11 05:22:08 PM PDT 24
Finished Aug 11 05:22:09 PM PDT 24
Peak memory 206892 kb
Host smart-5acc29c9-5bf2-4e0d-bba0-d5e076cac325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338335538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1338335538
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.195200996
Short name T900
Test name
Test status
Simulation time 48550356751 ps
CPU time 91.59 seconds
Started Aug 11 05:22:15 PM PDT 24
Finished Aug 11 05:23:47 PM PDT 24
Peak memory 251868 kb
Host smart-14290d1b-d9c1-46cb-a7f6-c1c796ca5632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195200996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.195200996
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3976612627
Short name T490
Test name
Test status
Simulation time 5630209632 ps
CPU time 28.81 seconds
Started Aug 11 05:22:14 PM PDT 24
Finished Aug 11 05:22:43 PM PDT 24
Peak memory 233084 kb
Host smart-91bc7437-486a-4e11-8452-7185c638883d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976612627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3976612627
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1010941311
Short name T402
Test name
Test status
Simulation time 10880128373 ps
CPU time 55.61 seconds
Started Aug 11 05:22:17 PM PDT 24
Finished Aug 11 05:23:13 PM PDT 24
Peak memory 250340 kb
Host smart-cc80aec5-6f50-4439-bd7f-d2edca47c8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010941311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1010941311
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.932439518
Short name T296
Test name
Test status
Simulation time 4773226182 ps
CPU time 41.01 seconds
Started Aug 11 05:22:14 PM PDT 24
Finished Aug 11 05:22:55 PM PDT 24
Peak memory 241288 kb
Host smart-5a7bd7e6-fdcb-425e-9c66-a5b74b3334ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932439518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.932439518
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.1524461429
Short name T581
Test name
Test status
Simulation time 22875410820 ps
CPU time 171.08 seconds
Started Aug 11 05:22:15 PM PDT 24
Finished Aug 11 05:25:06 PM PDT 24
Peak memory 254340 kb
Host smart-662e7f06-e317-48cc-8301-043aac6f47c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524461429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.1524461429
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2089301629
Short name T55
Test name
Test status
Simulation time 842497994 ps
CPU time 6.68 seconds
Started Aug 11 05:22:06 PM PDT 24
Finished Aug 11 05:22:13 PM PDT 24
Peak memory 229520 kb
Host smart-8dfdaa3e-2531-4c7a-9a10-dbe19bf7cfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089301629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2089301629
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2466679233
Short name T887
Test name
Test status
Simulation time 7383581081 ps
CPU time 26.07 seconds
Started Aug 11 05:22:12 PM PDT 24
Finished Aug 11 05:22:39 PM PDT 24
Peak memory 251620 kb
Host smart-6df89c62-d905-4a28-b5ce-dbb9fb5faf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466679233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2466679233
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1316994369
Short name T875
Test name
Test status
Simulation time 524694970 ps
CPU time 7.26 seconds
Started Aug 11 05:22:12 PM PDT 24
Finished Aug 11 05:22:20 PM PDT 24
Peak memory 233044 kb
Host smart-c8862621-c894-4f0a-93e3-b5aa1090e4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316994369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1316994369
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4247044916
Short name T672
Test name
Test status
Simulation time 4046276476 ps
CPU time 11.07 seconds
Started Aug 11 05:22:09 PM PDT 24
Finished Aug 11 05:22:20 PM PDT 24
Peak memory 239800 kb
Host smart-4557995d-540a-4646-989c-021b73873dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247044916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4247044916
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3706031584
Short name T974
Test name
Test status
Simulation time 191283499 ps
CPU time 3.78 seconds
Started Aug 11 05:22:17 PM PDT 24
Finished Aug 11 05:22:21 PM PDT 24
Peak memory 220676 kb
Host smart-c793b763-766e-4e7f-9845-5532d8a4f904
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3706031584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3706031584
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3702628125
Short name T650
Test name
Test status
Simulation time 3033949815 ps
CPU time 12.77 seconds
Started Aug 11 05:22:08 PM PDT 24
Finished Aug 11 05:22:21 PM PDT 24
Peak memory 217004 kb
Host smart-a3de1ec4-4e00-415d-a22e-851ca060c1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702628125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3702628125
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3301416353
Short name T321
Test name
Test status
Simulation time 104686906 ps
CPU time 1.48 seconds
Started Aug 11 05:22:08 PM PDT 24
Finished Aug 11 05:22:10 PM PDT 24
Peak memory 216556 kb
Host smart-105ecd67-4d0e-4df7-81d0-2945d71d6dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301416353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3301416353
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2143452890
Short name T568
Test name
Test status
Simulation time 141783719 ps
CPU time 1 seconds
Started Aug 11 05:22:08 PM PDT 24
Finished Aug 11 05:22:09 PM PDT 24
Peak memory 206268 kb
Host smart-1f44691e-4c32-40eb-8150-8c09cea1d2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143452890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2143452890
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.540835029
Short name T638
Test name
Test status
Simulation time 2062574651 ps
CPU time 11.31 seconds
Started Aug 11 05:22:17 PM PDT 24
Finished Aug 11 05:22:28 PM PDT 24
Peak memory 233076 kb
Host smart-3338e830-19d5-4c96-a425-d0598470b2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540835029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.540835029
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3339098045
Short name T826
Test name
Test status
Simulation time 12884569 ps
CPU time 0.73 seconds
Started Aug 11 05:18:31 PM PDT 24
Finished Aug 11 05:18:32 PM PDT 24
Peak memory 206112 kb
Host smart-5896a217-104d-4f25-b15c-653f51217165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339098045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
339098045
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.4232800026
Short name T177
Test name
Test status
Simulation time 125258735 ps
CPU time 3.54 seconds
Started Aug 11 05:18:24 PM PDT 24
Finished Aug 11 05:18:27 PM PDT 24
Peak memory 233068 kb
Host smart-d19ca494-10c3-420e-ae74-184aa56d105b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232800026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.4232800026
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.212156564
Short name T328
Test name
Test status
Simulation time 41647657 ps
CPU time 0.81 seconds
Started Aug 11 05:18:24 PM PDT 24
Finished Aug 11 05:18:25 PM PDT 24
Peak memory 206912 kb
Host smart-0fb2f3a9-ab5e-4f29-890b-da50342182c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212156564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.212156564
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.15108010
Short name T541
Test name
Test status
Simulation time 40169362902 ps
CPU time 90.59 seconds
Started Aug 11 05:18:33 PM PDT 24
Finished Aug 11 05:20:04 PM PDT 24
Peak memory 252560 kb
Host smart-77ae22c3-c53c-4b76-8939-1c27b333d364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15108010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.15108010
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.775812352
Short name T665
Test name
Test status
Simulation time 384441007 ps
CPU time 5.65 seconds
Started Aug 11 05:18:24 PM PDT 24
Finished Aug 11 05:18:30 PM PDT 24
Peak memory 239668 kb
Host smart-9019ec51-3d55-4f9d-b364-ad2b9d2856ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775812352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.775812352
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.482360833
Short name T857
Test name
Test status
Simulation time 21694136576 ps
CPU time 160.18 seconds
Started Aug 11 05:18:25 PM PDT 24
Finished Aug 11 05:21:05 PM PDT 24
Peak memory 249580 kb
Host smart-9599f453-d4a1-4d56-9f6d-8f2804da202d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482360833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
482360833
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.462767682
Short name T315
Test name
Test status
Simulation time 372614597 ps
CPU time 5.22 seconds
Started Aug 11 05:18:24 PM PDT 24
Finished Aug 11 05:18:29 PM PDT 24
Peak memory 224728 kb
Host smart-d1eed507-b307-40b8-aec5-e58c7a239c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462767682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.462767682
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.966854647
Short name T226
Test name
Test status
Simulation time 29918470937 ps
CPU time 78.55 seconds
Started Aug 11 05:18:25 PM PDT 24
Finished Aug 11 05:19:43 PM PDT 24
Peak memory 224896 kb
Host smart-feeffbfd-b886-4936-a3e7-8dc8a42cb6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966854647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.966854647
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.4276430832
Short name T511
Test name
Test status
Simulation time 256054401 ps
CPU time 2.71 seconds
Started Aug 11 05:18:23 PM PDT 24
Finished Aug 11 05:18:26 PM PDT 24
Peak memory 224668 kb
Host smart-f36e5bc6-fdba-406c-8c86-3f2c3c384c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276430832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.4276430832
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1582414207
Short name T809
Test name
Test status
Simulation time 325501394 ps
CPU time 4.38 seconds
Started Aug 11 05:18:26 PM PDT 24
Finished Aug 11 05:18:30 PM PDT 24
Peak memory 224876 kb
Host smart-da2f9d4d-f26b-4065-9a37-fadf28ef8e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582414207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1582414207
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.48655965
Short name T452
Test name
Test status
Simulation time 705447996 ps
CPU time 4.9 seconds
Started Aug 11 05:18:32 PM PDT 24
Finished Aug 11 05:18:37 PM PDT 24
Peak memory 220540 kb
Host smart-23ce2c6a-be52-4683-a799-bdaba1b164d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=48655965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct
.48655965
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4241706601
Short name T74
Test name
Test status
Simulation time 627221714 ps
CPU time 1.15 seconds
Started Aug 11 05:18:32 PM PDT 24
Finished Aug 11 05:18:33 PM PDT 24
Peak memory 236280 kb
Host smart-3bfb1f69-1713-4043-b8fb-c075717a2559
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241706601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4241706601
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.70015271
Short name T18
Test name
Test status
Simulation time 1327389425 ps
CPU time 16.33 seconds
Started Aug 11 05:18:31 PM PDT 24
Finished Aug 11 05:18:48 PM PDT 24
Peak memory 217892 kb
Host smart-93938c36-8ce2-4ad9-bd83-bbb1e420900e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70015271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_
all.70015271
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2631349282
Short name T739
Test name
Test status
Simulation time 4998508924 ps
CPU time 17.05 seconds
Started Aug 11 05:18:25 PM PDT 24
Finished Aug 11 05:18:42 PM PDT 24
Peak memory 220708 kb
Host smart-eeb5901c-afaa-4dee-a797-8397649582f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631349282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2631349282
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3899592681
Short name T564
Test name
Test status
Simulation time 17095809781 ps
CPU time 13.84 seconds
Started Aug 11 05:18:26 PM PDT 24
Finished Aug 11 05:18:40 PM PDT 24
Peak memory 216484 kb
Host smart-9adecbe8-116e-4b58-a22a-0c80490efcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899592681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3899592681
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1650584467
Short name T845
Test name
Test status
Simulation time 215415833 ps
CPU time 3.35 seconds
Started Aug 11 05:18:26 PM PDT 24
Finished Aug 11 05:18:30 PM PDT 24
Peak memory 216492 kb
Host smart-92551f89-8f06-4d7d-afc5-3192951cd86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650584467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1650584467
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1106439287
Short name T409
Test name
Test status
Simulation time 44196640 ps
CPU time 0.72 seconds
Started Aug 11 05:18:23 PM PDT 24
Finished Aug 11 05:18:24 PM PDT 24
Peak memory 206256 kb
Host smart-3cf3dfd2-74f9-4c31-814c-2d75bcb391f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106439287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1106439287
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1582413101
Short name T833
Test name
Test status
Simulation time 2068159534 ps
CPU time 4.99 seconds
Started Aug 11 05:18:24 PM PDT 24
Finished Aug 11 05:18:29 PM PDT 24
Peak memory 233048 kb
Host smart-08cbeaf1-e74a-479e-92f4-b13fd00bea12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582413101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1582413101
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1417194273
Short name T658
Test name
Test status
Simulation time 93687694 ps
CPU time 0.72 seconds
Started Aug 11 05:22:28 PM PDT 24
Finished Aug 11 05:22:29 PM PDT 24
Peak memory 205128 kb
Host smart-3b60b7a9-3cf5-4fe5-be11-8a0f2ef5b324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417194273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1417194273
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3029280151
Short name T317
Test name
Test status
Simulation time 150314550 ps
CPU time 2.56 seconds
Started Aug 11 05:22:21 PM PDT 24
Finished Aug 11 05:22:24 PM PDT 24
Peak memory 233024 kb
Host smart-ea470fc8-61a2-4d5f-af67-ffae62758e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029280151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3029280151
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3861315873
Short name T811
Test name
Test status
Simulation time 21427281 ps
CPU time 0.8 seconds
Started Aug 11 05:22:17 PM PDT 24
Finished Aug 11 05:22:18 PM PDT 24
Peak memory 207240 kb
Host smart-e8dd3890-1a64-4572-9e5a-aeb38568888d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861315873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3861315873
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2119875698
Short name T772
Test name
Test status
Simulation time 2580156254 ps
CPU time 7.18 seconds
Started Aug 11 05:22:19 PM PDT 24
Finished Aug 11 05:22:26 PM PDT 24
Peak memory 224928 kb
Host smart-a115f71d-0f43-4819-8897-ee80b31df959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119875698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2119875698
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3971849039
Short name T508
Test name
Test status
Simulation time 42842747320 ps
CPU time 89.24 seconds
Started Aug 11 05:22:22 PM PDT 24
Finished Aug 11 05:23:51 PM PDT 24
Peak memory 237800 kb
Host smart-ed886638-820b-488c-9329-99f7a83ce977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971849039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3971849039
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3142747486
Short name T221
Test name
Test status
Simulation time 9569181981 ps
CPU time 64.21 seconds
Started Aug 11 05:22:19 PM PDT 24
Finished Aug 11 05:23:24 PM PDT 24
Peak memory 257668 kb
Host smart-d4051235-91bb-43e8-bba1-69c369466e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142747486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3142747486
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2183114747
Short name T299
Test name
Test status
Simulation time 6306056293 ps
CPU time 25.32 seconds
Started Aug 11 05:22:20 PM PDT 24
Finished Aug 11 05:22:46 PM PDT 24
Peak memory 241268 kb
Host smart-83d2c4c9-801a-4f44-ae03-21cacdef5d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183114747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2183114747
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2960689316
Short name T86
Test name
Test status
Simulation time 1066340493 ps
CPU time 24.95 seconds
Started Aug 11 05:22:26 PM PDT 24
Finished Aug 11 05:22:51 PM PDT 24
Peak memory 249508 kb
Host smart-8208b5ed-9f5f-4135-a391-3b14e556dcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960689316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2960689316
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3992668504
Short name T598
Test name
Test status
Simulation time 581241431 ps
CPU time 2.09 seconds
Started Aug 11 05:22:15 PM PDT 24
Finished Aug 11 05:22:17 PM PDT 24
Peak memory 223316 kb
Host smart-76fded33-bc5e-4736-b2a0-9de197cde6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992668504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3992668504
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3539079102
Short name T876
Test name
Test status
Simulation time 15076260168 ps
CPU time 31.43 seconds
Started Aug 11 05:22:26 PM PDT 24
Finished Aug 11 05:22:57 PM PDT 24
Peak memory 224920 kb
Host smart-ea6b765f-2e57-4de2-9242-e48c88b2860a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539079102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3539079102
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.4103897342
Short name T426
Test name
Test status
Simulation time 26687147048 ps
CPU time 13.72 seconds
Started Aug 11 05:22:17 PM PDT 24
Finished Aug 11 05:22:31 PM PDT 24
Peak memory 254480 kb
Host smart-13c7c294-4858-42a6-8476-e90b4de3e6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103897342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.4103897342
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1286137388
Short name T179
Test name
Test status
Simulation time 176761786 ps
CPU time 2.79 seconds
Started Aug 11 05:22:17 PM PDT 24
Finished Aug 11 05:22:19 PM PDT 24
Peak memory 233088 kb
Host smart-743c618c-da3f-4521-b960-9f02fd2c04ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286137388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1286137388
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4049904537
Short name T924
Test name
Test status
Simulation time 347371770 ps
CPU time 5.15 seconds
Started Aug 11 05:22:20 PM PDT 24
Finished Aug 11 05:22:25 PM PDT 24
Peak memory 223356 kb
Host smart-57ae5212-24a2-49eb-925b-a714ebf73135
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4049904537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4049904537
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1823841462
Short name T52
Test name
Test status
Simulation time 6436994992 ps
CPU time 125.76 seconds
Started Aug 11 05:22:30 PM PDT 24
Finished Aug 11 05:24:35 PM PDT 24
Peak memory 257816 kb
Host smart-37f7ba44-8f38-4960-b53a-16d1eec3f6dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823841462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1823841462
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3258115957
Short name T813
Test name
Test status
Simulation time 1498846172 ps
CPU time 3.29 seconds
Started Aug 11 05:22:15 PM PDT 24
Finished Aug 11 05:22:18 PM PDT 24
Peak memory 216484 kb
Host smart-854cca18-ad1e-498c-83ce-3d984fdc0aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258115957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3258115957
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.4198021756
Short name T357
Test name
Test status
Simulation time 2735954854 ps
CPU time 6.45 seconds
Started Aug 11 05:22:15 PM PDT 24
Finished Aug 11 05:22:22 PM PDT 24
Peak memory 216632 kb
Host smart-af24b984-2cde-4f6c-a7f9-933e86f1b6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198021756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.4198021756
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.165091250
Short name T8
Test name
Test status
Simulation time 21453259 ps
CPU time 0.8 seconds
Started Aug 11 05:22:16 PM PDT 24
Finished Aug 11 05:22:17 PM PDT 24
Peak memory 206308 kb
Host smart-0ddd1c84-86af-47f5-85f0-27f72acbf4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165091250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.165091250
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.275692530
Short name T668
Test name
Test status
Simulation time 116620286 ps
CPU time 0.83 seconds
Started Aug 11 05:22:16 PM PDT 24
Finished Aug 11 05:22:17 PM PDT 24
Peak memory 206312 kb
Host smart-36e2523f-6509-4291-8426-47828d445b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275692530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.275692530
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.628245646
Short name T969
Test name
Test status
Simulation time 4759522543 ps
CPU time 17.45 seconds
Started Aug 11 05:22:22 PM PDT 24
Finished Aug 11 05:22:39 PM PDT 24
Peak memory 224892 kb
Host smart-7d5a6b49-185d-4bf6-b8e5-87744216a39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628245646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.628245646
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3822402817
Short name T326
Test name
Test status
Simulation time 20335090 ps
CPU time 0.73 seconds
Started Aug 11 05:22:32 PM PDT 24
Finished Aug 11 05:22:33 PM PDT 24
Peak memory 205776 kb
Host smart-bc2f5f0b-8573-4113-a221-caec60e50c87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822402817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3822402817
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2570528210
Short name T443
Test name
Test status
Simulation time 386441900 ps
CPU time 3.02 seconds
Started Aug 11 05:22:26 PM PDT 24
Finished Aug 11 05:22:29 PM PDT 24
Peak memory 224800 kb
Host smart-490ff89c-2b81-483a-b3bf-ecfe0da8edf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570528210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2570528210
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3942385982
Short name T64
Test name
Test status
Simulation time 71697951 ps
CPU time 0.81 seconds
Started Aug 11 05:22:25 PM PDT 24
Finished Aug 11 05:22:26 PM PDT 24
Peak memory 207132 kb
Host smart-42c1fc09-8282-4c65-8401-56c2aad5c5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942385982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3942385982
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.206490813
Short name T272
Test name
Test status
Simulation time 23386925370 ps
CPU time 86.79 seconds
Started Aug 11 05:22:33 PM PDT 24
Finished Aug 11 05:24:00 PM PDT 24
Peak memory 252620 kb
Host smart-caf5b789-8ccd-4f03-8775-5c127f9a74ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206490813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.206490813
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.962899535
Short name T778
Test name
Test status
Simulation time 32340944115 ps
CPU time 205.29 seconds
Started Aug 11 05:22:33 PM PDT 24
Finished Aug 11 05:25:59 PM PDT 24
Peak memory 253984 kb
Host smart-d757b0f3-78c1-478c-8ebb-aa00dab8530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962899535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.962899535
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1873021045
Short name T134
Test name
Test status
Simulation time 2043419366 ps
CPU time 32.01 seconds
Started Aug 11 05:22:30 PM PDT 24
Finished Aug 11 05:23:03 PM PDT 24
Peak memory 224828 kb
Host smart-ab46544a-058e-49b4-998a-8c2011bb7495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873021045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1873021045
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2949835338
Short name T419
Test name
Test status
Simulation time 8549230296 ps
CPU time 21.71 seconds
Started Aug 11 05:22:26 PM PDT 24
Finished Aug 11 05:22:48 PM PDT 24
Peak memory 224836 kb
Host smart-04822a04-1c93-4f4d-8f6b-4d2386e0846b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949835338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2949835338
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3525935176
Short name T439
Test name
Test status
Simulation time 6844651169 ps
CPU time 7.4 seconds
Started Aug 11 05:22:27 PM PDT 24
Finished Aug 11 05:22:35 PM PDT 24
Peak memory 224820 kb
Host smart-fca3bfb4-0454-456f-908d-048ed3eb6eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525935176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3525935176
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3863465693
Short name T474
Test name
Test status
Simulation time 2326327273 ps
CPU time 12.99 seconds
Started Aug 11 05:22:31 PM PDT 24
Finished Aug 11 05:22:44 PM PDT 24
Peak memory 234612 kb
Host smart-10b3f3e6-8509-44cc-9f5f-ad4563bb33d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863465693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3863465693
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3266209054
Short name T254
Test name
Test status
Simulation time 5716540689 ps
CPU time 19.14 seconds
Started Aug 11 05:22:26 PM PDT 24
Finished Aug 11 05:22:46 PM PDT 24
Peak memory 240728 kb
Host smart-ae24275f-ce75-4fa4-b6cf-2ebda64fcfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266209054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3266209054
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2044946611
Short name T238
Test name
Test status
Simulation time 21811281858 ps
CPU time 11.38 seconds
Started Aug 11 05:22:28 PM PDT 24
Finished Aug 11 05:22:40 PM PDT 24
Peak memory 233144 kb
Host smart-dbbbb357-5080-4481-ac9b-84659e6a47f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044946611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2044946611
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3445637451
Short name T825
Test name
Test status
Simulation time 3411230506 ps
CPU time 8.28 seconds
Started Aug 11 05:22:28 PM PDT 24
Finished Aug 11 05:22:36 PM PDT 24
Peak memory 219756 kb
Host smart-17cdbdb3-8de9-4b6f-82da-ebf03ce85c89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3445637451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3445637451
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.771594934
Short name T351
Test name
Test status
Simulation time 1119592982 ps
CPU time 7.4 seconds
Started Aug 11 05:22:27 PM PDT 24
Finished Aug 11 05:22:35 PM PDT 24
Peak memory 216688 kb
Host smart-ea7866b4-caf8-4fe1-a428-4535de04463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771594934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.771594934
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.375814089
Short name T26
Test name
Test status
Simulation time 11683321063 ps
CPU time 10.03 seconds
Started Aug 11 05:22:25 PM PDT 24
Finished Aug 11 05:22:35 PM PDT 24
Peak memory 216604 kb
Host smart-853ba666-141d-4959-a2c3-aa6b6230ddf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375814089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.375814089
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2696169166
Short name T445
Test name
Test status
Simulation time 640595998 ps
CPU time 2.54 seconds
Started Aug 11 05:22:28 PM PDT 24
Finished Aug 11 05:22:30 PM PDT 24
Peak memory 216564 kb
Host smart-b3f01e31-93fb-496c-8f0a-30e019c5adb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696169166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2696169166
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.4160727131
Short name T764
Test name
Test status
Simulation time 49694695 ps
CPU time 0.7 seconds
Started Aug 11 05:22:26 PM PDT 24
Finished Aug 11 05:22:26 PM PDT 24
Peak memory 205880 kb
Host smart-42cadef3-22dd-4c81-a66a-7e42b9a7f731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160727131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4160727131
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1678588568
Short name T486
Test name
Test status
Simulation time 790135228 ps
CPU time 7.56 seconds
Started Aug 11 05:22:26 PM PDT 24
Finished Aug 11 05:22:34 PM PDT 24
Peak memory 240916 kb
Host smart-4f81bfe4-7d36-4c36-9391-896dcf56a979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678588568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1678588568
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3967146243
Short name T847
Test name
Test status
Simulation time 12924953 ps
CPU time 0.71 seconds
Started Aug 11 05:22:40 PM PDT 24
Finished Aug 11 05:22:41 PM PDT 24
Peak memory 205092 kb
Host smart-fea605cd-af95-4501-9f87-d7a560f4eb53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967146243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3967146243
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.658216727
Short name T265
Test name
Test status
Simulation time 841315199 ps
CPU time 3.88 seconds
Started Aug 11 05:22:34 PM PDT 24
Finished Aug 11 05:22:38 PM PDT 24
Peak memory 233008 kb
Host smart-e7d011b4-6206-4d3d-a5f2-12aa0cb920ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658216727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.658216727
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2212462263
Short name T616
Test name
Test status
Simulation time 80268795 ps
CPU time 0.82 seconds
Started Aug 11 05:22:37 PM PDT 24
Finished Aug 11 05:22:38 PM PDT 24
Peak memory 206768 kb
Host smart-cf32e3b0-4ac9-41be-9824-8e0ee92ea40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212462263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2212462263
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1133772596
Short name T907
Test name
Test status
Simulation time 25621585043 ps
CPU time 32.32 seconds
Started Aug 11 05:22:35 PM PDT 24
Finished Aug 11 05:23:08 PM PDT 24
Peak memory 249504 kb
Host smart-ff8aba23-a103-4f02-889f-508b6af77379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133772596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1133772596
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3484417916
Short name T160
Test name
Test status
Simulation time 13816878346 ps
CPU time 76.7 seconds
Started Aug 11 05:22:37 PM PDT 24
Finished Aug 11 05:23:54 PM PDT 24
Peak memory 255560 kb
Host smart-4c151929-d5ce-4304-b5d2-8049b7cbea72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484417916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3484417916
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2511394106
Short name T36
Test name
Test status
Simulation time 32585208400 ps
CPU time 176.33 seconds
Started Aug 11 05:22:38 PM PDT 24
Finished Aug 11 05:25:35 PM PDT 24
Peak memory 251584 kb
Host smart-aa5d58fd-44e6-48fe-84cd-f84b855e0ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511394106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2511394106
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.4006196129
Short name T1005
Test name
Test status
Simulation time 846368733 ps
CPU time 4.57 seconds
Started Aug 11 05:22:33 PM PDT 24
Finished Aug 11 05:22:38 PM PDT 24
Peak memory 233732 kb
Host smart-ead2e94c-ebef-4637-b7ec-dfe6fff97a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006196129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4006196129
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2869762874
Short name T990
Test name
Test status
Simulation time 1658417155 ps
CPU time 34.06 seconds
Started Aug 11 05:22:32 PM PDT 24
Finished Aug 11 05:23:07 PM PDT 24
Peak memory 238208 kb
Host smart-a93004f3-5e61-4170-bcd0-4d093b83f44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869762874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2869762874
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3671508378
Short name T178
Test name
Test status
Simulation time 601296632 ps
CPU time 9.21 seconds
Started Aug 11 05:22:33 PM PDT 24
Finished Aug 11 05:22:42 PM PDT 24
Peak memory 224816 kb
Host smart-7782f02b-8e99-4e53-b396-3fa2afeb535e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671508378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3671508378
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1627821301
Short name T505
Test name
Test status
Simulation time 1908075995 ps
CPU time 22.74 seconds
Started Aug 11 05:22:31 PM PDT 24
Finished Aug 11 05:22:54 PM PDT 24
Peak memory 233016 kb
Host smart-b92925be-a596-4bfa-a7ab-ee4bd0168ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627821301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1627821301
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1395438068
Short name T844
Test name
Test status
Simulation time 38207828815 ps
CPU time 11.93 seconds
Started Aug 11 05:22:37 PM PDT 24
Finished Aug 11 05:22:49 PM PDT 24
Peak memory 224760 kb
Host smart-65deec5d-c58f-441a-9fb5-2026d0e8b152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395438068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1395438068
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1942719356
Short name T463
Test name
Test status
Simulation time 248593480 ps
CPU time 2.5 seconds
Started Aug 11 05:22:34 PM PDT 24
Finished Aug 11 05:22:37 PM PDT 24
Peak memory 224848 kb
Host smart-a5e32189-1267-4081-acaf-6b02294b66e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942719356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1942719356
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4269499657
Short name T792
Test name
Test status
Simulation time 165350183 ps
CPU time 4.27 seconds
Started Aug 11 05:22:37 PM PDT 24
Finished Aug 11 05:22:41 PM PDT 24
Peak memory 223452 kb
Host smart-0f986cae-f439-454b-a3b3-38fc22480697
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4269499657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4269499657
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1379950654
Short name T765
Test name
Test status
Simulation time 1500935690 ps
CPU time 22.29 seconds
Started Aug 11 05:22:32 PM PDT 24
Finished Aug 11 05:22:54 PM PDT 24
Peak memory 216728 kb
Host smart-9b2e59b1-a582-4184-8d01-3b0d279973a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379950654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1379950654
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1245230234
Short name T395
Test name
Test status
Simulation time 608139437 ps
CPU time 2.5 seconds
Started Aug 11 05:22:32 PM PDT 24
Finished Aug 11 05:22:35 PM PDT 24
Peak memory 208104 kb
Host smart-37231f53-bf0b-4d8a-adf7-a61b3885449e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245230234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1245230234
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1117241414
Short name T347
Test name
Test status
Simulation time 169953773 ps
CPU time 1.85 seconds
Started Aug 11 05:22:37 PM PDT 24
Finished Aug 11 05:22:39 PM PDT 24
Peak memory 216484 kb
Host smart-93565277-fe40-42f9-b7b5-089a51d2c65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117241414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1117241414
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.4188237710
Short name T755
Test name
Test status
Simulation time 900204681 ps
CPU time 1.03 seconds
Started Aug 11 05:22:31 PM PDT 24
Finished Aug 11 05:22:32 PM PDT 24
Peak memory 207324 kb
Host smart-134d4ecc-d6f5-4961-9167-56361098083e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188237710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.4188237710
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3125618908
Short name T941
Test name
Test status
Simulation time 311411468 ps
CPU time 2.57 seconds
Started Aug 11 05:22:32 PM PDT 24
Finished Aug 11 05:22:34 PM PDT 24
Peak memory 232904 kb
Host smart-7e5fde86-0d16-426f-9757-f8f0bd345cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125618908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3125618908
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3764167003
Short name T964
Test name
Test status
Simulation time 25182822 ps
CPU time 0.72 seconds
Started Aug 11 05:22:46 PM PDT 24
Finished Aug 11 05:22:47 PM PDT 24
Peak memory 205192 kb
Host smart-aff8fb55-8b42-4f63-bdac-8475d4afafe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764167003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3764167003
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1055831483
Short name T173
Test name
Test status
Simulation time 413141661 ps
CPU time 2.94 seconds
Started Aug 11 05:22:39 PM PDT 24
Finished Aug 11 05:22:43 PM PDT 24
Peak memory 224816 kb
Host smart-34d519ba-634a-4d0c-b5b3-1212ac357d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055831483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1055831483
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.230340773
Short name T946
Test name
Test status
Simulation time 19833826 ps
CPU time 0.78 seconds
Started Aug 11 05:22:38 PM PDT 24
Finished Aug 11 05:22:39 PM PDT 24
Peak memory 206848 kb
Host smart-5ccb959e-3033-477b-86d1-4c4f6b0d03b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230340773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.230340773
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1986664597
Short name T980
Test name
Test status
Simulation time 6483789202 ps
CPU time 48.52 seconds
Started Aug 11 05:22:45 PM PDT 24
Finished Aug 11 05:23:34 PM PDT 24
Peak memory 249772 kb
Host smart-08475edc-85d0-4bde-b63c-f07a8d149155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986664597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1986664597
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.653582271
Short name T279
Test name
Test status
Simulation time 22558198642 ps
CPU time 239.82 seconds
Started Aug 11 05:22:44 PM PDT 24
Finished Aug 11 05:26:44 PM PDT 24
Peak memory 257380 kb
Host smart-055b962c-5330-4437-bebd-5b59e60ded05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653582271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.653582271
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1301961962
Short name T776
Test name
Test status
Simulation time 4057604353 ps
CPU time 27.9 seconds
Started Aug 11 05:22:46 PM PDT 24
Finished Aug 11 05:23:13 PM PDT 24
Peak memory 237856 kb
Host smart-df45791d-abcb-4635-9e14-0cdf5f481b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301961962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1301961962
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2629781361
Short name T498
Test name
Test status
Simulation time 805053728 ps
CPU time 4.67 seconds
Started Aug 11 05:22:36 PM PDT 24
Finished Aug 11 05:22:40 PM PDT 24
Peak memory 233068 kb
Host smart-cfce07f1-7d32-409b-a41e-e456cea15c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629781361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2629781361
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3446439287
Short name T257
Test name
Test status
Simulation time 10684341172 ps
CPU time 68.5 seconds
Started Aug 11 05:22:36 PM PDT 24
Finished Aug 11 05:23:45 PM PDT 24
Peak memory 250000 kb
Host smart-ab3293ac-7670-4306-8248-98171187bdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446439287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3446439287
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1453194734
Short name T947
Test name
Test status
Simulation time 4378931562 ps
CPU time 14.35 seconds
Started Aug 11 05:22:38 PM PDT 24
Finished Aug 11 05:22:52 PM PDT 24
Peak memory 219152 kb
Host smart-6e7f631c-107b-4e17-9db2-42e703daf098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453194734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1453194734
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1690082734
Short name T796
Test name
Test status
Simulation time 1376499158 ps
CPU time 10.1 seconds
Started Aug 11 05:22:39 PM PDT 24
Finished Aug 11 05:22:49 PM PDT 24
Peak memory 233008 kb
Host smart-b4ee05be-d7eb-4708-9bce-f60075485f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690082734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1690082734
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1552768166
Short name T126
Test name
Test status
Simulation time 51793275 ps
CPU time 2.54 seconds
Started Aug 11 05:22:40 PM PDT 24
Finished Aug 11 05:22:43 PM PDT 24
Peak memory 232692 kb
Host smart-dbd48006-2c8f-41ac-9e79-75ecb0433bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552768166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1552768166
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2673860841
Short name T535
Test name
Test status
Simulation time 1188022744 ps
CPU time 2.92 seconds
Started Aug 11 05:22:42 PM PDT 24
Finished Aug 11 05:22:45 PM PDT 24
Peak memory 224692 kb
Host smart-721cea04-09cc-4bb0-ad7d-ebf98aac11bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673860841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2673860841
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.210330773
Short name T710
Test name
Test status
Simulation time 862991920 ps
CPU time 5.24 seconds
Started Aug 11 05:22:44 PM PDT 24
Finished Aug 11 05:22:49 PM PDT 24
Peak memory 223528 kb
Host smart-1652cf4e-4663-4041-873e-0ad8390f1ee5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=210330773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.210330773
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3305064903
Short name T58
Test name
Test status
Simulation time 2816808526 ps
CPU time 14.7 seconds
Started Aug 11 05:22:46 PM PDT 24
Finished Aug 11 05:23:00 PM PDT 24
Peak memory 224716 kb
Host smart-e46b0731-f9f5-42df-b37b-c71916da1760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305064903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3305064903
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3314959869
Short name T873
Test name
Test status
Simulation time 1800423992 ps
CPU time 23.49 seconds
Started Aug 11 05:22:39 PM PDT 24
Finished Aug 11 05:23:02 PM PDT 24
Peak memory 216604 kb
Host smart-a3ce9c8e-ab3d-4e3a-a570-f5d534d1c941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314959869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3314959869
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3958769422
Short name T961
Test name
Test status
Simulation time 3659706815 ps
CPU time 11.12 seconds
Started Aug 11 05:22:37 PM PDT 24
Finished Aug 11 05:22:48 PM PDT 24
Peak memory 216528 kb
Host smart-fa0d7be6-e569-49a0-8942-2ec0496369bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958769422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3958769422
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1221885243
Short name T735
Test name
Test status
Simulation time 36694684 ps
CPU time 0.71 seconds
Started Aug 11 05:22:36 PM PDT 24
Finished Aug 11 05:22:37 PM PDT 24
Peak memory 205932 kb
Host smart-4293758a-b30d-4533-a97f-c9d5e231ebd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221885243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1221885243
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1292592303
Short name T830
Test name
Test status
Simulation time 204323228 ps
CPU time 0.88 seconds
Started Aug 11 05:22:38 PM PDT 24
Finished Aug 11 05:22:39 PM PDT 24
Peak memory 206272 kb
Host smart-233902f6-53ce-4b00-9eb7-1d3aa7235edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292592303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1292592303
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.666502244
Short name T860
Test name
Test status
Simulation time 1860904915 ps
CPU time 3.72 seconds
Started Aug 11 05:22:39 PM PDT 24
Finished Aug 11 05:22:42 PM PDT 24
Peak memory 224848 kb
Host smart-696bb24e-f348-4efe-8e0c-3e4c61e95770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666502244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.666502244
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2609892040
Short name T867
Test name
Test status
Simulation time 22440110 ps
CPU time 0.74 seconds
Started Aug 11 05:22:58 PM PDT 24
Finished Aug 11 05:22:59 PM PDT 24
Peak memory 205752 kb
Host smart-f6cd9f4a-710a-4f68-bccb-9b3deb013806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609892040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2609892040
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.669628812
Short name T918
Test name
Test status
Simulation time 51410008 ps
CPU time 1.88 seconds
Started Aug 11 05:22:46 PM PDT 24
Finished Aug 11 05:22:48 PM PDT 24
Peak memory 223760 kb
Host smart-b7eb0ba9-b1a0-4292-bd7c-489f650fac66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669628812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.669628812
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1675182123
Short name T415
Test name
Test status
Simulation time 32198787 ps
CPU time 0.78 seconds
Started Aug 11 05:22:45 PM PDT 24
Finished Aug 11 05:22:46 PM PDT 24
Peak memory 206892 kb
Host smart-bba80564-43ef-4e29-b9e9-6486158cabe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675182123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1675182123
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3663654620
Short name T418
Test name
Test status
Simulation time 10581953435 ps
CPU time 53.24 seconds
Started Aug 11 05:22:59 PM PDT 24
Finished Aug 11 05:23:52 PM PDT 24
Peak memory 257712 kb
Host smart-05961c09-72f6-4695-a5c1-2745e6630e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663654620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3663654620
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1229642327
Short name T75
Test name
Test status
Simulation time 7029512044 ps
CPU time 102.62 seconds
Started Aug 11 05:22:57 PM PDT 24
Finished Aug 11 05:24:39 PM PDT 24
Peak memory 260384 kb
Host smart-63f3411d-052a-4432-b2d7-f6034e83d1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229642327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1229642327
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3273275177
Short name T276
Test name
Test status
Simulation time 57095466148 ps
CPU time 144.23 seconds
Started Aug 11 05:22:57 PM PDT 24
Finished Aug 11 05:25:22 PM PDT 24
Peak memory 252760 kb
Host smart-a58704ca-4d5b-4db7-8e8b-bd7b7a3f3d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273275177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3273275177
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2851841678
Short name T520
Test name
Test status
Simulation time 1244863454 ps
CPU time 11.11 seconds
Started Aug 11 05:22:43 PM PDT 24
Finished Aug 11 05:22:54 PM PDT 24
Peak memory 233040 kb
Host smart-b03bff6c-a649-4523-a769-5a0825f25c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851841678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2851841678
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1347365954
Short name T385
Test name
Test status
Simulation time 302917643 ps
CPU time 8.9 seconds
Started Aug 11 05:22:44 PM PDT 24
Finished Aug 11 05:22:53 PM PDT 24
Peak memory 239160 kb
Host smart-aa6992fc-c82c-4535-94ab-61cd85d6b91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347365954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1347365954
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.70713003
Short name T260
Test name
Test status
Simulation time 796769796 ps
CPU time 5.65 seconds
Started Aug 11 05:22:44 PM PDT 24
Finished Aug 11 05:22:50 PM PDT 24
Peak memory 233332 kb
Host smart-fa37e2de-0271-4aa5-bb29-e425674628e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70713003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.70713003
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4289593150
Short name T262
Test name
Test status
Simulation time 730301049 ps
CPU time 9.27 seconds
Started Aug 11 05:22:45 PM PDT 24
Finished Aug 11 05:22:55 PM PDT 24
Peak memory 234080 kb
Host smart-158021f2-7965-4399-bae1-339c64e33538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289593150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4289593150
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3316367879
Short name T218
Test name
Test status
Simulation time 2769236808 ps
CPU time 8.89 seconds
Started Aug 11 05:22:44 PM PDT 24
Finished Aug 11 05:22:53 PM PDT 24
Peak memory 233056 kb
Host smart-fd66e671-1f09-431d-a022-39506812166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316367879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3316367879
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1977686015
Short name T232
Test name
Test status
Simulation time 8907662369 ps
CPU time 26.48 seconds
Started Aug 11 05:22:46 PM PDT 24
Finished Aug 11 05:23:12 PM PDT 24
Peak memory 233120 kb
Host smart-0ecd50dd-cda0-4ae5-9510-fee149eacefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977686015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1977686015
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2416122187
Short name T136
Test name
Test status
Simulation time 7390383970 ps
CPU time 9 seconds
Started Aug 11 05:22:56 PM PDT 24
Finished Aug 11 05:23:05 PM PDT 24
Peak memory 223680 kb
Host smart-368a1b11-bc24-4664-b2c1-dd9702dc8698
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2416122187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2416122187
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2670887333
Short name T812
Test name
Test status
Simulation time 10060681515 ps
CPU time 66.91 seconds
Started Aug 11 05:22:56 PM PDT 24
Finished Aug 11 05:24:03 PM PDT 24
Peak memory 218284 kb
Host smart-d37b0ddb-7442-4d13-bf8d-4505faf64938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670887333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2670887333
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3673878282
Short name T28
Test name
Test status
Simulation time 5896290544 ps
CPU time 20.43 seconds
Started Aug 11 05:22:44 PM PDT 24
Finished Aug 11 05:23:05 PM PDT 24
Peak memory 220488 kb
Host smart-571555b1-723c-45f2-92af-d1f57a4892f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673878282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3673878282
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3716289326
Short name T883
Test name
Test status
Simulation time 23495560732 ps
CPU time 16.46 seconds
Started Aug 11 05:22:43 PM PDT 24
Finished Aug 11 05:23:00 PM PDT 24
Peak memory 216672 kb
Host smart-45976010-3153-4584-bf87-567a7562b21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716289326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3716289326
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.690830112
Short name T475
Test name
Test status
Simulation time 144666782 ps
CPU time 2.56 seconds
Started Aug 11 05:22:45 PM PDT 24
Finished Aug 11 05:22:48 PM PDT 24
Peak memory 216560 kb
Host smart-03196b09-8352-409f-8d2e-b66262caaf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690830112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.690830112
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4454205
Short name T370
Test name
Test status
Simulation time 53001876 ps
CPU time 0.66 seconds
Started Aug 11 05:22:46 PM PDT 24
Finished Aug 11 05:22:47 PM PDT 24
Peak memory 205884 kb
Host smart-faf0ebe7-9078-42e6-908e-23cf41c47ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4454205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4454205
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.4088332869
Short name T808
Test name
Test status
Simulation time 245947108 ps
CPU time 4.73 seconds
Started Aug 11 05:22:45 PM PDT 24
Finished Aug 11 05:22:50 PM PDT 24
Peak memory 224888 kb
Host smart-020b02f4-56f1-4b98-95c2-0314bf7380ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088332869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4088332869
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1013873958
Short name T704
Test name
Test status
Simulation time 46977427 ps
CPU time 0.75 seconds
Started Aug 11 05:23:05 PM PDT 24
Finished Aug 11 05:23:06 PM PDT 24
Peak memory 205836 kb
Host smart-66a1d57c-ffbc-4edd-bdb6-3177657181bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013873958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1013873958
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3877528483
Short name T176
Test name
Test status
Simulation time 643380068 ps
CPU time 2.8 seconds
Started Aug 11 05:23:02 PM PDT 24
Finished Aug 11 05:23:05 PM PDT 24
Peak memory 224788 kb
Host smart-c6040f22-0d60-419d-9980-f47950c017ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877528483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3877528483
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.67024971
Short name T416
Test name
Test status
Simulation time 13812148 ps
CPU time 0.81 seconds
Started Aug 11 05:22:56 PM PDT 24
Finished Aug 11 05:22:57 PM PDT 24
Peak memory 206916 kb
Host smart-9d86ce6e-bd2a-4db5-b6af-0a6c5daee4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67024971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.67024971
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.885988453
Short name T670
Test name
Test status
Simulation time 65642107924 ps
CPU time 232.92 seconds
Started Aug 11 05:23:06 PM PDT 24
Finished Aug 11 05:26:59 PM PDT 24
Peak memory 250524 kb
Host smart-a4b0140c-0545-45bd-b03f-2986c8441d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885988453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.885988453
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3039987127
Short name T777
Test name
Test status
Simulation time 11421606650 ps
CPU time 61.97 seconds
Started Aug 11 05:23:03 PM PDT 24
Finished Aug 11 05:24:05 PM PDT 24
Peak memory 252036 kb
Host smart-a0cc82ec-18db-4655-b16d-abec2ab6146a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039987127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3039987127
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3398741438
Short name T923
Test name
Test status
Simulation time 725191439 ps
CPU time 19.59 seconds
Started Aug 11 05:23:07 PM PDT 24
Finished Aug 11 05:23:26 PM PDT 24
Peak memory 241164 kb
Host smart-0166cbbe-ddbc-4fbb-844c-9833faf48b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398741438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3398741438
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2072701162
Short name T494
Test name
Test status
Simulation time 47300881421 ps
CPU time 111.11 seconds
Started Aug 11 05:23:04 PM PDT 24
Finished Aug 11 05:24:56 PM PDT 24
Peak memory 256604 kb
Host smart-4174eb4b-1df1-495e-9e49-e2f49ce4d259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072701162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2072701162
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2629800161
Short name T233
Test name
Test status
Simulation time 4802693271 ps
CPU time 8.53 seconds
Started Aug 11 05:23:02 PM PDT 24
Finished Aug 11 05:23:10 PM PDT 24
Peak memory 224956 kb
Host smart-e0c1f3cb-df44-4fc9-8289-a6336ee8c651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629800161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2629800161
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.969990269
Short name T499
Test name
Test status
Simulation time 17744745332 ps
CPU time 62.93 seconds
Started Aug 11 05:23:05 PM PDT 24
Finished Aug 11 05:24:08 PM PDT 24
Peak memory 233028 kb
Host smart-f9a2d515-2ee2-4886-9fb0-7ab5f42dafde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969990269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.969990269
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2740991574
Short name T524
Test name
Test status
Simulation time 79779494 ps
CPU time 2.55 seconds
Started Aug 11 05:23:05 PM PDT 24
Finished Aug 11 05:23:08 PM PDT 24
Peak memory 232776 kb
Host smart-6da31833-d3aa-4cda-92bd-6f318b7bff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740991574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2740991574
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.203934407
Short name T464
Test name
Test status
Simulation time 11391485747 ps
CPU time 10.91 seconds
Started Aug 11 05:22:58 PM PDT 24
Finished Aug 11 05:23:09 PM PDT 24
Peak memory 232956 kb
Host smart-e179035b-cd88-4038-97c7-aeb753850549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203934407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.203934407
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4251535044
Short name T355
Test name
Test status
Simulation time 184770153 ps
CPU time 4.7 seconds
Started Aug 11 05:23:02 PM PDT 24
Finished Aug 11 05:23:07 PM PDT 24
Peak memory 220096 kb
Host smart-049d9487-aa87-4f7d-85d3-5a1008ec79a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4251535044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4251535044
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2991238728
Short name T882
Test name
Test status
Simulation time 72918145808 ps
CPU time 224.8 seconds
Started Aug 11 05:23:06 PM PDT 24
Finished Aug 11 05:26:51 PM PDT 24
Peak memory 255872 kb
Host smart-caedaa8a-e854-48d1-8820-7ac03e2589c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991238728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2991238728
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1422940823
Short name T646
Test name
Test status
Simulation time 3001511364 ps
CPU time 17.06 seconds
Started Aug 11 05:22:57 PM PDT 24
Finished Aug 11 05:23:14 PM PDT 24
Peak memory 216608 kb
Host smart-99bcdda1-c141-440c-ab80-e55950870dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422940823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1422940823
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1215162984
Short name T488
Test name
Test status
Simulation time 9539361852 ps
CPU time 13.53 seconds
Started Aug 11 05:22:58 PM PDT 24
Finished Aug 11 05:23:12 PM PDT 24
Peak memory 216672 kb
Host smart-0dd3efc6-55d0-4115-96b2-7b37171aaae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215162984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1215162984
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.601335981
Short name T376
Test name
Test status
Simulation time 189400123 ps
CPU time 2.14 seconds
Started Aug 11 05:22:58 PM PDT 24
Finished Aug 11 05:23:01 PM PDT 24
Peak memory 216604 kb
Host smart-5d8c7a0c-7d27-4b72-bb33-db6f7687ea2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601335981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.601335981
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4143363980
Short name T801
Test name
Test status
Simulation time 37216816 ps
CPU time 0.72 seconds
Started Aug 11 05:22:57 PM PDT 24
Finished Aug 11 05:22:58 PM PDT 24
Peak memory 205924 kb
Host smart-3c7189f8-57d5-470c-b34c-04fff3cdba09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143363980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4143363980
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1079524297
Short name T198
Test name
Test status
Simulation time 3842892446 ps
CPU time 9.95 seconds
Started Aug 11 05:23:05 PM PDT 24
Finished Aug 11 05:23:15 PM PDT 24
Peak memory 233160 kb
Host smart-a4cbf1e7-65d8-4b04-9a3a-e429cf8c61a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079524297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1079524297
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.130186907
Short name T647
Test name
Test status
Simulation time 12160140 ps
CPU time 0.72 seconds
Started Aug 11 05:23:13 PM PDT 24
Finished Aug 11 05:23:14 PM PDT 24
Peak memory 205232 kb
Host smart-c6f78c02-c706-43ef-9c21-57c2064b4804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130186907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.130186907
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1257874340
Short name T993
Test name
Test status
Simulation time 847931736 ps
CPU time 6.64 seconds
Started Aug 11 05:23:12 PM PDT 24
Finished Aug 11 05:23:19 PM PDT 24
Peak memory 233028 kb
Host smart-a1c2bab0-e164-4b91-a3e6-ffbb2cbcbdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257874340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1257874340
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3587249263
Short name T341
Test name
Test status
Simulation time 23221342 ps
CPU time 0.77 seconds
Started Aug 11 05:23:02 PM PDT 24
Finished Aug 11 05:23:03 PM PDT 24
Peak memory 206848 kb
Host smart-424f17f4-db34-46e3-a840-aecfe0a423b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587249263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3587249263
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3202979700
Short name T866
Test name
Test status
Simulation time 503410834 ps
CPU time 10.42 seconds
Started Aug 11 05:23:10 PM PDT 24
Finished Aug 11 05:23:21 PM PDT 24
Peak memory 241192 kb
Host smart-a8f4ffa6-0fa0-4dec-a8e8-ff200861230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202979700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3202979700
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1386632778
Short name T42
Test name
Test status
Simulation time 32224494000 ps
CPU time 141.93 seconds
Started Aug 11 05:23:13 PM PDT 24
Finished Aug 11 05:25:35 PM PDT 24
Peak memory 255144 kb
Host smart-64cbe183-3407-48a7-9eaf-82a2fbafceb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386632778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1386632778
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1795809942
Short name T997
Test name
Test status
Simulation time 18692832220 ps
CPU time 162.98 seconds
Started Aug 11 05:23:09 PM PDT 24
Finished Aug 11 05:25:52 PM PDT 24
Peak memory 257824 kb
Host smart-27ca2a2c-f842-4f03-b81f-6d012f1e351f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795809942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1795809942
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1332384857
Short name T676
Test name
Test status
Simulation time 15762188611 ps
CPU time 32.47 seconds
Started Aug 11 05:23:12 PM PDT 24
Finished Aug 11 05:23:45 PM PDT 24
Peak memory 240852 kb
Host smart-b6a86d6c-d4cb-4e39-9dce-c27484abfc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332384857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1332384857
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1408833625
Short name T85
Test name
Test status
Simulation time 5685520438 ps
CPU time 62.39 seconds
Started Aug 11 05:23:11 PM PDT 24
Finished Aug 11 05:24:14 PM PDT 24
Peak memory 249824 kb
Host smart-a8647c52-fc74-4486-bc79-66f46cd9d6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408833625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1408833625
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3818258557
Short name T584
Test name
Test status
Simulation time 1270014868 ps
CPU time 14.7 seconds
Started Aug 11 05:23:04 PM PDT 24
Finished Aug 11 05:23:19 PM PDT 24
Peak memory 233064 kb
Host smart-3557cad8-fb93-45eb-a140-8b1da8bc0afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818258557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3818258557
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1335664498
Short name T199
Test name
Test status
Simulation time 10093862743 ps
CPU time 54.64 seconds
Started Aug 11 05:23:10 PM PDT 24
Finished Aug 11 05:24:05 PM PDT 24
Peak memory 224952 kb
Host smart-f72fa4d3-bc64-4824-b60a-f33f6ef94d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335664498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1335664498
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.4274116415
Short name T250
Test name
Test status
Simulation time 3242851993 ps
CPU time 4.29 seconds
Started Aug 11 05:23:04 PM PDT 24
Finished Aug 11 05:23:09 PM PDT 24
Peak memory 233088 kb
Host smart-37fe5853-825c-45ab-8347-c729fa5b15e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274116415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.4274116415
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3466591860
Short name T234
Test name
Test status
Simulation time 4771201742 ps
CPU time 7.7 seconds
Started Aug 11 05:23:05 PM PDT 24
Finished Aug 11 05:23:13 PM PDT 24
Peak memory 224860 kb
Host smart-7d83798f-2e53-4948-a9ac-09e45934d690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466591860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3466591860
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.434341746
Short name T493
Test name
Test status
Simulation time 198020667 ps
CPU time 4.78 seconds
Started Aug 11 05:23:10 PM PDT 24
Finished Aug 11 05:23:15 PM PDT 24
Peak memory 223376 kb
Host smart-26ef5779-4e3c-4c21-a89c-9de4d3e89b97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=434341746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.434341746
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1991082252
Short name T248
Test name
Test status
Simulation time 227547468477 ps
CPU time 612.05 seconds
Started Aug 11 05:23:13 PM PDT 24
Finished Aug 11 05:33:25 PM PDT 24
Peak memory 267948 kb
Host smart-3e66b4ab-9972-4552-bb0b-178b3e1b9197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991082252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1991082252
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2423173863
Short name T609
Test name
Test status
Simulation time 6728196698 ps
CPU time 34.16 seconds
Started Aug 11 05:23:02 PM PDT 24
Finished Aug 11 05:23:36 PM PDT 24
Peak memory 216584 kb
Host smart-a735d43d-1414-4087-a6d3-fd87d597cc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423173863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2423173863
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3438497795
Short name T467
Test name
Test status
Simulation time 447966246 ps
CPU time 3.38 seconds
Started Aug 11 05:23:04 PM PDT 24
Finished Aug 11 05:23:08 PM PDT 24
Peak memory 216560 kb
Host smart-b063347a-2d3b-4823-9c22-c27313a0c5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438497795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3438497795
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3768123637
Short name T62
Test name
Test status
Simulation time 1393196180 ps
CPU time 1.76 seconds
Started Aug 11 05:23:03 PM PDT 24
Finished Aug 11 05:23:05 PM PDT 24
Peak memory 208364 kb
Host smart-d56ac978-78dd-4799-af53-a2ac00c062b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768123637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3768123637
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1907601630
Short name T340
Test name
Test status
Simulation time 30401910 ps
CPU time 0.78 seconds
Started Aug 11 05:23:05 PM PDT 24
Finished Aug 11 05:23:06 PM PDT 24
Peak memory 206260 kb
Host smart-c713088c-b7f4-4137-b208-fb4d1261cde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907601630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1907601630
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2317454172
Short name T757
Test name
Test status
Simulation time 1443003169 ps
CPU time 5.71 seconds
Started Aug 11 05:23:13 PM PDT 24
Finished Aug 11 05:23:19 PM PDT 24
Peak memory 233076 kb
Host smart-dae4a52a-6f96-432e-bf2d-a4e7af954602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317454172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2317454172
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3081585612
Short name T597
Test name
Test status
Simulation time 21473504 ps
CPU time 0.71 seconds
Started Aug 11 05:23:17 PM PDT 24
Finished Aug 11 05:23:18 PM PDT 24
Peak memory 205184 kb
Host smart-3ab4145d-6f89-440b-950f-e3b5e8fecc6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081585612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3081585612
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3177162407
Short name T470
Test name
Test status
Simulation time 42949817 ps
CPU time 2.55 seconds
Started Aug 11 05:23:17 PM PDT 24
Finished Aug 11 05:23:20 PM PDT 24
Peak memory 232932 kb
Host smart-d890ab58-4a54-4075-a477-4ffc44d26a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177162407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3177162407
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.916912910
Short name T354
Test name
Test status
Simulation time 131184282 ps
CPU time 0.81 seconds
Started Aug 11 05:23:09 PM PDT 24
Finished Aug 11 05:23:10 PM PDT 24
Peak memory 207196 kb
Host smart-1b489daa-f790-42bc-b2a0-08f76db5f7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916912910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.916912910
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1078265312
Short name T411
Test name
Test status
Simulation time 80137887899 ps
CPU time 149.72 seconds
Started Aug 11 05:23:15 PM PDT 24
Finished Aug 11 05:25:45 PM PDT 24
Peak memory 256436 kb
Host smart-474e6e4d-5e31-4f6b-a659-c920faf36e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078265312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1078265312
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1180551230
Short name T982
Test name
Test status
Simulation time 4306367009 ps
CPU time 33.2 seconds
Started Aug 11 05:23:16 PM PDT 24
Finished Aug 11 05:23:49 PM PDT 24
Peak memory 218000 kb
Host smart-9f015e15-832c-4301-8471-84baf6dc682e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180551230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1180551230
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2891377742
Short name T491
Test name
Test status
Simulation time 32023760701 ps
CPU time 122.18 seconds
Started Aug 11 05:23:18 PM PDT 24
Finished Aug 11 05:25:20 PM PDT 24
Peak memory 255240 kb
Host smart-7279fb40-18ff-4846-b953-ca8aa4dd19a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891377742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2891377742
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.659249592
Short name T525
Test name
Test status
Simulation time 1569128267 ps
CPU time 26.22 seconds
Started Aug 11 05:23:19 PM PDT 24
Finished Aug 11 05:23:46 PM PDT 24
Peak memory 249424 kb
Host smart-6473da0b-20ec-4518-8e34-d2c43c14f1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659249592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.659249592
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1595512677
Short name T779
Test name
Test status
Simulation time 367707195090 ps
CPU time 247.78 seconds
Started Aug 11 05:23:14 PM PDT 24
Finished Aug 11 05:27:22 PM PDT 24
Peak memory 249504 kb
Host smart-18314005-71eb-4a66-a656-e730b3fe1c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595512677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1595512677
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2561165759
Short name T540
Test name
Test status
Simulation time 3642289299 ps
CPU time 6.82 seconds
Started Aug 11 05:23:07 PM PDT 24
Finished Aug 11 05:23:14 PM PDT 24
Peak memory 224892 kb
Host smart-5198a508-7ae1-4b05-9b1a-4c611a95fc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561165759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2561165759
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1765474764
Short name T935
Test name
Test status
Simulation time 3669848385 ps
CPU time 7.95 seconds
Started Aug 11 05:23:19 PM PDT 24
Finished Aug 11 05:23:28 PM PDT 24
Peak memory 233408 kb
Host smart-fb52cb2f-1e86-4ab9-bfd5-2c40b34675c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765474764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1765474764
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1024158981
Short name T656
Test name
Test status
Simulation time 217889848 ps
CPU time 4.17 seconds
Started Aug 11 05:23:12 PM PDT 24
Finished Aug 11 05:23:16 PM PDT 24
Peak memory 232960 kb
Host smart-ac53a3a6-5cab-488c-b7aa-b9dd0c1a5438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024158981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1024158981
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.805777738
Short name T890
Test name
Test status
Simulation time 435812571 ps
CPU time 3.95 seconds
Started Aug 11 05:23:09 PM PDT 24
Finished Aug 11 05:23:13 PM PDT 24
Peak memory 232928 kb
Host smart-cd4c4247-81c7-4e8e-9351-b72766133822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805777738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.805777738
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2008858541
Short name T621
Test name
Test status
Simulation time 1310468109 ps
CPU time 7.13 seconds
Started Aug 11 05:23:16 PM PDT 24
Finished Aug 11 05:23:23 PM PDT 24
Peak memory 222036 kb
Host smart-a425fc02-fdec-4990-8c89-9f50c7c64fb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2008858541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2008858541
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.468873501
Short name T865
Test name
Test status
Simulation time 843437504 ps
CPU time 9.82 seconds
Started Aug 11 05:23:16 PM PDT 24
Finished Aug 11 05:23:26 PM PDT 24
Peak memory 224776 kb
Host smart-4900d285-83bc-48db-b13a-d2941854ee1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468873501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.468873501
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1991928454
Short name T737
Test name
Test status
Simulation time 30776888978 ps
CPU time 45.09 seconds
Started Aug 11 05:23:12 PM PDT 24
Finished Aug 11 05:23:57 PM PDT 24
Peak memory 216620 kb
Host smart-e35ca37e-be96-47da-a92e-c354c0517c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991928454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1991928454
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.602039236
Short name T530
Test name
Test status
Simulation time 6163662451 ps
CPU time 21.19 seconds
Started Aug 11 05:23:14 PM PDT 24
Finished Aug 11 05:23:35 PM PDT 24
Peak memory 216616 kb
Host smart-2662f279-a639-4d7e-bd22-b0f15a9c831a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602039236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.602039236
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1121012689
Short name T987
Test name
Test status
Simulation time 146529582 ps
CPU time 0.95 seconds
Started Aug 11 05:23:12 PM PDT 24
Finished Aug 11 05:23:13 PM PDT 24
Peak memory 207400 kb
Host smart-3a9334a1-0562-4ee3-bb89-2f803e5d7dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121012689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1121012689
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2421836251
Short name T921
Test name
Test status
Simulation time 129555721 ps
CPU time 0.98 seconds
Started Aug 11 05:23:13 PM PDT 24
Finished Aug 11 05:23:14 PM PDT 24
Peak memory 206592 kb
Host smart-8618df2e-ff20-4788-8bfd-a9a6dab05a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421836251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2421836251
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3939119044
Short name T389
Test name
Test status
Simulation time 366362881 ps
CPU time 3.57 seconds
Started Aug 11 05:23:19 PM PDT 24
Finished Aug 11 05:23:23 PM PDT 24
Peak memory 232936 kb
Host smart-604ce198-7daa-4153-a1d5-dfeaca2999f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939119044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3939119044
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2556592506
Short name T749
Test name
Test status
Simulation time 12188658 ps
CPU time 0.73 seconds
Started Aug 11 05:23:24 PM PDT 24
Finished Aug 11 05:23:25 PM PDT 24
Peak memory 205984 kb
Host smart-5f6f202b-464d-4bdc-93ac-b649ac07384c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556592506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2556592506
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1384829958
Short name T560
Test name
Test status
Simulation time 141652711 ps
CPU time 2.74 seconds
Started Aug 11 05:23:15 PM PDT 24
Finished Aug 11 05:23:18 PM PDT 24
Peak memory 224716 kb
Host smart-539ad30a-d942-4598-9b63-2fd8742a044e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384829958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1384829958
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1235884857
Short name T751
Test name
Test status
Simulation time 16849982 ps
CPU time 0.8 seconds
Started Aug 11 05:23:16 PM PDT 24
Finished Aug 11 05:23:17 PM PDT 24
Peak memory 206904 kb
Host smart-001d4e62-b8f7-44ee-8451-a48f07e6251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235884857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1235884857
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1770499882
Short name T190
Test name
Test status
Simulation time 9201717145 ps
CPU time 36.46 seconds
Started Aug 11 05:23:23 PM PDT 24
Finished Aug 11 05:24:00 PM PDT 24
Peak memory 241224 kb
Host smart-ba410650-c0aa-40f2-9010-f0ab38d1a53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770499882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1770499882
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3324637846
Short name T556
Test name
Test status
Simulation time 2041880659 ps
CPU time 43.77 seconds
Started Aug 11 05:23:22 PM PDT 24
Finished Aug 11 05:24:06 PM PDT 24
Peak memory 249500 kb
Host smart-ae484fc2-93de-4efd-9dd5-964d6114dda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324637846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3324637846
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.97045946
Short name T580
Test name
Test status
Simulation time 994125008 ps
CPU time 11.34 seconds
Started Aug 11 05:23:17 PM PDT 24
Finished Aug 11 05:23:29 PM PDT 24
Peak memory 224804 kb
Host smart-436f78db-52e7-479e-b581-ce0fad8e86b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97045946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.97045946
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.413077989
Short name T963
Test name
Test status
Simulation time 197211616 ps
CPU time 4.08 seconds
Started Aug 11 05:23:18 PM PDT 24
Finished Aug 11 05:23:23 PM PDT 24
Peak memory 233040 kb
Host smart-39d4352c-5c58-4096-bbd3-e32a115593f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413077989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.413077989
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.349302676
Short name T206
Test name
Test status
Simulation time 20673320817 ps
CPU time 77.93 seconds
Started Aug 11 05:23:17 PM PDT 24
Finished Aug 11 05:24:35 PM PDT 24
Peak memory 241244 kb
Host smart-73a842a0-c540-4866-961d-d97c41c564d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349302676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.349302676
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.807502587
Short name T848
Test name
Test status
Simulation time 617002134 ps
CPU time 3.3 seconds
Started Aug 11 05:23:16 PM PDT 24
Finished Aug 11 05:23:20 PM PDT 24
Peak memory 224780 kb
Host smart-968842f3-c7a9-471f-a3e9-3e26ea81c449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807502587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.807502587
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2259564197
Short name T440
Test name
Test status
Simulation time 7123887739 ps
CPU time 21.42 seconds
Started Aug 11 05:23:18 PM PDT 24
Finished Aug 11 05:23:39 PM PDT 24
Peak memory 233104 kb
Host smart-6f74ecf2-747c-41a9-bc3b-e6671d36e47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259564197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2259564197
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.120991361
Short name T620
Test name
Test status
Simulation time 943860899 ps
CPU time 6.01 seconds
Started Aug 11 05:23:21 PM PDT 24
Finished Aug 11 05:23:27 PM PDT 24
Peak memory 223400 kb
Host smart-60b9ced2-95e8-4e58-a140-655a26a1531c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=120991361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.120991361
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2444207212
Short name T1000
Test name
Test status
Simulation time 169212259451 ps
CPU time 408.68 seconds
Started Aug 11 05:23:24 PM PDT 24
Finished Aug 11 05:30:13 PM PDT 24
Peak memory 257184 kb
Host smart-1b600257-9aef-4325-a6ab-822f9e57444a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444207212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2444207212
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1534612132
Short name T994
Test name
Test status
Simulation time 4621071401 ps
CPU time 33.41 seconds
Started Aug 11 05:23:17 PM PDT 24
Finished Aug 11 05:23:50 PM PDT 24
Peak memory 218676 kb
Host smart-abf9a1c3-2b4b-49db-a586-305ae341f3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534612132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1534612132
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3274536002
Short name T901
Test name
Test status
Simulation time 13698679 ps
CPU time 0.72 seconds
Started Aug 11 05:23:19 PM PDT 24
Finished Aug 11 05:23:20 PM PDT 24
Peak memory 205876 kb
Host smart-f0187b56-7177-4ee5-ab48-0acffbc0990b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274536002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3274536002
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2124497141
Short name T393
Test name
Test status
Simulation time 132283729 ps
CPU time 1.31 seconds
Started Aug 11 05:23:19 PM PDT 24
Finished Aug 11 05:23:20 PM PDT 24
Peak memory 216424 kb
Host smart-10ccf9a4-4b64-4630-9c40-af9ff94c0f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124497141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2124497141
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.256422316
Short name T410
Test name
Test status
Simulation time 100272960 ps
CPU time 0.86 seconds
Started Aug 11 05:23:18 PM PDT 24
Finished Aug 11 05:23:19 PM PDT 24
Peak memory 206244 kb
Host smart-cd89feb3-0334-4db9-9be4-9d7bb7b6aeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256422316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.256422316
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1177182552
Short name T989
Test name
Test status
Simulation time 62916146 ps
CPU time 2.15 seconds
Started Aug 11 05:23:17 PM PDT 24
Finished Aug 11 05:23:19 PM PDT 24
Peak memory 224556 kb
Host smart-e5e8023d-9866-4289-94a9-eb206477e173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177182552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1177182552
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1336520665
Short name T709
Test name
Test status
Simulation time 11803335 ps
CPU time 0.7 seconds
Started Aug 11 05:23:32 PM PDT 24
Finished Aug 11 05:23:33 PM PDT 24
Peak memory 205804 kb
Host smart-3370c414-8197-4f22-8cbb-1c19c78938c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336520665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1336520665
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2620114110
Short name T576
Test name
Test status
Simulation time 167356375 ps
CPU time 4.21 seconds
Started Aug 11 05:23:23 PM PDT 24
Finished Aug 11 05:23:27 PM PDT 24
Peak memory 232976 kb
Host smart-c50b1280-1964-484f-a410-c18d0bfbd27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620114110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2620114110
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4190226539
Short name T365
Test name
Test status
Simulation time 30643064 ps
CPU time 0.79 seconds
Started Aug 11 05:23:22 PM PDT 24
Finished Aug 11 05:23:23 PM PDT 24
Peak memory 206972 kb
Host smart-4fd9671a-e350-417b-b87e-bf42eaa90a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190226539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4190226539
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.4057556338
Short name T920
Test name
Test status
Simulation time 296365688417 ps
CPU time 190.12 seconds
Started Aug 11 05:23:32 PM PDT 24
Finished Aug 11 05:26:42 PM PDT 24
Peak memory 249560 kb
Host smart-7420573e-b2f8-456c-9db0-109db810d5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057556338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.4057556338
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.145194973
Short name T478
Test name
Test status
Simulation time 13791024105 ps
CPU time 35.78 seconds
Started Aug 11 05:23:26 PM PDT 24
Finished Aug 11 05:24:02 PM PDT 24
Peak memory 241300 kb
Host smart-985e2cfe-fbee-4ce9-8f11-ffe4dab7e5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145194973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.145194973
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3595286010
Short name T905
Test name
Test status
Simulation time 151340634013 ps
CPU time 372.26 seconds
Started Aug 11 05:23:26 PM PDT 24
Finished Aug 11 05:29:38 PM PDT 24
Peak memory 257620 kb
Host smart-f249116e-9fd7-4dc2-879e-de11086a659e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595286010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3595286010
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3981324342
Short name T438
Test name
Test status
Simulation time 783121643 ps
CPU time 4.13 seconds
Started Aug 11 05:23:28 PM PDT 24
Finished Aug 11 05:23:32 PM PDT 24
Peak memory 237508 kb
Host smart-4f394b46-84ce-4d8a-b8f8-59d2478beb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981324342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3981324342
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.940243479
Short name T48
Test name
Test status
Simulation time 125619917266 ps
CPU time 143.09 seconds
Started Aug 11 05:23:27 PM PDT 24
Finished Aug 11 05:25:50 PM PDT 24
Peak memory 255476 kb
Host smart-e8a8e750-e763-453d-843e-73903e8c45d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940243479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.940243479
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3682873143
Short name T480
Test name
Test status
Simulation time 366757662 ps
CPU time 4.16 seconds
Started Aug 11 05:23:24 PM PDT 24
Finished Aug 11 05:23:28 PM PDT 24
Peak memory 233076 kb
Host smart-693f2510-60e4-481b-8938-c7cda01fb845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682873143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3682873143
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2885427977
Short name T481
Test name
Test status
Simulation time 1032366167 ps
CPU time 19.09 seconds
Started Aug 11 05:23:21 PM PDT 24
Finished Aug 11 05:23:40 PM PDT 24
Peak memory 250064 kb
Host smart-70669b70-68e6-4495-9fae-c4964ef38c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885427977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2885427977
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3252109209
Short name T542
Test name
Test status
Simulation time 9781332566 ps
CPU time 8.33 seconds
Started Aug 11 05:23:23 PM PDT 24
Finished Aug 11 05:23:31 PM PDT 24
Peak memory 233056 kb
Host smart-a41157be-d5b2-4a06-9f99-a96205030cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252109209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3252109209
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3022273329
Short name T754
Test name
Test status
Simulation time 575961825 ps
CPU time 4.99 seconds
Started Aug 11 05:23:24 PM PDT 24
Finished Aug 11 05:23:29 PM PDT 24
Peak memory 233004 kb
Host smart-ef315a7a-07a2-49fa-8ae5-011ae98de047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022273329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3022273329
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.186792163
Short name T820
Test name
Test status
Simulation time 1621932278 ps
CPU time 6.4 seconds
Started Aug 11 05:23:27 PM PDT 24
Finished Aug 11 05:23:33 PM PDT 24
Peak memory 220832 kb
Host smart-f06475e7-64f7-44f0-a69b-44c13d0fe48b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=186792163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.186792163
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3683697151
Short name T156
Test name
Test status
Simulation time 226986694 ps
CPU time 1.06 seconds
Started Aug 11 05:23:30 PM PDT 24
Finished Aug 11 05:23:31 PM PDT 24
Peak memory 208060 kb
Host smart-db2dd476-9f39-4420-a2e6-3438dd2a42b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683697151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3683697151
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1310655795
Short name T305
Test name
Test status
Simulation time 2539169786 ps
CPU time 4.33 seconds
Started Aug 11 05:23:22 PM PDT 24
Finished Aug 11 05:23:26 PM PDT 24
Peak memory 216948 kb
Host smart-52064a2f-bc1a-46d4-8208-10f0156562d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310655795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1310655795
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2015320212
Short name T343
Test name
Test status
Simulation time 894504228 ps
CPU time 5.23 seconds
Started Aug 11 05:23:23 PM PDT 24
Finished Aug 11 05:23:29 PM PDT 24
Peak memory 216520 kb
Host smart-fa6a9fbb-8786-4534-97a6-3a2e4a0fc418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015320212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2015320212
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2325699223
Short name T509
Test name
Test status
Simulation time 21483164 ps
CPU time 0.96 seconds
Started Aug 11 05:23:23 PM PDT 24
Finished Aug 11 05:23:24 PM PDT 24
Peak memory 207648 kb
Host smart-18ceb730-8498-44d1-b4a7-191a2083e839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325699223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2325699223
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1704602090
Short name T398
Test name
Test status
Simulation time 97128241 ps
CPU time 0.89 seconds
Started Aug 11 05:23:22 PM PDT 24
Finished Aug 11 05:23:23 PM PDT 24
Peak memory 206236 kb
Host smart-17d8f852-b815-4d25-9ef8-c74d36e124ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704602090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1704602090
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.544398333
Short name T945
Test name
Test status
Simulation time 11039454264 ps
CPU time 9.83 seconds
Started Aug 11 05:23:22 PM PDT 24
Finished Aug 11 05:23:32 PM PDT 24
Peak memory 249512 kb
Host smart-8680c4e6-b97b-4a32-a324-f723d2dfab50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544398333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.544398333
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2512912751
Short name T886
Test name
Test status
Simulation time 14050797 ps
CPU time 0.73 seconds
Started Aug 11 05:18:46 PM PDT 24
Finished Aug 11 05:18:47 PM PDT 24
Peak memory 205744 kb
Host smart-8e75765e-7d88-45d7-b3c6-4dd3a7aabecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512912751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
512912751
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.946725410
Short name T992
Test name
Test status
Simulation time 3373596777 ps
CPU time 11.05 seconds
Started Aug 11 05:18:37 PM PDT 24
Finished Aug 11 05:18:48 PM PDT 24
Peak memory 233020 kb
Host smart-abedc7e7-a8ea-4b5e-b00e-ecb8556dadd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946725410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.946725410
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2307205782
Short name T519
Test name
Test status
Simulation time 69394105 ps
CPU time 0.82 seconds
Started Aug 11 05:18:33 PM PDT 24
Finished Aug 11 05:18:34 PM PDT 24
Peak memory 206892 kb
Host smart-f204a707-1fbd-4bd9-8926-04a9a7dffd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307205782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2307205782
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2547176191
Short name T922
Test name
Test status
Simulation time 11558214119 ps
CPU time 54.09 seconds
Started Aug 11 05:18:42 PM PDT 24
Finished Aug 11 05:19:36 PM PDT 24
Peak memory 249548 kb
Host smart-d8ada145-b62e-4d8a-91c1-c16bcd7f8334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547176191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2547176191
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1410817574
Short name T47
Test name
Test status
Simulation time 17059058745 ps
CPU time 154.76 seconds
Started Aug 11 05:18:44 PM PDT 24
Finished Aug 11 05:21:18 PM PDT 24
Peak memory 241124 kb
Host smart-97510e68-8c97-47c4-a08f-212e93d8c52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410817574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1410817574
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.594335560
Short name T615
Test name
Test status
Simulation time 9435327948 ps
CPU time 97.9 seconds
Started Aug 11 05:18:43 PM PDT 24
Finished Aug 11 05:20:21 PM PDT 24
Peak memory 240608 kb
Host smart-4a98d0ae-2069-4ea2-81bd-4f440482a3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594335560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
594335560
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.238345080
Short name T843
Test name
Test status
Simulation time 1140281243 ps
CPU time 23.13 seconds
Started Aug 11 05:18:35 PM PDT 24
Finished Aug 11 05:18:58 PM PDT 24
Peak memory 241256 kb
Host smart-63c6e39c-81dc-4d00-9e30-da7cc1738449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238345080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.238345080
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1272549679
Short name T420
Test name
Test status
Simulation time 1351095517 ps
CPU time 5.11 seconds
Started Aug 11 05:18:42 PM PDT 24
Finished Aug 11 05:18:47 PM PDT 24
Peak memory 233096 kb
Host smart-387cddce-151c-4eee-a46c-7cbb30c52178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272549679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1272549679
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1897179405
Short name T387
Test name
Test status
Simulation time 281579190 ps
CPU time 2.2 seconds
Started Aug 11 05:18:42 PM PDT 24
Finished Aug 11 05:18:44 PM PDT 24
Peak memory 224188 kb
Host smart-e2bc6305-acfd-4517-a22f-4cc13266bf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897179405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1897179405
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1246447910
Short name T695
Test name
Test status
Simulation time 434737601 ps
CPU time 3.01 seconds
Started Aug 11 05:18:37 PM PDT 24
Finished Aug 11 05:18:41 PM PDT 24
Peak memory 224868 kb
Host smart-cda54ce1-4f3d-457f-a993-5bcb84db69c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246447910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1246447910
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2220139372
Short name T554
Test name
Test status
Simulation time 188724749 ps
CPU time 4.2 seconds
Started Aug 11 05:18:36 PM PDT 24
Finished Aug 11 05:18:40 PM PDT 24
Peak memory 232928 kb
Host smart-c7e4bdae-a42b-4723-98e4-176438632a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220139372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2220139372
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3512321598
Short name T766
Test name
Test status
Simulation time 1394253889 ps
CPU time 18.68 seconds
Started Aug 11 05:18:36 PM PDT 24
Finished Aug 11 05:18:55 PM PDT 24
Peak memory 223496 kb
Host smart-e9bfa54d-3105-4afe-b95c-601e1bf94812
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3512321598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3512321598
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3499989018
Short name T71
Test name
Test status
Simulation time 85499743 ps
CPU time 1.21 seconds
Started Aug 11 05:18:45 PM PDT 24
Finished Aug 11 05:18:46 PM PDT 24
Peak memory 236868 kb
Host smart-d16eaacf-2e52-4b10-816c-475c7adca205
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499989018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3499989018
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.997770160
Short name T294
Test name
Test status
Simulation time 42365034988 ps
CPU time 104.56 seconds
Started Aug 11 05:18:45 PM PDT 24
Finished Aug 11 05:20:29 PM PDT 24
Peak memory 249604 kb
Host smart-8f110a1d-1e56-4ac7-ba31-6ef288a07f33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997770160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.997770160
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.85362533
Short name T943
Test name
Test status
Simulation time 519372369 ps
CPU time 7.1 seconds
Started Aug 11 05:18:35 PM PDT 24
Finished Aug 11 05:18:42 PM PDT 24
Peak memory 216740 kb
Host smart-2a102272-f568-4567-b469-1f4c60a591c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85362533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.85362533
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.817650522
Short name T399
Test name
Test status
Simulation time 2180199999 ps
CPU time 4.97 seconds
Started Aug 11 05:18:31 PM PDT 24
Finished Aug 11 05:18:36 PM PDT 24
Peak memory 216588 kb
Host smart-da81f40f-8ab8-496f-a304-e1470b43fca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817650522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.817650522
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.459774036
Short name T421
Test name
Test status
Simulation time 2490773221 ps
CPU time 4.34 seconds
Started Aug 11 05:18:38 PM PDT 24
Finished Aug 11 05:18:42 PM PDT 24
Peak memory 216668 kb
Host smart-ffdbdf45-ee59-4875-ae02-cf604d24f91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459774036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.459774036
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.982460290
Short name T791
Test name
Test status
Simulation time 102255282 ps
CPU time 0.78 seconds
Started Aug 11 05:18:38 PM PDT 24
Finished Aug 11 05:18:39 PM PDT 24
Peak memory 206264 kb
Host smart-24c214db-5902-44db-9c2d-de170ce8a5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982460290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.982460290
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2393269773
Short name T582
Test name
Test status
Simulation time 2799051134 ps
CPU time 8.58 seconds
Started Aug 11 05:18:36 PM PDT 24
Finished Aug 11 05:18:45 PM PDT 24
Peak memory 234328 kb
Host smart-0f2d67b3-af2d-4a7e-af0f-db2bd07b9e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393269773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2393269773
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3544759858
Short name T770
Test name
Test status
Simulation time 12693974 ps
CPU time 0.73 seconds
Started Aug 11 05:23:34 PM PDT 24
Finished Aug 11 05:23:35 PM PDT 24
Peak memory 205772 kb
Host smart-d396f48d-4c35-42ce-9fbf-075f9f2f6a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544759858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3544759858
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.793891577
Short name T424
Test name
Test status
Simulation time 352858452 ps
CPU time 6.23 seconds
Started Aug 11 05:23:28 PM PDT 24
Finished Aug 11 05:23:34 PM PDT 24
Peak memory 224836 kb
Host smart-3a574d03-d564-4d72-9f8a-a77085088ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793891577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.793891577
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.529550396
Short name T725
Test name
Test status
Simulation time 14660018 ps
CPU time 0.77 seconds
Started Aug 11 05:23:27 PM PDT 24
Finished Aug 11 05:23:28 PM PDT 24
Peak memory 206880 kb
Host smart-79ad23e4-927e-49d5-9b32-3eba76291bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529550396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.529550396
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1663926016
Short name T962
Test name
Test status
Simulation time 109270216 ps
CPU time 0.95 seconds
Started Aug 11 05:23:35 PM PDT 24
Finished Aug 11 05:23:36 PM PDT 24
Peak memory 216288 kb
Host smart-5225599d-d309-4e08-b15b-e3f1fcea47a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663926016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1663926016
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2199051437
Short name T127
Test name
Test status
Simulation time 26014553455 ps
CPU time 237.67 seconds
Started Aug 11 05:23:33 PM PDT 24
Finished Aug 11 05:27:31 PM PDT 24
Peak memory 257704 kb
Host smart-21794c36-529b-4489-ae4b-d55fb18dab70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199051437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2199051437
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.640164391
Short name T185
Test name
Test status
Simulation time 10573292027 ps
CPU time 46.62 seconds
Started Aug 11 05:23:37 PM PDT 24
Finished Aug 11 05:24:24 PM PDT 24
Peak memory 256928 kb
Host smart-81b963cc-7327-4355-a5b6-60ff1fac15c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640164391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.640164391
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3142189406
Short name T635
Test name
Test status
Simulation time 139985735 ps
CPU time 4.31 seconds
Started Aug 11 05:23:29 PM PDT 24
Finished Aug 11 05:23:34 PM PDT 24
Peak memory 225120 kb
Host smart-66c05aab-9d1d-4f63-bf74-dc2c985243d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142189406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3142189406
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3713520600
Short name T277
Test name
Test status
Simulation time 90304518383 ps
CPU time 198.14 seconds
Started Aug 11 05:23:27 PM PDT 24
Finished Aug 11 05:26:46 PM PDT 24
Peak memory 270380 kb
Host smart-5c18f5ab-44dc-40f3-a764-1efff1334b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713520600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3713520600
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1103102255
Short name T611
Test name
Test status
Simulation time 4328223465 ps
CPU time 4.33 seconds
Started Aug 11 05:23:26 PM PDT 24
Finished Aug 11 05:23:30 PM PDT 24
Peak memory 224860 kb
Host smart-c0405ad9-daae-421a-8763-fb2de47a7a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103102255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1103102255
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.559417728
Short name T125
Test name
Test status
Simulation time 1838925964 ps
CPU time 18.18 seconds
Started Aug 11 05:23:28 PM PDT 24
Finished Aug 11 05:23:46 PM PDT 24
Peak memory 232936 kb
Host smart-3335d615-49f0-40ad-9686-f60e521ae280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559417728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.559417728
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2163088955
Short name T803
Test name
Test status
Simulation time 110258425 ps
CPU time 2.2 seconds
Started Aug 11 05:23:28 PM PDT 24
Finished Aug 11 05:23:30 PM PDT 24
Peak memory 224308 kb
Host smart-023b6389-412e-4130-be75-96babd824ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163088955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2163088955
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4041834925
Short name T507
Test name
Test status
Simulation time 1337673274 ps
CPU time 6.5 seconds
Started Aug 11 05:23:29 PM PDT 24
Finished Aug 11 05:23:36 PM PDT 24
Peak memory 233096 kb
Host smart-febde4eb-d17a-484e-b0dc-d4d4ad678151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041834925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4041834925
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2101181530
Short name T54
Test name
Test status
Simulation time 1303291963 ps
CPU time 5.99 seconds
Started Aug 11 05:23:28 PM PDT 24
Finished Aug 11 05:23:34 PM PDT 24
Peak memory 219628 kb
Host smart-b33224cd-f8ba-4f2a-a353-9d239507c5aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2101181530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2101181530
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2410193519
Short name T50
Test name
Test status
Simulation time 16586621707 ps
CPU time 90.57 seconds
Started Aug 11 05:23:34 PM PDT 24
Finished Aug 11 05:25:04 PM PDT 24
Peak memory 252188 kb
Host smart-4c0742cb-101b-4a52-a981-c54e1f7fccaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410193519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2410193519
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.625463278
Short name T479
Test name
Test status
Simulation time 12396407592 ps
CPU time 18.78 seconds
Started Aug 11 05:23:28 PM PDT 24
Finished Aug 11 05:23:47 PM PDT 24
Peak memory 216612 kb
Host smart-d0968fa3-59fc-496d-89f4-ad6984342d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625463278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.625463278
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1776097001
Short name T82
Test name
Test status
Simulation time 2979052692 ps
CPU time 7.16 seconds
Started Aug 11 05:23:32 PM PDT 24
Finished Aug 11 05:23:39 PM PDT 24
Peak memory 216712 kb
Host smart-cbe2cfea-3aba-4843-a816-95fb65629b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776097001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1776097001
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2098323124
Short name T664
Test name
Test status
Simulation time 166416516 ps
CPU time 1.89 seconds
Started Aug 11 05:23:29 PM PDT 24
Finished Aug 11 05:23:31 PM PDT 24
Peak memory 216604 kb
Host smart-48567e01-c80f-41bc-ba0d-b4a961160484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098323124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2098323124
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3415742021
Short name T377
Test name
Test status
Simulation time 56424396 ps
CPU time 0.86 seconds
Started Aug 11 05:23:29 PM PDT 24
Finished Aug 11 05:23:30 PM PDT 24
Peak memory 206296 kb
Host smart-7d80b130-ffcb-4c32-bf89-25c104f3c26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415742021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3415742021
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3229258814
Short name T209
Test name
Test status
Simulation time 13175907695 ps
CPU time 12.43 seconds
Started Aug 11 05:23:27 PM PDT 24
Finished Aug 11 05:23:40 PM PDT 24
Peak memory 234064 kb
Host smart-9e516a7e-64be-4b6b-9f4a-62d61e403ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229258814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3229258814
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2656351333
Short name T693
Test name
Test status
Simulation time 44473416 ps
CPU time 0.74 seconds
Started Aug 11 05:23:44 PM PDT 24
Finished Aug 11 05:23:45 PM PDT 24
Peak memory 205808 kb
Host smart-6101145b-a248-40dc-b5a2-c8d2bc0a303c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656351333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2656351333
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3795004376
Short name T712
Test name
Test status
Simulation time 643961830 ps
CPU time 5.02 seconds
Started Aug 11 05:23:40 PM PDT 24
Finished Aug 11 05:23:46 PM PDT 24
Peak memory 233052 kb
Host smart-a5c8519d-2e1c-4616-8c79-80fbf820ddb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795004376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3795004376
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2935655462
Short name T465
Test name
Test status
Simulation time 60685702 ps
CPU time 0.79 seconds
Started Aug 11 05:23:35 PM PDT 24
Finished Aug 11 05:23:36 PM PDT 24
Peak memory 207480 kb
Host smart-10ac1fe8-b28f-4dfc-9b67-931cd3ab4d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935655462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2935655462
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.352182885
Short name T228
Test name
Test status
Simulation time 11125102999 ps
CPU time 66.69 seconds
Started Aug 11 05:23:39 PM PDT 24
Finished Aug 11 05:24:46 PM PDT 24
Peak memory 252092 kb
Host smart-6ac37973-a8aa-4679-b47d-dd7c80b9c7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352182885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.352182885
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2626167319
Short name T891
Test name
Test status
Simulation time 58834754919 ps
CPU time 253.61 seconds
Started Aug 11 05:23:41 PM PDT 24
Finished Aug 11 05:27:55 PM PDT 24
Peak memory 249504 kb
Host smart-60422afb-bdb9-4cdc-89d2-624ec85e3421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626167319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2626167319
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2951486431
Short name T651
Test name
Test status
Simulation time 46964292905 ps
CPU time 138.6 seconds
Started Aug 11 05:23:47 PM PDT 24
Finished Aug 11 05:26:06 PM PDT 24
Peak memory 257724 kb
Host smart-7b14007c-bd5a-4827-8b4d-4fbfa630ac3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951486431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2951486431
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2001343812
Short name T898
Test name
Test status
Simulation time 411541280 ps
CPU time 4.56 seconds
Started Aug 11 05:23:39 PM PDT 24
Finished Aug 11 05:23:44 PM PDT 24
Peak memory 235904 kb
Host smart-5c413759-9182-4d9d-a1d9-1415fe02a98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001343812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2001343812
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2612384355
Short name T10
Test name
Test status
Simulation time 28567386925 ps
CPU time 58.39 seconds
Started Aug 11 05:23:40 PM PDT 24
Finished Aug 11 05:24:39 PM PDT 24
Peak memory 251020 kb
Host smart-c0e044df-0505-4bd9-b00b-eac98b7e9a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612384355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2612384355
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3243289719
Short name T985
Test name
Test status
Simulation time 211504202 ps
CPU time 4.51 seconds
Started Aug 11 05:23:44 PM PDT 24
Finished Aug 11 05:23:48 PM PDT 24
Peak memory 233028 kb
Host smart-e6d45f46-84d6-4d38-a2a2-84380dd26df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243289719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3243289719
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2882289938
Short name T246
Test name
Test status
Simulation time 1681961273 ps
CPU time 21.12 seconds
Started Aug 11 05:23:42 PM PDT 24
Finished Aug 11 05:24:03 PM PDT 24
Peak memory 224916 kb
Host smart-72a90caa-15db-4287-bbce-1a3e517bb9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882289938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2882289938
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.811614667
Short name T293
Test name
Test status
Simulation time 2066123636 ps
CPU time 8.43 seconds
Started Aug 11 05:23:41 PM PDT 24
Finished Aug 11 05:23:50 PM PDT 24
Peak memory 233028 kb
Host smart-3a122750-38d3-4de8-8d4d-97bb6e0b617d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811614667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.811614667
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1518883007
Short name T457
Test name
Test status
Simulation time 3712324452 ps
CPU time 15.71 seconds
Started Aug 11 05:23:44 PM PDT 24
Finished Aug 11 05:24:00 PM PDT 24
Peak memory 241268 kb
Host smart-6596f334-f958-4b9c-8b83-65b45795a830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518883007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1518883007
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1642593603
Short name T547
Test name
Test status
Simulation time 593807814 ps
CPU time 3.78 seconds
Started Aug 11 05:23:39 PM PDT 24
Finished Aug 11 05:23:42 PM PDT 24
Peak memory 223384 kb
Host smart-fe8da3d7-9bf9-4f8b-a073-ade54a4d4e6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1642593603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1642593603
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1702426352
Short name T731
Test name
Test status
Simulation time 100518871 ps
CPU time 0.97 seconds
Started Aug 11 05:23:47 PM PDT 24
Finished Aug 11 05:23:48 PM PDT 24
Peak memory 207864 kb
Host smart-73546cf3-4c07-40dc-b78b-9221f05b6773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702426352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1702426352
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3199774213
Short name T747
Test name
Test status
Simulation time 6516020292 ps
CPU time 11.85 seconds
Started Aug 11 05:23:34 PM PDT 24
Finished Aug 11 05:23:46 PM PDT 24
Peak memory 216920 kb
Host smart-8d0a792d-1c69-43d0-a924-914321831a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199774213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3199774213
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.509973842
Short name T585
Test name
Test status
Simulation time 634579516 ps
CPU time 5.35 seconds
Started Aug 11 05:23:34 PM PDT 24
Finished Aug 11 05:23:40 PM PDT 24
Peak memory 216604 kb
Host smart-fa4de0db-584d-495c-a644-f2ae1ec143d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509973842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.509973842
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1704704008
Short name T877
Test name
Test status
Simulation time 30877649 ps
CPU time 1.15 seconds
Started Aug 11 05:23:40 PM PDT 24
Finished Aug 11 05:23:41 PM PDT 24
Peak memory 208000 kb
Host smart-af3e4b33-8727-4a6c-9922-545e92843ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704704008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1704704008
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3496515090
Short name T644
Test name
Test status
Simulation time 28267427 ps
CPU time 0.8 seconds
Started Aug 11 05:23:40 PM PDT 24
Finished Aug 11 05:23:41 PM PDT 24
Peak memory 206232 kb
Host smart-85a084ea-6a8f-4da2-8a19-bf81d0702ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496515090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3496515090
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2616471675
Short name T235
Test name
Test status
Simulation time 9503909264 ps
CPU time 14.14 seconds
Started Aug 11 05:23:38 PM PDT 24
Finished Aug 11 05:23:53 PM PDT 24
Peak memory 233060 kb
Host smart-d72c4e51-fa5c-4bba-a815-8c79a74152a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616471675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2616471675
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3390909798
Short name T888
Test name
Test status
Simulation time 4070668631 ps
CPU time 8.09 seconds
Started Aug 11 05:23:50 PM PDT 24
Finished Aug 11 05:23:58 PM PDT 24
Peak memory 233128 kb
Host smart-aa9908a9-04a8-4089-b2e3-c246d8bbe623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390909798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3390909798
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2665381983
Short name T649
Test name
Test status
Simulation time 85869840 ps
CPU time 0.77 seconds
Started Aug 11 05:23:47 PM PDT 24
Finished Aug 11 05:23:48 PM PDT 24
Peak memory 205720 kb
Host smart-5f36213a-c414-4276-bc10-b4bb5cea4973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665381983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2665381983
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.114980374
Short name T659
Test name
Test status
Simulation time 23925877817 ps
CPU time 88.11 seconds
Started Aug 11 05:23:53 PM PDT 24
Finished Aug 11 05:25:21 PM PDT 24
Peak memory 253380 kb
Host smart-8fcdabd1-a09b-4170-8163-d8507312ccfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114980374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.114980374
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3484349751
Short name T429
Test name
Test status
Simulation time 58225765313 ps
CPU time 137.63 seconds
Started Aug 11 05:23:52 PM PDT 24
Finished Aug 11 05:26:10 PM PDT 24
Peak memory 251604 kb
Host smart-1a5e6010-0862-43a7-9949-a04268400787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484349751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3484349751
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4173630034
Short name T222
Test name
Test status
Simulation time 8619733918 ps
CPU time 29.22 seconds
Started Aug 11 05:23:50 PM PDT 24
Finished Aug 11 05:24:20 PM PDT 24
Peak memory 224704 kb
Host smart-55e00baa-8cec-49dd-951b-070bac76533a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173630034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4173630034
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3770280414
Short name T545
Test name
Test status
Simulation time 966034412 ps
CPU time 6.15 seconds
Started Aug 11 05:23:46 PM PDT 24
Finished Aug 11 05:23:53 PM PDT 24
Peak memory 237284 kb
Host smart-25944d00-7cca-4e21-9ce8-38d227041f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770280414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3770280414
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1742322259
Short name T88
Test name
Test status
Simulation time 934690924 ps
CPU time 21.52 seconds
Started Aug 11 05:23:44 PM PDT 24
Finished Aug 11 05:24:06 PM PDT 24
Peak memory 239340 kb
Host smart-454aee70-486b-445f-b2ec-1d017ddbde40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742322259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1742322259
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3153629131
Short name T942
Test name
Test status
Simulation time 303602011 ps
CPU time 3.56 seconds
Started Aug 11 05:23:44 PM PDT 24
Finished Aug 11 05:23:47 PM PDT 24
Peak memory 233088 kb
Host smart-60ce4472-ff34-4bf4-bfc0-39c59f4045fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153629131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3153629131
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.853248034
Short name T96
Test name
Test status
Simulation time 5036106796 ps
CPU time 13.44 seconds
Started Aug 11 05:23:45 PM PDT 24
Finished Aug 11 05:23:59 PM PDT 24
Peak memory 224936 kb
Host smart-a1d73383-0cc9-4323-be80-47c7c1c65456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853248034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.853248034
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.471682472
Short name T753
Test name
Test status
Simulation time 2195776417 ps
CPU time 8.09 seconds
Started Aug 11 05:23:44 PM PDT 24
Finished Aug 11 05:23:52 PM PDT 24
Peak memory 233036 kb
Host smart-1e927121-f24c-4679-b50e-f3b18739c96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471682472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.471682472
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.4135841085
Short name T472
Test name
Test status
Simulation time 8268985849 ps
CPU time 12.98 seconds
Started Aug 11 05:23:48 PM PDT 24
Finished Aug 11 05:24:01 PM PDT 24
Peak memory 224908 kb
Host smart-64e2df13-7dbb-4308-8411-6d6e19c9dd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135841085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.4135841085
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.4039824394
Short name T543
Test name
Test status
Simulation time 4301364018 ps
CPU time 17.3 seconds
Started Aug 11 05:23:52 PM PDT 24
Finished Aug 11 05:24:10 PM PDT 24
Peak memory 219748 kb
Host smart-8bcbbe68-469f-4d47-835a-9cf90d3ca03f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4039824394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.4039824394
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2357086161
Short name T150
Test name
Test status
Simulation time 17730183110 ps
CPU time 66.53 seconds
Started Aug 11 05:23:49 PM PDT 24
Finished Aug 11 05:24:55 PM PDT 24
Peak memory 257620 kb
Host smart-65d1e28a-cbc7-49f8-82a0-f9f711222443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357086161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2357086161
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2949321514
Short name T404
Test name
Test status
Simulation time 5094106073 ps
CPU time 29.38 seconds
Started Aug 11 05:23:50 PM PDT 24
Finished Aug 11 05:24:20 PM PDT 24
Peak memory 216640 kb
Host smart-194a83df-7f21-47f7-b266-60a7c86eb903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949321514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2949321514
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1571888038
Short name T483
Test name
Test status
Simulation time 15281137961 ps
CPU time 11.24 seconds
Started Aug 11 05:23:44 PM PDT 24
Finished Aug 11 05:23:55 PM PDT 24
Peak memory 216932 kb
Host smart-03f60880-2791-46bc-850f-80417937b491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571888038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1571888038
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.226634911
Short name T759
Test name
Test status
Simulation time 129978814 ps
CPU time 3.44 seconds
Started Aug 11 05:23:44 PM PDT 24
Finished Aug 11 05:23:47 PM PDT 24
Peak memory 216484 kb
Host smart-b372e9c6-acdf-4011-b35d-0f4b48671da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226634911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.226634911
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2884049105
Short name T1010
Test name
Test status
Simulation time 80204101 ps
CPU time 0.78 seconds
Started Aug 11 05:23:45 PM PDT 24
Finished Aug 11 05:23:46 PM PDT 24
Peak memory 206228 kb
Host smart-b083a669-78c4-4026-b480-aa711db2ad3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884049105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2884049105
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1961833218
Short name T56
Test name
Test status
Simulation time 645699706 ps
CPU time 5.41 seconds
Started Aug 11 05:23:46 PM PDT 24
Finished Aug 11 05:23:52 PM PDT 24
Peak memory 233328 kb
Host smart-53505112-48d1-429e-bce0-183fffd42466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961833218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1961833218
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1193414221
Short name T661
Test name
Test status
Simulation time 13391842 ps
CPU time 0.74 seconds
Started Aug 11 05:23:57 PM PDT 24
Finished Aug 11 05:23:58 PM PDT 24
Peak memory 205816 kb
Host smart-f1525079-08af-439f-abb0-8eb842ee8523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193414221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1193414221
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.383168920
Short name T174
Test name
Test status
Simulation time 36679371 ps
CPU time 2.45 seconds
Started Aug 11 05:23:51 PM PDT 24
Finished Aug 11 05:23:54 PM PDT 24
Peak memory 233040 kb
Host smart-f412f45c-fd02-414c-bf32-8a4d75a83d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383168920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.383168920
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.677393533
Short name T692
Test name
Test status
Simulation time 18910019 ps
CPU time 0.77 seconds
Started Aug 11 05:23:50 PM PDT 24
Finished Aug 11 05:23:51 PM PDT 24
Peak memory 206796 kb
Host smart-56a6dbc0-13d9-4657-8967-0262792543fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677393533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.677393533
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3593717279
Short name T295
Test name
Test status
Simulation time 36052245102 ps
CPU time 83.77 seconds
Started Aug 11 05:24:00 PM PDT 24
Finished Aug 11 05:25:24 PM PDT 24
Peak memory 252192 kb
Host smart-108d3d7f-6786-4d7c-b2e9-7d7703b0ed19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593717279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3593717279
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2322418966
Short name T1007
Test name
Test status
Simulation time 24715693700 ps
CPU time 195.16 seconds
Started Aug 11 05:23:52 PM PDT 24
Finished Aug 11 05:27:07 PM PDT 24
Peak memory 249572 kb
Host smart-85038a33-b193-42d9-9bab-37a5dab2f171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322418966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2322418966
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2912540071
Short name T864
Test name
Test status
Simulation time 841719324 ps
CPU time 10.66 seconds
Started Aug 11 05:23:53 PM PDT 24
Finished Aug 11 05:24:03 PM PDT 24
Peak memory 233064 kb
Host smart-ae95e9a7-3197-42b5-824e-cafc23815b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912540071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2912540071
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1803733179
Short name T719
Test name
Test status
Simulation time 36565761565 ps
CPU time 59.86 seconds
Started Aug 11 05:23:51 PM PDT 24
Finished Aug 11 05:24:51 PM PDT 24
Peak memory 241308 kb
Host smart-1bde6fe0-b907-4b02-9980-77859dcef39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803733179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1803733179
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3242942548
Short name T454
Test name
Test status
Simulation time 4928251897 ps
CPU time 13.47 seconds
Started Aug 11 05:23:54 PM PDT 24
Finished Aug 11 05:24:08 PM PDT 24
Peak memory 224788 kb
Host smart-916ae5aa-b380-44a5-9c62-2d2b45656da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242942548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3242942548
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2918353285
Short name T666
Test name
Test status
Simulation time 29927675 ps
CPU time 2.19 seconds
Started Aug 11 05:23:52 PM PDT 24
Finished Aug 11 05:23:54 PM PDT 24
Peak memory 223428 kb
Host smart-0fb31b83-7a72-4b83-bb75-61a3a064f370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918353285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2918353285
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1633660630
Short name T333
Test name
Test status
Simulation time 19503110094 ps
CPU time 12.8 seconds
Started Aug 11 05:23:57 PM PDT 24
Finished Aug 11 05:24:10 PM PDT 24
Peak memory 222448 kb
Host smart-889dc2a5-3b09-40c1-8fc6-0b4bd8194ab0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1633660630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1633660630
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3453214321
Short name T834
Test name
Test status
Simulation time 27520951620 ps
CPU time 48.34 seconds
Started Aug 11 05:24:00 PM PDT 24
Finished Aug 11 05:24:48 PM PDT 24
Peak memory 233136 kb
Host smart-7eb2a875-9d50-4b34-b7e5-33f5c29694f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453214321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3453214321
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2394309288
Short name T306
Test name
Test status
Simulation time 11248748706 ps
CPU time 16.24 seconds
Started Aug 11 05:23:51 PM PDT 24
Finished Aug 11 05:24:07 PM PDT 24
Peak memory 220328 kb
Host smart-81f79695-c45d-4908-9754-13525522ceef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394309288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2394309288
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.810181324
Short name T691
Test name
Test status
Simulation time 771544042 ps
CPU time 2.47 seconds
Started Aug 11 05:23:51 PM PDT 24
Finished Aug 11 05:23:54 PM PDT 24
Peak memory 216604 kb
Host smart-6f1f8a9e-d941-4a60-9acf-5e4974a2315d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810181324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.810181324
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.329134479
Short name T400
Test name
Test status
Simulation time 196274775 ps
CPU time 4.37 seconds
Started Aug 11 05:23:51 PM PDT 24
Finished Aug 11 05:23:55 PM PDT 24
Peak memory 216676 kb
Host smart-863982c4-b5ff-41f1-9534-948a17966d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329134479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.329134479
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3280008885
Short name T81
Test name
Test status
Simulation time 38091190 ps
CPU time 0.75 seconds
Started Aug 11 05:23:52 PM PDT 24
Finished Aug 11 05:23:52 PM PDT 24
Peak memory 206264 kb
Host smart-1bfaa132-fc54-458d-8462-bca0f46657a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280008885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3280008885
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2832090598
Short name T348
Test name
Test status
Simulation time 319008081 ps
CPU time 2.7 seconds
Started Aug 11 05:23:51 PM PDT 24
Finished Aug 11 05:23:54 PM PDT 24
Peak memory 224776 kb
Host smart-8e43d60b-3a4a-4dd6-9a2c-de51110534ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832090598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2832090598
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.815264864
Short name T442
Test name
Test status
Simulation time 22449879 ps
CPU time 0.74 seconds
Started Aug 11 05:24:24 PM PDT 24
Finished Aug 11 05:24:25 PM PDT 24
Peak memory 205780 kb
Host smart-33ebac3c-56b7-49db-80f9-68fc3642bf02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815264864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.815264864
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.4151039204
Short name T696
Test name
Test status
Simulation time 100809636 ps
CPU time 2.1 seconds
Started Aug 11 05:23:59 PM PDT 24
Finished Aug 11 05:24:01 PM PDT 24
Peak memory 224492 kb
Host smart-ef1fd301-9352-4a59-b4fb-70d6262be19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151039204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.4151039204
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1936140967
Short name T690
Test name
Test status
Simulation time 12790155 ps
CPU time 0.77 seconds
Started Aug 11 05:23:58 PM PDT 24
Finished Aug 11 05:23:58 PM PDT 24
Peak memory 205812 kb
Host smart-8c92d65b-836f-474f-96e5-3c6633431af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936140967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1936140967
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1176733851
Short name T247
Test name
Test status
Simulation time 25558110353 ps
CPU time 215.29 seconds
Started Aug 11 05:23:59 PM PDT 24
Finished Aug 11 05:27:34 PM PDT 24
Peak memory 256356 kb
Host smart-308f7f40-1829-46af-b22e-a02f0fa9259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176733851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1176733851
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.161018122
Short name T629
Test name
Test status
Simulation time 4629017987 ps
CPU time 25.83 seconds
Started Aug 11 05:23:58 PM PDT 24
Finished Aug 11 05:24:24 PM PDT 24
Peak memory 236456 kb
Host smart-6f1de160-173f-4b7e-8512-30b6e08d72b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161018122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.161018122
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2553607554
Short name T278
Test name
Test status
Simulation time 77079844967 ps
CPU time 209.02 seconds
Started Aug 11 05:24:03 PM PDT 24
Finished Aug 11 05:27:32 PM PDT 24
Peak memory 251680 kb
Host smart-8abbb22a-c007-4e2a-8fe0-855a9ca8596d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553607554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2553607554
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1124177297
Short name T320
Test name
Test status
Simulation time 96872875 ps
CPU time 3.09 seconds
Started Aug 11 05:23:57 PM PDT 24
Finished Aug 11 05:24:00 PM PDT 24
Peak memory 233040 kb
Host smart-c980e940-fd65-4966-b22a-2d5d57ee51dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124177297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1124177297
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2087344520
Short name T273
Test name
Test status
Simulation time 2318814908 ps
CPU time 37.69 seconds
Started Aug 11 05:23:59 PM PDT 24
Finished Aug 11 05:24:37 PM PDT 24
Peak memory 250804 kb
Host smart-dd8c2bf2-7103-419f-9e9d-075c9f18fffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087344520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2087344520
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2681228457
Short name T208
Test name
Test status
Simulation time 202073836 ps
CPU time 5.23 seconds
Started Aug 11 05:23:58 PM PDT 24
Finished Aug 11 05:24:03 PM PDT 24
Peak memory 233060 kb
Host smart-388d6b20-9bd3-4657-9d3f-e04c66f19735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681228457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2681228457
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3499833354
Short name T537
Test name
Test status
Simulation time 1045265339 ps
CPU time 9.36 seconds
Started Aug 11 05:23:57 PM PDT 24
Finished Aug 11 05:24:06 PM PDT 24
Peak memory 224920 kb
Host smart-4a392210-46db-4622-ab86-5de3f7946411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499833354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3499833354
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1147853880
Short name T846
Test name
Test status
Simulation time 785530128 ps
CPU time 6.57 seconds
Started Aug 11 05:23:58 PM PDT 24
Finished Aug 11 05:24:05 PM PDT 24
Peak memory 232936 kb
Host smart-d267a468-cc81-4aae-8e6f-57f4d92b401d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147853880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1147853880
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1468165303
Short name T605
Test name
Test status
Simulation time 1899108615 ps
CPU time 10.26 seconds
Started Aug 11 05:23:58 PM PDT 24
Finished Aug 11 05:24:08 PM PDT 24
Peak memory 233052 kb
Host smart-e8f148b6-3aa8-445c-bb81-7a878e67b883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468165303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1468165303
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.932142242
Short name T931
Test name
Test status
Simulation time 781173871 ps
CPU time 8.54 seconds
Started Aug 11 05:23:59 PM PDT 24
Finished Aug 11 05:24:07 PM PDT 24
Peak memory 218916 kb
Host smart-92496bec-2497-436a-9f56-1a5f0bc4f956
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=932142242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.932142242
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1383244724
Short name T740
Test name
Test status
Simulation time 60106764 ps
CPU time 1.15 seconds
Started Aug 11 05:24:04 PM PDT 24
Finished Aug 11 05:24:05 PM PDT 24
Peak memory 207252 kb
Host smart-77664358-64ca-4a4f-9662-f9e664897b4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383244724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1383244724
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2085744577
Short name T785
Test name
Test status
Simulation time 35004247024 ps
CPU time 41.88 seconds
Started Aug 11 05:24:01 PM PDT 24
Finished Aug 11 05:24:43 PM PDT 24
Peak memory 217696 kb
Host smart-382aec0e-4083-4e76-a0d2-6f1b3ae3a6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085744577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2085744577
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1370981870
Short name T369
Test name
Test status
Simulation time 215416427 ps
CPU time 1.66 seconds
Started Aug 11 05:24:01 PM PDT 24
Finished Aug 11 05:24:02 PM PDT 24
Peak memory 208188 kb
Host smart-9060433c-660b-41a2-9d47-4448bf5d3535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370981870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1370981870
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1380021808
Short name T349
Test name
Test status
Simulation time 497489641 ps
CPU time 1.65 seconds
Started Aug 11 05:23:57 PM PDT 24
Finished Aug 11 05:23:59 PM PDT 24
Peak memory 216564 kb
Host smart-6c5364be-64e0-4deb-a367-c96cc23c8840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380021808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1380021808
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2959704783
Short name T669
Test name
Test status
Simulation time 295433912 ps
CPU time 0.94 seconds
Started Aug 11 05:24:00 PM PDT 24
Finished Aug 11 05:24:01 PM PDT 24
Peak memory 206220 kb
Host smart-610b6e4b-c1f1-48ae-8049-374dad0426e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959704783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2959704783
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.845833861
Short name T822
Test name
Test status
Simulation time 7634117214 ps
CPU time 8.55 seconds
Started Aug 11 05:23:59 PM PDT 24
Finished Aug 11 05:24:08 PM PDT 24
Peak memory 233092 kb
Host smart-d0649a65-4a80-4aec-9a57-8040193a130d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845833861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.845833861
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1485194177
Short name T617
Test name
Test status
Simulation time 27001514 ps
CPU time 0.75 seconds
Started Aug 11 05:24:13 PM PDT 24
Finished Aug 11 05:24:14 PM PDT 24
Peak memory 206048 kb
Host smart-da5b4779-4c03-4228-87b3-4a09b01ea83a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485194177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1485194177
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2587675882
Short name T434
Test name
Test status
Simulation time 297070210 ps
CPU time 3.53 seconds
Started Aug 11 05:24:08 PM PDT 24
Finished Aug 11 05:24:11 PM PDT 24
Peak memory 224672 kb
Host smart-8d7ea172-bd72-4b56-8e7e-298169012baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587675882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2587675882
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.4204514453
Short name T332
Test name
Test status
Simulation time 18182842 ps
CPU time 0.78 seconds
Started Aug 11 05:24:03 PM PDT 24
Finished Aug 11 05:24:03 PM PDT 24
Peak memory 206836 kb
Host smart-ede13ee2-6837-4f60-9c7c-02534255e773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204514453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.4204514453
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3075799418
Short name T49
Test name
Test status
Simulation time 3352388518 ps
CPU time 54.31 seconds
Started Aug 11 05:24:07 PM PDT 24
Finished Aug 11 05:25:01 PM PDT 24
Peak memory 250012 kb
Host smart-229a340d-81b7-4b2b-ba87-5435e897d4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075799418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3075799418
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1571681301
Short name T119
Test name
Test status
Simulation time 13620775790 ps
CPU time 81.11 seconds
Started Aug 11 05:24:02 PM PDT 24
Finished Aug 11 05:25:24 PM PDT 24
Peak memory 251484 kb
Host smart-150f0f5e-7144-431e-ae5b-65378adcc63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571681301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1571681301
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4027111777
Short name T699
Test name
Test status
Simulation time 2244427461 ps
CPU time 3.03 seconds
Started Aug 11 05:24:13 PM PDT 24
Finished Aug 11 05:24:16 PM PDT 24
Peak memory 218024 kb
Host smart-eeb47ddc-53a5-42a1-9276-15dbaa22cc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027111777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4027111777
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3197177930
Short name T388
Test name
Test status
Simulation time 4167541313 ps
CPU time 13.8 seconds
Started Aug 11 05:24:04 PM PDT 24
Finished Aug 11 05:24:18 PM PDT 24
Peak memory 224852 kb
Host smart-94ac5cdb-d49b-4885-a509-aa197609db5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197177930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3197177930
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.816928980
Short name T292
Test name
Test status
Simulation time 261892311656 ps
CPU time 465.36 seconds
Started Aug 11 05:24:03 PM PDT 24
Finished Aug 11 05:31:49 PM PDT 24
Peak memory 268148 kb
Host smart-c2fa1e51-8e7c-4456-bd3c-bf905b9c6b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816928980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.816928980
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1439277569
Short name T83
Test name
Test status
Simulation time 186067155 ps
CPU time 6.01 seconds
Started Aug 11 05:24:05 PM PDT 24
Finished Aug 11 05:24:11 PM PDT 24
Peak memory 224836 kb
Host smart-3ed673d4-ad1a-4162-888f-9509badff53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439277569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1439277569
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3644485626
Short name T828
Test name
Test status
Simulation time 1584312345 ps
CPU time 10.75 seconds
Started Aug 11 05:24:05 PM PDT 24
Finished Aug 11 05:24:16 PM PDT 24
Peak memory 237888 kb
Host smart-e287d5ee-b535-4efb-b04d-86cbdf3aff43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644485626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3644485626
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.4166685777
Short name T266
Test name
Test status
Simulation time 1823809227 ps
CPU time 8.02 seconds
Started Aug 11 05:24:04 PM PDT 24
Finished Aug 11 05:24:12 PM PDT 24
Peak memory 232984 kb
Host smart-f1a20bff-c23e-4790-9ee2-03ca05fc8e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166685777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.4166685777
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3407119559
Short name T61
Test name
Test status
Simulation time 23104914256 ps
CPU time 44.65 seconds
Started Aug 11 05:24:03 PM PDT 24
Finished Aug 11 05:24:48 PM PDT 24
Peak memory 249552 kb
Host smart-0885c391-1d66-45eb-92dd-0c34452c2e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407119559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3407119559
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1176848521
Short name T773
Test name
Test status
Simulation time 346291837 ps
CPU time 6.41 seconds
Started Aug 11 05:24:08 PM PDT 24
Finished Aug 11 05:24:14 PM PDT 24
Peak memory 223320 kb
Host smart-88eab21c-01d1-4be3-bce2-b065fb44b0bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1176848521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1176848521
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3240378061
Short name T51
Test name
Test status
Simulation time 17588280331 ps
CPU time 148.66 seconds
Started Aug 11 05:24:12 PM PDT 24
Finished Aug 11 05:26:40 PM PDT 24
Peak memory 249548 kb
Host smart-756c0093-2494-4175-8f60-20da461c364f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240378061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3240378061
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.749731299
Short name T802
Test name
Test status
Simulation time 8940952261 ps
CPU time 29.89 seconds
Started Aug 11 05:24:04 PM PDT 24
Finished Aug 11 05:24:34 PM PDT 24
Peak memory 216812 kb
Host smart-8184acd6-2096-4dd0-9981-dd8daefc226e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749731299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.749731299
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2960090342
Short name T430
Test name
Test status
Simulation time 1205306780 ps
CPU time 4.21 seconds
Started Aug 11 05:24:06 PM PDT 24
Finished Aug 11 05:24:10 PM PDT 24
Peak memory 216612 kb
Host smart-891423fe-36b2-4db8-9922-c82a3566162e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960090342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2960090342
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2815840171
Short name T596
Test name
Test status
Simulation time 517805679 ps
CPU time 3.26 seconds
Started Aug 11 05:24:04 PM PDT 24
Finished Aug 11 05:24:08 PM PDT 24
Peak memory 216524 kb
Host smart-7097bc93-5556-47c6-b544-205c3d81a146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815840171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2815840171
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.145504527
Short name T501
Test name
Test status
Simulation time 57443670 ps
CPU time 0.91 seconds
Started Aug 11 05:24:04 PM PDT 24
Finished Aug 11 05:24:05 PM PDT 24
Peak memory 206284 kb
Host smart-1e5b92eb-251e-4238-806d-870580106346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145504527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.145504527
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1632801532
Short name T407
Test name
Test status
Simulation time 2033845614 ps
CPU time 3.54 seconds
Started Aug 11 05:24:06 PM PDT 24
Finished Aug 11 05:24:09 PM PDT 24
Peak memory 224884 kb
Host smart-86b2674e-21c0-43ac-8510-9cfed4e4f138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632801532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1632801532
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2104699138
Short name T906
Test name
Test status
Simulation time 47861128 ps
CPU time 0.71 seconds
Started Aug 11 05:24:15 PM PDT 24
Finished Aug 11 05:24:16 PM PDT 24
Peak memory 205748 kb
Host smart-333db269-8b0a-470e-89c8-27accfbcade2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104699138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2104699138
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3863421940
Short name T587
Test name
Test status
Simulation time 243036890 ps
CPU time 6.76 seconds
Started Aug 11 05:24:13 PM PDT 24
Finished Aug 11 05:24:20 PM PDT 24
Peak memory 241012 kb
Host smart-175da683-2503-40a2-8b3d-75389aa187cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863421940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3863421940
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1611539031
Short name T374
Test name
Test status
Simulation time 33582879 ps
CPU time 0.79 seconds
Started Aug 11 05:24:11 PM PDT 24
Finished Aug 11 05:24:12 PM PDT 24
Peak memory 207264 kb
Host smart-c6be6c1c-e488-44cc-a915-b00339274e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611539031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1611539031
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3772407322
Short name T748
Test name
Test status
Simulation time 1849734230 ps
CPU time 23.73 seconds
Started Aug 11 05:24:12 PM PDT 24
Finished Aug 11 05:24:35 PM PDT 24
Peak memory 251632 kb
Host smart-7efeaefb-5c6c-4d1d-8887-bc7ed12e14f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772407322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3772407322
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1794605244
Short name T30
Test name
Test status
Simulation time 7911293092 ps
CPU time 168.79 seconds
Started Aug 11 05:24:10 PM PDT 24
Finished Aug 11 05:26:59 PM PDT 24
Peak memory 257696 kb
Host smart-6ae5c03b-89ef-41ba-a3c7-90ddc54e9d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794605244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1794605244
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.484252023
Short name T831
Test name
Test status
Simulation time 7732663054 ps
CPU time 56.35 seconds
Started Aug 11 05:24:16 PM PDT 24
Finished Aug 11 05:25:12 PM PDT 24
Peak memory 251924 kb
Host smart-5a10eada-1af9-4f6d-9cf8-b6306159a8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484252023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.484252023
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1145618083
Short name T928
Test name
Test status
Simulation time 16823866689 ps
CPU time 34 seconds
Started Aug 11 05:24:11 PM PDT 24
Finished Aug 11 05:24:45 PM PDT 24
Peak memory 224940 kb
Host smart-53ee4a36-96bd-4e75-9cb0-5fcbf8d45d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145618083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1145618083
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2986845447
Short name T201
Test name
Test status
Simulation time 10267560440 ps
CPU time 108.99 seconds
Started Aug 11 05:24:09 PM PDT 24
Finished Aug 11 05:25:58 PM PDT 24
Peak memory 249720 kb
Host smart-a5f98262-b13b-4c7c-8118-e20e11bb6db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986845447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2986845447
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3481408637
Short name T23
Test name
Test status
Simulation time 624771465 ps
CPU time 8.3 seconds
Started Aug 11 05:24:11 PM PDT 24
Finished Aug 11 05:24:19 PM PDT 24
Peak memory 233056 kb
Host smart-5a86f151-d663-4e33-96d1-03ccfa099c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481408637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3481408637
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.631864958
Short name T461
Test name
Test status
Simulation time 454080266 ps
CPU time 4.1 seconds
Started Aug 11 05:24:08 PM PDT 24
Finished Aug 11 05:24:13 PM PDT 24
Peak memory 233068 kb
Host smart-996d8649-7145-48ab-b2b0-d29b6f91b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631864958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.631864958
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1042420428
Short name T957
Test name
Test status
Simulation time 2875563803 ps
CPU time 5.12 seconds
Started Aug 11 05:24:10 PM PDT 24
Finished Aug 11 05:24:16 PM PDT 24
Peak memory 233140 kb
Host smart-e1c095c0-2ba5-44f7-a930-e0fa1cfc642b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042420428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1042420428
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1368433023
Short name T394
Test name
Test status
Simulation time 3888293410 ps
CPU time 11.41 seconds
Started Aug 11 05:24:11 PM PDT 24
Finished Aug 11 05:24:22 PM PDT 24
Peak memory 224908 kb
Host smart-f23287df-73d1-4c31-8a80-d478e547428e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368433023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1368433023
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3785908822
Short name T577
Test name
Test status
Simulation time 920107164 ps
CPU time 6.02 seconds
Started Aug 11 05:24:13 PM PDT 24
Finished Aug 11 05:24:19 PM PDT 24
Peak memory 222544 kb
Host smart-8bb30bf6-be74-47a7-9513-ea443b2fc234
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3785908822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3785908822
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.237834963
Short name T738
Test name
Test status
Simulation time 154707875355 ps
CPU time 292.41 seconds
Started Aug 11 05:24:16 PM PDT 24
Finished Aug 11 05:29:08 PM PDT 24
Peak memory 252756 kb
Host smart-769e59a3-e66e-4b16-b76b-c14e24f567be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237834963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.237834963
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2733880840
Short name T760
Test name
Test status
Simulation time 5344735215 ps
CPU time 22.19 seconds
Started Aug 11 05:24:12 PM PDT 24
Finished Aug 11 05:24:34 PM PDT 24
Peak memory 217032 kb
Host smart-963548a7-61c6-4d07-9e85-f42533818f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733880840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2733880840
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3778605368
Short name T510
Test name
Test status
Simulation time 12889357521 ps
CPU time 18.4 seconds
Started Aug 11 05:24:10 PM PDT 24
Finished Aug 11 05:24:29 PM PDT 24
Peak memory 216672 kb
Host smart-a77f8d33-7e01-464c-9fac-13b0b6b36137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778605368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3778605368
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3816053548
Short name T984
Test name
Test status
Simulation time 115724205 ps
CPU time 1.64 seconds
Started Aug 11 05:24:12 PM PDT 24
Finished Aug 11 05:24:14 PM PDT 24
Peak memory 216628 kb
Host smart-f8b68b16-8cca-4c81-849b-606a46ec8698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816053548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3816053548
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2117069067
Short name T752
Test name
Test status
Simulation time 64588439 ps
CPU time 0.78 seconds
Started Aug 11 05:24:11 PM PDT 24
Finished Aug 11 05:24:12 PM PDT 24
Peak memory 206212 kb
Host smart-359ffbf3-b186-4b4c-a404-5a7705e393bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117069067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2117069067
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1554706476
Short name T842
Test name
Test status
Simulation time 2145116595 ps
CPU time 8.26 seconds
Started Aug 11 05:24:11 PM PDT 24
Finished Aug 11 05:24:19 PM PDT 24
Peak memory 233012 kb
Host smart-724f6669-0cd1-4f99-9b0f-d14152a541e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554706476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1554706476
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1831241561
Short name T743
Test name
Test status
Simulation time 11337975 ps
CPU time 0.7 seconds
Started Aug 11 05:24:23 PM PDT 24
Finished Aug 11 05:24:24 PM PDT 24
Peak memory 205992 kb
Host smart-c38a9799-0f3f-444b-9261-e41b4d2a6237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831241561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1831241561
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1874296633
Short name T927
Test name
Test status
Simulation time 390865239 ps
CPU time 6.89 seconds
Started Aug 11 05:24:29 PM PDT 24
Finished Aug 11 05:24:36 PM PDT 24
Peak memory 224804 kb
Host smart-39b768f2-c845-4fa0-809e-dfb4f1ee29fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874296633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1874296633
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1789521342
Short name T663
Test name
Test status
Simulation time 66969662 ps
CPU time 0.8 seconds
Started Aug 11 05:24:17 PM PDT 24
Finished Aug 11 05:24:18 PM PDT 24
Peak memory 206888 kb
Host smart-22480a9b-78f6-4885-9cff-7b0d93e3131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789521342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1789521342
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1498768355
Short name T432
Test name
Test status
Simulation time 6632437471 ps
CPU time 27.53 seconds
Started Aug 11 05:24:22 PM PDT 24
Finished Aug 11 05:24:50 PM PDT 24
Peak memory 250416 kb
Host smart-27b88a83-cc43-4066-a026-48573be4c9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498768355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1498768355
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2982286808
Short name T642
Test name
Test status
Simulation time 10426802860 ps
CPU time 92.02 seconds
Started Aug 11 05:24:26 PM PDT 24
Finished Aug 11 05:25:58 PM PDT 24
Peak memory 257712 kb
Host smart-5088e936-7292-4638-9f06-86729078ec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982286808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2982286808
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1847529116
Short name T267
Test name
Test status
Simulation time 21842797557 ps
CPU time 89.12 seconds
Started Aug 11 05:24:26 PM PDT 24
Finished Aug 11 05:25:55 PM PDT 24
Peak memory 249592 kb
Host smart-992cad73-05bd-4327-9a87-21bc199e2527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847529116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1847529116
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.857377265
Short name T437
Test name
Test status
Simulation time 1557081745 ps
CPU time 9.61 seconds
Started Aug 11 05:24:26 PM PDT 24
Finished Aug 11 05:24:36 PM PDT 24
Peak memory 233016 kb
Host smart-4dfe802e-2e7a-4cea-b101-0c07d7959775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857377265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.857377265
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.607092034
Short name T89
Test name
Test status
Simulation time 8631238738 ps
CPU time 23.82 seconds
Started Aug 11 05:24:22 PM PDT 24
Finished Aug 11 05:24:46 PM PDT 24
Peak memory 249564 kb
Host smart-ce9f52ad-a1a7-40f8-bde4-20ac3dd9422b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607092034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.607092034
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3565890941
Short name T450
Test name
Test status
Simulation time 10100817105 ps
CPU time 8.51 seconds
Started Aug 11 05:24:23 PM PDT 24
Finished Aug 11 05:24:31 PM PDT 24
Peak memory 233144 kb
Host smart-900a8df4-5e98-4282-85d3-d0ffac403d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565890941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3565890941
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.21726874
Short name T599
Test name
Test status
Simulation time 3725221491 ps
CPU time 14.01 seconds
Started Aug 11 05:24:25 PM PDT 24
Finished Aug 11 05:24:39 PM PDT 24
Peak memory 220100 kb
Host smart-4c16a8fe-bc6d-41b5-a249-a2ca83cada70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21726874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.21726874
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4193027390
Short name T908
Test name
Test status
Simulation time 949635684 ps
CPU time 4.53 seconds
Started Aug 11 05:24:16 PM PDT 24
Finished Aug 11 05:24:21 PM PDT 24
Peak memory 224764 kb
Host smart-36c38bb9-0c5d-4944-8856-7de7d50ad2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193027390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4193027390
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1536413995
Short name T934
Test name
Test status
Simulation time 7177053097 ps
CPU time 7.39 seconds
Started Aug 11 05:24:17 PM PDT 24
Finished Aug 11 05:24:24 PM PDT 24
Peak memory 224840 kb
Host smart-72e3bd02-2fc3-4c0f-9e07-fd6deac64a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536413995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1536413995
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1676136504
Short name T384
Test name
Test status
Simulation time 1450338933 ps
CPU time 5.58 seconds
Started Aug 11 05:24:24 PM PDT 24
Finished Aug 11 05:24:30 PM PDT 24
Peak memory 222872 kb
Host smart-44d67b44-aff9-492b-a5a2-b5d634b76f8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1676136504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1676136504
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2576953887
Short name T19
Test name
Test status
Simulation time 558200346 ps
CPU time 1.04 seconds
Started Aug 11 05:24:23 PM PDT 24
Finished Aug 11 05:24:25 PM PDT 24
Peak memory 207396 kb
Host smart-7ffaf089-3efc-4d94-8230-2fb6ae1572fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576953887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2576953887
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3068461577
Short name T714
Test name
Test status
Simulation time 10169720182 ps
CPU time 16.75 seconds
Started Aug 11 05:24:17 PM PDT 24
Finished Aug 11 05:24:34 PM PDT 24
Peak memory 216724 kb
Host smart-e9bdefd1-9ed4-4c4b-97d4-430d3fc81bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068461577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3068461577
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4145219106
Short name T386
Test name
Test status
Simulation time 159670257 ps
CPU time 1.97 seconds
Started Aug 11 05:24:17 PM PDT 24
Finished Aug 11 05:24:19 PM PDT 24
Peak memory 216308 kb
Host smart-8fa55840-0884-4a0a-a150-543861633159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145219106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4145219106
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1751650261
Short name T468
Test name
Test status
Simulation time 454374458 ps
CPU time 1.79 seconds
Started Aug 11 05:24:16 PM PDT 24
Finished Aug 11 05:24:18 PM PDT 24
Peak memory 216608 kb
Host smart-7dcceb1f-debb-4e57-9a01-b03874465f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751650261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1751650261
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3670716153
Short name T859
Test name
Test status
Simulation time 105498383 ps
CPU time 1.05 seconds
Started Aug 11 05:24:16 PM PDT 24
Finished Aug 11 05:24:18 PM PDT 24
Peak memory 207244 kb
Host smart-a72e4502-81f5-4228-99f2-cfa21d26699c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670716153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3670716153
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3496634679
Short name T909
Test name
Test status
Simulation time 137105320 ps
CPU time 2.1 seconds
Started Aug 11 05:24:26 PM PDT 24
Finished Aug 11 05:24:28 PM PDT 24
Peak memory 224512 kb
Host smart-660159cf-4ef7-4a6a-a019-d9fd30c25c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496634679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3496634679
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2326711862
Short name T342
Test name
Test status
Simulation time 39796043 ps
CPU time 0.72 seconds
Started Aug 11 05:24:33 PM PDT 24
Finished Aug 11 05:24:34 PM PDT 24
Peak memory 205780 kb
Host smart-a3638b01-9795-4cb1-a849-e9a929e825c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326711862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2326711862
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1715456509
Short name T229
Test name
Test status
Simulation time 564054355 ps
CPU time 2.69 seconds
Started Aug 11 05:24:31 PM PDT 24
Finished Aug 11 05:24:34 PM PDT 24
Peak memory 233052 kb
Host smart-20196ef1-3759-4782-9ebc-4645e8ba76cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715456509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1715456509
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3217253306
Short name T939
Test name
Test status
Simulation time 108725615 ps
CPU time 0.77 seconds
Started Aug 11 05:24:23 PM PDT 24
Finished Aug 11 05:24:24 PM PDT 24
Peak memory 206884 kb
Host smart-c782ed4f-e819-4438-b83c-71e7ac32adb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217253306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3217253306
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2602910870
Short name T4
Test name
Test status
Simulation time 78416127943 ps
CPU time 162.94 seconds
Started Aug 11 05:24:30 PM PDT 24
Finished Aug 11 05:27:13 PM PDT 24
Peak memory 256844 kb
Host smart-4e33c964-3391-497a-869f-b4435d3eec7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602910870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2602910870
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2684515882
Short name T761
Test name
Test status
Simulation time 29160087443 ps
CPU time 103.83 seconds
Started Aug 11 05:24:29 PM PDT 24
Finished Aug 11 05:26:13 PM PDT 24
Peak memory 250688 kb
Host smart-25d48b92-b148-4146-b65d-98f9f41af277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684515882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2684515882
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3978608288
Short name T500
Test name
Test status
Simulation time 13805156614 ps
CPU time 109.52 seconds
Started Aug 11 05:24:30 PM PDT 24
Finished Aug 11 05:26:19 PM PDT 24
Peak memory 223156 kb
Host smart-1ebbd402-391f-465c-ab04-7488420c632a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978608288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3978608288
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1688394400
Short name T784
Test name
Test status
Simulation time 187792544 ps
CPU time 2.86 seconds
Started Aug 11 05:24:29 PM PDT 24
Finished Aug 11 05:24:32 PM PDT 24
Peak memory 232984 kb
Host smart-37fbdf55-ec9a-4d3b-ae86-ee680c65e193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688394400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1688394400
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1257522581
Short name T698
Test name
Test status
Simulation time 40315958904 ps
CPU time 67.25 seconds
Started Aug 11 05:24:28 PM PDT 24
Finished Aug 11 05:25:36 PM PDT 24
Peak memory 249404 kb
Host smart-09dfe015-4a65-42c6-b4d2-32fb09226bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257522581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1257522581
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1675184745
Short name T210
Test name
Test status
Simulation time 5500801807 ps
CPU time 14.28 seconds
Started Aug 11 05:24:32 PM PDT 24
Finished Aug 11 05:24:46 PM PDT 24
Peak memory 233180 kb
Host smart-e2b48ce2-0cfd-4315-a093-0da20fdb3e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675184745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1675184745
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.597418301
Short name T782
Test name
Test status
Simulation time 1092044650 ps
CPU time 20.25 seconds
Started Aug 11 05:24:30 PM PDT 24
Finished Aug 11 05:24:50 PM PDT 24
Peak memory 239740 kb
Host smart-c547f187-24b6-4e3b-8c9c-d82032ad0a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597418301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.597418301
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2677541609
Short name T971
Test name
Test status
Simulation time 32687447298 ps
CPU time 24.8 seconds
Started Aug 11 05:24:30 PM PDT 24
Finished Aug 11 05:24:55 PM PDT 24
Peak memory 232468 kb
Host smart-71663c49-e4ef-4db6-87db-e9f23d8b7794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677541609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2677541609
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.643712874
Short name T40
Test name
Test status
Simulation time 586546980 ps
CPU time 6.46 seconds
Started Aug 11 05:24:24 PM PDT 24
Finished Aug 11 05:24:30 PM PDT 24
Peak memory 240812 kb
Host smart-83d423fe-ace5-41af-bf02-e13f0014d07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643712874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.643712874
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3813030060
Short name T583
Test name
Test status
Simulation time 1297781768 ps
CPU time 15.66 seconds
Started Aug 11 05:24:29 PM PDT 24
Finished Aug 11 05:24:45 PM PDT 24
Peak memory 220948 kb
Host smart-dc7a25ca-1f8b-4e04-9a3e-9949ab657060
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3813030060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3813030060
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4155474796
Short name T518
Test name
Test status
Simulation time 5591811339 ps
CPU time 36.87 seconds
Started Aug 11 05:24:24 PM PDT 24
Finished Aug 11 05:25:01 PM PDT 24
Peak memory 216596 kb
Host smart-56696eb7-e65c-43db-a95a-de0c4eb95565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155474796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4155474796
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2046367870
Short name T29
Test name
Test status
Simulation time 2859133670 ps
CPU time 3.08 seconds
Started Aug 11 05:24:23 PM PDT 24
Finished Aug 11 05:24:26 PM PDT 24
Peak memory 216520 kb
Host smart-a66f6c5f-cd65-4e6c-89bc-33decbec3828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046367870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2046367870
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3392019447
Short name T958
Test name
Test status
Simulation time 3964504018 ps
CPU time 8.58 seconds
Started Aug 11 05:24:25 PM PDT 24
Finished Aug 11 05:24:34 PM PDT 24
Peak memory 216552 kb
Host smart-83e76535-0f67-4ea7-b3d5-88715f5cc75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392019447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3392019447
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2941823224
Short name T858
Test name
Test status
Simulation time 119191602 ps
CPU time 0.83 seconds
Started Aug 11 05:24:23 PM PDT 24
Finished Aug 11 05:24:24 PM PDT 24
Peak memory 206136 kb
Host smart-62c94ad5-67de-4073-84a3-485543b08df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941823224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2941823224
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.750315108
Short name T932
Test name
Test status
Simulation time 14651559522 ps
CPU time 15.08 seconds
Started Aug 11 05:24:31 PM PDT 24
Finished Aug 11 05:24:47 PM PDT 24
Peak memory 224916 kb
Host smart-855ada52-4f4a-436f-b742-69ab8d9e8343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750315108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.750315108
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.858059201
Short name T497
Test name
Test status
Simulation time 18624412 ps
CPU time 0.73 seconds
Started Aug 11 05:24:35 PM PDT 24
Finished Aug 11 05:24:36 PM PDT 24
Peak memory 205644 kb
Host smart-26c57ccd-7478-4940-9ac3-ea5868863e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858059201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.858059201
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.729004022
Short name T727
Test name
Test status
Simulation time 658573470 ps
CPU time 8.35 seconds
Started Aug 11 05:24:35 PM PDT 24
Finished Aug 11 05:24:43 PM PDT 24
Peak memory 233088 kb
Host smart-348cb525-9d2c-4d8e-adb6-14d19517e53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729004022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.729004022
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1497936968
Short name T1012
Test name
Test status
Simulation time 56174121 ps
CPU time 0.82 seconds
Started Aug 11 05:24:30 PM PDT 24
Finished Aug 11 05:24:31 PM PDT 24
Peak memory 206272 kb
Host smart-2b38f753-058b-430b-ba04-40ad00239a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497936968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1497936968
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.870957292
Short name T269
Test name
Test status
Simulation time 75349225533 ps
CPU time 150.59 seconds
Started Aug 11 05:24:36 PM PDT 24
Finished Aug 11 05:27:07 PM PDT 24
Peak memory 249544 kb
Host smart-23d6df60-08ae-45c1-9818-5a9afa1a1451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870957292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.870957292
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.280317957
Short name T895
Test name
Test status
Simulation time 1891007680 ps
CPU time 30.42 seconds
Started Aug 11 05:24:36 PM PDT 24
Finished Aug 11 05:25:07 PM PDT 24
Peak memory 218064 kb
Host smart-97109907-5173-4057-9b70-2c959fb6180c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280317957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.280317957
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2647804868
Short name T566
Test name
Test status
Simulation time 34653411897 ps
CPU time 342.79 seconds
Started Aug 11 05:24:37 PM PDT 24
Finished Aug 11 05:30:20 PM PDT 24
Peak memory 251044 kb
Host smart-626543bc-b505-4c26-97cb-a03175a52661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647804868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2647804868
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3808471981
Short name T838
Test name
Test status
Simulation time 288945654 ps
CPU time 6.55 seconds
Started Aug 11 05:24:36 PM PDT 24
Finished Aug 11 05:24:43 PM PDT 24
Peak memory 224748 kb
Host smart-945ca92d-a09b-42af-a991-841d016c7f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808471981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3808471981
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2307128774
Short name T256
Test name
Test status
Simulation time 5738748373 ps
CPU time 7.15 seconds
Started Aug 11 05:24:29 PM PDT 24
Finished Aug 11 05:24:36 PM PDT 24
Peak memory 233064 kb
Host smart-b6c861cf-8c79-477b-bfc1-fed78025ea02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307128774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2307128774
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.221423036
Short name T840
Test name
Test status
Simulation time 29643777845 ps
CPU time 226.08 seconds
Started Aug 11 05:24:30 PM PDT 24
Finished Aug 11 05:28:16 PM PDT 24
Peak memory 240544 kb
Host smart-f1230f67-436f-478a-91ad-ef2aa4274384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221423036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.221423036
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1789647109
Short name T90
Test name
Test status
Simulation time 15555212228 ps
CPU time 15.12 seconds
Started Aug 11 05:24:31 PM PDT 24
Finished Aug 11 05:24:46 PM PDT 24
Peak memory 224852 kb
Host smart-0d9af474-e7a8-48f4-ba05-ce150af4f2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789647109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1789647109
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.198164571
Short name T948
Test name
Test status
Simulation time 122682251 ps
CPU time 2.23 seconds
Started Aug 11 05:24:30 PM PDT 24
Finished Aug 11 05:24:33 PM PDT 24
Peak memory 224704 kb
Host smart-6e954321-dc76-40dd-b67f-a2c4edd7736a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198164571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.198164571
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1461065033
Short name T11
Test name
Test status
Simulation time 381054393 ps
CPU time 4.31 seconds
Started Aug 11 05:24:36 PM PDT 24
Finished Aug 11 05:24:40 PM PDT 24
Peak memory 223452 kb
Host smart-b881f8b6-a2e2-4a45-b83e-7e35a5086149
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1461065033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1461065033
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1757313880
Short name T832
Test name
Test status
Simulation time 95264193602 ps
CPU time 240.32 seconds
Started Aug 11 05:24:35 PM PDT 24
Finished Aug 11 05:28:36 PM PDT 24
Peak memory 274056 kb
Host smart-a620c5f2-6f12-4b9d-941d-e4373804c1a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757313880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1757313880
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2355069530
Short name T780
Test name
Test status
Simulation time 5289635201 ps
CPU time 26.03 seconds
Started Aug 11 05:24:30 PM PDT 24
Finished Aug 11 05:24:56 PM PDT 24
Peak memory 216872 kb
Host smart-9ab30ac4-fd76-4374-8bb9-8f3147a7d55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355069530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2355069530
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1160073000
Short name T819
Test name
Test status
Simulation time 21868682284 ps
CPU time 10.27 seconds
Started Aug 11 05:24:31 PM PDT 24
Finished Aug 11 05:24:42 PM PDT 24
Peak memory 218908 kb
Host smart-152f80d4-0a0e-4233-b63a-9b333b3f8e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160073000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1160073000
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2273589998
Short name T516
Test name
Test status
Simulation time 281304795 ps
CPU time 2.14 seconds
Started Aug 11 05:24:32 PM PDT 24
Finished Aug 11 05:24:34 PM PDT 24
Peak memory 216616 kb
Host smart-81cac54f-3805-410c-93e9-099d2a6ff7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273589998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2273589998
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2976133237
Short name T571
Test name
Test status
Simulation time 87726596 ps
CPU time 0.79 seconds
Started Aug 11 05:24:28 PM PDT 24
Finished Aug 11 05:24:29 PM PDT 24
Peak memory 206216 kb
Host smart-357dcfd7-f447-49a2-87c4-619608ecad91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976133237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2976133237
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3709211815
Short name T9
Test name
Test status
Simulation time 339413333 ps
CPU time 5.71 seconds
Started Aug 11 05:24:31 PM PDT 24
Finished Aug 11 05:24:36 PM PDT 24
Peak memory 233000 kb
Host smart-0595c84f-0f71-44b5-98db-8cbadaa17ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709211815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3709211815
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.4201569485
Short name T417
Test name
Test status
Simulation time 15325042 ps
CPU time 0.74 seconds
Started Aug 11 05:18:56 PM PDT 24
Finished Aug 11 05:18:57 PM PDT 24
Peak memory 205176 kb
Host smart-73d72878-f6ea-41c7-8c96-fcaf605df831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201569485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4
201569485
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.811526226
Short name T632
Test name
Test status
Simulation time 1378090213 ps
CPU time 7.96 seconds
Started Aug 11 05:18:51 PM PDT 24
Finished Aug 11 05:18:59 PM PDT 24
Peak memory 224888 kb
Host smart-627fb454-7e74-4c7e-8f40-6498cd75a8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811526226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.811526226
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4136213096
Short name T723
Test name
Test status
Simulation time 80407737 ps
CPU time 0.77 seconds
Started Aug 11 05:18:45 PM PDT 24
Finished Aug 11 05:18:46 PM PDT 24
Peak memory 206912 kb
Host smart-9817a1af-51e6-4e31-91a1-86020b27922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136213096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4136213096
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3401365393
Short name T183
Test name
Test status
Simulation time 7645032072 ps
CPU time 51.6 seconds
Started Aug 11 05:18:50 PM PDT 24
Finished Aug 11 05:19:41 PM PDT 24
Peak memory 257492 kb
Host smart-6f0f06da-8232-4d25-a8e3-ef5efcefc55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401365393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3401365393
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2553796839
Short name T287
Test name
Test status
Simulation time 8854701218 ps
CPU time 60.95 seconds
Started Aug 11 05:18:57 PM PDT 24
Finished Aug 11 05:19:58 PM PDT 24
Peak memory 256964 kb
Host smart-b3290ab8-ec87-434a-98cb-607cb0b43179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553796839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2553796839
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2429445127
Short name T211
Test name
Test status
Simulation time 73875049007 ps
CPU time 342.71 seconds
Started Aug 11 05:18:57 PM PDT 24
Finished Aug 11 05:24:40 PM PDT 24
Peak memory 255168 kb
Host smart-1b957961-c3f4-439a-a81d-d532f0f2304f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429445127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2429445127
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1506549107
Short name T446
Test name
Test status
Simulation time 425090827 ps
CPU time 8.11 seconds
Started Aug 11 05:18:50 PM PDT 24
Finished Aug 11 05:18:59 PM PDT 24
Peak memory 224796 kb
Host smart-073700b9-83b3-4662-8e77-d2c006acceb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506549107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1506549107
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1935574927
Short name T359
Test name
Test status
Simulation time 17659664070 ps
CPU time 97.52 seconds
Started Aug 11 05:18:51 PM PDT 24
Finished Aug 11 05:20:28 PM PDT 24
Peak memory 249448 kb
Host smart-ed1d7a5a-ff4b-4fe6-bb2c-dd7148e1df96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935574927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1935574927
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1810756856
Short name T681
Test name
Test status
Simulation time 150314238 ps
CPU time 2.7 seconds
Started Aug 11 05:18:50 PM PDT 24
Finished Aug 11 05:18:52 PM PDT 24
Peak memory 224772 kb
Host smart-779c9b0c-54b8-48d4-a666-2d04dc6fb283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810756856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1810756856
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2508113949
Short name T925
Test name
Test status
Simulation time 34717882485 ps
CPU time 250.61 seconds
Started Aug 11 05:18:52 PM PDT 24
Finished Aug 11 05:23:03 PM PDT 24
Peak memory 238776 kb
Host smart-90e67eb2-0560-4855-a5f3-026efc1fa1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508113949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2508113949
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.4276955460
Short name T758
Test name
Test status
Simulation time 5034151759 ps
CPU time 16.13 seconds
Started Aug 11 05:18:51 PM PDT 24
Finished Aug 11 05:19:07 PM PDT 24
Peak memory 233112 kb
Host smart-eeac56bc-9713-40b7-9120-73368d8f9916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276955460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.4276955460
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3255699383
Short name T634
Test name
Test status
Simulation time 284816627 ps
CPU time 2.25 seconds
Started Aug 11 05:18:47 PM PDT 24
Finished Aug 11 05:18:49 PM PDT 24
Peak memory 222880 kb
Host smart-80c3672c-7a92-4f38-a6bb-379e579895cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255699383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3255699383
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3675782173
Short name T689
Test name
Test status
Simulation time 1213609902 ps
CPU time 9.33 seconds
Started Aug 11 05:18:52 PM PDT 24
Finished Aug 11 05:19:01 PM PDT 24
Peak memory 219564 kb
Host smart-92c2acf4-a701-4e98-8eb6-43fe03125120
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3675782173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3675782173
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2706028199
Short name T734
Test name
Test status
Simulation time 5239999389 ps
CPU time 28.97 seconds
Started Aug 11 05:18:47 PM PDT 24
Finished Aug 11 05:19:16 PM PDT 24
Peak memory 215088 kb
Host smart-78151684-d919-44fb-ae91-3cfba1681a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706028199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2706028199
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.323054005
Short name T570
Test name
Test status
Simulation time 8855347502 ps
CPU time 27.44 seconds
Started Aug 11 05:18:44 PM PDT 24
Finished Aug 11 05:19:12 PM PDT 24
Peak memory 216636 kb
Host smart-156c179e-0df6-4697-8c72-0dbca9a5c601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323054005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.323054005
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1355070417
Short name T913
Test name
Test status
Simulation time 124661477 ps
CPU time 1.29 seconds
Started Aug 11 05:18:45 PM PDT 24
Finished Aug 11 05:18:46 PM PDT 24
Peak memory 216360 kb
Host smart-518e3319-b2b8-4e93-ae12-c07859715561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355070417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1355070417
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3574629864
Short name T862
Test name
Test status
Simulation time 170989589 ps
CPU time 0.73 seconds
Started Aug 11 05:18:45 PM PDT 24
Finished Aug 11 05:18:46 PM PDT 24
Peak memory 206316 kb
Host smart-0893b59b-0d4c-4927-832c-33e26e43b2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574629864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3574629864
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3381746566
Short name T998
Test name
Test status
Simulation time 22319062828 ps
CPU time 24.2 seconds
Started Aug 11 05:18:51 PM PDT 24
Finished Aug 11 05:19:15 PM PDT 24
Peak memory 240968 kb
Host smart-5c2621b2-b47b-41a2-9dfb-b9d468c42508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381746566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3381746566
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3768007776
Short name T122
Test name
Test status
Simulation time 21580089 ps
CPU time 0.73 seconds
Started Aug 11 05:19:04 PM PDT 24
Finished Aug 11 05:19:05 PM PDT 24
Peak memory 205208 kb
Host smart-23ae1157-03e3-4b15-84fe-1cc2700c1026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768007776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
768007776
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2967367766
Short name T523
Test name
Test status
Simulation time 1229225812 ps
CPU time 12.03 seconds
Started Aug 11 05:18:58 PM PDT 24
Finished Aug 11 05:19:10 PM PDT 24
Peak memory 233048 kb
Host smart-38ecc0b2-57b8-4d46-831a-202ea21f167e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967367766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2967367766
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1648038012
Short name T643
Test name
Test status
Simulation time 93783192 ps
CPU time 0.78 seconds
Started Aug 11 05:18:55 PM PDT 24
Finished Aug 11 05:18:56 PM PDT 24
Peak memory 207176 kb
Host smart-adfbb9f2-bfb6-4ca7-ac71-6f1fdab84964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648038012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1648038012
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.132410872
Short name T956
Test name
Test status
Simulation time 239856817229 ps
CPU time 253.91 seconds
Started Aug 11 05:19:02 PM PDT 24
Finished Aug 11 05:23:16 PM PDT 24
Peak memory 267552 kb
Host smart-22e65eed-a28d-44f5-b95f-6afbc745faeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132410872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.132410872
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3908579146
Short name T194
Test name
Test status
Simulation time 4358349378 ps
CPU time 26.43 seconds
Started Aug 11 05:19:03 PM PDT 24
Finished Aug 11 05:19:30 PM PDT 24
Peak memory 238768 kb
Host smart-540c302a-90e1-4dc9-84a6-3b666991393b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908579146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3908579146
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2976142119
Short name T515
Test name
Test status
Simulation time 11081948427 ps
CPU time 98.45 seconds
Started Aug 11 05:19:02 PM PDT 24
Finished Aug 11 05:20:41 PM PDT 24
Peak memory 257632 kb
Host smart-5ee2b454-f96b-43c4-9b2f-4f5b0b3d6e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976142119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2976142119
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3351787771
Short name T135
Test name
Test status
Simulation time 1394766975 ps
CPU time 27.3 seconds
Started Aug 11 05:18:57 PM PDT 24
Finished Aug 11 05:19:25 PM PDT 24
Peak memory 241140 kb
Host smart-11da5647-f328-49b5-b1a5-23d78b8c74e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351787771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3351787771
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3551799783
Short name T87
Test name
Test status
Simulation time 247844083578 ps
CPU time 432.28 seconds
Started Aug 11 05:18:55 PM PDT 24
Finished Aug 11 05:26:08 PM PDT 24
Peak memory 253488 kb
Host smart-4e72ff67-e3fd-4439-82dc-4aa4b8b016c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551799783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3551799783
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.524794448
Short name T561
Test name
Test status
Simulation time 3126488220 ps
CPU time 26.32 seconds
Started Aug 11 05:18:58 PM PDT 24
Finished Aug 11 05:19:24 PM PDT 24
Peak memory 224812 kb
Host smart-6d630bbc-a9a5-4ee4-8466-34c7a2635929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524794448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.524794448
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1205530999
Short name T722
Test name
Test status
Simulation time 100978906 ps
CPU time 2.08 seconds
Started Aug 11 05:18:57 PM PDT 24
Finished Aug 11 05:18:59 PM PDT 24
Peak memory 224112 kb
Host smart-cb5192c8-2ddb-4e18-a9d0-dc30c9bd3703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205530999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1205530999
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3894657216
Short name T978
Test name
Test status
Simulation time 637294549 ps
CPU time 4.6 seconds
Started Aug 11 05:18:57 PM PDT 24
Finished Aug 11 05:19:01 PM PDT 24
Peak memory 232972 kb
Host smart-2e236b5d-09ee-4c16-9ccd-56011520119b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894657216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3894657216
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1541980352
Short name T601
Test name
Test status
Simulation time 2425747116 ps
CPU time 11.61 seconds
Started Aug 11 05:18:57 PM PDT 24
Finished Aug 11 05:19:09 PM PDT 24
Peak memory 233036 kb
Host smart-1627871e-25e8-4471-ad29-85dcd55ea529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541980352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1541980352
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3784014518
Short name T1
Test name
Test status
Simulation time 324980254 ps
CPU time 6.14 seconds
Started Aug 11 05:19:02 PM PDT 24
Finished Aug 11 05:19:08 PM PDT 24
Peak memory 222460 kb
Host smart-b04baf58-9139-4d7a-b3c0-258816697586
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3784014518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3784014518
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1159469355
Short name T310
Test name
Test status
Simulation time 3703976673 ps
CPU time 8.06 seconds
Started Aug 11 05:18:56 PM PDT 24
Finished Aug 11 05:19:04 PM PDT 24
Peak memory 216884 kb
Host smart-408ba5b3-ac0e-409b-92a0-9599412b2b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159469355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1159469355
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2245370569
Short name T123
Test name
Test status
Simulation time 16058473592 ps
CPU time 13.26 seconds
Started Aug 11 05:18:57 PM PDT 24
Finished Aug 11 05:19:11 PM PDT 24
Peak memory 217008 kb
Host smart-4dc32aea-ec47-4ff1-9242-69ca8f42e11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245370569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2245370569
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1960349071
Short name T381
Test name
Test status
Simulation time 263509747 ps
CPU time 1.68 seconds
Started Aug 11 05:18:59 PM PDT 24
Finished Aug 11 05:19:00 PM PDT 24
Peak memory 216588 kb
Host smart-ec0c287d-d2fe-4fcb-92ec-8e585519abe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960349071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1960349071
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3178136851
Short name T406
Test name
Test status
Simulation time 38813690 ps
CPU time 0.88 seconds
Started Aug 11 05:18:55 PM PDT 24
Finished Aug 11 05:18:56 PM PDT 24
Peak memory 206220 kb
Host smart-c52a8241-dc39-42e2-bc11-b12c0b6e8568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178136851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3178136851
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1985322454
Short name T506
Test name
Test status
Simulation time 826481472 ps
CPU time 6.87 seconds
Started Aug 11 05:18:59 PM PDT 24
Finished Aug 11 05:19:05 PM PDT 24
Peak memory 224788 kb
Host smart-4fa821da-2c9e-4f21-a1b3-d1524242b0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985322454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1985322454
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3120652761
Short name T608
Test name
Test status
Simulation time 16555673 ps
CPU time 0.77 seconds
Started Aug 11 05:19:09 PM PDT 24
Finished Aug 11 05:19:10 PM PDT 24
Peak memory 205804 kb
Host smart-95f38760-b828-4824-bf99-7ca8efa9c7c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120652761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
120652761
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1512125365
Short name T57
Test name
Test status
Simulation time 302703669 ps
CPU time 2.42 seconds
Started Aug 11 05:19:03 PM PDT 24
Finished Aug 11 05:19:06 PM PDT 24
Peak memory 232584 kb
Host smart-1861ebad-99a1-43df-b17d-7f15b2fcc51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512125365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1512125365
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3689006360
Short name T999
Test name
Test status
Simulation time 16160566 ps
CPU time 0.79 seconds
Started Aug 11 05:19:03 PM PDT 24
Finished Aug 11 05:19:03 PM PDT 24
Peak memory 207260 kb
Host smart-be1865ca-f3e7-479f-90e4-95f03e8d817e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689006360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3689006360
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1982331135
Short name T872
Test name
Test status
Simulation time 1087883998 ps
CPU time 20.41 seconds
Started Aug 11 05:19:10 PM PDT 24
Finished Aug 11 05:19:30 PM PDT 24
Peak memory 239068 kb
Host smart-54e5c6d9-50fb-42ff-975b-a90fee1e42c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982331135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1982331135
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2263874042
Short name T983
Test name
Test status
Simulation time 458489617 ps
CPU time 2.07 seconds
Started Aug 11 05:19:11 PM PDT 24
Finished Aug 11 05:19:13 PM PDT 24
Peak memory 223840 kb
Host smart-dc2c325b-4019-422f-903d-16c56a888b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263874042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2263874042
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.720211808
Short name T412
Test name
Test status
Simulation time 2771632665 ps
CPU time 55.59 seconds
Started Aug 11 05:19:11 PM PDT 24
Finished Aug 11 05:20:06 PM PDT 24
Peak memory 239308 kb
Host smart-b19dee74-7788-41ed-a437-d821c052076a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720211808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
720211808
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3305648378
Short name T996
Test name
Test status
Simulation time 1748544423 ps
CPU time 8.85 seconds
Started Aug 11 05:19:10 PM PDT 24
Finished Aug 11 05:19:19 PM PDT 24
Peak memory 241312 kb
Host smart-b76a1c8a-2f80-4b88-9797-e6da3e669585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305648378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3305648378
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2293709137
Short name T623
Test name
Test status
Simulation time 58632251459 ps
CPU time 210.97 seconds
Started Aug 11 05:19:08 PM PDT 24
Finished Aug 11 05:22:39 PM PDT 24
Peak memory 267848 kb
Host smart-65cf29d4-cf00-4a05-86eb-0dd47714002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293709137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2293709137
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1561023043
Short name T955
Test name
Test status
Simulation time 78036547 ps
CPU time 2.42 seconds
Started Aug 11 05:19:01 PM PDT 24
Finished Aug 11 05:19:03 PM PDT 24
Peak memory 227036 kb
Host smart-0ba3a89a-639d-40fc-a1b7-82f0abf214fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561023043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1561023043
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1006401918
Short name T575
Test name
Test status
Simulation time 3772381257 ps
CPU time 41.01 seconds
Started Aug 11 05:19:03 PM PDT 24
Finished Aug 11 05:19:45 PM PDT 24
Peak memory 224888 kb
Host smart-ea583fc9-5776-4237-8acc-bf322feefaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006401918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1006401918
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1089011860
Short name T884
Test name
Test status
Simulation time 1530866015 ps
CPU time 4.39 seconds
Started Aug 11 05:19:03 PM PDT 24
Finished Aug 11 05:19:07 PM PDT 24
Peak memory 233036 kb
Host smart-51c8a5b2-10df-43c0-9a70-2ef3af7b6d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089011860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1089011860
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.399564821
Short name T988
Test name
Test status
Simulation time 13653355292 ps
CPU time 10.77 seconds
Started Aug 11 05:19:06 PM PDT 24
Finished Aug 11 05:19:17 PM PDT 24
Peak memory 233040 kb
Host smart-33bab41c-5a63-447e-a5af-e1a80ec9ed13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399564821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.399564821
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.868430857
Short name T137
Test name
Test status
Simulation time 2036015648 ps
CPU time 6.33 seconds
Started Aug 11 05:19:12 PM PDT 24
Finished Aug 11 05:19:18 PM PDT 24
Peak memory 219156 kb
Host smart-4cb4367f-4246-4837-abe7-a26f454c0dc3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=868430857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.868430857
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1391585029
Short name T152
Test name
Test status
Simulation time 25128319075 ps
CPU time 240.63 seconds
Started Aug 11 05:19:11 PM PDT 24
Finished Aug 11 05:23:11 PM PDT 24
Peak memory 256808 kb
Host smart-c320cea5-a000-433a-b618-0681d79e441d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391585029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1391585029
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1802746852
Short name T304
Test name
Test status
Simulation time 1399986493 ps
CPU time 7.95 seconds
Started Aug 11 05:19:04 PM PDT 24
Finished Aug 11 05:19:12 PM PDT 24
Peak memory 216636 kb
Host smart-1a4d0316-6c1e-4934-89e3-23445fc53f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802746852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1802746852
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1851076770
Short name T594
Test name
Test status
Simulation time 426761058 ps
CPU time 3.5 seconds
Started Aug 11 05:19:04 PM PDT 24
Finished Aug 11 05:19:08 PM PDT 24
Peak memory 216548 kb
Host smart-94a041ee-af63-4794-954f-cc7a55a064b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851076770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1851076770
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2138413356
Short name T730
Test name
Test status
Simulation time 12900786 ps
CPU time 0.69 seconds
Started Aug 11 05:19:04 PM PDT 24
Finished Aug 11 05:19:05 PM PDT 24
Peak memory 205940 kb
Host smart-df75c9e4-a283-44da-b324-0fb2c8ec71b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138413356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2138413356
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.138383332
Short name T702
Test name
Test status
Simulation time 221379272 ps
CPU time 0.94 seconds
Started Aug 11 05:19:03 PM PDT 24
Finished Aug 11 05:19:04 PM PDT 24
Peak memory 206180 kb
Host smart-8ba0a9f9-b1a2-4df0-bf9d-a2c23c2aa35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138383332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.138383332
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.483719705
Short name T912
Test name
Test status
Simulation time 804712556 ps
CPU time 7.44 seconds
Started Aug 11 05:19:03 PM PDT 24
Finished Aug 11 05:19:11 PM PDT 24
Peak memory 232996 kb
Host smart-3574b45b-2501-40ea-90de-435687180c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483719705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.483719705
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.112220212
Short name T667
Test name
Test status
Simulation time 30110248 ps
CPU time 0.77 seconds
Started Aug 11 05:19:16 PM PDT 24
Finished Aug 11 05:19:17 PM PDT 24
Peak memory 205652 kb
Host smart-e4557451-14ed-4833-a715-939bf0f9d787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112220212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.112220212
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3161030673
Short name T733
Test name
Test status
Simulation time 42069484 ps
CPU time 2.55 seconds
Started Aug 11 05:19:16 PM PDT 24
Finished Aug 11 05:19:19 PM PDT 24
Peak memory 233032 kb
Host smart-a931795e-e125-4aac-96a5-32a50d2cd2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161030673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3161030673
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3600692230
Short name T717
Test name
Test status
Simulation time 75949882 ps
CPU time 0.73 seconds
Started Aug 11 05:19:11 PM PDT 24
Finished Aug 11 05:19:12 PM PDT 24
Peak memory 207248 kb
Host smart-b1da8199-5423-4260-8a9f-54e0bb860a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600692230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3600692230
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3560991793
Short name T283
Test name
Test status
Simulation time 14461358806 ps
CPU time 31.55 seconds
Started Aug 11 05:19:16 PM PDT 24
Finished Aug 11 05:19:48 PM PDT 24
Peak memory 240420 kb
Host smart-af45a1ba-5ba3-4518-8846-b30d08781e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560991793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3560991793
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1468271608
Short name T200
Test name
Test status
Simulation time 134095590264 ps
CPU time 169.02 seconds
Started Aug 11 05:19:18 PM PDT 24
Finished Aug 11 05:22:07 PM PDT 24
Peak memory 249764 kb
Host smart-dabeb0ef-7688-4220-81ee-38a20f357f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468271608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1468271608
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2060017855
Short name T313
Test name
Test status
Simulation time 4896950587 ps
CPU time 52.29 seconds
Started Aug 11 05:19:17 PM PDT 24
Finished Aug 11 05:20:09 PM PDT 24
Peak memory 236844 kb
Host smart-49187f62-b3da-46ce-a610-cd01cea0fbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060017855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2060017855
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1798767191
Short name T622
Test name
Test status
Simulation time 942341649 ps
CPU time 6.36 seconds
Started Aug 11 05:19:16 PM PDT 24
Finished Aug 11 05:19:23 PM PDT 24
Peak memory 233000 kb
Host smart-db29abd5-8729-47f8-88cb-9042a8d19042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798767191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1798767191
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1373978030
Short name T574
Test name
Test status
Simulation time 98333998267 ps
CPU time 120.6 seconds
Started Aug 11 05:19:16 PM PDT 24
Finished Aug 11 05:21:17 PM PDT 24
Peak memory 249548 kb
Host smart-78d60bf4-e22f-439d-b70a-c5c1dd64cecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373978030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1373978030
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2971489476
Short name T237
Test name
Test status
Simulation time 877157802 ps
CPU time 7.56 seconds
Started Aug 11 05:19:15 PM PDT 24
Finished Aug 11 05:19:23 PM PDT 24
Peak memory 224772 kb
Host smart-b2667c00-395a-4e18-84b9-e86fca6d3c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971489476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2971489476
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1986061434
Short name T220
Test name
Test status
Simulation time 54253752376 ps
CPU time 82.98 seconds
Started Aug 11 05:19:19 PM PDT 24
Finished Aug 11 05:20:42 PM PDT 24
Peak memory 250832 kb
Host smart-8b151080-8095-4ed2-9734-635003196284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986061434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1986061434
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3680988132
Short name T775
Test name
Test status
Simulation time 2908354371 ps
CPU time 8.94 seconds
Started Aug 11 05:19:18 PM PDT 24
Finished Aug 11 05:19:27 PM PDT 24
Peak memory 224864 kb
Host smart-7b4e63b5-68b5-4e57-8a29-d97f39463946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680988132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3680988132
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3539180469
Short name T856
Test name
Test status
Simulation time 563706656 ps
CPU time 5.62 seconds
Started Aug 11 05:19:11 PM PDT 24
Finished Aug 11 05:19:17 PM PDT 24
Peak memory 233112 kb
Host smart-a15066ef-46fe-4b2c-9fdf-1d8a6f9f91fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539180469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3539180469
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3359512448
Short name T904
Test name
Test status
Simulation time 1560523634 ps
CPU time 10.67 seconds
Started Aug 11 05:19:18 PM PDT 24
Finished Aug 11 05:19:29 PM PDT 24
Peak memory 222984 kb
Host smart-149d8efd-b3f1-40e0-b919-1a4d5df23e8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3359512448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3359512448
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.869519029
Short name T573
Test name
Test status
Simulation time 49258965 ps
CPU time 1.09 seconds
Started Aug 11 05:19:16 PM PDT 24
Finished Aug 11 05:19:18 PM PDT 24
Peak memory 207876 kb
Host smart-0084fd1a-d32c-43db-9b6f-19a6b5d57633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869519029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.869519029
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.580801173
Short name T25
Test name
Test status
Simulation time 6298204310 ps
CPU time 9.66 seconds
Started Aug 11 05:19:11 PM PDT 24
Finished Aug 11 05:19:21 PM PDT 24
Peak memory 216660 kb
Host smart-375a773c-c791-4164-af6d-63b8e5d1edae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580801173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.580801173
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.797672785
Short name T700
Test name
Test status
Simulation time 15370322 ps
CPU time 0.75 seconds
Started Aug 11 05:19:09 PM PDT 24
Finished Aug 11 05:19:10 PM PDT 24
Peak memory 206028 kb
Host smart-c661bc81-d9b2-46e6-9a48-ad114e575ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797672785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.797672785
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2875910912
Short name T322
Test name
Test status
Simulation time 122353767 ps
CPU time 3.13 seconds
Started Aug 11 05:19:12 PM PDT 24
Finished Aug 11 05:19:15 PM PDT 24
Peak memory 216608 kb
Host smart-ce4c04f4-8580-46ed-84be-cf72ea3c8979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875910912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2875910912
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3617782832
Short name T337
Test name
Test status
Simulation time 14781397 ps
CPU time 0.75 seconds
Started Aug 11 05:19:11 PM PDT 24
Finished Aug 11 05:19:11 PM PDT 24
Peak memory 206272 kb
Host smart-65004de0-e3e1-44c4-b5bd-a7f22505be51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617782832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3617782832
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.735550902
Short name T851
Test name
Test status
Simulation time 633083864 ps
CPU time 5.79 seconds
Started Aug 11 05:19:17 PM PDT 24
Finished Aug 11 05:19:23 PM PDT 24
Peak memory 233056 kb
Host smart-8fab32c7-2471-492e-9e09-ec5aae497b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735550902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.735550902
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.361085367
Short name T447
Test name
Test status
Simulation time 39539468 ps
CPU time 0.71 seconds
Started Aug 11 05:19:28 PM PDT 24
Finished Aug 11 05:19:29 PM PDT 24
Peak memory 205760 kb
Host smart-fd4dbae7-4ac7-49de-9a22-a3a830c933d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361085367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.361085367
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3200851311
Short name T227
Test name
Test status
Simulation time 484902351 ps
CPU time 3.63 seconds
Started Aug 11 05:19:23 PM PDT 24
Finished Aug 11 05:19:27 PM PDT 24
Peak memory 224812 kb
Host smart-6ac11282-5307-49d7-bc47-6f817879bbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200851311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3200851311
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2012071374
Short name T12
Test name
Test status
Simulation time 77760354 ps
CPU time 0.78 seconds
Started Aug 11 05:19:18 PM PDT 24
Finished Aug 11 05:19:19 PM PDT 24
Peak memory 206836 kb
Host smart-e7d5561b-1830-4df8-993f-de7649e05d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012071374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2012071374
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1188617300
Short name T544
Test name
Test status
Simulation time 52792246507 ps
CPU time 189.71 seconds
Started Aug 11 05:19:25 PM PDT 24
Finished Aug 11 05:22:35 PM PDT 24
Peak memory 252096 kb
Host smart-b1d895a6-d1ed-4e8c-83e3-be571cc6ff16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188617300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1188617300
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.776000430
Short name T60
Test name
Test status
Simulation time 6478054994 ps
CPU time 93.94 seconds
Started Aug 11 05:19:25 PM PDT 24
Finished Aug 11 05:20:59 PM PDT 24
Peak memory 257788 kb
Host smart-db149c0d-ba30-4559-aabd-6aa3a19ca3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776000430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.776000430
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2653051690
Short name T536
Test name
Test status
Simulation time 29546510926 ps
CPU time 78.44 seconds
Started Aug 11 05:19:28 PM PDT 24
Finished Aug 11 05:20:47 PM PDT 24
Peak memory 249540 kb
Host smart-0bc3eed0-c4c5-47ec-a567-ebdc729e0183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653051690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2653051690
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2904869886
Short name T346
Test name
Test status
Simulation time 1253285687 ps
CPU time 4.05 seconds
Started Aug 11 05:19:22 PM PDT 24
Finished Aug 11 05:19:26 PM PDT 24
Peak memory 224860 kb
Host smart-0dbfb06b-ca37-4e53-816f-fe9b0d37a1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904869886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2904869886
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3018157988
Short name T897
Test name
Test status
Simulation time 2191594613 ps
CPU time 8.16 seconds
Started Aug 11 05:19:22 PM PDT 24
Finished Aug 11 05:19:30 PM PDT 24
Peak memory 233364 kb
Host smart-47f83a90-b534-4fbb-bae2-499a33438436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018157988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3018157988
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1066286343
Short name T896
Test name
Test status
Simulation time 438682354 ps
CPU time 3.98 seconds
Started Aug 11 05:19:22 PM PDT 24
Finished Aug 11 05:19:26 PM PDT 24
Peak memory 232980 kb
Host smart-37ba31af-711a-47bc-a41e-e177edc243a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066286343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1066286343
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3097463506
Short name T917
Test name
Test status
Simulation time 17386521571 ps
CPU time 72.43 seconds
Started Aug 11 05:19:25 PM PDT 24
Finished Aug 11 05:20:38 PM PDT 24
Peak memory 241208 kb
Host smart-cb9df302-9695-4b87-8a7b-25ff92fd3f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097463506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3097463506
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2339290633
Short name T270
Test name
Test status
Simulation time 586214531 ps
CPU time 4.05 seconds
Started Aug 11 05:19:24 PM PDT 24
Finished Aug 11 05:19:28 PM PDT 24
Peak memory 233032 kb
Host smart-1032191f-ecbe-416c-9873-a812e3df7be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339290633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2339290633
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3190213073
Short name T874
Test name
Test status
Simulation time 478995778 ps
CPU time 3.7 seconds
Started Aug 11 05:19:22 PM PDT 24
Finished Aug 11 05:19:26 PM PDT 24
Peak memory 224772 kb
Host smart-4263bf3d-951e-4432-93df-6aaacad0532a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190213073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3190213073
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.398388550
Short name T657
Test name
Test status
Simulation time 4755590392 ps
CPU time 6.99 seconds
Started Aug 11 05:19:23 PM PDT 24
Finished Aug 11 05:19:30 PM PDT 24
Peak memory 223636 kb
Host smart-7d2032b6-5b10-4ee5-aa62-207363bf918d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=398388550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.398388550
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.35690080
Short name T1001
Test name
Test status
Simulation time 138859690 ps
CPU time 0.97 seconds
Started Aug 11 05:19:28 PM PDT 24
Finished Aug 11 05:19:29 PM PDT 24
Peak memory 207260 kb
Host smart-bb3c5c9f-06fc-4a34-8452-9abcbd135aed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35690080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_
all.35690080
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2438117841
Short name T713
Test name
Test status
Simulation time 33358277316 ps
CPU time 42.72 seconds
Started Aug 11 05:19:24 PM PDT 24
Finished Aug 11 05:20:07 PM PDT 24
Peak memory 216680 kb
Host smart-a7b080ff-d419-48ec-940c-bae9bc25ea27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438117841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2438117841
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1042150607
Short name T628
Test name
Test status
Simulation time 1169043622 ps
CPU time 4.31 seconds
Started Aug 11 05:19:26 PM PDT 24
Finished Aug 11 05:19:31 PM PDT 24
Peak memory 216612 kb
Host smart-10bf7716-95db-4148-88d8-497a679e31dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042150607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1042150607
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2565871790
Short name T448
Test name
Test status
Simulation time 16461192 ps
CPU time 0.95 seconds
Started Aug 11 05:19:22 PM PDT 24
Finished Aug 11 05:19:23 PM PDT 24
Peak memory 208424 kb
Host smart-384d7558-bd74-4b35-8e93-ac501db439e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565871790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2565871790
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1912258618
Short name T804
Test name
Test status
Simulation time 76374461 ps
CPU time 0.8 seconds
Started Aug 11 05:19:22 PM PDT 24
Finished Aug 11 05:19:23 PM PDT 24
Peak memory 206316 kb
Host smart-d0baa063-fd65-441e-af78-caab7f01767a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912258618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1912258618
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3128954517
Short name T588
Test name
Test status
Simulation time 8022894617 ps
CPU time 31.77 seconds
Started Aug 11 05:19:24 PM PDT 24
Finished Aug 11 05:19:56 PM PDT 24
Peak memory 241392 kb
Host smart-86221407-967f-41f8-9ba3-302a1e8a481c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128954517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3128954517
Directory /workspace/9.spi_device_upload/latest
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