Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2604777	1			T1	123		T4	1		T5	171
all_values[1]	2604777	1			T1	123		T4	1		T5	171
all_values[2]	2604777	1			T1	123		T4	1		T5	171
all_values[3]	2604777	1			T1	123		T4	1		T5	171
all_values[4]	2604777	1			T1	123		T4	1		T5	171
all_values[5]	2604777	1			T1	123		T4	1		T5	171
all_values[6]	2604777	1			T1	123		T4	1		T5	171
all_values[7]	2604777	1			T1	123		T4	1		T5	171

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19710327

1

T1

984

T4

8

T5

1368

auto[1]

1127889

1

T14

113107

T16

57

T17

110

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20809421

1

T1

984

T4

8

T5

1368

auto[1]

28795

1

T6

286

T13

301

T14

620

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2473636	1			T1	123		T4	1		T5	171
all_values[0]	auto[0]	auto[1]	12776	1			T6	112		T13	150		T14	2
all_values[0]	auto[1]	auto[0]	117326	1			T14	27972		T16	6		T17	10
all_values[0]	auto[1]	auto[1]	1039	1			T14	299		T17	7		T18	1
all_values[1]	auto[0]	auto[0]	2483060	1			T1	123		T4	1		T5	171
all_values[1]	auto[0]	auto[1]	8567	1			T6	91		T13	109		T25	53
all_values[1]	auto[1]	auto[0]	112326	1			T14	28047		T16	5		T17	6
all_values[1]	auto[1]	auto[1]	824	1			T14	225		T16	1		T17	8
all_values[2]	auto[0]	auto[0]	2490708	1			T1	123		T4	1		T5	171
all_values[2]	auto[0]	auto[1]	3632	1			T6	83		T13	42		T14	71
all_values[2]	auto[1]	auto[0]	110136	1			T14	3		T16	3		T17	9
all_values[2]	auto[1]	auto[1]	301	1			T14	3		T16	3		T17	3
all_values[3]	auto[0]	auto[0]	2462992	1			T1	123		T4	1		T5	171
all_values[3]	auto[0]	auto[1]	182	1			T14	3		T16	9		T31	1
all_values[3]	auto[1]	auto[0]	141440	1			T14	5		T16	1		T17	11
all_values[3]	auto[1]	auto[1]	163	1			T14	1		T16	3		T17	3
all_values[4]	auto[0]	auto[0]	2522922	1			T1	123		T4	1		T5	171
all_values[4]	auto[0]	auto[1]	169	1			T16	3		T17	4		T19	2
all_values[4]	auto[1]	auto[0]	81537	1			T14	28265		T16	7		T17	12
all_values[4]	auto[1]	auto[1]	149	1			T14	5		T16	1		T17	4
all_values[5]	auto[0]	auto[0]	2342714	1			T1	123		T4	1		T5	171
all_values[5]	auto[0]	auto[1]	150	1			T16	5		T17	5		T18	2
all_values[5]	auto[1]	auto[0]	261729	1			T14	28266		T16	4		T17	5
all_values[5]	auto[1]	auto[1]	184	1			T14	6		T16	4		T17	5
all_values[6]	auto[0]	auto[0]	2448400	1			T1	123		T4	1		T5	171
all_values[6]	auto[0]	auto[1]	157	1			T14	3		T16	1		T17	1
all_values[6]	auto[1]	auto[0]	156037	1			T14	5		T16	11		T17	12
all_values[6]	auto[1]	auto[1]	183	1			T17	5		T18	2		T19	5
all_values[7]	auto[0]	auto[0]	2460082	1			T1	123		T4	1		T5	171
all_values[7]	auto[0]	auto[1]	180	1			T14	2		T16	7		T17	6
all_values[7]	auto[1]	auto[0]	144376	1			T14	5		T16	4		T17	6
all_values[7]	auto[1]	auto[1]	139	1			T16	4		T17	4		T19	2