Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	39994	1			T1	172		T5	12		T6	85
auto[SpiFlashAddrCfg]	8613	1			T1	28		T5	3		T6	19
auto[SpiFlashAddr3b]	10294	1			T1	28		T5	5		T6	36
auto[SpiFlashAddr4b]	8466	1			T1	20		T6	32		T11	20

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38755

1

T1

120

T5

11

T6

96

auto[1]

28612

1

T1

128

T5

9

T6

76

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34481

1

T1

107

T5

8

T6

77

auto[1]

32886

1

T1

141

T5

12

T6

95

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	45108	1			T1	188		T5	13		T6	95
values[1]	1222	1			T1	3		T6	3		T11	2
values[2]	1684	1			T1	4		T5	1		T6	6
values[3]	1606	1			T1	7		T5	1		T6	10
values[4]	1580	1			T1	3		T6	11		T8	2
values[5]	1658	1			T1	1		T6	9		T11	10
values[6]	1696	1			T1	3		T5	1		T6	5
values[7]	1600	1			T1	6		T6	3		T11	8
values[8]	11213	1			T1	33		T5	4		T6	30

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32101

1

T1

248

T6

172

T7

20

auto[1]

35266

1

T5

20

T14

325

T25

109

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

63678

1

T1

238

T5

16

T6

160

write

3689

1

T1

10

T5

4

T6

12

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

21504

1

T1

54

T5

6

T6

75

valids[0x1]

45863

1

T1

194

T5

14

T6

97

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1808	1			T1	2		T6	8		T11	5
internal_process_ops[0x5a]	1745	1			T1	1		T5	2		T6	4
internal_process_ops[0x05]	24368	1			T1	153		T5	1		T6	38
internal_process_ops[0x35]	1796	1			T1	2		T5	2		T6	8
internal_process_ops[0x15]	1700	1			T1	2		T5	1		T6	1
internal_process_ops[0x03]	1158	1			T1	6		T6	2		T11	7
internal_process_ops[0x0b]	1141	1			T1	4		T6	3		T11	3
internal_process_ops[0x3b]	1110	1			T1	4		T6	6		T11	8
internal_process_ops[0x6b]	1127	1			T1	4		T6	4		T8	4
internal_process_ops[0xbb]	1170	1			T1	1		T6	7		T8	2
internal_process_ops[0xeb]	1103	1			T1	1		T6	9		T11	12

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65470

1

T1

243

T5

16

T6

170

auto[1]

1897

1

T1

5

T5

4

T6

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64715

1

T1

243

T5

16

T6

166

auto[1]

2652

1

T1

5

T5

4

T6

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11305

1

T1

81

T6

49

T7

20

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6401

1

T1

91

T6

34

T11

154

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2126

1

T1

17

T6

11

T11

5

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1933

1

T1

8

T6

6

T11

13

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2472

1

T1

10

T6

14

T8

12

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2276

1

T1

15

T6

18

T11

18

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2095

1

T1

8

T6

19

T11

12

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1901

1

T1

8

T6

9

T11

8

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

111

1

T13

2

T30

3

T34

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

95

1

T11

5

T13

2

T30

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

77

1

T11

2

T16

2

T36

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

66

1

T6

2

T13

1

T30

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

121

1

T11

1

T13

5

T36

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

122

1

T11

2

T16

1

T30

7

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T6

2

T11

1

T36

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

113

1

T1

3

T11

1

T16

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

98

1

T6

1

T13

3

T36

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

99

1

T11

1

T34

1

T36

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

99

1

T1

1

T6

3

T13

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

110

1

T1

2

T13

1

T16

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

120

1

T1

4

T6

2

T13

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

80

1

T13

2

T21

2

T64

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

85

1

T6

2

T13

1

T16

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

101

1

T16

2

T19

3

T36

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12983

1

T5

4

T14

127

T25

35

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8470

1

T5

4

T14

49

T25

15

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1834

1

T5

2

T14

15

T25

9

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1728

1

T5

1

T14

13

T25

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2345

1

T5

5

T14

22

T25

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2278

1

T14

26

T25

11

T16

9

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1767

1

T14

19

T25

5

T16

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1764

1

T14

23

T25

13

T16

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

110

1

T14

2

T102

1

T27

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

120

1

T14

2

T18

2

T104

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

109

1

T14

2

T18

5

T102

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

147

1

T5

4

T18

5

T104

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

122

1

T14

1

T18

1

T102

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

146

1

T14

4

T25

1

T157

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

126

1

T14

3

T25

1

T16

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

147

1

T14

3

T25

2

T19

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

125

1

T25

3

T16

1

T77

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

118

1

T14

1

T25

2

T77

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

131

1

T14

1

T25

1

T18

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

143

1

T14

4

T18

2

T102

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

107

1

T14

1

T16

1

T18

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

134

1

T14

3

T25

1

T102

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

156

1

T14

3

T18

2

T77

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

156

1

T14

1

T18

4

T102

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3935	1			T1	12		T6	23		T7	20
auto[0]	values[0]	valids[0x1]	16596	1			T1	176		T6	72		T8	6
auto[0]	values[1]	valids[0x1]	548	1			T1	3		T6	3		T11	2
auto[0]	values[2]	valids[0x0]	529	1			T6	2		T8	4		T11	3
auto[0]	values[2]	valids[0x1]	365	1			T1	4		T6	4		T12	4
auto[0]	values[3]	valids[0x0]	543	1			T1	7		T6	9		T11	7
auto[0]	values[3]	valids[0x1]	305	1			T6	1		T11	5		T16	3
auto[0]	values[4]	valids[0x0]	503	1			T1	1		T6	7		T8	2
auto[0]	values[4]	valids[0x1]	361	1			T1	2		T6	4		T11	2
auto[0]	values[5]	valids[0x0]	603	1			T1	1		T6	7		T11	4
auto[0]	values[5]	valids[0x1]	328	1			T6	2		T11	6		T12	2
auto[0]	values[6]	valids[0x0]	614	1			T1	3		T6	5		T11	3
auto[0]	values[6]	valids[0x1]	274	1			T11	1		T30	3		T34	2
auto[0]	values[7]	valids[0x0]	543	1			T1	6		T6	3		T11	7
auto[0]	values[7]	valids[0x1]	290	1			T11	1		T13	4		T16	3
auto[0]	values[8]	valids[0x0]	3627	1			T1	24		T6	19		T11	16
auto[0]	values[8]	valids[0x1]	2137	1			T1	9		T6	11		T11	16
auto[1]	values[0]	valids[0x0]	4668	1			T5	3		T14	67		T25	19
auto[1]	values[0]	valids[0x1]	19909	1			T5	10		T14	158		T25	42
auto[1]	values[1]	valids[0x1]	674	1			T14	6		T25	1		T16	3
auto[1]	values[2]	valids[0x0]	482	1			T14	8		T16	2		T18	4
auto[1]	values[2]	valids[0x1]	308	1			T5	1		T14	3		T25	1
auto[1]	values[3]	valids[0x0]	427	1			T5	1		T14	5		T25	3
auto[1]	values[3]	valids[0x1]	331	1			T14	10		T25	3		T18	5
auto[1]	values[4]	valids[0x0]	444	1			T14	2		T16	1		T18	5
auto[1]	values[4]	valids[0x1]	272	1			T14	1		T25	5		T16	1
auto[1]	values[5]	valids[0x0]	438	1			T14	5		T25	3		T16	1
auto[1]	values[5]	valids[0x1]	289	1			T14	5		T19	3		T102	1
auto[1]	values[6]	valids[0x0]	488	1			T5	1		T14	4		T25	8
auto[1]	values[6]	valids[0x1]	320	1			T14	3		T25	1		T102	5
auto[1]	values[7]	valids[0x0]	481	1			T14	2		T25	2		T16	3
auto[1]	values[7]	valids[0x1]	286	1			T14	2		T18	1		T102	4
auto[1]	values[8]	valids[0x0]	3179	1			T5	1		T14	22		T25	9
auto[1]	values[8]	valids[0x1]	2270	1			T5	3		T14	22		T25	12