Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3529328

1

T1

5439

T5

812

T6

11833

auto[1]

39868

1

T1

148

T5

10

T6

32

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

962487

1

T1

30

T5

50

T6

42

auto[1]

2606709

1

T1

5557

T5

772

T6

11823

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	599713	1			T1	4721		T5	161		T6	6726
auto[524288:1048575]	432744	1			T1	279		T8	1407		T11	2604
auto[1048576:1572863]	433241	1			T6	645		T8	373		T11	133
auto[1572864:2097151]	424291	1			T5	652		T6	277		T7	2
auto[2097152:2621439]	457060	1			T1	148		T6	423		T7	1
auto[2621440:3145727]	416410	1			T1	1		T5	9		T6	137
auto[3145728:3670015]	404958	1			T1	438		T6	3657		T8	3525
auto[3670016:4194303]	400779	1			T7	510		T8	1531		T11	6669

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2647357

1

T1

5586

T5

820

T6

11865

auto[1]

921839

1

T1

1

T5

2

T7

37

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3101302

1

T1

5585

T5

822

T6

7588

auto[1]

467894

1

T1

2

T6

4277

T7

250

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	172079	1			T1	6		T5	22		T6	9
auto[0]	auto[0]	auto[0:524287]	auto[1]	366082	1			T1	4683		T5	132		T6	2422
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	94011	1			T1	3		T8	1407		T11	5
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	277414	1			T1	257		T11	2552		T13	2364
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	124192	1			T6	3		T8	373		T11	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	246955	1			T6	641		T11	132		T13	6912
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	123743	1			T5	12		T6	8		T7	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	242175	1			T5	640		T6	258		T11	256
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	113009	1			T1	4		T6	2		T7	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	270235	1			T1	129		T6	421		T11	1869
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	120901	1			T1	1		T5	6		T6	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	220603	1			T6	131		T11	1		T13	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	93924	1			T1	9		T6	6		T8	3525
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	254323	1			T1	345		T6	3649		T11	130
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	105610	1			T7	264		T8	1531		T11	7
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	242825	1			T11	1080		T13	3105		T25	515
auto[0]	auto[1]	auto[0:524287]	auto[0]	1144	1			T6	2		T7	4		T13	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	53447	1			T6	4275		T14	260		T25	4
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	765	1			T1	1		T11	1		T13	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	54265	1			T11	1		T13	1153		T16	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	713	1			T13	2		T30	3		T77	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	57597	1			T19	5373		T36	5		T191	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2295	1			T13	2		T14	12		T16	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	52425	1			T14	2		T30	2791		T18	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	937	1			T1	1		T13	2		T16	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	68593	1			T13	4055		T16	512		T19	512
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2592	1			T11	3		T13	1		T14	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	67514	1			T11	5		T13	613		T14	364
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	927	1			T13	1		T14	5		T16	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	50125	1			T14	3		T16	257		T36	512
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	912	1			T7	246		T11	2		T13	6
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	46996	1			T11	5488		T13	3		T25	258
auto[1]	auto[0]	auto[0:524287]	auto[0]	617	1			T1	1		T5	7		T6	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	5866	1			T1	31		T6	16		T14	6
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	524	1			T1	1		T11	1		T13	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3903	1			T1	17		T11	8		T13	30
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	456	1			T6	1		T13	2		T14	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2870	1			T13	25		T14	9		T16	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	393	1			T6	2		T13	2		T14	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2595	1			T6	9		T13	28		T14	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	512	1			T1	1		T11	2		T13	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3081	1			T1	13		T11	74		T13	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	437	1			T5	3		T11	1		T13	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3489	1			T11	14		T13	4		T14	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	438	1			T1	2		T6	1		T11	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	4696	1			T1	82		T6	1		T11	82
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	493	1			T11	4		T13	1		T25	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2851	1			T11	88		T13	5		T25	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	104	1			T14	1		T25	2		T30	7
auto[1]	auto[1]	auto[0:524287]	auto[1]	374	1			T19	2		T36	33		T180	5
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	124	1			T11	1		T13	1		T16	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1738	1			T11	35		T16	3		T104	14
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	89	1			T21	2		T188	1		T120	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	369	1			T21	5		T120	5		T207	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	115	1			T14	2		T30	12		T18	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	550	1			T14	9		T30	5		T18	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	129	1			T13	1		T36	1		T64	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	564	1			T13	6		T36	11		T64	24
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	107	1			T11	1		T14	1		T16	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	767	1			T11	43		T16	4		T36	23
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	93	1			T14	3		T30	3		T102	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	432	1			T14	3		T102	13		T129	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	102	1			T13	3		T191	3		T21	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	990	1			T13	16		T191	45		T21	5

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2151278	1			T1	5436		T5	812		T6	7556
auto[0]	auto[0]	auto[1]	916803	1			T1	1		T7	37		T8	8676
auto[0]	auto[1]	auto[0]	456957	1			T1	2		T6	4277		T7	250
auto[0]	auto[1]	auto[1]	4290	1			T11	1		T13	2		T36	4
auto[1]	auto[0]	auto[0]	32608	1			T1	148		T5	8		T6	32
auto[1]	auto[0]	auto[1]	613	1			T5	2		T11	1		T13	3
auto[1]	auto[1]	auto[0]	6514	1			T11	80		T13	27		T14	19
auto[1]	auto[1]	auto[1]	133	1			T30	3		T36	4		T37	1