Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2604777	1			T1	123		T4	1		T5	171
all_pins[1]	2604777	1			T1	123		T4	1		T5	171
all_pins[2]	2604777	1			T1	123		T4	1		T5	171
all_pins[3]	2604777	1			T1	123		T4	1		T5	171
all_pins[4]	2604777	1			T1	123		T4	1		T5	171
all_pins[5]	2604777	1			T1	123		T4	1		T5	171
all_pins[6]	2604777	1			T1	123		T4	1		T5	171
all_pins[7]	2604777	1			T1	123		T4	1		T5	171

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20679517	1			T1	984		T4	8		T5	1368
values[0x1]	158699	1			T14	1128		T16	16		T17	39
transitions[0x0=>0x1]	156467	1			T14	882		T16	14		T17	29
transitions[0x1=>0x0]	156477	1			T14	882		T16	14		T17	29

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2603651	1			T1	123		T4	1		T5	171
all_pins[0]	values[0x1]	1126	1			T14	326		T17	7		T18	1
all_pins[0]	transitions[0x0=>0x1]	366	1			T14	84		T17	4		T18	1
all_pins[0]	transitions[0x1=>0x0]	125	1			T14	3		T16	1		T17	5
all_pins[1]	values[0x0]	2603892	1			T1	123		T4	1		T5	171
all_pins[1]	values[0x1]	885	1			T14	245		T16	1		T17	8
all_pins[1]	transitions[0x0=>0x1]	803	1			T14	244		T17	8		T18	3
all_pins[1]	transitions[0x1=>0x0]	232	1			T14	2		T16	2		T17	3
all_pins[2]	values[0x0]	2604463	1			T1	123		T4	1		T5	171
all_pins[2]	values[0x1]	314	1			T14	3		T16	3		T17	3
all_pins[2]	transitions[0x0=>0x1]	266	1			T14	3		T16	2		T17	2
all_pins[2]	transitions[0x1=>0x0]	115	1			T14	1		T16	2		T17	2
all_pins[3]	values[0x0]	2604614	1			T1	123		T4	1		T5	171
all_pins[3]	values[0x1]	163	1			T14	1		T16	3		T17	3
all_pins[3]	transitions[0x0=>0x1]	119	1			T14	1		T16	3		T17	2
all_pins[3]	transitions[0x1=>0x0]	105	1			T14	5		T16	1		T17	3
all_pins[4]	values[0x0]	2604628	1			T1	123		T4	1		T5	171
all_pins[4]	values[0x1]	149	1			T14	5		T16	1		T17	4
all_pins[4]	transitions[0x0=>0x1]	117	1			T14	2		T16	1		T17	3
all_pins[4]	transitions[0x1=>0x0]	3172	1			T14	545		T16	4		T17	4
all_pins[5]	values[0x0]	2601573	1			T1	123		T4	1		T5	171
all_pins[5]	values[0x1]	3204	1			T14	548		T16	4		T17	5
all_pins[5]	transitions[0x0=>0x1]	2013	1			T14	548		T16	4		T17	4
all_pins[5]	transitions[0x1=>0x0]	151528	1			T17	4		T18	2		T19	5
all_pins[6]	values[0x0]	2452058	1			T1	123		T4	1		T5	171
all_pins[6]	values[0x1]	152719	1			T17	5		T18	2		T19	5
all_pins[6]	transitions[0x0=>0x1]	152675	1			T17	3		T18	2		T19	5
all_pins[6]	transitions[0x1=>0x0]	95	1			T16	4		T17	2		T19	2
all_pins[7]	values[0x0]	2604638	1			T1	123		T4	1		T5	171
all_pins[7]	values[0x1]	139	1			T16	4		T17	4		T19	2
all_pins[7]	transitions[0x0=>0x1]	108	1			T16	4		T17	3		T19	1
all_pins[7]	transitions[0x1=>0x0]	1105	1			T14	326		T17	6		T18	1