Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18844

1

T1

120

T6

96

T7

20

auto[1]

13257

1

T1

128

T6

76

T11

197

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4135	1			T6	20		T16	60		T30	20
values[1]	4188	1			T1	38		T11	84		T13	79
values[2]	3723	1			T6	40		T11	125		T13	68
values[3]	3720	1			T1	20		T6	20		T76	14
values[4]	4624	1			T6	20		T11	35		T12	18
values[5]	3484	1			T1	20		T6	39		T7	20
values[6]	4127	1			T1	104		T11	71		T13	20
values[7]	4100	1			T1	66		T6	33		T8	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4373	1			T11	35		T13	27		T16	92
values[1]	3270	1			T1	58		T6	39		T11	71
values[2]	3943	1			T6	20		T13	29		T16	28
values[3]	4079	1			T1	66		T11	20		T13	20
values[4]	4167	1			T6	40		T11	215		T13	40
values[5]	3671	1			T1	20		T6	20		T8	12
values[6]	4171	1			T6	53		T11	91		T13	175
values[7]	4427	1			T1	104		T7	20		T11	64

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	202	1			T16	18		T30	6		T36	10
auto[0]	values[0]	values[1]	267	1			T119	13		T120	13		T126	16
auto[0]	values[0]	values[2]	376	1			T6	8		T16	8		T37	36
auto[0]	values[0]	values[3]	218	1			T36	11		T21	9		T188	9
auto[0]	values[0]	values[4]	320	1			T19	12		T64	14		T188	15
auto[0]	values[0]	values[5]	284	1			T130	21		T193	6		T183	9
auto[0]	values[0]	values[6]	455	1			T19	11		T36	11		T21	10
auto[0]	values[0]	values[7]	305	1			T190	4		T197	12		T129	4
auto[0]	values[1]	values[0]	668	1			T181	16		T201	209		T130	21
auto[0]	values[1]	values[1]	206	1			T1	32		T36	10		T195	10
auto[0]	values[1]	values[2]	219	1			T36	86		T208	2		T173	6
auto[0]	values[1]	values[3]	295	1			T11	9		T30	10		T28	9
auto[0]	values[1]	values[4]	345	1			T16	12		T64	15		T209	2
auto[0]	values[1]	values[5]	316	1			T210	10		T132	8		T51	11
auto[0]	values[1]	values[6]	209	1			T13	11		T34	21		T175	28
auto[0]	values[1]	values[7]	596	1			T11	60		T175	58		T153	67
auto[0]	values[2]	values[0]	245	1			T16	13		T100	4		T175	14
auto[0]	values[2]	values[1]	189	1			T13	7		T37	34		T211	14
auto[0]	values[2]	values[2]	286	1			T19	28		T36	12		T21	14
auto[0]	values[2]	values[3]	303	1			T64	14		T197	9		T212	18
auto[0]	values[2]	values[4]	515	1			T6	25		T11	114		T19	14
auto[0]	values[2]	values[5]	183	1			T80	10		T173	9		T213	13
auto[0]	values[2]	values[6]	284	1			T13	33		T19	6		T21	25
auto[0]	values[2]	values[7]	212	1			T21	14		T182	12		T214	9
auto[0]	values[3]	values[0]	180	1			T37	9		T188	11		T129	17
auto[0]	values[3]	values[1]	269	1			T1	14		T153	15		T131	16
auto[0]	values[3]	values[2]	183	1			T181	13		T197	11		T28	28
auto[0]	values[3]	values[3]	379	1			T86	20		T36	6		T21	26
auto[0]	values[3]	values[4]	199	1			T30	12		T36	7		T21	8
auto[0]	values[3]	values[5]	283	1			T6	13		T76	14		T37	11
auto[0]	values[3]	values[6]	423	1			T181	14		T129	13		T175	15
auto[0]	values[3]	values[7]	229	1			T21	4		T197	11		T215	4
auto[0]	values[4]	values[0]	427	1			T11	11		T16	13		T21	10
auto[0]	values[4]	values[1]	226	1			T12	18		T13	22		T30	22
auto[0]	values[4]	values[2]	346	1			T34	49		T21	14		T129	10
auto[0]	values[4]	values[3]	380	1			T30	26		T21	11		T181	15
auto[0]	values[4]	values[4]	239	1			T121	16		T153	10		T216	4
auto[0]	values[4]	values[5]	261	1			T13	11		T19	9		T36	31
auto[0]	values[4]	values[6]	260	1			T6	14		T13	45		T37	11
auto[0]	values[4]	values[7]	353	1			T36	12		T21	7		T197	11
auto[0]	values[5]	values[0]	186	1			T13	10		T21	11		T181	10
auto[0]	values[5]	values[1]	281	1			T6	9		T13	11		T30	5
auto[0]	values[5]	values[2]	185	1			T13	15		T79	16		T37	11
auto[0]	values[5]	values[3]	172	1			T16	16		T64	10		T153	16
auto[0]	values[5]	values[4]	264	1			T11	81		T13	14		T19	8
auto[0]	values[5]	values[5]	415	1			T1	7		T119	38		T153	17
auto[0]	values[5]	values[6]	236	1			T37	11		T64	23		T39	10
auto[0]	values[5]	values[7]	283	1			T7	20		T19	17		T21	13
auto[0]	values[6]	values[0]	316	1			T197	19		T153	83		T217	11
auto[0]	values[6]	values[1]	195	1			T11	11		T78	20		T181	8
auto[0]	values[6]	values[2]	315	1			T30	9		T180	13		T119	8
auto[0]	values[6]	values[3]	151	1			T13	7		T119	11		T197	11
auto[0]	values[6]	values[4]	232	1			T30	7		T188	4		T218	6
auto[0]	values[6]	values[5]	166	1			T21	12		T120	9		T219	20
auto[0]	values[6]	values[6]	598	1			T15	16		T37	8		T197	10
auto[0]	values[6]	values[7]	371	1			T1	10		T30	9		T19	6
auto[0]	values[7]	values[0]	318	1			T16	12		T30	9		T21	9
auto[0]	values[7]	values[1]	209	1			T19	10		T188	14		T132	18
auto[0]	values[7]	values[2]	168	1			T19	8		T64	23		T188	15
auto[0]	values[7]	values[3]	452	1			T1	57		T36	6		T21	22
auto[0]	values[7]	values[4]	255	1			T13	11		T30	11		T21	9
auto[0]	values[7]	values[5]	264	1			T8	12		T30	8		T180	53
auto[0]	values[7]	values[6]	374	1			T6	27		T11	13		T181	13
auto[0]	values[7]	values[7]	303	1			T36	27		T21	27		T181	11
auto[1]	values[0]	values[0]	195	1			T16	14		T30	14		T36	45
auto[1]	values[0]	values[1]	163	1			T119	36		T120	7		T129	5
auto[1]	values[0]	values[2]	238	1			T6	12		T16	20		T37	12
auto[1]	values[0]	values[3]	111	1			T36	9		T21	12		T188	11
auto[1]	values[0]	values[4]	260	1			T19	8		T64	6		T188	5
auto[1]	values[0]	values[5]	159	1			T130	4		T183	11		T39	8
auto[1]	values[0]	values[6]	220	1			T19	9		T36	9		T21	10
auto[1]	values[0]	values[7]	362	1			T197	12		T129	16		T182	10
auto[1]	values[1]	values[0]	163	1			T181	5		T130	26		T182	5
auto[1]	values[1]	values[1]	71	1			T1	6		T36	10		T29	7
auto[1]	values[1]	values[2]	258	1			T36	12		T173	14		T220	7
auto[1]	values[1]	values[3]	190	1			T11	11		T30	10		T28	11
auto[1]	values[1]	values[4]	114	1			T16	10		T64	16		T49	6
auto[1]	values[1]	values[5]	233	1			T132	27		T51	9		T186	11
auto[1]	values[1]	values[6]	164	1			T13	68		T34	7		T175	9
auto[1]	values[1]	values[7]	141	1			T11	4		T175	7		T153	6
auto[1]	values[2]	values[0]	228	1			T16	7		T101	20		T175	6
auto[1]	values[2]	values[1]	160	1			T13	16		T37	19		T188	8
auto[1]	values[2]	values[2]	245	1			T19	9		T36	15		T21	13
auto[1]	values[2]	values[3]	362	1			T64	12		T177	2		T197	19
auto[1]	values[2]	values[4]	163	1			T6	15		T11	11		T19	6
auto[1]	values[2]	values[5]	117	1			T173	11		T213	11		T221	12
auto[1]	values[2]	values[6]	119	1			T13	12		T19	14		T21	9
auto[1]	values[2]	values[7]	112	1			T21	6		T182	8		T214	13
auto[1]	values[3]	values[0]	194	1			T37	11		T188	12		T129	3
auto[1]	values[3]	values[1]	250	1			T1	6		T222	12		T153	41
auto[1]	values[3]	values[2]	164	1			T181	10		T197	9		T28	16
auto[1]	values[3]	values[3]	229	1			T36	14		T21	18		T64	7
auto[1]	values[3]	values[4]	233	1			T30	8		T36	13		T21	12
auto[1]	values[3]	values[5]	170	1			T6	7		T37	31		T129	5
auto[1]	values[3]	values[6]	129	1			T181	7		T129	7		T175	5
auto[1]	values[3]	values[7]	206	1			T21	22		T197	10		T182	10
auto[1]	values[4]	values[0]	439	1			T11	24		T16	7		T21	74
auto[1]	values[4]	values[1]	127	1			T13	30		T30	18		T19	14
auto[1]	values[4]	values[2]	242	1			T34	10		T21	11		T129	11
auto[1]	values[4]	values[3]	272	1			T30	14		T21	21		T181	7
auto[1]	values[4]	values[4]	358	1			T153	10		T131	31		T132	98
auto[1]	values[4]	values[5]	220	1			T13	9		T19	11		T36	13
auto[1]	values[4]	values[6]	160	1			T6	6		T13	6		T37	19
auto[1]	values[4]	values[7]	314	1			T36	14		T21	13		T197	9
auto[1]	values[5]	values[0]	181	1			T13	17		T21	16		T181	10
auto[1]	values[5]	values[1]	272	1			T6	30		T13	10		T30	15
auto[1]	values[5]	values[2]	117	1			T13	14		T37	9		T197	10
auto[1]	values[5]	values[3]	187	1			T16	10		T64	10		T153	4
auto[1]	values[5]	values[4]	222	1			T11	9		T13	6		T19	12
auto[1]	values[5]	values[5]	242	1			T1	13		T35	18		T223	12
auto[1]	values[5]	values[6]	99	1			T37	25		T64	14		T39	10
auto[1]	values[5]	values[7]	142	1			T19	3		T21	8		T120	14
auto[1]	values[6]	values[0]	224	1			T197	6		T153	13		T217	9
auto[1]	values[6]	values[1]	215	1			T11	60		T181	14		T129	14
auto[1]	values[6]	values[2]	375	1			T30	11		T180	8		T119	12
auto[1]	values[6]	values[3]	126	1			T13	13		T119	9		T197	11
auto[1]	values[6]	values[4]	171	1			T30	13		T188	23		T49	19
auto[1]	values[6]	values[5]	125	1			T21	19		T120	21		T49	11
auto[1]	values[6]	values[6]	177	1			T37	12		T197	11		T129	17
auto[1]	values[6]	values[7]	370	1			T1	94		T30	11		T19	18
auto[1]	values[7]	values[0]	207	1			T16	8		T30	11		T202	16
auto[1]	values[7]	values[1]	170	1			T19	31		T188	6		T132	2
auto[1]	values[7]	values[2]	226	1			T19	15		T64	6		T188	7
auto[1]	values[7]	values[3]	252	1			T1	9		T36	16		T21	26
auto[1]	values[7]	values[4]	277	1			T13	9		T30	9		T21	11
auto[1]	values[7]	values[5]	233	1			T30	12		T180	6		T182	9
auto[1]	values[7]	values[6]	264	1			T6	6		T11	78		T181	7
auto[1]	values[7]	values[7]	128	1			T36	9		T21	13		T181	9