Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	475	1			T1	1		T6	4		T11	1
auto[ReadAddrCrossIntoMailbox]	329	1			T6	3		T13	6		T16	1
auto[ReadAddrCrossOutOfMailbox]	348	1			T6	5		T13	5		T16	2
auto[ReadAddrCrossAllMailbox]	214	1			T13	5		T30	1		T36	2
auto[ReadAddrOutsideMailbox]	3559	1			T1	19		T6	19		T8	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2454

1

T1

10

T6

14

T8

3

auto[1]

2471

1

T1

10

T6

17

T8

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	865	1			T1	6		T6	2		T11	7
read_ops[0x0b]	822	1			T1	4		T6	3		T11	3
read_ops[0x3b]	802	1			T1	4		T6	6		T11	8
read_ops[0x6b]	792	1			T1	4		T6	4		T8	4
read_ops[0xbb]	864	1			T1	1		T6	7		T8	2
read_ops[0xeb]	780	1			T1	1		T6	9		T11	12

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T16	1		T36	1		T37	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T11	1		T13	1		T36	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T19	1		T37	1		T195	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T64	3		T129	1		T175	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T13	1		T36	1		T197	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T21	2		T129	1		T195	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T36	1		T37	2		T21	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T13	1		T216	1		T178	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	322	1			T1	4		T6	1		T11	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	324	1			T1	2		T6	1		T11	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T6	1		T13	1		T34	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T13	2		T64	1		T175	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T21	1		T130	1		T153	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T16	1		T30	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T13	1		T30	1		T64	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T36	2		T37	2		T129	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T37	1		T197	1		T49	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T36	1		T64	1		T175	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T1	3		T6	1		T11	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	295	1			T1	1		T6	1		T11	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T13	1		T16	1		T19	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T19	1		T36	1		T37	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T13	2		T129	1		T224	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T21	2		T180	1		T224	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T13	1		T19	1		T37	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T6	2		T13	1		T36	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T37	1		T21	1		T197	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T129	1		T173	1		T183	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	286	1			T1	2		T6	1		T11	5
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T1	2		T6	3		T11	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T21	1		T203	2		T153	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T6	1		T13	1		T19	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T36	1		T180	1		T120	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T13	2		T19	1		T130	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T36	1		T119	1		T197	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T19	1		T130	1		T225	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T13	1		T37	1		T119	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T28	1		T131	2		T132	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	279	1			T6	2		T8	2		T11	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T1	4		T6	1		T8	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T1	1		T6	1		T37	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T30	1		T36	3		T64	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	37	1			T6	1		T36	2		T21	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T6	1		T21	2		T51	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T13	1		T21	1		T197	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T6	1		T16	1		T19	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T13	1		T30	1		T152	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T37	1		T130	1		T131	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	309	1			T8	1		T11	2		T13	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T6	3		T8	1		T11	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T6	1		T13	3		T36	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T19	1		T36	1		T37	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T6	1		T13	2		T21	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T36	1		T21	1		T119	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T6	2		T64	2		T197	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T16	1		T36	1		T37	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T13	2		T21	1		T153	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T37	1		T64	1		T129	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	274	1			T6	2		T11	2		T13	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	277	1			T1	1		T6	3		T11	10