Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3851	1			T6	59		T11	126		T13	55
values[1]	3641	1			T7	20		T11	20		T13	108
values[2]	3782	1			T13	85		T19	23		T36	44
values[3]	4164	1			T8	12		T11	125		T12	18
values[4]	3721	1			T1	58		T6	20		T11	135
values[5]	4111	1			T1	20		T6	40		T13	51
values[6]	4510	1			T1	66		T6	20		T13	20
values[7]	4321	1			T1	104		T6	33		T11	90

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3946	1			T1	20		T6	59		T13	49
values[1]	3815	1			T1	20		T13	23		T16	52
values[2]	3827	1			T6	20		T8	12		T11	125
values[3]	3758	1			T1	66		T6	53		T11	71
values[4]	4256	1			T1	38		T13	41		T15	16
values[5]	4374	1			T1	104		T6	20		T11	174
values[6]	4117	1			T6	20		T7	20		T11	91
values[7]	4008	1			T11	35		T16	26		T19	40

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31315

1

T1

243

T6

170

T7

20

auto[1]

786

1

T1

5

T6

2

T11

9

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	514	1			T6	39		T21	25		T64	20
auto[0]	values[0]	values[1]	607	1			T13	23		T16	29		T79	16
auto[0]	values[0]	values[2]	370	1			T13	31		T175	77		T28	20
auto[0]	values[0]	values[3]	302	1			T6	18		T37	20		T226	4
auto[0]	values[0]	values[4]	410	1			T21	43		T210	10		T175	59
auto[0]	values[0]	values[5]	334	1			T36	24		T119	35		T129	69
auto[0]	values[0]	values[6]	543	1			T11	88		T21	20		T181	20
auto[0]	values[0]	values[7]	673	1			T11	33		T180	20		T188	22
auto[0]	values[1]	values[0]	597	1			T13	26		T16	21		T36	19
auto[0]	values[1]	values[1]	393	1			T36	53		T37	37		T129	27
auto[0]	values[1]	values[2]	466	1			T13	78		T180	20		T153	26
auto[0]	values[1]	values[3]	349	1			T21	20		T180	19		T64	31
auto[0]	values[1]	values[4]	417	1			T181	21		T64	23		T188	19
auto[0]	values[1]	values[5]	572	1			T11	20		T16	19		T64	63
auto[0]	values[1]	values[6]	443	1			T7	20		T30	19		T227	6
auto[0]	values[1]	values[7]	289	1			T36	19		T228	20		T53	14
auto[0]	values[2]	values[0]	355	1			T129	20		T193	6		T131	21
auto[0]	values[2]	values[1]	370	1			T36	44		T229	2		T182	36
auto[0]	values[2]	values[2]	443	1			T37	31		T190	4		T132	19
auto[0]	values[2]	values[3]	383	1			T13	65		T19	23		T37	42
auto[0]	values[2]	values[4]	432	1			T13	20		T119	18		T212	18
auto[0]	values[2]	values[5]	689	1			T132	106		T204	20		T176	98
auto[0]	values[2]	values[6]	545	1			T21	40		T197	21		T28	19
auto[0]	values[2]	values[7]	460	1			T21	31		T181	20		T230	50
auto[0]	values[3]	values[0]	597	1			T101	20		T21	21		T188	20
auto[0]	values[3]	values[1]	349	1			T78	20		T30	20		T222	12
auto[0]	values[3]	values[2]	450	1			T8	12		T11	125		T12	18
auto[0]	values[3]	values[3]	536	1			T30	18		T21	84		T231	6
auto[0]	values[3]	values[4]	674	1			T30	17		T21	41		T232	2
auto[0]	values[3]	values[5]	366	1			T76	14		T129	24		T182	37
auto[0]	values[3]	values[6]	520	1			T16	28		T36	20		T120	20
auto[0]	values[3]	values[7]	573	1			T21	20		T129	20		T130	19
auto[0]	values[4]	values[0]	398	1			T1	20		T19	20		T21	31
auto[0]	values[4]	values[1]	436	1			T16	20		T129	20		T153	20
auto[0]	values[4]	values[2]	585	1			T36	76		T37	20		T188	27
auto[0]	values[4]	values[3]	355	1			T11	68		T30	20		T21	25
auto[0]	values[4]	values[4]	374	1			T1	37		T30	20		T211	14
auto[0]	values[4]	values[5]	588	1			T11	63		T19	20		T21	33
auto[0]	values[4]	values[6]	335	1			T6	20		T19	37		T153	20
auto[0]	values[4]	values[7]	562	1			T28	24		T153	94		T132	71
auto[0]	values[5]	values[0]	409	1			T30	19		T19	19		T21	20
auto[0]	values[5]	values[1]	704	1			T1	20		T30	20		T194	16
auto[0]	values[5]	values[2]	281	1			T6	20		T30	18		T64	20
auto[0]	values[5]	values[3]	386	1			T86	20		T182	19		T173	43
auto[0]	values[5]	values[4]	620	1			T35	14		T185	73		T233	12
auto[0]	values[5]	values[5]	560	1			T6	20		T13	50		T19	20
auto[0]	values[5]	values[6]	722	1			T37	37		T21	28		T64	37
auto[0]	values[5]	values[7]	326	1			T180	59		T153	21		T234	4
auto[0]	values[6]	values[0]	468	1			T6	20		T13	20		T16	20
auto[0]	values[6]	values[1]	460	1			T100	4		T80	10		T119	20
auto[0]	values[6]	values[2]	666	1			T181	42		T201	209		T197	20
auto[0]	values[6]	values[3]	779	1			T1	64		T30	16		T19	20
auto[0]	values[6]	values[4]	720	1			T30	20		T36	20		T37	29
auto[0]	values[6]	values[5]	313	1			T21	20		T197	22		T175	64
auto[0]	values[6]	values[6]	409	1			T21	20		T197	19		T175	20
auto[0]	values[6]	values[7]	604	1			T19	20		T49	65		T235	41
auto[0]	values[7]	values[0]	526	1			T37	48		T64	51		T182	40
auto[0]	values[7]	values[1]	414	1			T34	58		T19	18		T153	55
auto[0]	values[7]	values[2]	481	1			T13	47		T36	22		T21	32
auto[0]	values[7]	values[3]	579	1			T6	33		T37	36		T21	19
auto[0]	values[7]	values[4]	478	1			T13	21		T15	16		T30	18
auto[0]	values[7]	values[5]	844	1			T1	102		T11	90		T13	20
auto[0]	values[7]	values[6]	483	1			T19	23		T37	20		T236	14
auto[0]	values[7]	values[7]	429	1			T16	25		T19	20		T119	48
auto[1]	values[0]	values[0]	6	1			T21	2		T237	2		T238	2
auto[1]	values[0]	values[1]	14	1			T16	3		T21	2		T64	1
auto[1]	values[0]	values[2]	4	1			T13	1		T28	1		T239	2
auto[1]	values[0]	values[3]	19	1			T6	2		T42	2		T43	4
auto[1]	values[0]	values[4]	12	1			T21	2		T187	1		T240	1
auto[1]	values[0]	values[5]	18	1			T36	2		T129	4		T51	3
auto[1]	values[0]	values[6]	14	1			T11	3		T129	3		T241	1
auto[1]	values[0]	values[7]	11	1			T11	2		T188	1		T221	2
auto[1]	values[1]	values[0]	21	1			T13	3		T16	1		T36	1
auto[1]	values[1]	values[1]	12	1			T36	2		T129	1		T242	3
auto[1]	values[1]	values[2]	18	1			T13	1		T180	1		T173	3
auto[1]	values[1]	values[3]	7	1			T180	2		T240	2		T243	2
auto[1]	values[1]	values[4]	12	1			T64	2		T188	1		T131	3
auto[1]	values[1]	values[5]	19	1			T16	1		T64	5		T51	1
auto[1]	values[1]	values[6]	19	1			T30	1		T188	3		T120	2
auto[1]	values[1]	values[7]	7	1			T36	1		T187	1		T196	1
auto[1]	values[2]	values[0]	9	1			T217	3		T134	2		T244	4
auto[1]	values[2]	values[1]	12	1			T182	3		T187	2		T179	1
auto[1]	values[2]	values[2]	18	1			T37	2		T132	1		T41	5
auto[1]	values[2]	values[3]	2	1			T21	2		-	-		-	-
auto[1]	values[2]	values[4]	18	1			T119	2		T182	1		T176	1
auto[1]	values[2]	values[5]	11	1			T240	2		T41	1		T245	1
auto[1]	values[2]	values[6]	18	1			T28	1		T51	2		T189	4
auto[1]	values[2]	values[7]	17	1			T21	2		T235	5		T40	1
auto[1]	values[3]	values[0]	9	1			T197	1		T129	1		T175	1
auto[1]	values[3]	values[1]	4	1			T246	2		T247	1		T248	1
auto[1]	values[3]	values[2]	7	1			T182	2		T240	2		T43	2
auto[1]	values[3]	values[3]	14	1			T30	2		T155	2		T249	5
auto[1]	values[3]	values[4]	22	1			T30	3		T21	3		T40	1
auto[1]	values[3]	values[5]	10	1			T129	1		T182	1		T196	1
auto[1]	values[3]	values[6]	15	1			T242	3		T47	6		T49	1
auto[1]	values[3]	values[7]	18	1			T21	1		T130	1		T29	4
auto[1]	values[4]	values[0]	8	1			T228	1		T42	1		T243	2
auto[1]	values[4]	values[1]	8	1			T173	1		T204	1		T220	3
auto[1]	values[4]	values[2]	6	1			T36	2		T182	2		T45	1
auto[1]	values[4]	values[3]	9	1			T11	3		T21	1		T64	1
auto[1]	values[4]	values[4]	11	1			T1	1		T250	1		T251	2
auto[1]	values[4]	values[5]	16	1			T11	1		T21	1		T153	2
auto[1]	values[4]	values[6]	14	1			T183	4		T131	1		T214	3
auto[1]	values[4]	values[7]	16	1			T153	2		T132	2		T155	4
auto[1]	values[5]	values[0]	5	1			T30	1		T19	1		T252	2
auto[1]	values[5]	values[1]	16	1			T28	1		T132	1		T214	2
auto[1]	values[5]	values[2]	8	1			T30	2		T253	1		T254	3
auto[1]	values[5]	values[3]	8	1			T182	1		T173	2		T132	1
auto[1]	values[5]	values[4]	26	1			T35	4		T220	5		T255	1
auto[1]	values[5]	values[5]	19	1			T13	1		T36	1		T180	6
auto[1]	values[5]	values[6]	17	1			T37	3		T188	1		T235	3
auto[1]	values[5]	values[7]	4	1			T252	2		T249	2		-	-
auto[1]	values[6]	values[0]	10	1			T40	1		T240	3		T256	2
auto[1]	values[6]	values[1]	5	1			T182	1		T253	1		T251	1
auto[1]	values[6]	values[2]	15	1			T181	1		T182	3		T155	2
auto[1]	values[6]	values[3]	23	1			T1	2		T30	4		T181	1
auto[1]	values[6]	values[4]	14	1			T37	1		T182	1		T173	1
auto[1]	values[6]	values[5]	3	1			T175	1		T256	2		-	-
auto[1]	values[6]	values[6]	8	1			T197	1		T182	2		T131	2
auto[1]	values[6]	values[7]	13	1			T179	1		T240	1		T257	2
auto[1]	values[7]	values[0]	14	1			T64	1		T241	1		T196	4
auto[1]	values[7]	values[1]	11	1			T34	1		T19	2		T153	1
auto[1]	values[7]	values[2]	9	1			T188	3		T39	1		T257	1
auto[1]	values[7]	values[3]	7	1			T21	1		T130	1		T153	3
auto[1]	values[7]	values[4]	16	1			T30	2		T34	2		T64	1
auto[1]	values[7]	values[5]	12	1			T1	2		T19	1		T175	2
auto[1]	values[7]	values[6]	12	1			T19	1		T236	2		T247	3
auto[1]	values[7]	values[7]	6	1			T16	1		T119	1		T255	2