| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 8 | 0 | 8 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_flip_position | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
| cp_opcode | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 74 | 1 | T31 | 2 | T143 | 3 | T144 | 2 | ||||
| auto[1] | 23 | 1 | T143 | 1 | T258 | 1 | T259 | 1 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 6 | 0 | 6 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| read_ops[0x03] | 14 | 1 | T260 | 1 | T261 | 2 | T262 | 1 | ||||
| read_ops[0x0b] | 6 | 1 | T263 | 2 | T264 | 4 | - | - | ||||
| read_ops[0x3b] | 25 | 1 | T31 | 2 | T143 | 2 | T258 | 4 | ||||
| read_ops[0x6b] | 7 | 1 | T144 | 2 | T259 | 1 | T265 | 2 | ||||
| read_ops[0xbb] | 29 | 1 | T143 | 2 | T266 | 1 | T267 | 1 | ||||
| read_ops[0xeb] | 16 | 1 | T259 | 2 | T268 | 4 | T265 | 2 | 
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |