Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	736	1			T14	10		T16	14		T17	21
all_values[1]	736	1			T14	10		T16	14		T17	21
all_values[2]	736	1			T14	10		T16	14		T17	21
all_values[3]	736	1			T14	10		T16	14		T17	21
all_values[4]	736	1			T14	10		T16	14		T17	21
all_values[5]	736	1			T14	10		T16	14		T17	21
all_values[6]	736	1			T14	10		T16	14		T17	21
all_values[7]	736	1			T14	10		T16	14		T17	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3120

1

T14

33

T16

71

T17

88

auto[1]

2768

1

T14

47

T16

41

T17

80

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2398

1

T14

28

T16

49

T17

79

auto[1]

3490

1

T14

52

T16

63

T17

89

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3409

1

T14

39

T16

65

T17

98

auto[1]

2479

1

T14

41

T16

47

T17

70

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	148	1			T16	5		T17	4		T18	2
all_values[0]	auto[0]	auto[0]	auto[1]	82	1			T16	1		T17	1		T18	2
all_values[0]	auto[0]	auto[1]	auto[0]	115	1			T14	1		T16	2		T17	4
all_values[0]	auto[0]	auto[1]	auto[1]	80	1			T14	3		T16	1		T17	2
all_values[0]	auto[1]	auto[0]	auto[1]	170	1			T14	3		T16	4		T17	4
all_values[0]	auto[1]	auto[1]	auto[1]	141	1			T14	3		T16	1		T17	6
all_values[1]	auto[0]	auto[0]	auto[0]	171	1			T14	1		T16	4		T17	8
all_values[1]	auto[0]	auto[0]	auto[1]	61	1			T16	1		T17	1		T19	3
all_values[1]	auto[0]	auto[1]	auto[0]	127	1			T14	1		T16	5		T17	3
all_values[1]	auto[0]	auto[1]	auto[1]	77	1			T14	2		T16	1		T17	2
all_values[1]	auto[1]	auto[0]	auto[1]	161	1			T14	2		T16	3		T17	3
all_values[1]	auto[1]	auto[1]	auto[1]	139	1			T14	4		T17	4		T18	2
all_values[2]	auto[0]	auto[0]	auto[0]	157	1			T14	4		T16	3		T17	7
all_values[2]	auto[0]	auto[0]	auto[1]	68	1			T16	2		T19	3		T130	1
all_values[2]	auto[0]	auto[1]	auto[0]	115	1			T14	1		T16	2		T17	4
all_values[2]	auto[0]	auto[1]	auto[1]	70	1			T17	2		T18	1		T19	1
all_values[2]	auto[1]	auto[0]	auto[1]	166	1			T16	4		T17	1		T19	4
all_values[2]	auto[1]	auto[1]	auto[1]	160	1			T14	5		T16	3		T17	7
all_values[3]	auto[0]	auto[0]	auto[0]	139	1			T14	2		T16	1		T17	8
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T14	1		T16	2		T17	2
all_values[3]	auto[0]	auto[1]	auto[0]	139	1			T14	2		T17	3		T18	3
all_values[3]	auto[0]	auto[1]	auto[1]	70	1			T16	2		T19	3		T21	1
all_values[3]	auto[1]	auto[0]	auto[1]	157	1			T14	1		T16	8		T17	3
all_values[3]	auto[1]	auto[1]	auto[1]	150	1			T14	4		T16	1		T17	5
all_values[4]	auto[0]	auto[0]	auto[0]	167	1			T14	2		T16	4		T17	3
all_values[4]	auto[0]	auto[0]	auto[1]	73	1			T14	1		T17	2		T19	1
all_values[4]	auto[0]	auto[1]	auto[0]	125	1			T16	4		T17	5		T19	1
all_values[4]	auto[0]	auto[1]	auto[1]	68	1			T14	2		T17	2		T18	1
all_values[4]	auto[1]	auto[0]	auto[1]	164	1			T14	1		T16	3		T17	5
all_values[4]	auto[1]	auto[1]	auto[1]	139	1			T14	4		T16	3		T17	4
all_values[5]	auto[0]	auto[0]	auto[0]	193	1			T14	3		T16	3		T17	7
all_values[5]	auto[0]	auto[1]	auto[0]	209	1			T14	1		T16	2		T17	4
all_values[5]	auto[1]	auto[0]	auto[1]	177	1			T14	1		T16	6		T17	8
all_values[5]	auto[1]	auto[1]	auto[1]	157	1			T14	5		T16	3		T17	2
all_values[6]	auto[0]	auto[0]	auto[0]	143	1			T14	1		T16	6		T17	8
all_values[6]	auto[0]	auto[0]	auto[1]	69	1			T14	2		T18	2		T19	1
all_values[6]	auto[0]	auto[1]	auto[0]	142	1			T14	4		T16	5		T17	5
all_values[6]	auto[0]	auto[1]	auto[1]	76	1			T17	3		T19	2		T21	1
all_values[6]	auto[1]	auto[0]	auto[1]	156	1			T14	1		T16	2		T17	1
all_values[6]	auto[1]	auto[1]	auto[1]	150	1			T14	2		T16	1		T17	4
all_values[7]	auto[0]	auto[0]	auto[0]	172	1			T14	4		T16	1		T17	3
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T16	4		T17	1		T18	2
all_values[7]	auto[0]	auto[1]	auto[0]	136	1			T14	1		T16	2		T17	3
all_values[7]	auto[0]	auto[1]	auto[1]	58	1			T16	2		T17	1		T19	1
all_values[7]	auto[1]	auto[0]	auto[1]	167	1			T14	3		T16	4		T17	8
all_values[7]	auto[1]	auto[1]	auto[1]	125	1			T14	2		T16	1		T17	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal