Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1868

1

T4

7

T6

8

T13

4

auto[1]

1911

1

T4

3

T6

15

T13

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2180

1

T6

23

T13

6

T14

19

auto[1]

1599

1

T4

10

T13

2

T14

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2957

1

T4

10

T6

14

T13

5

auto[1]

822

1

T6

9

T13

3

T14

7

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	735	1			T6	3		T13	3		T14	3
valid[1]	748	1			T4	3		T6	5		T13	2
valid[2]	757	1			T6	6		T13	2		T14	2
valid[3]	774	1			T4	6		T6	6		T13	1
valid[4]	765	1			T4	1		T6	3		T14	7

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	139	1			T6	1		T13	1		T25	1
auto[0]	auto[0]	valid[0]	auto[1]	156	1			T26	2		T71	1		T276	4
auto[0]	auto[0]	valid[1]	auto[0]	139	1			T6	1		T13	1		T14	2
auto[0]	auto[0]	valid[1]	auto[1]	145	1			T4	2		T26	1		T276	3
auto[0]	auto[0]	valid[2]	auto[0]	130	1			T13	1		T16	3		T26	3
auto[0]	auto[0]	valid[2]	auto[1]	155	1			T16	1		T71	1		T277	1
auto[0]	auto[0]	valid[3]	auto[0]	147	1			T6	1		T26	2		T19	2
auto[0]	auto[0]	valid[3]	auto[1]	163	1			T4	4		T71	2		T21	1
auto[0]	auto[0]	valid[4]	auto[0]	117	1			T6	1		T14	1		T16	2
auto[0]	auto[0]	valid[4]	auto[1]	183	1			T4	1		T16	1		T26	1
auto[0]	auto[1]	valid[0]	auto[0]	117	1			T6	1		T14	3		T26	2
auto[0]	auto[1]	valid[0]	auto[1]	154	1			T13	1		T16	1		T71	2
auto[0]	auto[1]	valid[1]	auto[0]	120	1			T6	2		T14	1		T16	2
auto[0]	auto[1]	valid[1]	auto[1]	172	1			T4	1		T13	1		T16	1
auto[0]	auto[1]	valid[2]	auto[0]	142	1			T6	4		T14	1		T24	1
auto[0]	auto[1]	valid[2]	auto[1]	161	1			T14	1		T26	2		T71	2
auto[0]	auto[1]	valid[3]	auto[0]	154	1			T6	2		T14	1		T25	1
auto[0]	auto[1]	valid[3]	auto[1]	168	1			T4	2		T26	2		T71	1
auto[0]	auto[1]	valid[4]	auto[0]	153	1			T6	1		T14	3		T25	2
auto[0]	auto[1]	valid[4]	auto[1]	142	1			T16	2		T26	1		T71	2
auto[1]	auto[0]	valid[0]	auto[0]	83	1			T6	1		T13	1		T16	1
auto[1]	auto[0]	valid[1]	auto[0]	86	1			T6	1		T16	1		T18	1
auto[1]	auto[0]	valid[2]	auto[0]	80	1			T16	1		T19	1		T21	1
auto[1]	auto[0]	valid[3]	auto[0]	68	1			T6	2		T14	1		T24	1
auto[1]	auto[0]	valid[4]	auto[0]	77	1			T14	1		T25	1		T16	1
auto[1]	auto[1]	valid[0]	auto[0]	86	1			T16	1		T18	1		T36	1
auto[1]	auto[1]	valid[1]	auto[0]	86	1			T6	1		T25	1		T16	3
auto[1]	auto[1]	valid[2]	auto[0]	89	1			T6	2		T13	1		T25	1
auto[1]	auto[1]	valid[3]	auto[0]	74	1			T6	1		T13	1		T14	3
auto[1]	auto[1]	valid[4]	auto[0]	93	1			T6	1		T14	2		T26	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal