Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53790

1

T6

430

T9

12

T10

12

auto[1]

16502

1

T4

10

T13

51

T14

43

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50778

1

T4

10

T6

295

T9

7

auto[1]

19514

1

T6

135

T9

5

T10

6

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	36265	1			T4	10		T6	206		T9	6
others[1]	5846	1			T6	33		T10	4		T13	29
others[2]	6019	1			T6	40		T9	4		T13	20
others[3]	6744	1			T6	43		T9	1		T13	13
interest[1]	3827	1			T6	23		T13	12		T14	26
interest[4]	23736	1			T4	10		T6	147		T9	3
interest[64]	11591	1			T6	85		T9	1		T10	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17674	1			T6	154		T9	3		T10	5
auto[0]	auto[0]	others[1]	2873	1			T6	22		T10	1		T13	14
auto[0]	auto[0]	others[2]	2894	1			T6	25		T9	3		T13	11
auto[0]	auto[0]	others[3]	3227	1			T6	25		T9	1		T13	4
auto[0]	auto[0]	interest[1]	1912	1			T6	16		T13	7		T14	14
auto[0]	auto[0]	interest[4]	11518	1			T6	105		T9	2		T10	4
auto[0]	auto[0]	interest[64]	5696	1			T6	53		T13	11		T14	60
auto[0]	auto[1]	others[0]	8627	1			T4	10		T13	29		T14	20
auto[0]	auto[1]	others[1]	1367	1			T13	4		T14	3		T24	1
auto[0]	auto[1]	others[2]	1370	1			T13	2		T14	3		T16	8
auto[0]	auto[1]	others[3]	1629	1			T13	3		T14	6		T24	1
auto[0]	auto[1]	interest[1]	872	1			T13	2		T14	3		T24	2
auto[0]	auto[1]	interest[4]	5775	1			T4	10		T13	22		T14	11
auto[0]	auto[1]	interest[64]	2637	1			T13	11		T14	8		T24	1
auto[1]	auto[0]	others[0]	9964	1			T6	52		T9	3		T10	2
auto[1]	auto[0]	others[1]	1606	1			T6	11		T10	3		T13	11
auto[1]	auto[0]	others[2]	1755	1			T6	15		T9	1		T13	7
auto[1]	auto[0]	others[3]	1888	1			T6	18		T13	6		T14	14
auto[1]	auto[0]	interest[1]	1043	1			T6	7		T13	3		T14	9
auto[1]	auto[0]	interest[4]	6443	1			T6	42		T9	1		T10	2
auto[1]	auto[0]	interest[64]	3258	1			T6	32		T9	1		T10	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal