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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
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T1032 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3527034045 Aug 12 06:23:12 PM PDT 24 Aug 12 06:23:12 PM PDT 24 20067071 ps
T1033 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1985654308 Aug 12 06:23:04 PM PDT 24 Aug 12 06:23:07 PM PDT 24 37678355 ps
T1034 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3576318090 Aug 12 06:23:40 PM PDT 24 Aug 12 06:23:41 PM PDT 24 14769256 ps
T1035 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1606390869 Aug 12 06:23:22 PM PDT 24 Aug 12 06:23:23 PM PDT 24 72858611 ps
T1036 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3422490761 Aug 12 06:23:11 PM PDT 24 Aug 12 06:23:12 PM PDT 24 40329801 ps
T158 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3490714743 Aug 12 06:23:14 PM PDT 24 Aug 12 06:23:28 PM PDT 24 554665323 ps
T88 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2286774770 Aug 12 06:23:03 PM PDT 24 Aug 12 06:23:08 PM PDT 24 76273525 ps
T1037 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1885406717 Aug 12 06:23:31 PM PDT 24 Aug 12 06:23:32 PM PDT 24 18569726 ps
T1038 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1377424609 Aug 12 06:23:12 PM PDT 24 Aug 12 06:23:13 PM PDT 24 53947824 ps
T111 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4283333735 Aug 12 06:23:27 PM PDT 24 Aug 12 06:23:29 PM PDT 24 40424001 ps
T112 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1756275988 Aug 12 06:23:02 PM PDT 24 Aug 12 06:23:04 PM PDT 24 75426478 ps
T1039 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3869006269 Aug 12 06:23:14 PM PDT 24 Aug 12 06:23:15 PM PDT 24 16443418 ps
T1040 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.319316163 Aug 12 06:23:08 PM PDT 24 Aug 12 06:23:12 PM PDT 24 71370710 ps
T1041 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2621131084 Aug 12 06:23:19 PM PDT 24 Aug 12 06:23:20 PM PDT 24 16999031 ps
T150 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2591447668 Aug 12 06:23:02 PM PDT 24 Aug 12 06:23:03 PM PDT 24 45804009 ps
T1042 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.874428661 Aug 12 06:22:56 PM PDT 24 Aug 12 06:22:57 PM PDT 24 22798060 ps
T89 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3089793087 Aug 12 06:23:16 PM PDT 24 Aug 12 06:23:21 PM PDT 24 356922105 ps
T159 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3546506476 Aug 12 06:22:57 PM PDT 24 Aug 12 06:23:10 PM PDT 24 405213783 ps
T87 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3437731962 Aug 12 06:23:14 PM PDT 24 Aug 12 06:23:16 PM PDT 24 165634790 ps
T162 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1960825253 Aug 12 06:23:06 PM PDT 24 Aug 12 06:23:22 PM PDT 24 1141858455 ps
T1043 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2004860719 Aug 12 06:23:13 PM PDT 24 Aug 12 06:23:17 PM PDT 24 154934559 ps
T1044 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3360337702 Aug 12 06:23:16 PM PDT 24 Aug 12 06:23:17 PM PDT 24 57487380 ps
T113 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2026156909 Aug 12 06:23:12 PM PDT 24 Aug 12 06:23:14 PM PDT 24 35594442 ps
T163 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1481292039 Aug 12 06:23:05 PM PDT 24 Aug 12 06:23:19 PM PDT 24 598352939 ps
T114 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4108094537 Aug 12 06:23:02 PM PDT 24 Aug 12 06:23:04 PM PDT 24 89024498 ps
T164 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2378605786 Aug 12 06:23:05 PM PDT 24 Aug 12 06:23:23 PM PDT 24 1004002295 ps
T1045 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1370469900 Aug 12 06:23:32 PM PDT 24 Aug 12 06:23:33 PM PDT 24 14113219 ps
T151 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2131663897 Aug 12 06:23:10 PM PDT 24 Aug 12 06:23:19 PM PDT 24 359820612 ps
T115 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3287665124 Aug 12 06:23:05 PM PDT 24 Aug 12 06:23:07 PM PDT 24 100008354 ps
T1046 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4277813769 Aug 12 06:23:11 PM PDT 24 Aug 12 06:23:12 PM PDT 24 29447872 ps
T1047 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.885190581 Aug 12 06:23:21 PM PDT 24 Aug 12 06:23:22 PM PDT 24 18151556 ps
T1048 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.173866877 Aug 12 06:22:57 PM PDT 24 Aug 12 06:23:12 PM PDT 24 1165917454 ps
T1049 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2371778711 Aug 12 06:23:09 PM PDT 24 Aug 12 06:23:11 PM PDT 24 439309831 ps
T1050 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.126655547 Aug 12 06:23:04 PM PDT 24 Aug 12 06:23:10 PM PDT 24 108048048 ps
T92 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.931738789 Aug 12 06:22:59 PM PDT 24 Aug 12 06:23:01 PM PDT 24 81470129 ps
T160 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1596494988 Aug 12 06:23:18 PM PDT 24 Aug 12 06:23:25 PM PDT 24 1262432863 ps
T116 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3559598690 Aug 12 06:23:05 PM PDT 24 Aug 12 06:23:07 PM PDT 24 322948826 ps
T165 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2270653432 Aug 12 06:23:13 PM PDT 24 Aug 12 06:23:28 PM PDT 24 1111978990 ps
T117 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3764430439 Aug 12 06:23:12 PM PDT 24 Aug 12 06:23:36 PM PDT 24 3758873188 ps
T1051 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3585106630 Aug 12 06:23:17 PM PDT 24 Aug 12 06:23:18 PM PDT 24 33240194 ps
T1052 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1008052688 Aug 12 06:23:15 PM PDT 24 Aug 12 06:23:23 PM PDT 24 299834627 ps
T1053 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3045941294 Aug 12 06:23:03 PM PDT 24 Aug 12 06:23:04 PM PDT 24 41492588 ps
T1054 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2384012798 Aug 12 06:23:12 PM PDT 24 Aug 12 06:23:27 PM PDT 24 2232560039 ps
T1055 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2723754933 Aug 12 06:23:34 PM PDT 24 Aug 12 06:23:35 PM PDT 24 28223078 ps
T1056 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3687978842 Aug 12 06:23:08 PM PDT 24 Aug 12 06:23:08 PM PDT 24 49507145 ps
T118 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3258289238 Aug 12 06:23:11 PM PDT 24 Aug 12 06:23:13 PM PDT 24 150088558 ps
T1057 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.903261004 Aug 12 06:23:16 PM PDT 24 Aug 12 06:23:20 PM PDT 24 310201081 ps
T1058 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.943766844 Aug 12 06:23:11 PM PDT 24 Aug 12 06:23:13 PM PDT 24 48484414 ps
T90 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2334699931 Aug 12 06:23:03 PM PDT 24 Aug 12 06:23:06 PM PDT 24 479852117 ps
T1059 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.790564650 Aug 12 06:23:12 PM PDT 24 Aug 12 06:23:15 PM PDT 24 106686353 ps
T1060 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2789059467 Aug 12 06:23:18 PM PDT 24 Aug 12 06:23:19 PM PDT 24 115294836 ps
T1061 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1473760704 Aug 12 06:23:05 PM PDT 24 Aug 12 06:23:05 PM PDT 24 155101528 ps
T1062 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2362390800 Aug 12 06:23:16 PM PDT 24 Aug 12 06:23:17 PM PDT 24 87418710 ps
T1063 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3935391415 Aug 12 06:23:15 PM PDT 24 Aug 12 06:23:16 PM PDT 24 38236029 ps
T166 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2649019349 Aug 12 06:23:00 PM PDT 24 Aug 12 06:23:08 PM PDT 24 1619764636 ps
T1064 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3579017474 Aug 12 06:23:13 PM PDT 24 Aug 12 06:23:49 PM PDT 24 2347620648 ps
T1065 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3343741125 Aug 12 06:23:20 PM PDT 24 Aug 12 06:23:21 PM PDT 24 21095310 ps
T1066 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.989380334 Aug 12 06:23:06 PM PDT 24 Aug 12 06:23:09 PM PDT 24 177506857 ps
T1067 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1992453722 Aug 12 06:23:10 PM PDT 24 Aug 12 06:23:10 PM PDT 24 33823813 ps
T1068 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1479738446 Aug 12 06:22:52 PM PDT 24 Aug 12 06:22:55 PM PDT 24 133660525 ps
T1069 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.973301791 Aug 12 06:23:28 PM PDT 24 Aug 12 06:23:29 PM PDT 24 28606037 ps
T1070 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3836857935 Aug 12 06:23:06 PM PDT 24 Aug 12 06:23:22 PM PDT 24 709862690 ps
T1071 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.309418625 Aug 12 06:23:12 PM PDT 24 Aug 12 06:23:14 PM PDT 24 68378966 ps
T1072 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2597612023 Aug 12 06:23:17 PM PDT 24 Aug 12 06:23:21 PM PDT 24 179840410 ps
T94 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1921024629 Aug 12 06:23:03 PM PDT 24 Aug 12 06:23:05 PM PDT 24 56345253 ps
T1073 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.486093175 Aug 12 06:23:13 PM PDT 24 Aug 12 06:23:14 PM PDT 24 32127776 ps
T1074 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.935717274 Aug 12 06:23:07 PM PDT 24 Aug 12 06:23:35 PM PDT 24 794734535 ps
T66 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3498769979 Aug 12 06:22:48 PM PDT 24 Aug 12 06:22:49 PM PDT 24 29180110 ps
T1075 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3777326858 Aug 12 06:23:11 PM PDT 24 Aug 12 06:23:13 PM PDT 24 400650862 ps
T1076 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1165702485 Aug 12 06:23:10 PM PDT 24 Aug 12 06:23:12 PM PDT 24 146269944 ps
T1077 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2782669279 Aug 12 06:23:11 PM PDT 24 Aug 12 06:23:14 PM PDT 24 236195757 ps
T91 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4031228072 Aug 12 06:23:11 PM PDT 24 Aug 12 06:23:14 PM PDT 24 37506070 ps
T1078 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2335737830 Aug 12 06:22:59 PM PDT 24 Aug 12 06:23:18 PM PDT 24 3595893214 ps
T1079 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1022433419 Aug 12 06:23:08 PM PDT 24 Aug 12 06:23:09 PM PDT 24 14225797 ps
T67 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.98580314 Aug 12 06:23:06 PM PDT 24 Aug 12 06:23:08 PM PDT 24 18760330 ps
T1080 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1950388386 Aug 12 06:23:06 PM PDT 24 Aug 12 06:23:09 PM PDT 24 52565876 ps
T1081 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1138560648 Aug 12 06:23:07 PM PDT 24 Aug 12 06:23:09 PM PDT 24 57827049 ps
T1082 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.698424396 Aug 12 06:23:10 PM PDT 24 Aug 12 06:23:11 PM PDT 24 14482706 ps
T1083 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3672642709 Aug 12 06:23:12 PM PDT 24 Aug 12 06:23:14 PM PDT 24 96224428 ps
T1084 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.891701046 Aug 12 06:22:57 PM PDT 24 Aug 12 06:23:00 PM PDT 24 832896620 ps
T1085 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3196646539 Aug 12 06:23:22 PM PDT 24 Aug 12 06:23:23 PM PDT 24 15405413 ps
T68 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3345030547 Aug 12 06:23:05 PM PDT 24 Aug 12 06:23:06 PM PDT 24 19281154 ps
T1086 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4059472337 Aug 12 06:23:03 PM PDT 24 Aug 12 06:23:28 PM PDT 24 2383560804 ps
T1087 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2516436314 Aug 12 06:23:16 PM PDT 24 Aug 12 06:23:17 PM PDT 24 44340432 ps
T1088 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.880668661 Aug 12 06:23:34 PM PDT 24 Aug 12 06:23:35 PM PDT 24 13740861 ps
T1089 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3868852912 Aug 12 06:23:12 PM PDT 24 Aug 12 06:23:16 PM PDT 24 716857613 ps
T1090 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1649974927 Aug 12 06:23:28 PM PDT 24 Aug 12 06:23:29 PM PDT 24 77666316 ps
T1091 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.316182027 Aug 12 06:23:14 PM PDT 24 Aug 12 06:23:15 PM PDT 24 16466048 ps
T1092 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2409274745 Aug 12 06:23:10 PM PDT 24 Aug 12 06:23:13 PM PDT 24 92912454 ps
T1093 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3819104858 Aug 12 06:23:03 PM PDT 24 Aug 12 06:23:06 PM PDT 24 42293635 ps
T1094 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1290815692 Aug 12 06:23:09 PM PDT 24 Aug 12 06:23:11 PM PDT 24 64426086 ps
T1095 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.80066872 Aug 12 06:23:12 PM PDT 24 Aug 12 06:23:13 PM PDT 24 83447072 ps
T1096 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1623288527 Aug 12 06:23:31 PM PDT 24 Aug 12 06:23:32 PM PDT 24 67656511 ps
T93 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3016895065 Aug 12 06:23:06 PM PDT 24 Aug 12 06:23:09 PM PDT 24 159951778 ps
T1097 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.54837898 Aug 12 06:23:34 PM PDT 24 Aug 12 06:23:35 PM PDT 24 14243231 ps
T1098 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3330465666 Aug 12 06:23:13 PM PDT 24 Aug 12 06:23:14 PM PDT 24 14707593 ps
T1099 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1804849150 Aug 12 06:23:13 PM PDT 24 Aug 12 06:23:15 PM PDT 24 231508212 ps
T1100 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1843529236 Aug 12 06:23:11 PM PDT 24 Aug 12 06:23:14 PM PDT 24 366987909 ps
T1101 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3846833633 Aug 12 06:23:23 PM PDT 24 Aug 12 06:23:24 PM PDT 24 42055249 ps
T1102 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1372096615 Aug 12 06:23:13 PM PDT 24 Aug 12 06:23:14 PM PDT 24 17983199 ps
T1103 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1516965003 Aug 12 06:23:35 PM PDT 24 Aug 12 06:23:36 PM PDT 24 11845053 ps
T69 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.632105179 Aug 12 06:23:02 PM PDT 24 Aug 12 06:23:03 PM PDT 24 271980096 ps
T1104 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.99503708 Aug 12 06:23:07 PM PDT 24 Aug 12 06:23:09 PM PDT 24 47251227 ps
T1105 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1644608657 Aug 12 06:23:14 PM PDT 24 Aug 12 06:23:17 PM PDT 24 211170657 ps
T1106 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2608793692 Aug 12 06:23:11 PM PDT 24 Aug 12 06:23:13 PM PDT 24 23593445 ps
T1107 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.787823434 Aug 12 06:23:26 PM PDT 24 Aug 12 06:23:27 PM PDT 24 40836201 ps
T1108 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3656461421 Aug 12 06:23:09 PM PDT 24 Aug 12 06:23:12 PM PDT 24 48352775 ps
T1109 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2099893733 Aug 12 06:23:11 PM PDT 24 Aug 12 06:23:13 PM PDT 24 61294447 ps
T1110 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.241433136 Aug 12 06:23:13 PM PDT 24 Aug 12 06:23:15 PM PDT 24 28804813 ps
T1111 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.800897631 Aug 12 06:23:10 PM PDT 24 Aug 12 06:23:11 PM PDT 24 17041094 ps
T1112 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3002410483 Aug 12 06:23:06 PM PDT 24 Aug 12 06:23:10 PM PDT 24 614542489 ps
T1113 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2979727635 Aug 12 06:23:17 PM PDT 24 Aug 12 06:23:21 PM PDT 24 3256765781 ps
T1114 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.635696844 Aug 12 06:23:28 PM PDT 24 Aug 12 06:23:31 PM PDT 24 200734163 ps
T1115 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2027264744 Aug 12 06:23:08 PM PDT 24 Aug 12 06:23:32 PM PDT 24 9507317694 ps
T1116 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.281799128 Aug 12 06:23:11 PM PDT 24 Aug 12 06:23:13 PM PDT 24 61415603 ps
T70 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.4260476519 Aug 12 06:23:03 PM PDT 24 Aug 12 06:23:05 PM PDT 24 90540988 ps
T1117 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.823153842 Aug 12 06:23:13 PM PDT 24 Aug 12 06:23:16 PM PDT 24 110278512 ps
T1118 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2921529672 Aug 12 06:23:12 PM PDT 24 Aug 12 06:23:15 PM PDT 24 45921195 ps
T1119 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3367623862 Aug 12 06:23:05 PM PDT 24 Aug 12 06:23:08 PM PDT 24 86857665 ps
T1120 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3457148405 Aug 12 06:23:22 PM PDT 24 Aug 12 06:23:23 PM PDT 24 14368125 ps
T1121 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1956919254 Aug 12 06:23:09 PM PDT 24 Aug 12 06:23:11 PM PDT 24 47738948 ps
T1122 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.907864961 Aug 12 06:23:05 PM PDT 24 Aug 12 06:23:10 PM PDT 24 207626356 ps
T1123 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3534993249 Aug 12 06:23:26 PM PDT 24 Aug 12 06:23:31 PM PDT 24 715425766 ps
T1124 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3299104101 Aug 12 06:23:04 PM PDT 24 Aug 12 06:23:05 PM PDT 24 69220857 ps
T1125 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4255574435 Aug 12 06:23:11 PM PDT 24 Aug 12 06:23:12 PM PDT 24 40848755 ps
T1126 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3133048990 Aug 12 06:23:10 PM PDT 24 Aug 12 06:23:12 PM PDT 24 56547372 ps
T1127 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1250841023 Aug 12 06:23:30 PM PDT 24 Aug 12 06:23:35 PM PDT 24 174894828 ps
T1128 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.233791692 Aug 12 06:23:23 PM PDT 24 Aug 12 06:23:38 PM PDT 24 614162269 ps
T1129 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3341369242 Aug 12 06:23:16 PM PDT 24 Aug 12 06:23:17 PM PDT 24 18282226 ps
T1130 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2139707759 Aug 12 06:23:21 PM PDT 24 Aug 12 06:23:23 PM PDT 24 320191471 ps
T1131 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.562913328 Aug 12 06:23:28 PM PDT 24 Aug 12 06:23:29 PM PDT 24 11891567 ps

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2794209102
Short name T6
Test name
Test status
Simulation time 72510988101 ps
CPU time 133.08 seconds
Started Aug 12 06:26:18 PM PDT 24
Finished Aug 12 06:28:31 PM PDT 24
Peak memory 266820 kb
Host smart-af4e518d-a557-414a-82f4-b50c722f6f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794209102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2794209102
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.302999070
Short name T21
Test name
Test status
Simulation time 176007611682 ps
CPU time 559.75 seconds
Started Aug 12 06:25:28 PM PDT 24
Finished Aug 12 06:34:48 PM PDT 24
Peak memory 301512 kb
Host smart-3a7233b7-abdc-4605-9757-fa415e1c00af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302999070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.302999070
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2570151171
Short name T16
Test name
Test status
Simulation time 95635312863 ps
CPU time 249.34 seconds
Started Aug 12 06:24:49 PM PDT 24
Finished Aug 12 06:28:59 PM PDT 24
Peak memory 265808 kb
Host smart-c761df61-b056-47c7-9f1e-5f5bdd19fe56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570151171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2570151171
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2350300146
Short name T82
Test name
Test status
Simulation time 2017727338 ps
CPU time 23.8 seconds
Started Aug 12 06:23:20 PM PDT 24
Finished Aug 12 06:23:43 PM PDT 24
Peak memory 223704 kb
Host smart-3e992c16-9f98-4b43-ba7d-337701fc3ce8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350300146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2350300146
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1044694120
Short name T60
Test name
Test status
Simulation time 25133066 ps
CPU time 0.75 seconds
Started Aug 12 06:24:00 PM PDT 24
Finished Aug 12 06:24:01 PM PDT 24
Peak memory 217104 kb
Host smart-051a6174-3aed-41ba-aa77-67456c7dcc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044694120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1044694120
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.941540971
Short name T14
Test name
Test status
Simulation time 113340175358 ps
CPU time 269.42 seconds
Started Aug 12 06:25:12 PM PDT 24
Finished Aug 12 06:29:41 PM PDT 24
Peak memory 266776 kb
Host smart-a74c6aab-15e6-491e-bcb8-149ce41da3d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941540971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.941540971
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.87782231
Short name T182
Test name
Test status
Simulation time 22017009924 ps
CPU time 246.42 seconds
Started Aug 12 06:25:20 PM PDT 24
Finished Aug 12 06:29:27 PM PDT 24
Peak memory 274860 kb
Host smart-2b1347b4-3b5e-4809-95a5-20e2e2376711
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87782231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress
_all.87782231
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2280960851
Short name T19
Test name
Test status
Simulation time 7624214569 ps
CPU time 170.05 seconds
Started Aug 12 06:24:32 PM PDT 24
Finished Aug 12 06:27:22 PM PDT 24
Peak memory 274380 kb
Host smart-63a81781-6c82-400f-a96e-fd38171ddd67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280960851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2280960851
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3117617407
Short name T132
Test name
Test status
Simulation time 116133633657 ps
CPU time 122.52 seconds
Started Aug 12 06:26:20 PM PDT 24
Finished Aug 12 06:28:22 PM PDT 24
Peak memory 257404 kb
Host smart-b1414d56-24cf-427f-999e-02119eb022de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117617407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3117617407
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.4101941417
Short name T3
Test name
Test status
Simulation time 108894918 ps
CPU time 0.95 seconds
Started Aug 12 06:24:11 PM PDT 24
Finished Aug 12 06:24:12 PM PDT 24
Peak memory 236312 kb
Host smart-3e812e67-2069-4c1a-932b-4c0f7d98b08d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101941417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.4101941417
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2770295327
Short name T85
Test name
Test status
Simulation time 227075299 ps
CPU time 5.27 seconds
Started Aug 12 06:23:10 PM PDT 24
Finished Aug 12 06:23:15 PM PDT 24
Peak memory 215632 kb
Host smart-ddeada7e-e4bf-4e20-8a1b-d2e4b9b78d82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770295327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2770295327
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2051087472
Short name T31
Test name
Test status
Simulation time 466688539 ps
CPU time 5.4 seconds
Started Aug 12 06:25:08 PM PDT 24
Finished Aug 12 06:25:14 PM PDT 24
Peak memory 242004 kb
Host smart-a82284fb-2014-4956-afc1-add84227b40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051087472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2051087472
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3833817025
Short name T13
Test name
Test status
Simulation time 19014729941 ps
CPU time 238.32 seconds
Started Aug 12 06:25:44 PM PDT 24
Finished Aug 12 06:29:43 PM PDT 24
Peak memory 258608 kb
Host smart-b65a4685-bae8-4dee-b278-a650af872457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833817025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3833817025
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1174871113
Short name T41
Test name
Test status
Simulation time 541279123578 ps
CPU time 1032.77 seconds
Started Aug 12 06:24:06 PM PDT 24
Finished Aug 12 06:41:19 PM PDT 24
Peak memory 289496 kb
Host smart-ecfd9209-90f5-4b80-b4fb-029efc928add
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174871113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1174871113
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2654266180
Short name T105
Test name
Test status
Simulation time 437819949 ps
CPU time 2.55 seconds
Started Aug 12 06:23:04 PM PDT 24
Finished Aug 12 06:23:06 PM PDT 24
Peak memory 215432 kb
Host smart-3e53d1ca-f312-4fa3-bce2-548325f2d0ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654266180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2654266180
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.419960897
Short name T39
Test name
Test status
Simulation time 240723763499 ps
CPU time 595.33 seconds
Started Aug 12 06:25:01 PM PDT 24
Finished Aug 12 06:34:57 PM PDT 24
Peak memory 274368 kb
Host smart-1e97044e-5493-4add-873f-175dcb0f724c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419960897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.419960897
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.111431263
Short name T36
Test name
Test status
Simulation time 297126003237 ps
CPU time 266.72 seconds
Started Aug 12 06:24:02 PM PDT 24
Finished Aug 12 06:28:29 PM PDT 24
Peak memory 269188 kb
Host smart-a25a0c30-2588-433b-ad61-fa061b80b8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111431263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
111431263
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3782301136
Short name T249
Test name
Test status
Simulation time 53596201601 ps
CPU time 413.88 seconds
Started Aug 12 06:24:26 PM PDT 24
Finished Aug 12 06:31:20 PM PDT 24
Peak memory 266548 kb
Host smart-6162addc-1aca-4d01-ae02-4eb0db28685c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782301136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3782301136
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1306317804
Short name T204
Test name
Test status
Simulation time 12102331232 ps
CPU time 71.48 seconds
Started Aug 12 06:24:54 PM PDT 24
Finished Aug 12 06:26:05 PM PDT 24
Peak memory 258380 kb
Host smart-fb6af734-ef0c-4894-b93b-885ff4b4683b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306317804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1306317804
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3565533397
Short name T64
Test name
Test status
Simulation time 1448474254625 ps
CPU time 597.27 seconds
Started Aug 12 06:24:19 PM PDT 24
Finished Aug 12 06:34:16 PM PDT 24
Peak memory 273200 kb
Host smart-cbe29014-f735-4c3b-a0c2-bff7341c11ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565533397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3565533397
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1189790777
Short name T119
Test name
Test status
Simulation time 881261114903 ps
CPU time 397.08 seconds
Started Aug 12 06:24:58 PM PDT 24
Finished Aug 12 06:31:35 PM PDT 24
Peak memory 265576 kb
Host smart-17b61a2a-457c-4f7b-b4e0-36b1879c860a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189790777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1189790777
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3123692087
Short name T146
Test name
Test status
Simulation time 20375360 ps
CPU time 0.72 seconds
Started Aug 12 06:24:54 PM PDT 24
Finished Aug 12 06:24:55 PM PDT 24
Peak memory 206792 kb
Host smart-1ac8afd3-01cc-4796-8e18-95915828a3c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123692087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3123692087
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1125396681
Short name T240
Test name
Test status
Simulation time 18758110515 ps
CPU time 287.92 seconds
Started Aug 12 06:24:01 PM PDT 24
Finished Aug 12 06:28:49 PM PDT 24
Peak memory 274700 kb
Host smart-c2518ca1-124c-491d-9329-ae67d36a71ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125396681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1125396681
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1899679128
Short name T30
Test name
Test status
Simulation time 82918021262 ps
CPU time 278.27 seconds
Started Aug 12 06:24:08 PM PDT 24
Finished Aug 12 06:28:46 PM PDT 24
Peak memory 266712 kb
Host smart-074bbdab-8ec0-4b96-8058-d289a45f83a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899679128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1899679128
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2334699931
Short name T90
Test name
Test status
Simulation time 479852117 ps
CPU time 3.4 seconds
Started Aug 12 06:23:03 PM PDT 24
Finished Aug 12 06:23:06 PM PDT 24
Peak memory 215644 kb
Host smart-1decddd0-f794-4a5a-a257-52b33507bd3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334699931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
334699931
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3836857935
Short name T1070
Test name
Test status
Simulation time 709862690 ps
CPU time 16.18 seconds
Started Aug 12 06:23:06 PM PDT 24
Finished Aug 12 06:23:22 PM PDT 24
Peak memory 216248 kb
Host smart-8dac03eb-1d5c-495c-9fc7-fdcd123b416a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836857935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3836857935
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.4233721372
Short name T37
Test name
Test status
Simulation time 260827077476 ps
CPU time 467.94 seconds
Started Aug 12 06:24:20 PM PDT 24
Finished Aug 12 06:32:08 PM PDT 24
Peak memory 250864 kb
Host smart-74d2523b-dff2-48b8-8653-5aeb4a20024f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233721372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.4233721372
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2421624387
Short name T276
Test name
Test status
Simulation time 4290812436 ps
CPU time 11.65 seconds
Started Aug 12 06:24:28 PM PDT 24
Finished Aug 12 06:24:40 PM PDT 24
Peak memory 217428 kb
Host smart-c2c7f0ca-341c-489c-934c-5e257113450d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421624387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2421624387
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3112285743
Short name T265
Test name
Test status
Simulation time 596891589 ps
CPU time 12.66 seconds
Started Aug 12 06:24:47 PM PDT 24
Finished Aug 12 06:25:00 PM PDT 24
Peak memory 238336 kb
Host smart-ec1eecdc-9434-4de8-aba4-139ceee40d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112285743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3112285743
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.4029921987
Short name T11
Test name
Test status
Simulation time 1915999799 ps
CPU time 48.27 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:25:38 PM PDT 24
Peak memory 257076 kb
Host smart-cd7cd024-3341-4c08-8121-3662bd29c6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029921987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.4029921987
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2384012798
Short name T1054
Test name
Test status
Simulation time 2232560039 ps
CPU time 14.31 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:27 PM PDT 24
Peak memory 216248 kb
Host smart-465206d6-4da1-48c9-9710-888ec5e3c0cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384012798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2384012798
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2892381234
Short name T251
Test name
Test status
Simulation time 97146476122 ps
CPU time 188.2 seconds
Started Aug 12 06:24:42 PM PDT 24
Finished Aug 12 06:27:50 PM PDT 24
Peak memory 272196 kb
Host smart-b3b36084-0641-4b3d-a3f5-fa2f84969952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892381234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2892381234
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2842473112
Short name T263
Test name
Test status
Simulation time 1744590037 ps
CPU time 14.45 seconds
Started Aug 12 06:24:56 PM PDT 24
Finished Aug 12 06:25:10 PM PDT 24
Peak memory 233796 kb
Host smart-448ad742-ce91-49ac-a61b-816d3d9151f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842473112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2842473112
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2379053261
Short name T42
Test name
Test status
Simulation time 35937443762 ps
CPU time 382.04 seconds
Started Aug 12 06:25:16 PM PDT 24
Finished Aug 12 06:31:38 PM PDT 24
Peak memory 266744 kb
Host smart-fb55926d-f7c4-4d9f-88c7-193af98394a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379053261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2379053261
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.474872111
Short name T155
Test name
Test status
Simulation time 346018890123 ps
CPU time 909.86 seconds
Started Aug 12 06:24:26 PM PDT 24
Finished Aug 12 06:39:36 PM PDT 24
Peak memory 284564 kb
Host smart-97403776-d879-4b10-a38e-7a853133c8b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474872111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.474872111
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2844903466
Short name T97
Test name
Test status
Simulation time 719983312 ps
CPU time 16.27 seconds
Started Aug 12 06:23:22 PM PDT 24
Finished Aug 12 06:23:38 PM PDT 24
Peak memory 215604 kb
Host smart-2e64360d-724e-463a-b285-217a6e8e97ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844903466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2844903466
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3023868391
Short name T262
Test name
Test status
Simulation time 1737416150 ps
CPU time 25.07 seconds
Started Aug 12 06:24:44 PM PDT 24
Finished Aug 12 06:25:10 PM PDT 24
Peak memory 225620 kb
Host smart-82ed306f-af01-4cb0-af6b-6c8be61c99bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023868391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3023868391
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3758488834
Short name T217
Test name
Test status
Simulation time 29048462981 ps
CPU time 88.46 seconds
Started Aug 12 06:24:56 PM PDT 24
Finished Aug 12 06:26:25 PM PDT 24
Peak memory 274064 kb
Host smart-333dd66d-07ba-4b73-b398-59fe785aec04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758488834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3758488834
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3456408490
Short name T175
Test name
Test status
Simulation time 36079416925 ps
CPU time 167.42 seconds
Started Aug 12 06:24:56 PM PDT 24
Finished Aug 12 06:27:43 PM PDT 24
Peak memory 258400 kb
Host smart-e41db41b-1b8b-4bd8-a3d4-5549814b1660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456408490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3456408490
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.4289264972
Short name T247
Test name
Test status
Simulation time 135464530117 ps
CPU time 248.61 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:29:03 PM PDT 24
Peak memory 258244 kb
Host smart-9bb2a2f0-b18d-4c29-9bd7-03995b4ce297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289264972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.4289264972
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2070907809
Short name T75
Test name
Test status
Simulation time 825869803 ps
CPU time 5.45 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:24:11 PM PDT 24
Peak memory 233764 kb
Host smart-a2b6bf2c-481c-4676-90fc-504c8c476435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070907809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2070907809
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4031228072
Short name T91
Test name
Test status
Simulation time 37506070 ps
CPU time 2.52 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 215592 kb
Host smart-6c20b892-4a37-4188-862a-d0a0067167ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031228072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4
031228072
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2199126061
Short name T80
Test name
Test status
Simulation time 2101848979 ps
CPU time 4.87 seconds
Started Aug 12 06:24:02 PM PDT 24
Finished Aug 12 06:24:08 PM PDT 24
Peak memory 225628 kb
Host smart-2b8854c1-27a2-4e4d-a070-904412239cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199126061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2199126061
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.98580314
Short name T67
Test name
Test status
Simulation time 18760330 ps
CPU time 1.13 seconds
Started Aug 12 06:23:06 PM PDT 24
Finished Aug 12 06:23:08 PM PDT 24
Peak memory 207188 kb
Host smart-5a4fbf84-7e02-4c1b-af55-9313d285d9ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98580314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_
hw_reset.98580314
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3611570552
Short name T33
Test name
Test status
Simulation time 1179295446 ps
CPU time 8.43 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:25:00 PM PDT 24
Peak memory 224236 kb
Host smart-382d5493-3a78-4edc-a7f9-0fc9e8f325b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3611570552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3611570552
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.203361844
Short name T29
Test name
Test status
Simulation time 9532541943 ps
CPU time 68.35 seconds
Started Aug 12 06:24:41 PM PDT 24
Finished Aug 12 06:25:49 PM PDT 24
Peak memory 250352 kb
Host smart-16f92fc2-9f8b-4376-97d7-8db1241a640e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203361844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.203361844
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4059472337
Short name T1086
Test name
Test status
Simulation time 2383560804 ps
CPU time 24.78 seconds
Started Aug 12 06:23:03 PM PDT 24
Finished Aug 12 06:23:28 PM PDT 24
Peak memory 215624 kb
Host smart-cede3aa1-c08f-4f74-9db6-22b873059fa3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059472337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.4059472337
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1994098703
Short name T107
Test name
Test status
Simulation time 1654271081 ps
CPU time 24.04 seconds
Started Aug 12 06:22:58 PM PDT 24
Finished Aug 12 06:23:22 PM PDT 24
Peak memory 207376 kb
Host smart-a0ad3e2a-75ca-4e8a-8639-b56771a055dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994098703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1994098703
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3498769979
Short name T66
Test name
Test status
Simulation time 29180110 ps
CPU time 1.39 seconds
Started Aug 12 06:22:48 PM PDT 24
Finished Aug 12 06:22:49 PM PDT 24
Peak memory 207032 kb
Host smart-4d7306a6-cc50-4ed1-b203-848f7e643a8d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498769979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3498769979
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.903261004
Short name T1057
Test name
Test status
Simulation time 310201081 ps
CPU time 3.57 seconds
Started Aug 12 06:23:16 PM PDT 24
Finished Aug 12 06:23:20 PM PDT 24
Peak memory 218516 kb
Host smart-a0d8d404-c4fa-4248-ac74-578dd3cfcf23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903261004 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.903261004
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2591447668
Short name T150
Test name
Test status
Simulation time 45804009 ps
CPU time 1.31 seconds
Started Aug 12 06:23:02 PM PDT 24
Finished Aug 12 06:23:03 PM PDT 24
Peak memory 206832 kb
Host smart-a2c64bcc-6bb0-49c1-822f-16df166e0551
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591447668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
591447668
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3557203015
Short name T1026
Test name
Test status
Simulation time 19802440 ps
CPU time 0.78 seconds
Started Aug 12 06:23:05 PM PDT 24
Finished Aug 12 06:23:06 PM PDT 24
Peak memory 204032 kb
Host smart-7283dcb1-4b04-4417-a44b-5e32af5d1bc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557203015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
557203015
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3076574902
Short name T106
Test name
Test status
Simulation time 19059617 ps
CPU time 1.24 seconds
Started Aug 12 06:23:04 PM PDT 24
Finished Aug 12 06:23:06 PM PDT 24
Peak memory 215436 kb
Host smart-05b9e1af-c627-466e-8d9c-c64b823d545a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076574902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3076574902
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.895447318
Short name T1010
Test name
Test status
Simulation time 19105286 ps
CPU time 0.65 seconds
Started Aug 12 06:23:00 PM PDT 24
Finished Aug 12 06:23:01 PM PDT 24
Peak memory 203944 kb
Host smart-4e3288a5-997f-407f-806f-325df95519ee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895447318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.895447318
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2921529672
Short name T1118
Test name
Test status
Simulation time 45921195 ps
CPU time 2.86 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:15 PM PDT 24
Peak memory 215476 kb
Host smart-3a2ba858-98b6-4472-ac39-8f84dcf16603
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921529672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2921529672
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3016895065
Short name T93
Test name
Test status
Simulation time 159951778 ps
CPU time 2.39 seconds
Started Aug 12 06:23:06 PM PDT 24
Finished Aug 12 06:23:09 PM PDT 24
Peak memory 215552 kb
Host smart-665dd50c-bf33-4e4c-9eb5-7bfcddb0b633
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016895065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
016895065
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1304740619
Short name T109
Test name
Test status
Simulation time 432308039 ps
CPU time 14.91 seconds
Started Aug 12 06:23:07 PM PDT 24
Finished Aug 12 06:23:22 PM PDT 24
Peak memory 214060 kb
Host smart-82ba6adb-815e-4b51-9818-faf00910e175
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304740619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1304740619
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3623510009
Short name T1031
Test name
Test status
Simulation time 10614787498 ps
CPU time 35.89 seconds
Started Aug 12 06:22:59 PM PDT 24
Finished Aug 12 06:23:35 PM PDT 24
Peak memory 207376 kb
Host smart-d183477a-6512-4a0a-a052-5b58fadeff83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623510009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3623510009
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1479738446
Short name T1068
Test name
Test status
Simulation time 133660525 ps
CPU time 2.35 seconds
Started Aug 12 06:22:52 PM PDT 24
Finished Aug 12 06:22:55 PM PDT 24
Peak memory 217060 kb
Host smart-dc3fad53-a487-4b6a-acfb-af1d3d59f832
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479738446 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1479738446
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2026156909
Short name T113
Test name
Test status
Simulation time 35594442 ps
CPU time 1.27 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 207196 kb
Host smart-9b45f7fa-4b64-4c44-873b-ec02b2a20cef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026156909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
026156909
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3422490761
Short name T1036
Test name
Test status
Simulation time 40329801 ps
CPU time 0.71 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:12 PM PDT 24
Peak memory 204032 kb
Host smart-5412de0c-db36-4712-8c84-0345c3ecb1f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422490761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
422490761
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.943766844
Short name T1058
Test name
Test status
Simulation time 48484414 ps
CPU time 1.83 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 214100 kb
Host smart-96cb7c01-617a-4bcb-8a9c-4dab8899abf7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943766844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.943766844
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.874428661
Short name T1042
Test name
Test status
Simulation time 22798060 ps
CPU time 0.66 seconds
Started Aug 12 06:22:56 PM PDT 24
Finished Aug 12 06:22:57 PM PDT 24
Peak memory 204268 kb
Host smart-baeced71-637b-44d2-99cf-8913662e1fa7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874428661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.874428661
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1138560648
Short name T1081
Test name
Test status
Simulation time 57827049 ps
CPU time 1.75 seconds
Started Aug 12 06:23:07 PM PDT 24
Finished Aug 12 06:23:09 PM PDT 24
Peak memory 215492 kb
Host smart-07debd49-b55b-42e1-94b4-c147423cc2c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138560648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1138560648
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3546506476
Short name T159
Test name
Test status
Simulation time 405213783 ps
CPU time 12.83 seconds
Started Aug 12 06:22:57 PM PDT 24
Finished Aug 12 06:23:10 PM PDT 24
Peak memory 215496 kb
Host smart-a038a9b6-c308-4f08-86b5-dbb132091d5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546506476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3546506476
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2219952506
Short name T1028
Test name
Test status
Simulation time 250749659 ps
CPU time 3.41 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:15 PM PDT 24
Peak memory 217312 kb
Host smart-f23aa172-e015-4d1c-8f94-0485e45a4e5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219952506 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2219952506
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3559598690
Short name T116
Test name
Test status
Simulation time 322948826 ps
CPU time 2.23 seconds
Started Aug 12 06:23:05 PM PDT 24
Finished Aug 12 06:23:07 PM PDT 24
Peak memory 215504 kb
Host smart-de42c48a-fc46-42e3-af6b-9237b529db0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559598690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3559598690
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.316182027
Short name T1091
Test name
Test status
Simulation time 16466048 ps
CPU time 0.75 seconds
Started Aug 12 06:23:14 PM PDT 24
Finished Aug 12 06:23:15 PM PDT 24
Peak memory 204040 kb
Host smart-8f97c2df-aa60-46b2-a762-e06048bf3947
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316182027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.316182027
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3805097637
Short name T1016
Test name
Test status
Simulation time 158454984 ps
CPU time 4.03 seconds
Started Aug 12 06:23:19 PM PDT 24
Finished Aug 12 06:23:23 PM PDT 24
Peak memory 215500 kb
Host smart-c535be76-c01b-43f9-ad6f-5258f78b3f84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805097637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3805097637
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.126655547
Short name T1050
Test name
Test status
Simulation time 108048048 ps
CPU time 6.05 seconds
Started Aug 12 06:23:04 PM PDT 24
Finished Aug 12 06:23:10 PM PDT 24
Peak memory 215496 kb
Host smart-3c40d011-bc98-4139-98cf-765b4cab2c53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126655547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.126655547
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1682110169
Short name T59
Test name
Test status
Simulation time 121194496 ps
CPU time 3.56 seconds
Started Aug 12 06:23:09 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 217208 kb
Host smart-e04f8389-754e-4339-8af8-301476036152
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682110169 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1682110169
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.309418625
Short name T1071
Test name
Test status
Simulation time 68378966 ps
CPU time 1.92 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 207228 kb
Host smart-4b6cb491-680a-4209-8984-9d99d70ebe58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309418625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.309418625
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1981505495
Short name T1015
Test name
Test status
Simulation time 80368347 ps
CPU time 0.76 seconds
Started Aug 12 06:23:16 PM PDT 24
Finished Aug 12 06:23:17 PM PDT 24
Peak memory 204360 kb
Host smart-618c3cfd-decc-4d9d-952c-72d9e1584d15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981505495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1981505495
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1250841023
Short name T1127
Test name
Test status
Simulation time 174894828 ps
CPU time 4.23 seconds
Started Aug 12 06:23:30 PM PDT 24
Finished Aug 12 06:23:35 PM PDT 24
Peak memory 215452 kb
Host smart-106359ce-857d-4700-b5ea-06a79b45f1c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250841023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1250841023
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3089793087
Short name T89
Test name
Test status
Simulation time 356922105 ps
CPU time 4.25 seconds
Started Aug 12 06:23:16 PM PDT 24
Finished Aug 12 06:23:21 PM PDT 24
Peak memory 215588 kb
Host smart-7902ef15-af5e-43cf-a21d-50961b335086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089793087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3089793087
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3843848421
Short name T58
Test name
Test status
Simulation time 717849911 ps
CPU time 16.05 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:28 PM PDT 24
Peak memory 219136 kb
Host smart-698e010f-4d22-4d9b-add4-9e80224e84f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843848421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3843848421
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1985654308
Short name T1033
Test name
Test status
Simulation time 37678355 ps
CPU time 2.29 seconds
Started Aug 12 06:23:04 PM PDT 24
Finished Aug 12 06:23:07 PM PDT 24
Peak memory 216756 kb
Host smart-6390722b-4257-48cf-bb58-1d4653759d33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985654308 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1985654308
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4283333735
Short name T111
Test name
Test status
Simulation time 40424001 ps
CPU time 2.47 seconds
Started Aug 12 06:23:27 PM PDT 24
Finished Aug 12 06:23:29 PM PDT 24
Peak memory 215448 kb
Host smart-20639bb5-45ca-4b93-86e5-724785682e1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283333735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4283333735
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.775630529
Short name T1029
Test name
Test status
Simulation time 48730062 ps
CPU time 0.7 seconds
Started Aug 12 06:23:03 PM PDT 24
Finished Aug 12 06:23:04 PM PDT 24
Peak memory 204028 kb
Host smart-df984bcc-4c0f-482c-83d6-a4ce54fb750e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775630529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.775630529
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2004860719
Short name T1043
Test name
Test status
Simulation time 154934559 ps
CPU time 3.94 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:17 PM PDT 24
Peak memory 215544 kb
Host smart-114da509-15aa-4e09-b21c-29f5d865e59d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004860719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2004860719
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3534993249
Short name T1123
Test name
Test status
Simulation time 715425766 ps
CPU time 5.36 seconds
Started Aug 12 06:23:26 PM PDT 24
Finished Aug 12 06:23:31 PM PDT 24
Peak memory 215812 kb
Host smart-d528417a-b283-4d7a-bd72-1053216d76fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534993249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3534993249
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1596494988
Short name T160
Test name
Test status
Simulation time 1262432863 ps
CPU time 7.45 seconds
Started Aug 12 06:23:18 PM PDT 24
Finished Aug 12 06:23:25 PM PDT 24
Peak memory 215580 kb
Host smart-de63c36f-5a02-4af1-be65-15e801e51307
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596494988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1596494988
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2608793692
Short name T1106
Test name
Test status
Simulation time 23593445 ps
CPU time 1.72 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 215600 kb
Host smart-e41140b2-4772-4823-b048-cd52ff0ade56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608793692 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2608793692
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.281799128
Short name T1116
Test name
Test status
Simulation time 61415603 ps
CPU time 1.99 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 207212 kb
Host smart-a87a9677-3f58-4f5f-bb5f-050878faa10c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281799128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.281799128
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1992453722
Short name T1067
Test name
Test status
Simulation time 33823813 ps
CPU time 0.72 seconds
Started Aug 12 06:23:10 PM PDT 24
Finished Aug 12 06:23:10 PM PDT 24
Peak memory 204360 kb
Host smart-4d6101e6-edb6-42d7-9c45-9ea18be7cc7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992453722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1992453722
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.989380334
Short name T1066
Test name
Test status
Simulation time 177506857 ps
CPU time 2.83 seconds
Started Aug 12 06:23:06 PM PDT 24
Finished Aug 12 06:23:09 PM PDT 24
Peak memory 215504 kb
Host smart-1a895369-2838-445b-a565-dc443c393170
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989380334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.989380334
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2139707759
Short name T1130
Test name
Test status
Simulation time 320191471 ps
CPU time 2.16 seconds
Started Aug 12 06:23:21 PM PDT 24
Finished Aug 12 06:23:23 PM PDT 24
Peak memory 216684 kb
Host smart-9ac31ad3-d11a-48a3-9499-78163d31d349
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139707759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2139707759
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1481292039
Short name T163
Test name
Test status
Simulation time 598352939 ps
CPU time 14.2 seconds
Started Aug 12 06:23:05 PM PDT 24
Finished Aug 12 06:23:19 PM PDT 24
Peak memory 215696 kb
Host smart-b5e08334-e446-4410-b41c-ee31deada2e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481292039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1481292039
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3133048990
Short name T1126
Test name
Test status
Simulation time 56547372 ps
CPU time 1.69 seconds
Started Aug 12 06:23:10 PM PDT 24
Finished Aug 12 06:23:12 PM PDT 24
Peak memory 215416 kb
Host smart-6f054f94-09c5-47e2-9c33-1e2f8ff0bc43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133048990 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3133048990
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.241433136
Short name T1110
Test name
Test status
Simulation time 28804813 ps
CPU time 1.8 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:15 PM PDT 24
Peak memory 207128 kb
Host smart-b1d74e1d-209f-49f6-b913-3c0fe75cefec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241433136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.241433136
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3330465666
Short name T1098
Test name
Test status
Simulation time 14707593 ps
CPU time 0.73 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 204044 kb
Host smart-62f3de51-1bd0-4175-bfa3-b213f50cc5ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330465666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3330465666
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2372014532
Short name T1018
Test name
Test status
Simulation time 41811196 ps
CPU time 2.85 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:17 PM PDT 24
Peak memory 215480 kb
Host smart-f2f14bea-36a4-4492-ba67-35af8e8b894e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372014532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2372014532
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.99503708
Short name T1104
Test name
Test status
Simulation time 47251227 ps
CPU time 1.72 seconds
Started Aug 12 06:23:07 PM PDT 24
Finished Aug 12 06:23:09 PM PDT 24
Peak memory 215588 kb
Host smart-fdce0834-372f-4f87-abb8-5f2843484210
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99503708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.99503708
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3490714743
Short name T158
Test name
Test status
Simulation time 554665323 ps
CPU time 13.93 seconds
Started Aug 12 06:23:14 PM PDT 24
Finished Aug 12 06:23:28 PM PDT 24
Peak memory 215508 kb
Host smart-486607be-6b33-4dc7-81d5-22639a5e7c93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490714743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3490714743
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2597612023
Short name T1072
Test name
Test status
Simulation time 179840410 ps
CPU time 3.74 seconds
Started Aug 12 06:23:17 PM PDT 24
Finished Aug 12 06:23:21 PM PDT 24
Peak memory 217780 kb
Host smart-d1dc02ce-76b1-40da-83f6-076adbaf82fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597612023 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2597612023
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.235816010
Short name T1011
Test name
Test status
Simulation time 22679115 ps
CPU time 0.72 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 204064 kb
Host smart-dc08b08d-aebc-4fb0-b1b8-a91bfb615ab1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235816010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.235816010
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.635696844
Short name T1114
Test name
Test status
Simulation time 200734163 ps
CPU time 3.56 seconds
Started Aug 12 06:23:28 PM PDT 24
Finished Aug 12 06:23:31 PM PDT 24
Peak memory 215416 kb
Host smart-0551a511-e3e6-4acf-9939-4b31a6e9ec28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635696844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.635696844
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3367623862
Short name T1119
Test name
Test status
Simulation time 86857665 ps
CPU time 2.91 seconds
Started Aug 12 06:23:05 PM PDT 24
Finished Aug 12 06:23:08 PM PDT 24
Peak memory 215616 kb
Host smart-78091b18-f909-4e16-92f3-9798869fe0d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367623862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3367623862
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4047724647
Short name T96
Test name
Test status
Simulation time 188185395 ps
CPU time 4.02 seconds
Started Aug 12 06:23:15 PM PDT 24
Finished Aug 12 06:23:19 PM PDT 24
Peak memory 218304 kb
Host smart-5c79737a-2d15-4b8e-86ff-d35c91f6923f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047724647 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.4047724647
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1372096615
Short name T1102
Test name
Test status
Simulation time 17983199 ps
CPU time 1.2 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 207236 kb
Host smart-5cfee205-b5df-47e7-a19e-c973a81e87ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372096615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1372096615
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3045941294
Short name T1053
Test name
Test status
Simulation time 41492588 ps
CPU time 0.68 seconds
Started Aug 12 06:23:03 PM PDT 24
Finished Aug 12 06:23:04 PM PDT 24
Peak memory 204096 kb
Host smart-77cb3024-5b49-4f2e-9c22-d19d40384c38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045941294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3045941294
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.319316163
Short name T1040
Test name
Test status
Simulation time 71370710 ps
CPU time 3.96 seconds
Started Aug 12 06:23:08 PM PDT 24
Finished Aug 12 06:23:12 PM PDT 24
Peak memory 215512 kb
Host smart-a5d2ee19-dd9b-4cf8-b937-9f53bac3c124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319316163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.319316163
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3437731962
Short name T87
Test name
Test status
Simulation time 165634790 ps
CPU time 1.85 seconds
Started Aug 12 06:23:14 PM PDT 24
Finished Aug 12 06:23:16 PM PDT 24
Peak memory 216632 kb
Host smart-4ba0eca3-88a8-45c5-a833-6a3b008045ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437731962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3437731962
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3868852912
Short name T1089
Test name
Test status
Simulation time 716857613 ps
CPU time 3.82 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:16 PM PDT 24
Peak memory 217780 kb
Host smart-1f119db2-5f48-409a-9c42-f9950965bf13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868852912 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3868852912
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1644608657
Short name T1105
Test name
Test status
Simulation time 211170657 ps
CPU time 2.75 seconds
Started Aug 12 06:23:14 PM PDT 24
Finished Aug 12 06:23:17 PM PDT 24
Peak memory 215508 kb
Host smart-c50f8d1d-a235-4a54-9fb3-c149086c8225
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644608657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1644608657
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.787823434
Short name T1107
Test name
Test status
Simulation time 40836201 ps
CPU time 0.79 seconds
Started Aug 12 06:23:26 PM PDT 24
Finished Aug 12 06:23:27 PM PDT 24
Peak memory 204060 kb
Host smart-0d09d2a9-3a3e-42cf-9cd9-ac514b14e9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787823434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.787823434
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1804849150
Short name T1099
Test name
Test status
Simulation time 231508212 ps
CPU time 1.77 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:15 PM PDT 24
Peak memory 215432 kb
Host smart-85a630ca-0d74-4cb8-abb5-4736b88531d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804849150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1804849150
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.823153842
Short name T1117
Test name
Test status
Simulation time 110278512 ps
CPU time 2.54 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:16 PM PDT 24
Peak memory 215616 kb
Host smart-35a34264-d4d9-4cd4-b9f8-f81fc69da1f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823153842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.823153842
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1960825253
Short name T162
Test name
Test status
Simulation time 1141858455 ps
CPU time 15.25 seconds
Started Aug 12 06:23:06 PM PDT 24
Finished Aug 12 06:23:22 PM PDT 24
Peak memory 215420 kb
Host smart-5c35aa78-0fbf-4728-a2fe-c59ce999e81d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960825253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1960825253
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2291845110
Short name T81
Test name
Test status
Simulation time 185520800 ps
CPU time 3.4 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:16 PM PDT 24
Peak memory 218228 kb
Host smart-ff5d18b8-e145-42c7-af55-9c275fd5438c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291845110 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2291845110
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3565340536
Short name T108
Test name
Test status
Simulation time 61934240 ps
CPU time 1.94 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 215524 kb
Host smart-2b463a28-6d8e-49f7-adf6-e59982bbfd0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565340536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3565340536
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.536828810
Short name T1009
Test name
Test status
Simulation time 39402192 ps
CPU time 0.73 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 204096 kb
Host smart-9c94dc5b-3a9b-4941-b72a-a383e0cb9a0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536828810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.536828810
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1950388386
Short name T1080
Test name
Test status
Simulation time 52565876 ps
CPU time 3.08 seconds
Started Aug 12 06:23:06 PM PDT 24
Finished Aug 12 06:23:09 PM PDT 24
Peak memory 215516 kb
Host smart-bc7f0761-e6c9-46ed-8aa5-b7885b2a30ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950388386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1950388386
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3656461421
Short name T1108
Test name
Test status
Simulation time 48352775 ps
CPU time 2.99 seconds
Started Aug 12 06:23:09 PM PDT 24
Finished Aug 12 06:23:12 PM PDT 24
Peak memory 215572 kb
Host smart-c3080204-d4cb-4943-b510-feb4f701f7fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656461421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3656461421
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1008052688
Short name T1052
Test name
Test status
Simulation time 299834627 ps
CPU time 8.01 seconds
Started Aug 12 06:23:15 PM PDT 24
Finished Aug 12 06:23:23 PM PDT 24
Peak memory 223752 kb
Host smart-7149e0ce-d7d3-4b75-8c5f-b03da715542f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008052688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1008052688
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1956919254
Short name T1121
Test name
Test status
Simulation time 47738948 ps
CPU time 1.77 seconds
Started Aug 12 06:23:09 PM PDT 24
Finished Aug 12 06:23:11 PM PDT 24
Peak memory 216716 kb
Host smart-9acb60e8-686f-484d-9ff9-f3a741bcba65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956919254 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1956919254
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1165702485
Short name T1076
Test name
Test status
Simulation time 146269944 ps
CPU time 2.05 seconds
Started Aug 12 06:23:10 PM PDT 24
Finished Aug 12 06:23:12 PM PDT 24
Peak memory 215520 kb
Host smart-1de5151a-ec66-4b83-aee4-dc137d7a14ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165702485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1165702485
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.885190581
Short name T1047
Test name
Test status
Simulation time 18151556 ps
CPU time 0.76 seconds
Started Aug 12 06:23:21 PM PDT 24
Finished Aug 12 06:23:22 PM PDT 24
Peak memory 204068 kb
Host smart-f86f7afe-c763-4af0-886a-94b0542681cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885190581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.885190581
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1649974927
Short name T1090
Test name
Test status
Simulation time 77666316 ps
CPU time 1.58 seconds
Started Aug 12 06:23:28 PM PDT 24
Finished Aug 12 06:23:29 PM PDT 24
Peak memory 215404 kb
Host smart-5406db77-7929-40a5-aca9-cdab988e64b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649974927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1649974927
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.907864961
Short name T1122
Test name
Test status
Simulation time 207626356 ps
CPU time 4.88 seconds
Started Aug 12 06:23:05 PM PDT 24
Finished Aug 12 06:23:10 PM PDT 24
Peak memory 215748 kb
Host smart-53162ea2-e364-4fbe-abed-e56d4ed5a429
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907864961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.907864961
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.233791692
Short name T1128
Test name
Test status
Simulation time 614162269 ps
CPU time 14.99 seconds
Started Aug 12 06:23:23 PM PDT 24
Finished Aug 12 06:23:38 PM PDT 24
Peak memory 207156 kb
Host smart-8407fb1f-4555-4ad2-ac69-eaf18138bb2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233791692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.233791692
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3579017474
Short name T1064
Test name
Test status
Simulation time 2347620648 ps
CPU time 35.51 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:49 PM PDT 24
Peak memory 215488 kb
Host smart-c09ec31d-c2a4-4335-aa7a-4e55a0d8e24b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579017474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3579017474
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.4260476519
Short name T70
Test name
Test status
Simulation time 90540988 ps
CPU time 1.38 seconds
Started Aug 12 06:23:03 PM PDT 24
Finished Aug 12 06:23:05 PM PDT 24
Peak memory 207184 kb
Host smart-c6ac77f3-98e1-467b-bb3c-0f2c0ffb36ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260476519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.4260476519
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3861490664
Short name T99
Test name
Test status
Simulation time 621057421 ps
CPU time 3.88 seconds
Started Aug 12 06:23:05 PM PDT 24
Finished Aug 12 06:23:09 PM PDT 24
Peak memory 217504 kb
Host smart-ee3c4244-4c93-4b4c-83a7-0c370e8444ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861490664 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3861490664
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4108094537
Short name T114
Test name
Test status
Simulation time 89024498 ps
CPU time 2.23 seconds
Started Aug 12 06:23:02 PM PDT 24
Finished Aug 12 06:23:04 PM PDT 24
Peak memory 207288 kb
Host smart-93fce0c5-3498-4da3-ad1e-73ac235b7f38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108094537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
108094537
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4255574435
Short name T1125
Test name
Test status
Simulation time 40848755 ps
CPU time 0.75 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:12 PM PDT 24
Peak memory 203984 kb
Host smart-b2a93cbc-5d93-45b2-9b53-0b231db06ff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255574435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.4
255574435
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1756275988
Short name T112
Test name
Test status
Simulation time 75426478 ps
CPU time 2.13 seconds
Started Aug 12 06:23:02 PM PDT 24
Finished Aug 12 06:23:04 PM PDT 24
Peak memory 215436 kb
Host smart-f62568cb-08ad-4ff5-9c40-edbf27152afa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756275988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1756275988
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1003287729
Short name T1012
Test name
Test status
Simulation time 14100606 ps
CPU time 0.65 seconds
Started Aug 12 06:22:57 PM PDT 24
Finished Aug 12 06:22:57 PM PDT 24
Peak memory 204220 kb
Host smart-2981ba0e-8428-4253-a18c-cff26dc39ff7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003287729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1003287729
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3672642709
Short name T1083
Test name
Test status
Simulation time 96224428 ps
CPU time 1.68 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 215452 kb
Host smart-78477471-26da-4999-a212-b088e8692bc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672642709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3672642709
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1921024629
Short name T94
Test name
Test status
Simulation time 56345253 ps
CPU time 1.83 seconds
Started Aug 12 06:23:03 PM PDT 24
Finished Aug 12 06:23:05 PM PDT 24
Peak memory 215608 kb
Host smart-d08cb572-c0f5-4139-a584-be193f038911
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921024629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
921024629
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2270653432
Short name T165
Test name
Test status
Simulation time 1111978990 ps
CPU time 14.11 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:28 PM PDT 24
Peak memory 215484 kb
Host smart-2f9d1af1-4830-4fc2-a6d4-49675a0a7349
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270653432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2270653432
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1022433419
Short name T1079
Test name
Test status
Simulation time 14225797 ps
CPU time 0.77 seconds
Started Aug 12 06:23:08 PM PDT 24
Finished Aug 12 06:23:09 PM PDT 24
Peak memory 204008 kb
Host smart-5250c820-2e19-4419-90a4-be1196f752cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022433419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1022433419
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3895629859
Short name T1025
Test name
Test status
Simulation time 45410377 ps
CPU time 0.78 seconds
Started Aug 12 06:23:10 PM PDT 24
Finished Aug 12 06:23:11 PM PDT 24
Peak memory 204320 kb
Host smart-e1fe0b59-7ec3-41e7-ac28-0160f6dfe7b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895629859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3895629859
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4277813769
Short name T1046
Test name
Test status
Simulation time 29447872 ps
CPU time 0.72 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:12 PM PDT 24
Peak memory 204008 kb
Host smart-9e087a6e-63ba-446a-a97e-8e0c1c2673b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277813769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4277813769
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3687978842
Short name T1056
Test name
Test status
Simulation time 49507145 ps
CPU time 0.68 seconds
Started Aug 12 06:23:08 PM PDT 24
Finished Aug 12 06:23:08 PM PDT 24
Peak memory 203944 kb
Host smart-2ccf36bb-1e9d-4bde-93a2-03a4c58126da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687978842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3687978842
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3341369242
Short name T1129
Test name
Test status
Simulation time 18282226 ps
CPU time 0.77 seconds
Started Aug 12 06:23:16 PM PDT 24
Finished Aug 12 06:23:17 PM PDT 24
Peak memory 204004 kb
Host smart-10eb7edf-df79-4c68-b8cf-f392795dfe68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341369242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3341369242
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1885406717
Short name T1037
Test name
Test status
Simulation time 18569726 ps
CPU time 0.74 seconds
Started Aug 12 06:23:31 PM PDT 24
Finished Aug 12 06:23:32 PM PDT 24
Peak memory 204328 kb
Host smart-a24dc26a-d12b-4802-8759-23bf80950c80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885406717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1885406717
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1377424609
Short name T1038
Test name
Test status
Simulation time 53947824 ps
CPU time 0.78 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 204216 kb
Host smart-d1d938dc-c0c1-4b51-8966-ec399c9ad8c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377424609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1377424609
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3585106630
Short name T1051
Test name
Test status
Simulation time 33240194 ps
CPU time 0.72 seconds
Started Aug 12 06:23:17 PM PDT 24
Finished Aug 12 06:23:18 PM PDT 24
Peak memory 203996 kb
Host smart-ede71f8b-f259-4064-acec-1ee4db0ca5ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585106630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3585106630
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.54837898
Short name T1097
Test name
Test status
Simulation time 14243231 ps
CPU time 0.74 seconds
Started Aug 12 06:23:34 PM PDT 24
Finished Aug 12 06:23:35 PM PDT 24
Peak memory 204060 kb
Host smart-4758b107-3088-454f-8a9e-3360714d8648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54837898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.54837898
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.698424396
Short name T1082
Test name
Test status
Simulation time 14482706 ps
CPU time 0.73 seconds
Started Aug 12 06:23:10 PM PDT 24
Finished Aug 12 06:23:11 PM PDT 24
Peak memory 204332 kb
Host smart-21248029-0cdf-47ad-9ac5-77485688af69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698424396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.698424396
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2027264744
Short name T1115
Test name
Test status
Simulation time 9507317694 ps
CPU time 24.09 seconds
Started Aug 12 06:23:08 PM PDT 24
Finished Aug 12 06:23:32 PM PDT 24
Peak memory 215480 kb
Host smart-e84e2a2e-4e8e-4f6c-a40e-b72ff05c550a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027264744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2027264744
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.935717274
Short name T1074
Test name
Test status
Simulation time 794734535 ps
CPU time 12.58 seconds
Started Aug 12 06:23:07 PM PDT 24
Finished Aug 12 06:23:35 PM PDT 24
Peak memory 215396 kb
Host smart-dc7d9a48-a232-4d88-99f5-5ca1bb8f7f83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935717274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.935717274
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.632105179
Short name T69
Test name
Test status
Simulation time 271980096 ps
CPU time 1.21 seconds
Started Aug 12 06:23:02 PM PDT 24
Finished Aug 12 06:23:03 PM PDT 24
Peak memory 206848 kb
Host smart-5f4fdaf6-d3ae-4200-8783-e6c3df09ee6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632105179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.632105179
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2271266319
Short name T1030
Test name
Test status
Simulation time 30794696 ps
CPU time 1.99 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 216624 kb
Host smart-9e92dfde-217f-48e6-af55-0cd667f7efd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271266319 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2271266319
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3258289238
Short name T118
Test name
Test status
Simulation time 150088558 ps
CPU time 2.1 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 207228 kb
Host smart-ac969eea-08f6-4c77-8d03-e5ef62fdcd68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258289238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
258289238
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2679919971
Short name T1021
Test name
Test status
Simulation time 16799777 ps
CPU time 0.74 seconds
Started Aug 12 06:23:04 PM PDT 24
Finished Aug 12 06:23:05 PM PDT 24
Peak memory 204012 kb
Host smart-389609b7-8372-463e-b640-15a5399b49bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679919971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
679919971
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2210678027
Short name T110
Test name
Test status
Simulation time 76198415 ps
CPU time 1.7 seconds
Started Aug 12 06:23:03 PM PDT 24
Finished Aug 12 06:23:04 PM PDT 24
Peak memory 215444 kb
Host smart-ab6c7634-f462-4e3b-8b48-cf1275685f39
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210678027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2210678027
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3434165371
Short name T1024
Test name
Test status
Simulation time 51294612 ps
CPU time 0.67 seconds
Started Aug 12 06:23:06 PM PDT 24
Finished Aug 12 06:23:07 PM PDT 24
Peak memory 203920 kb
Host smart-4a8acd9c-6914-4cdc-9f75-2f6b278652ec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434165371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3434165371
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.601219553
Short name T1014
Test name
Test status
Simulation time 30068193 ps
CPU time 1.77 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 215412 kb
Host smart-04c96283-b2e7-4718-bd0c-9d000a6f3dbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601219553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.601219553
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.931738789
Short name T92
Test name
Test status
Simulation time 81470129 ps
CPU time 2.59 seconds
Started Aug 12 06:22:59 PM PDT 24
Finished Aug 12 06:23:01 PM PDT 24
Peak memory 215660 kb
Host smart-60511c9a-3990-450a-9b20-0a76ff35bbd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931738789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.931738789
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2131663897
Short name T151
Test name
Test status
Simulation time 359820612 ps
CPU time 8.63 seconds
Started Aug 12 06:23:10 PM PDT 24
Finished Aug 12 06:23:19 PM PDT 24
Peak memory 223684 kb
Host smart-08f2e244-d4a3-4150-ab5d-815ffe00fa7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131663897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2131663897
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.486093175
Short name T1073
Test name
Test status
Simulation time 32127776 ps
CPU time 0.76 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 203952 kb
Host smart-c55aa911-54b7-4e71-9743-d5fc46321d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486093175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.486093175
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1606390869
Short name T1035
Test name
Test status
Simulation time 72858611 ps
CPU time 0.7 seconds
Started Aug 12 06:23:22 PM PDT 24
Finished Aug 12 06:23:23 PM PDT 24
Peak memory 204036 kb
Host smart-65a1e24c-59d8-4499-ad0c-21187d4e931c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606390869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1606390869
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3457148405
Short name T1120
Test name
Test status
Simulation time 14368125 ps
CPU time 0.68 seconds
Started Aug 12 06:23:22 PM PDT 24
Finished Aug 12 06:23:23 PM PDT 24
Peak memory 204052 kb
Host smart-0ba0fd13-a35c-4047-aef6-dad762bea4d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457148405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3457148405
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3846833633
Short name T1101
Test name
Test status
Simulation time 42055249 ps
CPU time 0.73 seconds
Started Aug 12 06:23:23 PM PDT 24
Finished Aug 12 06:23:24 PM PDT 24
Peak memory 203996 kb
Host smart-5f1b249c-7cc8-4d66-9d3b-12e0a177304b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846833633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3846833633
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2621131084
Short name T1041
Test name
Test status
Simulation time 16999031 ps
CPU time 0.72 seconds
Started Aug 12 06:23:19 PM PDT 24
Finished Aug 12 06:23:20 PM PDT 24
Peak memory 204056 kb
Host smart-50b2b683-2562-4fce-bc72-f04ba41ad5cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621131084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2621131084
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1370469900
Short name T1045
Test name
Test status
Simulation time 14113219 ps
CPU time 0.76 seconds
Started Aug 12 06:23:32 PM PDT 24
Finished Aug 12 06:23:33 PM PDT 24
Peak memory 204192 kb
Host smart-5ba74219-66e4-42d3-9383-3290f46d6a77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370469900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1370469900
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2789059467
Short name T1060
Test name
Test status
Simulation time 115294836 ps
CPU time 0.72 seconds
Started Aug 12 06:23:18 PM PDT 24
Finished Aug 12 06:23:19 PM PDT 24
Peak memory 204360 kb
Host smart-e8682916-e8c5-4977-80cd-ead0be22392e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789059467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2789059467
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3576318090
Short name T1034
Test name
Test status
Simulation time 14769256 ps
CPU time 0.75 seconds
Started Aug 12 06:23:40 PM PDT 24
Finished Aug 12 06:23:41 PM PDT 24
Peak memory 204028 kb
Host smart-64f73acc-61d4-442f-a640-69c8bdc74101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576318090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3576318090
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1516965003
Short name T1103
Test name
Test status
Simulation time 11845053 ps
CPU time 0.75 seconds
Started Aug 12 06:23:35 PM PDT 24
Finished Aug 12 06:23:36 PM PDT 24
Peak memory 204308 kb
Host smart-89a71873-8aad-4b2b-bade-8e8e2b8eba4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516965003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1516965003
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2362390800
Short name T1062
Test name
Test status
Simulation time 87418710 ps
CPU time 0.72 seconds
Started Aug 12 06:23:16 PM PDT 24
Finished Aug 12 06:23:17 PM PDT 24
Peak memory 204412 kb
Host smart-b3c48994-fbe9-47f0-9f6b-7295d2853e6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362390800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2362390800
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3764430439
Short name T117
Test name
Test status
Simulation time 3758873188 ps
CPU time 23.89 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:36 PM PDT 24
Peak memory 215440 kb
Host smart-6acd0f03-6d7c-4f1f-a2d7-9042ced8356f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764430439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3764430439
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1641257527
Short name T1013
Test name
Test status
Simulation time 1212282253 ps
CPU time 24.64 seconds
Started Aug 12 06:22:58 PM PDT 24
Finished Aug 12 06:23:23 PM PDT 24
Peak memory 207236 kb
Host smart-4e42d748-ee06-4fa1-be07-3f3b30bf73c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641257527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1641257527
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3345030547
Short name T68
Test name
Test status
Simulation time 19281154 ps
CPU time 1.14 seconds
Started Aug 12 06:23:05 PM PDT 24
Finished Aug 12 06:23:06 PM PDT 24
Peak memory 207260 kb
Host smart-acc8b446-f794-47cd-baf3-cc6672ce27c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345030547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3345030547
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.790564650
Short name T1059
Test name
Test status
Simulation time 106686353 ps
CPU time 2.71 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:15 PM PDT 24
Peak memory 218028 kb
Host smart-2d09b244-b937-4c39-b61a-85417464d803
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790564650 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.790564650
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1290815692
Short name T1094
Test name
Test status
Simulation time 64426086 ps
CPU time 1.3 seconds
Started Aug 12 06:23:09 PM PDT 24
Finished Aug 12 06:23:11 PM PDT 24
Peak memory 215560 kb
Host smart-d4b6921d-9033-4691-ad16-9f3f2af52481
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290815692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
290815692
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3527034045
Short name T1032
Test name
Test status
Simulation time 20067071 ps
CPU time 0.7 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:12 PM PDT 24
Peak memory 204016 kb
Host smart-ed2138da-0910-45a6-9cb2-f013095979a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527034045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
527034045
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3299104101
Short name T1124
Test name
Test status
Simulation time 69220857 ps
CPU time 1.25 seconds
Started Aug 12 06:23:04 PM PDT 24
Finished Aug 12 06:23:05 PM PDT 24
Peak memory 215488 kb
Host smart-1742d59c-db4e-4fd2-adc5-41e1542a23b4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299104101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3299104101
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1473760704
Short name T1061
Test name
Test status
Simulation time 155101528 ps
CPU time 0.67 seconds
Started Aug 12 06:23:05 PM PDT 24
Finished Aug 12 06:23:05 PM PDT 24
Peak memory 204248 kb
Host smart-d9cf61cf-8706-4d9d-a18c-0140038b47a5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473760704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1473760704
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.891701046
Short name T1084
Test name
Test status
Simulation time 832896620 ps
CPU time 2.68 seconds
Started Aug 12 06:22:57 PM PDT 24
Finished Aug 12 06:23:00 PM PDT 24
Peak memory 215460 kb
Host smart-3e51488f-f9e7-4e2b-a497-09c9269c2575
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891701046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.891701046
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2099893733
Short name T1109
Test name
Test status
Simulation time 61294447 ps
CPU time 1.91 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 216516 kb
Host smart-ddecc0c2-e0cb-4b23-a620-f8797ac36cbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099893733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
099893733
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2649019349
Short name T166
Test name
Test status
Simulation time 1619764636 ps
CPU time 7.93 seconds
Started Aug 12 06:23:00 PM PDT 24
Finished Aug 12 06:23:08 PM PDT 24
Peak memory 216200 kb
Host smart-10bde779-b142-4f6b-8e5b-97f2d1bb35c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649019349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2649019349
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.562913328
Short name T1131
Test name
Test status
Simulation time 11891567 ps
CPU time 0.69 seconds
Started Aug 12 06:23:28 PM PDT 24
Finished Aug 12 06:23:29 PM PDT 24
Peak memory 203944 kb
Host smart-63b39944-83e1-48ad-aa84-fe02b7a90bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562913328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.562913328
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3343741125
Short name T1065
Test name
Test status
Simulation time 21095310 ps
CPU time 0.7 seconds
Started Aug 12 06:23:20 PM PDT 24
Finished Aug 12 06:23:21 PM PDT 24
Peak memory 204044 kb
Host smart-cf6a40c6-4a07-4d4c-87e0-3b86b61a8cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343741125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3343741125
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2516436314
Short name T1087
Test name
Test status
Simulation time 44340432 ps
CPU time 0.69 seconds
Started Aug 12 06:23:16 PM PDT 24
Finished Aug 12 06:23:17 PM PDT 24
Peak memory 204052 kb
Host smart-b90fe92e-57a2-40d0-a7da-10042ccab64d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516436314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2516436314
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3372660182
Short name T1020
Test name
Test status
Simulation time 69810500 ps
CPU time 0.7 seconds
Started Aug 12 06:23:15 PM PDT 24
Finished Aug 12 06:23:15 PM PDT 24
Peak memory 204004 kb
Host smart-c6293fdb-bb28-4773-abac-9de2dc192721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372660182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3372660182
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.880668661
Short name T1088
Test name
Test status
Simulation time 13740861 ps
CPU time 0.74 seconds
Started Aug 12 06:23:34 PM PDT 24
Finished Aug 12 06:23:35 PM PDT 24
Peak memory 204392 kb
Host smart-5e9fc524-7e20-4d58-9c84-10e1175ffa67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880668661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.880668661
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2723754933
Short name T1055
Test name
Test status
Simulation time 28223078 ps
CPU time 0.75 seconds
Started Aug 12 06:23:34 PM PDT 24
Finished Aug 12 06:23:35 PM PDT 24
Peak memory 203952 kb
Host smart-9f9dc234-5d11-41d3-b79d-af5050e350e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723754933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2723754933
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3869006269
Short name T1039
Test name
Test status
Simulation time 16443418 ps
CPU time 0.74 seconds
Started Aug 12 06:23:14 PM PDT 24
Finished Aug 12 06:23:15 PM PDT 24
Peak memory 204368 kb
Host smart-922660b8-4d85-408e-b876-a34593b8ad4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869006269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3869006269
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.80066872
Short name T1095
Test name
Test status
Simulation time 83447072 ps
CPU time 0.69 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 204048 kb
Host smart-1ac1d804-7456-43f0-aabf-7f40dd67cdd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80066872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.80066872
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3360337702
Short name T1044
Test name
Test status
Simulation time 57487380 ps
CPU time 0.7 seconds
Started Aug 12 06:23:16 PM PDT 24
Finished Aug 12 06:23:17 PM PDT 24
Peak memory 204056 kb
Host smart-e70cc81a-6705-42e6-bfc5-16be5112877b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360337702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3360337702
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.973301791
Short name T1069
Test name
Test status
Simulation time 28606037 ps
CPU time 0.74 seconds
Started Aug 12 06:23:28 PM PDT 24
Finished Aug 12 06:23:29 PM PDT 24
Peak memory 204040 kb
Host smart-bf9e691a-fdb7-499f-89d2-0fdf28856b0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973301791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.973301791
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3819104858
Short name T1093
Test name
Test status
Simulation time 42293635 ps
CPU time 2.92 seconds
Started Aug 12 06:23:03 PM PDT 24
Finished Aug 12 06:23:06 PM PDT 24
Peak memory 217264 kb
Host smart-26eeb56c-4b3a-4082-87e5-a0b0c26c378b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819104858 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3819104858
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3935391415
Short name T1063
Test name
Test status
Simulation time 38236029 ps
CPU time 1.33 seconds
Started Aug 12 06:23:15 PM PDT 24
Finished Aug 12 06:23:16 PM PDT 24
Peak memory 215424 kb
Host smart-1b87bc7d-3cfb-4a3d-ade7-b5f12d74b31b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935391415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
935391415
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1778440869
Short name T1017
Test name
Test status
Simulation time 12102709 ps
CPU time 0.73 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:12 PM PDT 24
Peak memory 204056 kb
Host smart-26459851-1c30-4271-9d5c-7e85d1c03c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778440869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
778440869
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2782669279
Short name T1077
Test name
Test status
Simulation time 236195757 ps
CPU time 2.93 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 215484 kb
Host smart-591104b9-48fc-461f-b5a9-60a6f9ed0419
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782669279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2782669279
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2378605786
Short name T164
Test name
Test status
Simulation time 1004002295 ps
CPU time 18.2 seconds
Started Aug 12 06:23:05 PM PDT 24
Finished Aug 12 06:23:23 PM PDT 24
Peak memory 215628 kb
Host smart-737aa070-8d15-4a03-9f71-bd297e5ecc20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378605786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2378605786
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2198280989
Short name T95
Test name
Test status
Simulation time 800537283 ps
CPU time 2.67 seconds
Started Aug 12 06:23:02 PM PDT 24
Finished Aug 12 06:23:04 PM PDT 24
Peak memory 216672 kb
Host smart-be47f759-7e7b-40a2-ac41-331e295864ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198280989 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2198280989
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3287665124
Short name T115
Test name
Test status
Simulation time 100008354 ps
CPU time 1.33 seconds
Started Aug 12 06:23:05 PM PDT 24
Finished Aug 12 06:23:07 PM PDT 24
Peak memory 215496 kb
Host smart-959fa343-9a05-4bc1-9950-75a3c1e04549
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287665124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
287665124
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3196646539
Short name T1085
Test name
Test status
Simulation time 15405413 ps
CPU time 0.75 seconds
Started Aug 12 06:23:22 PM PDT 24
Finished Aug 12 06:23:23 PM PDT 24
Peak memory 204364 kb
Host smart-fe3ecfd8-222f-46c4-902b-402b841ef3d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196646539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
196646539
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3323809164
Short name T1027
Test name
Test status
Simulation time 92347432 ps
CPU time 3.73 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:15 PM PDT 24
Peak memory 215580 kb
Host smart-2490c7c8-7024-4f80-a832-9812dd506038
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323809164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3323809164
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2286774770
Short name T88
Test name
Test status
Simulation time 76273525 ps
CPU time 4.69 seconds
Started Aug 12 06:23:03 PM PDT 24
Finished Aug 12 06:23:08 PM PDT 24
Peak memory 215584 kb
Host smart-0b6e65f7-821f-41dc-b2ae-beb4a2de1038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286774770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
286774770
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2335737830
Short name T1078
Test name
Test status
Simulation time 3595893214 ps
CPU time 18.82 seconds
Started Aug 12 06:22:59 PM PDT 24
Finished Aug 12 06:23:18 PM PDT 24
Peak memory 215824 kb
Host smart-62e4f1a5-7826-42c1-b81c-d0e31ea1e7af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335737830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2335737830
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3777326858
Short name T1075
Test name
Test status
Simulation time 400650862 ps
CPU time 1.86 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 215640 kb
Host smart-0ecafcae-7b3a-45d4-8a3b-2771e592e30e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777326858 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3777326858
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2944767197
Short name T1019
Test name
Test status
Simulation time 275998692 ps
CPU time 2.37 seconds
Started Aug 12 06:23:00 PM PDT 24
Finished Aug 12 06:23:03 PM PDT 24
Peak memory 215456 kb
Host smart-297d90fd-fa62-4eed-8fb9-456cc6a4018a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944767197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
944767197
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3602369664
Short name T1022
Test name
Test status
Simulation time 22456485 ps
CPU time 0.75 seconds
Started Aug 12 06:23:05 PM PDT 24
Finished Aug 12 06:23:06 PM PDT 24
Peak memory 204088 kb
Host smart-5c4d5b1c-c875-4965-b0da-1449d933b634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602369664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
602369664
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3859065302
Short name T1023
Test name
Test status
Simulation time 27651443 ps
CPU time 1.68 seconds
Started Aug 12 06:23:05 PM PDT 24
Finished Aug 12 06:23:07 PM PDT 24
Peak memory 207316 kb
Host smart-1f228793-2a01-4536-934e-730a14664c64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859065302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3859065302
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.626165074
Short name T84
Test name
Test status
Simulation time 57321564 ps
CPU time 1.55 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 215648 kb
Host smart-9d0b4d44-de51-4283-b92b-34d185cc6e8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626165074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.626165074
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3726708353
Short name T83
Test name
Test status
Simulation time 2682520017 ps
CPU time 14.93 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:26 PM PDT 24
Peak memory 215952 kb
Host smart-ef77949b-aaad-4676-8591-30bf64de3809
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726708353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3726708353
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3002410483
Short name T1112
Test name
Test status
Simulation time 614542489 ps
CPU time 3.61 seconds
Started Aug 12 06:23:06 PM PDT 24
Finished Aug 12 06:23:10 PM PDT 24
Peak memory 217628 kb
Host smart-1275a007-4432-4404-9e31-5441c3ab03b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002410483 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3002410483
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1843529236
Short name T1100
Test name
Test status
Simulation time 366987909 ps
CPU time 2.71 seconds
Started Aug 12 06:23:11 PM PDT 24
Finished Aug 12 06:23:14 PM PDT 24
Peak memory 215388 kb
Host smart-e8bddd99-4d54-45f7-8ef7-69f4946b0ea6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843529236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
843529236
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1371883968
Short name T1008
Test name
Test status
Simulation time 21266554 ps
CPU time 0.71 seconds
Started Aug 12 06:23:06 PM PDT 24
Finished Aug 12 06:23:06 PM PDT 24
Peak memory 204380 kb
Host smart-3152e9f0-6776-43f3-9c46-602cf835675d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371883968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
371883968
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2409274745
Short name T1092
Test name
Test status
Simulation time 92912454 ps
CPU time 3 seconds
Started Aug 12 06:23:10 PM PDT 24
Finished Aug 12 06:23:13 PM PDT 24
Peak memory 215512 kb
Host smart-0c589066-edfd-49de-9e77-2ea02c8e4a12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409274745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2409274745
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2979727635
Short name T1113
Test name
Test status
Simulation time 3256765781 ps
CPU time 3.97 seconds
Started Aug 12 06:23:17 PM PDT 24
Finished Aug 12 06:23:21 PM PDT 24
Peak memory 215632 kb
Host smart-985d6135-b204-4698-bea8-a7312f24e268
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979727635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
979727635
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.173866877
Short name T1048
Test name
Test status
Simulation time 1165917454 ps
CPU time 15.01 seconds
Started Aug 12 06:22:57 PM PDT 24
Finished Aug 12 06:23:12 PM PDT 24
Peak memory 216204 kb
Host smart-a039f1ca-a70e-48e9-aeb7-d69abc154a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173866877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.173866877
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.380572389
Short name T98
Test name
Test status
Simulation time 521667998 ps
CPU time 2.49 seconds
Started Aug 12 06:23:12 PM PDT 24
Finished Aug 12 06:23:15 PM PDT 24
Peak memory 217840 kb
Host smart-a180c971-6490-4862-98a3-478f4ce737f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380572389 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.380572389
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1623288527
Short name T1096
Test name
Test status
Simulation time 67656511 ps
CPU time 1.24 seconds
Started Aug 12 06:23:31 PM PDT 24
Finished Aug 12 06:23:32 PM PDT 24
Peak memory 207188 kb
Host smart-9033fa04-30d4-452e-85c6-9f3bd4ef2e5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623288527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
623288527
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.800897631
Short name T1111
Test name
Test status
Simulation time 17041094 ps
CPU time 0.72 seconds
Started Aug 12 06:23:10 PM PDT 24
Finished Aug 12 06:23:11 PM PDT 24
Peak memory 204084 kb
Host smart-60050e59-c412-4498-a84f-369b27a4a709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800897631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.800897631
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2371778711
Short name T1049
Test name
Test status
Simulation time 439309831 ps
CPU time 1.91 seconds
Started Aug 12 06:23:09 PM PDT 24
Finished Aug 12 06:23:11 PM PDT 24
Peak memory 215524 kb
Host smart-3f90151c-8ffc-4351-aaf2-c0772a2f8528
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371778711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2371778711
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3126794578
Short name T57
Test name
Test status
Simulation time 574639107 ps
CPU time 3.63 seconds
Started Aug 12 06:23:13 PM PDT 24
Finished Aug 12 06:23:17 PM PDT 24
Peak memory 215620 kb
Host smart-be8fe4d9-43d6-4eac-aaa2-c508aa0f7c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126794578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
126794578
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2464264266
Short name T161
Test name
Test status
Simulation time 234593221 ps
CPU time 6.11 seconds
Started Aug 12 06:22:59 PM PDT 24
Finished Aug 12 06:23:05 PM PDT 24
Peak memory 215900 kb
Host smart-1e80d46f-281c-4acf-91ff-a49718337a48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464264266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2464264266
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2959783020
Short name T464
Test name
Test status
Simulation time 37302501 ps
CPU time 0.7 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:24:06 PM PDT 24
Peak memory 205856 kb
Host smart-4f6568b8-9436-4489-82d7-2f9674ce3b6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959783020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
959783020
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.742103992
Short name T837
Test name
Test status
Simulation time 3874513889 ps
CPU time 21.49 seconds
Started Aug 12 06:24:00 PM PDT 24
Finished Aug 12 06:24:22 PM PDT 24
Peak memory 225636 kb
Host smart-88773542-5a6b-48e8-9e66-6c023ccfe16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742103992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.742103992
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2227801914
Short name T930
Test name
Test status
Simulation time 71202181 ps
CPU time 0.79 seconds
Started Aug 12 06:23:59 PM PDT 24
Finished Aug 12 06:24:00 PM PDT 24
Peak memory 207612 kb
Host smart-59bff92b-5aee-4770-b2aa-1ec943674585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227801914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2227801914
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4198769214
Short name T747
Test name
Test status
Simulation time 14595088771 ps
CPU time 25.04 seconds
Started Aug 12 06:23:50 PM PDT 24
Finished Aug 12 06:24:15 PM PDT 24
Peak memory 241344 kb
Host smart-f4fb44c9-98a8-48b4-9ee9-e4ceafffe916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198769214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4198769214
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1446824782
Short name T25
Test name
Test status
Simulation time 46075906175 ps
CPU time 100.46 seconds
Started Aug 12 06:23:59 PM PDT 24
Finished Aug 12 06:25:39 PM PDT 24
Peak memory 257648 kb
Host smart-dbd35bc1-62d8-4433-bdb4-ce87dcc68753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446824782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1446824782
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2673450365
Short name T732
Test name
Test status
Simulation time 152566574113 ps
CPU time 164.25 seconds
Started Aug 12 06:23:49 PM PDT 24
Finished Aug 12 06:26:33 PM PDT 24
Peak memory 258372 kb
Host smart-3ab6a7ef-2317-411a-af77-9f8d53ff6eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673450365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2673450365
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.367232789
Short name T371
Test name
Test status
Simulation time 3608743647 ps
CPU time 26.13 seconds
Started Aug 12 06:23:57 PM PDT 24
Finished Aug 12 06:24:23 PM PDT 24
Peak memory 238416 kb
Host smart-7e8bf21f-b127-4ac3-9e58-ae0e520ae10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367232789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.367232789
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2571190285
Short name T802
Test name
Test status
Simulation time 25435261285 ps
CPU time 58.43 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:25:04 PM PDT 24
Peak memory 250264 kb
Host smart-6c7ae8b3-9726-4c94-8070-0c2618231e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571190285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2571190285
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2568899881
Short name T453
Test name
Test status
Simulation time 395555248 ps
CPU time 4.53 seconds
Started Aug 12 06:24:02 PM PDT 24
Finished Aug 12 06:24:08 PM PDT 24
Peak memory 233832 kb
Host smart-a3a5fd32-5ea0-4600-b436-9d4734220c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568899881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2568899881
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3227563660
Short name T659
Test name
Test status
Simulation time 20026918284 ps
CPU time 75.16 seconds
Started Aug 12 06:23:52 PM PDT 24
Finished Aug 12 06:25:07 PM PDT 24
Peak memory 220068 kb
Host smart-c184acbf-1348-44f0-b477-37c1c1f5a729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227563660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3227563660
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.473372139
Short name T236
Test name
Test status
Simulation time 1725516663 ps
CPU time 8.81 seconds
Started Aug 12 06:23:56 PM PDT 24
Finished Aug 12 06:24:05 PM PDT 24
Peak memory 233676 kb
Host smart-c778c0f7-f2dd-4ab3-b009-a72ad9ff7c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473372139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
473372139
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.4096713016
Short name T636
Test name
Test status
Simulation time 869013662 ps
CPU time 9.16 seconds
Started Aug 12 06:23:56 PM PDT 24
Finished Aug 12 06:24:05 PM PDT 24
Peak memory 224128 kb
Host smart-2e74f5f6-ebb7-4965-8cb8-87dc9ce8a2f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4096713016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.4096713016
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1713600469
Short name T62
Test name
Test status
Simulation time 250930381 ps
CPU time 1.22 seconds
Started Aug 12 06:24:02 PM PDT 24
Finished Aug 12 06:24:04 PM PDT 24
Peak memory 236404 kb
Host smart-132d5578-098c-49ac-9ea3-a9497ba877e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713600469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1713600469
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.386842977
Short name T173
Test name
Test status
Simulation time 3773801083 ps
CPU time 74.79 seconds
Started Aug 12 06:24:02 PM PDT 24
Finished Aug 12 06:25:17 PM PDT 24
Peak memory 257388 kb
Host smart-f54acfd6-852b-454a-9c03-a3894f19df16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386842977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.386842977
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3465637820
Short name T601
Test name
Test status
Simulation time 14275124 ps
CPU time 0.78 seconds
Started Aug 12 06:24:01 PM PDT 24
Finished Aug 12 06:24:02 PM PDT 24
Peak memory 206736 kb
Host smart-ba1bf1f5-bff4-45a8-bece-2570c0389d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465637820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3465637820
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3075423738
Short name T305
Test name
Test status
Simulation time 7015202751 ps
CPU time 5.49 seconds
Started Aug 12 06:23:57 PM PDT 24
Finished Aug 12 06:24:08 PM PDT 24
Peak memory 217472 kb
Host smart-54cb149c-4696-4981-b1aa-505e3e514b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075423738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3075423738
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2658810581
Short name T128
Test name
Test status
Simulation time 46131657 ps
CPU time 2.14 seconds
Started Aug 12 06:24:03 PM PDT 24
Finished Aug 12 06:24:06 PM PDT 24
Peak memory 217324 kb
Host smart-4a10952c-ca3a-4389-b1e6-0cfb760655d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658810581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2658810581
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2689034449
Short name T4
Test name
Test status
Simulation time 369354131 ps
CPU time 0.91 seconds
Started Aug 12 06:24:01 PM PDT 24
Finished Aug 12 06:24:02 PM PDT 24
Peak memory 206980 kb
Host smart-53d1d310-600d-4e99-a7c6-e9e6f936c4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689034449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2689034449
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1445289280
Short name T620
Test name
Test status
Simulation time 289877660 ps
CPU time 4.56 seconds
Started Aug 12 06:24:08 PM PDT 24
Finished Aug 12 06:24:13 PM PDT 24
Peak memory 225544 kb
Host smart-9ae8deeb-116f-4202-9078-3fc08b533307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445289280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1445289280
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.698465063
Short name T377
Test name
Test status
Simulation time 14785441 ps
CPU time 0.73 seconds
Started Aug 12 06:24:20 PM PDT 24
Finished Aug 12 06:24:20 PM PDT 24
Peak memory 205880 kb
Host smart-5cc19632-d489-4a9f-bfc2-9039c6eb45d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698465063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.698465063
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3339158325
Short name T613
Test name
Test status
Simulation time 18944415 ps
CPU time 0.78 seconds
Started Aug 12 06:24:10 PM PDT 24
Finished Aug 12 06:24:11 PM PDT 24
Peak memory 206932 kb
Host smart-af8f2193-e74e-4468-85fe-4b8a7e6d5d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339158325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3339158325
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.204705406
Short name T563
Test name
Test status
Simulation time 657798480 ps
CPU time 12.06 seconds
Started Aug 12 06:23:58 PM PDT 24
Finished Aug 12 06:24:10 PM PDT 24
Peak memory 241724 kb
Host smart-1583566d-c93c-4593-ae87-f27d2be70609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204705406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.204705406
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3128174830
Short name T432
Test name
Test status
Simulation time 4384423677 ps
CPU time 31 seconds
Started Aug 12 06:24:03 PM PDT 24
Finished Aug 12 06:24:34 PM PDT 24
Peak memory 241076 kb
Host smart-3b1537bf-2732-49cd-971f-1a9550d0bf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128174830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3128174830
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.4221099652
Short name T579
Test name
Test status
Simulation time 112344398 ps
CPU time 0.93 seconds
Started Aug 12 06:24:02 PM PDT 24
Finished Aug 12 06:24:04 PM PDT 24
Peak memory 218204 kb
Host smart-07fb7572-6259-4f91-a489-9606832709eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221099652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.4221099652
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.581911373
Short name T482
Test name
Test status
Simulation time 3366119381 ps
CPU time 43.65 seconds
Started Aug 12 06:24:06 PM PDT 24
Finished Aug 12 06:24:50 PM PDT 24
Peak memory 234728 kb
Host smart-1809c71d-dd44-48e3-ba01-53cd8b13d31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581911373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.581911373
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.783430625
Short name T787
Test name
Test status
Simulation time 51539514202 ps
CPU time 151.43 seconds
Started Aug 12 06:24:08 PM PDT 24
Finished Aug 12 06:26:40 PM PDT 24
Peak memory 268244 kb
Host smart-b7d1d679-78e4-44cb-8e4b-cf8da6531e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783430625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
783430625
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.415068441
Short name T352
Test name
Test status
Simulation time 62549408 ps
CPU time 2.23 seconds
Started Aug 12 06:24:08 PM PDT 24
Finished Aug 12 06:24:11 PM PDT 24
Peak memory 233496 kb
Host smart-5c4553be-8075-4a36-b2a0-0a54f9943cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415068441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.415068441
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1276414
Short name T862
Test name
Test status
Simulation time 5481320173 ps
CPU time 24.18 seconds
Started Aug 12 06:24:12 PM PDT 24
Finished Aug 12 06:24:37 PM PDT 24
Peak memory 242040 kb
Host smart-26d9f472-aada-4ac4-a9b1-8c453ffa6220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1276414
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1694701648
Short name T321
Test name
Test status
Simulation time 180438875 ps
CPU time 2.81 seconds
Started Aug 12 06:24:03 PM PDT 24
Finished Aug 12 06:24:06 PM PDT 24
Peak memory 225512 kb
Host smart-8c209b0c-0b8d-4f41-8556-225a1bebb4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694701648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1694701648
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.945666203
Short name T425
Test name
Test status
Simulation time 7628244522 ps
CPU time 20.03 seconds
Started Aug 12 06:24:02 PM PDT 24
Finished Aug 12 06:24:22 PM PDT 24
Peak memory 233872 kb
Host smart-5cf9a32a-92ff-4a99-a571-f9bd9da192b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945666203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.945666203
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.49511490
Short name T582
Test name
Test status
Simulation time 1012971487 ps
CPU time 13.01 seconds
Started Aug 12 06:24:22 PM PDT 24
Finished Aug 12 06:24:36 PM PDT 24
Peak memory 220924 kb
Host smart-9cb3f74c-2489-43ea-aa34-bcbb1382826c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=49511490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct
.49511490
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2595920884
Short name T63
Test name
Test status
Simulation time 148798777 ps
CPU time 0.96 seconds
Started Aug 12 06:24:20 PM PDT 24
Finished Aug 12 06:24:21 PM PDT 24
Peak memory 237368 kb
Host smart-42152429-8ad4-4832-bcc0-381c6b8b784a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595920884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2595920884
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2573812965
Short name T152
Test name
Test status
Simulation time 11426943343 ps
CPU time 36.31 seconds
Started Aug 12 06:24:08 PM PDT 24
Finished Aug 12 06:24:45 PM PDT 24
Peak memory 250372 kb
Host smart-4da34bc4-66a4-4531-ab29-53b5cc6204c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573812965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2573812965
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2026176092
Short name T548
Test name
Test status
Simulation time 7566608028 ps
CPU time 37.11 seconds
Started Aug 12 06:23:57 PM PDT 24
Finished Aug 12 06:24:35 PM PDT 24
Peak memory 217488 kb
Host smart-ccda8a91-2705-4ba0-883d-d7a80b85ab10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026176092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2026176092
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.12660075
Short name T687
Test name
Test status
Simulation time 6083885741 ps
CPU time 14.2 seconds
Started Aug 12 06:24:00 PM PDT 24
Finished Aug 12 06:24:19 PM PDT 24
Peak memory 217384 kb
Host smart-9c3c4c6e-951a-4166-aba2-3606e42d0918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12660075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.12660075
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.337246256
Short name T818
Test name
Test status
Simulation time 54037080 ps
CPU time 0.67 seconds
Started Aug 12 06:24:07 PM PDT 24
Finished Aug 12 06:24:08 PM PDT 24
Peak memory 206716 kb
Host smart-306959b2-53a5-43e3-89a9-4d3c29486d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337246256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.337246256
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2682199611
Short name T538
Test name
Test status
Simulation time 101516499 ps
CPU time 0.87 seconds
Started Aug 12 06:24:09 PM PDT 24
Finished Aug 12 06:24:10 PM PDT 24
Peak memory 206968 kb
Host smart-a1196087-1f2e-4b6a-ba10-a58789b657fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682199611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2682199611
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2990626509
Short name T751
Test name
Test status
Simulation time 3686321836 ps
CPU time 9.95 seconds
Started Aug 12 06:24:08 PM PDT 24
Finished Aug 12 06:24:19 PM PDT 24
Peak memory 242096 kb
Host smart-d56ad1f8-8849-49ac-9e6e-3468a3f8578d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990626509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2990626509
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1477475637
Short name T479
Test name
Test status
Simulation time 14375291 ps
CPU time 0.7 seconds
Started Aug 12 06:24:25 PM PDT 24
Finished Aug 12 06:24:26 PM PDT 24
Peak memory 205796 kb
Host smart-82b0469d-7abc-4457-beab-8af705360d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477475637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1477475637
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1229437535
Short name T573
Test name
Test status
Simulation time 284817797 ps
CPU time 3.19 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:24:09 PM PDT 24
Peak memory 225556 kb
Host smart-c6b51919-5acb-4f58-8353-3753bcaf23a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229437535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1229437535
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1089199560
Short name T449
Test name
Test status
Simulation time 12301225 ps
CPU time 0.74 seconds
Started Aug 12 06:24:14 PM PDT 24
Finished Aug 12 06:24:15 PM PDT 24
Peak memory 206576 kb
Host smart-5a5248db-8351-4be3-a439-cb8f82f38e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089199560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1089199560
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.813041791
Short name T729
Test name
Test status
Simulation time 28924959956 ps
CPU time 218.88 seconds
Started Aug 12 06:24:16 PM PDT 24
Finished Aug 12 06:27:55 PM PDT 24
Peak memory 251292 kb
Host smart-be8e586e-2352-4f2a-8a6b-6d982e599f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813041791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.813041791
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1954691989
Short name T437
Test name
Test status
Simulation time 51634631217 ps
CPU time 106.95 seconds
Started Aug 12 06:24:03 PM PDT 24
Finished Aug 12 06:25:51 PM PDT 24
Peak memory 256572 kb
Host smart-ce4558ba-8e56-4c38-9d5c-ad8cae09f9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954691989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1954691989
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2129094100
Short name T40
Test name
Test status
Simulation time 3690834543 ps
CPU time 89.35 seconds
Started Aug 12 06:24:25 PM PDT 24
Finished Aug 12 06:25:55 PM PDT 24
Peak memory 268800 kb
Host smart-175e054b-fad6-478b-97e6-e8b3e485dd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129094100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2129094100
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.515961004
Short name T622
Test name
Test status
Simulation time 18002121627 ps
CPU time 33.85 seconds
Started Aug 12 06:24:15 PM PDT 24
Finished Aug 12 06:24:49 PM PDT 24
Peak memory 242112 kb
Host smart-8d026f4d-8a74-418d-9c8d-ae4bc38d1bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515961004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.515961004
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.456375301
Short name T252
Test name
Test status
Simulation time 51465433197 ps
CPU time 338.34 seconds
Started Aug 12 06:24:18 PM PDT 24
Finished Aug 12 06:29:56 PM PDT 24
Peak memory 256068 kb
Host smart-dab235f8-b292-414b-aea4-7304504be43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456375301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.456375301
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.765286910
Short name T516
Test name
Test status
Simulation time 2152794243 ps
CPU time 21.29 seconds
Started Aug 12 06:24:18 PM PDT 24
Finished Aug 12 06:24:40 PM PDT 24
Peak memory 225800 kb
Host smart-7ebc0dbf-b2dd-4b50-91f0-2e5ab9461ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765286910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.765286910
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1866085395
Short name T929
Test name
Test status
Simulation time 3587064036 ps
CPU time 18.29 seconds
Started Aug 12 06:24:20 PM PDT 24
Finished Aug 12 06:24:38 PM PDT 24
Peak memory 233900 kb
Host smart-cded3d18-4b49-4b22-952b-2e2187d15779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866085395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1866085395
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.469897043
Short name T47
Test name
Test status
Simulation time 394407966 ps
CPU time 5.39 seconds
Started Aug 12 06:24:25 PM PDT 24
Finished Aug 12 06:24:30 PM PDT 24
Peak memory 233804 kb
Host smart-a4b5b7f2-84a4-4a5d-a8ad-db2d8198a41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469897043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.469897043
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1291117859
Short name T665
Test name
Test status
Simulation time 3859712501 ps
CPU time 7.87 seconds
Started Aug 12 06:24:20 PM PDT 24
Finished Aug 12 06:24:30 PM PDT 24
Peak memory 233860 kb
Host smart-d3342e97-f403-44eb-a219-5cd9a207095b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291117859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1291117859
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.459788132
Short name T790
Test name
Test status
Simulation time 209994342 ps
CPU time 3.31 seconds
Started Aug 12 06:24:25 PM PDT 24
Finished Aug 12 06:24:28 PM PDT 24
Peak memory 221516 kb
Host smart-c33e4bb2-e3ae-47f8-9e9f-12acfa51344e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=459788132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.459788132
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1492859168
Short name T196
Test name
Test status
Simulation time 88356393713 ps
CPU time 389.76 seconds
Started Aug 12 06:24:30 PM PDT 24
Finished Aug 12 06:31:00 PM PDT 24
Peak memory 258556 kb
Host smart-afd22d4c-22fc-4ea8-a798-d8e3bceb3e8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492859168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1492859168
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2278774532
Short name T845
Test name
Test status
Simulation time 1646856417 ps
CPU time 19.23 seconds
Started Aug 12 06:24:21 PM PDT 24
Finished Aug 12 06:24:41 PM PDT 24
Peak memory 217576 kb
Host smart-89039446-2c76-4892-96a9-23f5fca7ced2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278774532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2278774532
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.191085160
Short name T430
Test name
Test status
Simulation time 6376341346 ps
CPU time 7.21 seconds
Started Aug 12 06:24:20 PM PDT 24
Finished Aug 12 06:24:27 PM PDT 24
Peak memory 217420 kb
Host smart-989f004a-bee8-4e0d-be08-e19e45a42cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191085160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.191085160
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3212521775
Short name T672
Test name
Test status
Simulation time 68728069 ps
CPU time 0.91 seconds
Started Aug 12 06:24:30 PM PDT 24
Finished Aug 12 06:24:31 PM PDT 24
Peak memory 207984 kb
Host smart-d24cbc2e-c578-491b-b8a3-ba172c61aa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212521775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3212521775
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2689531169
Short name T71
Test name
Test status
Simulation time 117267272 ps
CPU time 1.04 seconds
Started Aug 12 06:24:19 PM PDT 24
Finished Aug 12 06:24:20 PM PDT 24
Peak memory 208056 kb
Host smart-80422d7d-e864-4172-bdb5-986f132555a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689531169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2689531169
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2118019932
Short name T872
Test name
Test status
Simulation time 827662308 ps
CPU time 8.87 seconds
Started Aug 12 06:24:51 PM PDT 24
Finished Aug 12 06:25:00 PM PDT 24
Peak memory 241948 kb
Host smart-22a185e5-f558-4566-9229-400463fdb269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118019932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2118019932
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1839607522
Short name T456
Test name
Test status
Simulation time 17050576 ps
CPU time 0.69 seconds
Started Aug 12 06:24:45 PM PDT 24
Finished Aug 12 06:24:46 PM PDT 24
Peak memory 205916 kb
Host smart-255e1d5f-bd80-404c-9c01-3681f2faa8ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839607522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1839607522
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3184690749
Short name T648
Test name
Test status
Simulation time 47941052 ps
CPU time 2.59 seconds
Started Aug 12 06:24:22 PM PDT 24
Finished Aug 12 06:24:25 PM PDT 24
Peak memory 233792 kb
Host smart-ef24a98b-02c6-49f1-9522-bf2bdad1624e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184690749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3184690749
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4003011901
Short name T344
Test name
Test status
Simulation time 17982647 ps
CPU time 0.79 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:24:06 PM PDT 24
Peak memory 207636 kb
Host smart-07647af7-ec1f-4940-835d-2bf4778c724c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003011901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4003011901
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3685962524
Short name T759
Test name
Test status
Simulation time 19703973465 ps
CPU time 89.24 seconds
Started Aug 12 06:24:27 PM PDT 24
Finished Aug 12 06:25:56 PM PDT 24
Peak memory 256436 kb
Host smart-5b019cb5-039f-491a-9201-0317a2f4b04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685962524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3685962524
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2010413998
Short name T583
Test name
Test status
Simulation time 70337248 ps
CPU time 0.8 seconds
Started Aug 12 06:24:26 PM PDT 24
Finished Aug 12 06:24:27 PM PDT 24
Peak memory 217972 kb
Host smart-772b4fde-3510-44cd-b8b3-4b340dd06b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010413998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2010413998
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.501351633
Short name T258
Test name
Test status
Simulation time 1426365567 ps
CPU time 13.74 seconds
Started Aug 12 06:24:30 PM PDT 24
Finished Aug 12 06:24:44 PM PDT 24
Peak memory 225612 kb
Host smart-75b04b4b-09c8-497b-8116-1d5755f84bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501351633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.501351633
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2914897954
Short name T189
Test name
Test status
Simulation time 4588481464 ps
CPU time 23.35 seconds
Started Aug 12 06:24:24 PM PDT 24
Finished Aug 12 06:24:47 PM PDT 24
Peak memory 242084 kb
Host smart-982b7d96-1a11-4e68-87f0-745d3d8d86b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914897954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2914897954
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1355194048
Short name T495
Test name
Test status
Simulation time 30760098 ps
CPU time 2.07 seconds
Started Aug 12 06:24:24 PM PDT 24
Finished Aug 12 06:24:27 PM PDT 24
Peak memory 224832 kb
Host smart-95d1dc8a-a840-4869-8122-4e8242aba239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355194048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1355194048
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1572233501
Short name T927
Test name
Test status
Simulation time 9710856467 ps
CPU time 23.95 seconds
Started Aug 12 06:24:26 PM PDT 24
Finished Aug 12 06:24:50 PM PDT 24
Peak memory 242080 kb
Host smart-0f91b43f-0795-4741-a508-6353b9316336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572233501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1572233501
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1514844945
Short name T369
Test name
Test status
Simulation time 738055338 ps
CPU time 7.76 seconds
Started Aug 12 06:24:23 PM PDT 24
Finished Aug 12 06:24:41 PM PDT 24
Peak memory 233688 kb
Host smart-3b2b5d7c-2562-4f32-a55a-d897c82e8060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514844945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1514844945
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.4110089761
Short name T211
Test name
Test status
Simulation time 2560241304 ps
CPU time 8.53 seconds
Started Aug 12 06:24:18 PM PDT 24
Finished Aug 12 06:24:26 PM PDT 24
Peak memory 225688 kb
Host smart-961f006d-f6f7-4c8b-be73-b2e9c8b1d258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110089761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.4110089761
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.22657160
Short name T448
Test name
Test status
Simulation time 339607931 ps
CPU time 4.77 seconds
Started Aug 12 06:24:25 PM PDT 24
Finished Aug 12 06:24:30 PM PDT 24
Peak memory 224320 kb
Host smart-9b8de44c-d918-4a0d-b911-79e53e97ce3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=22657160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direc
t.22657160
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2284348778
Short name T816
Test name
Test status
Simulation time 180451543 ps
CPU time 0.92 seconds
Started Aug 12 06:24:36 PM PDT 24
Finished Aug 12 06:24:37 PM PDT 24
Peak memory 206652 kb
Host smart-7f6fff52-7e96-4a06-9e95-11e9f14b5370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284348778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2284348778
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3427423690
Short name T861
Test name
Test status
Simulation time 29532988 ps
CPU time 0.71 seconds
Started Aug 12 06:24:27 PM PDT 24
Finished Aug 12 06:24:28 PM PDT 24
Peak memory 206900 kb
Host smart-7272c988-40c3-40cc-ad66-43ce9ce2024c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427423690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3427423690
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2025302895
Short name T863
Test name
Test status
Simulation time 2242969762 ps
CPU time 4.82 seconds
Started Aug 12 06:24:20 PM PDT 24
Finished Aug 12 06:24:25 PM PDT 24
Peak memory 217412 kb
Host smart-204438db-abe8-410f-be7b-e18a2bdf1149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025302895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2025302895
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2237900235
Short name T745
Test name
Test status
Simulation time 934900291 ps
CPU time 1.25 seconds
Started Aug 12 06:24:19 PM PDT 24
Finished Aug 12 06:24:20 PM PDT 24
Peak memory 209124 kb
Host smart-948bc472-ccaa-4748-95f7-c91ae63e2091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237900235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2237900235
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2082570159
Short name T810
Test name
Test status
Simulation time 229764298 ps
CPU time 0.92 seconds
Started Aug 12 06:24:08 PM PDT 24
Finished Aug 12 06:24:10 PM PDT 24
Peak memory 207000 kb
Host smart-b4a5bfc2-564c-4638-93ad-d9b281241edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082570159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2082570159
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1624253309
Short name T76
Test name
Test status
Simulation time 702547087 ps
CPU time 4.09 seconds
Started Aug 12 06:24:35 PM PDT 24
Finished Aug 12 06:24:40 PM PDT 24
Peak memory 241944 kb
Host smart-b97b51a0-fa5c-4db6-8453-1c2b7320d50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624253309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1624253309
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2131998954
Short name T841
Test name
Test status
Simulation time 40912315 ps
CPU time 0.7 seconds
Started Aug 12 06:24:26 PM PDT 24
Finished Aug 12 06:24:27 PM PDT 24
Peak memory 205852 kb
Host smart-06b56779-8aaa-4974-93e6-a5d80b45f769
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131998954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2131998954
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.540177441
Short name T673
Test name
Test status
Simulation time 126986089 ps
CPU time 2.52 seconds
Started Aug 12 06:24:30 PM PDT 24
Finished Aug 12 06:24:33 PM PDT 24
Peak memory 233528 kb
Host smart-2b07ced8-770d-4167-a7b7-af6b4aca4bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540177441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.540177441
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1105762549
Short name T450
Test name
Test status
Simulation time 22812151 ps
CPU time 0.79 seconds
Started Aug 12 06:24:35 PM PDT 24
Finished Aug 12 06:24:36 PM PDT 24
Peak memory 207632 kb
Host smart-30649d94-5e4c-405b-880b-8e7d79ab1b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105762549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1105762549
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1015841000
Short name T380
Test name
Test status
Simulation time 44220486212 ps
CPU time 76.42 seconds
Started Aug 12 06:24:28 PM PDT 24
Finished Aug 12 06:25:45 PM PDT 24
Peak memory 242144 kb
Host smart-8fb6c478-69ba-4c39-839b-a88569f4561c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015841000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1015841000
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3322035718
Short name T838
Test name
Test status
Simulation time 8458993436 ps
CPU time 63.46 seconds
Started Aug 12 06:24:30 PM PDT 24
Finished Aug 12 06:25:34 PM PDT 24
Peak memory 264560 kb
Host smart-0d4d1278-ccaa-47bd-83d8-dbf5ecff9d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322035718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3322035718
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.4030076691
Short name T144
Test name
Test status
Simulation time 165078887 ps
CPU time 4.19 seconds
Started Aug 12 06:24:22 PM PDT 24
Finished Aug 12 06:24:27 PM PDT 24
Peak memory 225616 kb
Host smart-a269a9fe-4281-4c5f-b68b-52d4fe9a0717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030076691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.4030076691
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.835680232
Short name T979
Test name
Test status
Simulation time 1182519959 ps
CPU time 16.93 seconds
Started Aug 12 06:24:35 PM PDT 24
Finished Aug 12 06:24:52 PM PDT 24
Peak memory 242008 kb
Host smart-4cf67304-10c0-455a-9bd7-b826aa33dec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835680232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.835680232
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1249545582
Short name T741
Test name
Test status
Simulation time 5972919818 ps
CPU time 14.69 seconds
Started Aug 12 06:24:27 PM PDT 24
Finished Aug 12 06:24:42 PM PDT 24
Peak memory 225636 kb
Host smart-16eff838-f2f3-4751-b8c7-420df21930fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249545582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1249545582
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2290033911
Short name T224
Test name
Test status
Simulation time 553214560 ps
CPU time 13.37 seconds
Started Aug 12 06:24:29 PM PDT 24
Finished Aug 12 06:24:42 PM PDT 24
Peak memory 241972 kb
Host smart-1d5ec4e0-7d6f-4865-a109-30dce1fbc2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290033911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2290033911
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.822433394
Short name T226
Test name
Test status
Simulation time 1218690709 ps
CPU time 8.54 seconds
Started Aug 12 06:24:20 PM PDT 24
Finished Aug 12 06:24:29 PM PDT 24
Peak memory 225524 kb
Host smart-a849dba3-c55d-4281-b195-c41be5deac83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822433394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.822433394
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3029458393
Short name T524
Test name
Test status
Simulation time 7787496560 ps
CPU time 7.34 seconds
Started Aug 12 06:24:29 PM PDT 24
Finished Aug 12 06:24:36 PM PDT 24
Peak memory 233908 kb
Host smart-a1a3f632-ab8a-4119-b8f6-25430602d4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029458393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3029458393
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2769061371
Short name T345
Test name
Test status
Simulation time 8682205751 ps
CPU time 14.67 seconds
Started Aug 12 06:24:19 PM PDT 24
Finished Aug 12 06:24:34 PM PDT 24
Peak memory 221540 kb
Host smart-18f9ba43-d250-49f1-85dc-efdab4dcdb74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2769061371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2769061371
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.4239867003
Short name T706
Test name
Test status
Simulation time 23911573 ps
CPU time 0.71 seconds
Started Aug 12 06:24:29 PM PDT 24
Finished Aug 12 06:24:30 PM PDT 24
Peak memory 206696 kb
Host smart-d85c9579-7434-44b2-9369-12b9925c3e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239867003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.4239867003
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2175511926
Short name T789
Test name
Test status
Simulation time 181548022 ps
CPU time 5.23 seconds
Started Aug 12 06:24:27 PM PDT 24
Finished Aug 12 06:24:32 PM PDT 24
Peak memory 217368 kb
Host smart-cfc6ad6e-8783-4102-a723-e654f48835f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175511926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2175511926
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3167673559
Short name T587
Test name
Test status
Simulation time 12379955 ps
CPU time 0.73 seconds
Started Aug 12 06:24:25 PM PDT 24
Finished Aug 12 06:24:26 PM PDT 24
Peak memory 207056 kb
Host smart-662d9308-4d20-406e-a601-3b26c2d9afba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167673559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3167673559
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.835868363
Short name T797
Test name
Test status
Simulation time 5550605457 ps
CPU time 21.68 seconds
Started Aug 12 06:24:32 PM PDT 24
Finished Aug 12 06:24:54 PM PDT 24
Peak memory 242068 kb
Host smart-385275c2-407d-4fa1-b98c-f711b15190c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835868363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.835868363
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.368402562
Short name T521
Test name
Test status
Simulation time 14037176 ps
CPU time 0.74 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:24:53 PM PDT 24
Peak memory 206828 kb
Host smart-12776e5c-9f13-4770-9b41-be826819c46d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368402562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.368402562
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.432277827
Short name T210
Test name
Test status
Simulation time 1299719618 ps
CPU time 4.87 seconds
Started Aug 12 06:24:19 PM PDT 24
Finished Aug 12 06:24:24 PM PDT 24
Peak memory 233752 kb
Host smart-593d95a3-fb27-42ce-98a3-b9fdf370268a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432277827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.432277827
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2677638998
Short name T569
Test name
Test status
Simulation time 17795276 ps
CPU time 0.79 seconds
Started Aug 12 06:24:44 PM PDT 24
Finished Aug 12 06:24:45 PM PDT 24
Peak memory 207628 kb
Host smart-6890a394-3067-4423-82eb-bd392021991e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677638998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2677638998
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1281500337
Short name T698
Test name
Test status
Simulation time 7235151330 ps
CPU time 34.32 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:25:24 PM PDT 24
Peak memory 242104 kb
Host smart-d03e0630-0e0c-4566-98c9-3b73ecfe7839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281500337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1281500337
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.714425076
Short name T214
Test name
Test status
Simulation time 40175693911 ps
CPU time 114.65 seconds
Started Aug 12 06:24:41 PM PDT 24
Finished Aug 12 06:26:36 PM PDT 24
Peak memory 256680 kb
Host smart-e1f06db0-06f4-4911-acbf-aef5b0f8f138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714425076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.714425076
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1798839754
Short name T400
Test name
Test status
Simulation time 5926297897 ps
CPU time 29.25 seconds
Started Aug 12 06:24:44 PM PDT 24
Finished Aug 12 06:25:13 PM PDT 24
Peak memory 218792 kb
Host smart-2c2751e4-a8ab-412d-9c9d-e6dd72d7266b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798839754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1798839754
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.603920721
Short name T615
Test name
Test status
Simulation time 132800699 ps
CPU time 2.68 seconds
Started Aug 12 06:24:44 PM PDT 24
Finished Aug 12 06:24:47 PM PDT 24
Peak memory 233736 kb
Host smart-d763bb27-decd-4648-9cfa-cb8485dd271f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603920721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.603920721
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.4143555927
Short name T168
Test name
Test status
Simulation time 76275130922 ps
CPU time 141.28 seconds
Started Aug 12 06:24:31 PM PDT 24
Finished Aug 12 06:26:53 PM PDT 24
Peak memory 250480 kb
Host smart-eae4378c-4960-4ce8-9de0-4f90b1ee9e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143555927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.4143555927
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3837932959
Short name T956
Test name
Test status
Simulation time 47265030 ps
CPU time 2.82 seconds
Started Aug 12 06:24:19 PM PDT 24
Finished Aug 12 06:24:22 PM PDT 24
Peak memory 233828 kb
Host smart-ee035ee3-5c6e-4725-86b5-36eb4930c3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837932959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3837932959
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.695400361
Short name T600
Test name
Test status
Simulation time 11288038113 ps
CPU time 44.41 seconds
Started Aug 12 06:24:21 PM PDT 24
Finished Aug 12 06:25:05 PM PDT 24
Peak memory 225744 kb
Host smart-02165b0c-73fa-4de8-b00a-a19dc2ef130f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695400361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.695400361
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2357001177
Short name T101
Test name
Test status
Simulation time 14439228016 ps
CPU time 8.64 seconds
Started Aug 12 06:24:18 PM PDT 24
Finished Aug 12 06:24:27 PM PDT 24
Peak memory 240972 kb
Host smart-82492486-4650-46b0-9c6c-313d4796208f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357001177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2357001177
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1438052762
Short name T757
Test name
Test status
Simulation time 2673514109 ps
CPU time 11.85 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:25:04 PM PDT 24
Peak memory 225636 kb
Host smart-39f1f266-e81b-424f-8cbd-fe01cf484053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438052762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1438052762
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1653625344
Short name T798
Test name
Test status
Simulation time 870933492 ps
CPU time 4.74 seconds
Started Aug 12 06:24:27 PM PDT 24
Finished Aug 12 06:24:32 PM PDT 24
Peak memory 224120 kb
Host smart-beeb290e-0d25-49be-88f9-3d0c4871c238
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1653625344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1653625344
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2594609671
Short name T770
Test name
Test status
Simulation time 7126813703 ps
CPU time 144.71 seconds
Started Aug 12 06:24:45 PM PDT 24
Finished Aug 12 06:27:10 PM PDT 24
Peak memory 269272 kb
Host smart-917713c5-5f1a-45cb-bc82-d0af57f3cc1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594609671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2594609671
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3691868333
Short name T700
Test name
Test status
Simulation time 75207665193 ps
CPU time 38.51 seconds
Started Aug 12 06:24:24 PM PDT 24
Finished Aug 12 06:25:02 PM PDT 24
Peak memory 217488 kb
Host smart-2d56e7c5-89e1-4a88-9136-7d4fe22a0e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691868333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3691868333
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.611810850
Short name T362
Test name
Test status
Simulation time 3492636961 ps
CPU time 7.45 seconds
Started Aug 12 06:24:38 PM PDT 24
Finished Aug 12 06:24:46 PM PDT 24
Peak memory 217384 kb
Host smart-1d2a9e90-5cba-4e58-ab0a-7748a17c16d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611810850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.611810850
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3976782224
Short name T466
Test name
Test status
Simulation time 444678411 ps
CPU time 6.03 seconds
Started Aug 12 06:24:23 PM PDT 24
Finished Aug 12 06:24:29 PM PDT 24
Peak memory 217344 kb
Host smart-26679477-a938-4cff-8c8c-5a426a36a302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976782224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3976782224
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3323484816
Short name T833
Test name
Test status
Simulation time 183997369 ps
CPU time 0.91 seconds
Started Aug 12 06:24:21 PM PDT 24
Finished Aug 12 06:24:24 PM PDT 24
Peak memory 208008 kb
Host smart-c206c4ae-2c40-4aea-bd25-1c0ad7f93cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323484816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3323484816
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3180665581
Short name T755
Test name
Test status
Simulation time 221675595 ps
CPU time 2.63 seconds
Started Aug 12 06:24:34 PM PDT 24
Finished Aug 12 06:24:37 PM PDT 24
Peak memory 233732 kb
Host smart-13278bef-9e73-439e-88f8-bc36af69417a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180665581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3180665581
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3134074075
Short name T731
Test name
Test status
Simulation time 23929653 ps
CPU time 0.72 seconds
Started Aug 12 06:24:48 PM PDT 24
Finished Aug 12 06:24:49 PM PDT 24
Peak memory 206848 kb
Host smart-cb1fbe94-d982-466a-ae70-b9dd3f89a444
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134074075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3134074075
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1367170763
Short name T7
Test name
Test status
Simulation time 145427132 ps
CPU time 3.93 seconds
Started Aug 12 06:24:45 PM PDT 24
Finished Aug 12 06:24:49 PM PDT 24
Peak memory 233760 kb
Host smart-6f92e09a-57f0-4d77-a59c-23d57a2c8ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367170763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1367170763
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.327855913
Short name T627
Test name
Test status
Simulation time 19521334 ps
CPU time 0.78 seconds
Started Aug 12 06:24:44 PM PDT 24
Finished Aug 12 06:24:45 PM PDT 24
Peak memory 207952 kb
Host smart-4922ab4c-a2d0-4322-acc2-143ffc15e8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327855913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.327855913
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.195826097
Short name T486
Test name
Test status
Simulation time 1941972613 ps
CPU time 43.01 seconds
Started Aug 12 06:24:46 PM PDT 24
Finished Aug 12 06:25:29 PM PDT 24
Peak memory 250660 kb
Host smart-712dd1ef-3833-45bb-8f1f-eefeaf08242e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195826097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.195826097
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.757674962
Short name T973
Test name
Test status
Simulation time 3902558346 ps
CPU time 6.58 seconds
Started Aug 12 06:24:48 PM PDT 24
Finished Aug 12 06:24:55 PM PDT 24
Peak memory 218848 kb
Host smart-8f60a3ad-564f-4aaf-84ef-2384afe49198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757674962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.757674962
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2231021022
Short name T135
Test name
Test status
Simulation time 56742370510 ps
CPU time 164.99 seconds
Started Aug 12 06:24:38 PM PDT 24
Finished Aug 12 06:27:23 PM PDT 24
Peak memory 262208 kb
Host smart-9b690659-113a-4538-a5d4-4b972dbb8553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231021022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2231021022
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1031674445
Short name T446
Test name
Test status
Simulation time 158754492 ps
CPU time 4.65 seconds
Started Aug 12 06:24:33 PM PDT 24
Finished Aug 12 06:24:38 PM PDT 24
Peak memory 225564 kb
Host smart-75dc2e8f-c2ae-4cea-9b55-00175cbf75f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031674445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1031674445
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2634282080
Short name T233
Test name
Test status
Simulation time 3407253311 ps
CPU time 10.56 seconds
Started Aug 12 06:24:41 PM PDT 24
Finished Aug 12 06:24:51 PM PDT 24
Peak memory 233860 kb
Host smart-927331ca-5f51-4d05-a0db-c56a43130e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634282080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2634282080
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2134124273
Short name T225
Test name
Test status
Simulation time 6886739072 ps
CPU time 72.25 seconds
Started Aug 12 06:24:42 PM PDT 24
Finished Aug 12 06:26:00 PM PDT 24
Peak memory 253004 kb
Host smart-7861ece1-8950-452b-b4a9-6458d2b42c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134124273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2134124273
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2834306506
Short name T674
Test name
Test status
Simulation time 48775301670 ps
CPU time 31.02 seconds
Started Aug 12 06:24:44 PM PDT 24
Finished Aug 12 06:25:16 PM PDT 24
Peak memory 233876 kb
Host smart-feeb51ad-676c-402d-a718-f2548b58dd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834306506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2834306506
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2253698816
Short name T100
Test name
Test status
Simulation time 955580517 ps
CPU time 4.51 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:25:00 PM PDT 24
Peak memory 233756 kb
Host smart-235073d4-eb08-4f82-bb9a-234e8c65bcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253698816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2253698816
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2890306194
Short name T1003
Test name
Test status
Simulation time 3395540872 ps
CPU time 7.15 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:25:02 PM PDT 24
Peak memory 224480 kb
Host smart-5a1a3fca-b6f5-40d5-87fe-9d3dd1aed2bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2890306194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2890306194
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.830670185
Short name T504
Test name
Test status
Simulation time 33976415663 ps
CPU time 43.63 seconds
Started Aug 12 06:24:38 PM PDT 24
Finished Aug 12 06:25:22 PM PDT 24
Peak memory 241256 kb
Host smart-3c6ce51d-369b-462a-8615-6b82f02ce594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830670185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.830670185
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2397941697
Short name T340
Test name
Test status
Simulation time 2010704378 ps
CPU time 8.67 seconds
Started Aug 12 06:24:49 PM PDT 24
Finished Aug 12 06:24:58 PM PDT 24
Peak memory 217280 kb
Host smart-599486c4-e2f9-4a14-ace5-bc083dcc16c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397941697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2397941697
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3628268627
Short name T748
Test name
Test status
Simulation time 5117426689 ps
CPU time 9.69 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:25:05 PM PDT 24
Peak memory 217404 kb
Host smart-494e04fa-b49a-4994-8732-6987520d449e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628268627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3628268627
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1335778460
Short name T708
Test name
Test status
Simulation time 40600403 ps
CPU time 0.87 seconds
Started Aug 12 06:24:45 PM PDT 24
Finished Aug 12 06:24:46 PM PDT 24
Peak memory 208048 kb
Host smart-4eb71dca-dd9e-45c2-8805-f1b30f04a787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335778460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1335778460
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1503508011
Short name T712
Test name
Test status
Simulation time 34386800 ps
CPU time 0.7 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:24:53 PM PDT 24
Peak memory 206648 kb
Host smart-d38b4932-4165-412d-8fdf-de62bbeb391d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503508011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1503508011
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1070147467
Short name T715
Test name
Test status
Simulation time 3638348542 ps
CPU time 13.04 seconds
Started Aug 12 06:24:51 PM PDT 24
Finished Aug 12 06:25:05 PM PDT 24
Peak memory 233940 kb
Host smart-ebdc7c26-6074-4ad1-bdb8-958bdda656cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070147467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1070147467
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.910199411
Short name T719
Test name
Test status
Simulation time 79913524 ps
CPU time 0.7 seconds
Started Aug 12 06:24:43 PM PDT 24
Finished Aug 12 06:24:44 PM PDT 24
Peak memory 205936 kb
Host smart-86fe0441-738d-4d7c-95fb-26030bdd4fe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910199411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.910199411
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1498676585
Short name T656
Test name
Test status
Simulation time 382281804 ps
CPU time 2.83 seconds
Started Aug 12 06:24:42 PM PDT 24
Finished Aug 12 06:24:45 PM PDT 24
Peak memory 225604 kb
Host smart-e4869ee1-08e3-499c-af9a-883b4550958e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498676585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1498676585
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3601288698
Short name T310
Test name
Test status
Simulation time 59183362 ps
CPU time 0.79 seconds
Started Aug 12 06:24:42 PM PDT 24
Finished Aug 12 06:24:43 PM PDT 24
Peak memory 206576 kb
Host smart-13f1e8cd-4315-4346-ad0d-6dcfab7378fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601288698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3601288698
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.425518828
Short name T364
Test name
Test status
Simulation time 2711389929 ps
CPU time 12.76 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:25:03 PM PDT 24
Peak memory 237940 kb
Host smart-0d19cdc5-49b6-46ba-9419-26fe9e22d38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425518828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.425518828
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3666743341
Short name T654
Test name
Test status
Simulation time 6325398800 ps
CPU time 108.83 seconds
Started Aug 12 06:24:47 PM PDT 24
Finished Aug 12 06:26:36 PM PDT 24
Peak memory 258556 kb
Host smart-d08aa2a8-1f49-4011-8cdc-ab5881a0de7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666743341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3666743341
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2406496640
Short name T178
Test name
Test status
Simulation time 39650168753 ps
CPU time 154.55 seconds
Started Aug 12 06:24:37 PM PDT 24
Finished Aug 12 06:27:11 PM PDT 24
Peak memory 238920 kb
Host smart-0582ba0b-7d96-4d26-8ba9-18e96e74b0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406496640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2406496640
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.617708915
Short name T959
Test name
Test status
Simulation time 119635910916 ps
CPU time 89.74 seconds
Started Aug 12 06:24:53 PM PDT 24
Finished Aug 12 06:26:23 PM PDT 24
Peak memory 265688 kb
Host smart-570bd453-7efe-4aa5-87cc-c5caaaee790c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617708915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.617708915
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2313235758
Short name T415
Test name
Test status
Simulation time 10658789875 ps
CPU time 22.78 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:25:18 PM PDT 24
Peak memory 233916 kb
Host smart-c004b26f-dcbf-4b00-a6ca-e007ff8b4e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313235758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2313235758
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2420494720
Short name T385
Test name
Test status
Simulation time 2461973745 ps
CPU time 4.83 seconds
Started Aug 12 06:24:48 PM PDT 24
Finished Aug 12 06:24:53 PM PDT 24
Peak memory 233852 kb
Host smart-ee52354f-ce28-4274-bbcc-a954c6094146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420494720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2420494720
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2374254814
Short name T174
Test name
Test status
Simulation time 174676830 ps
CPU time 3.1 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:24:53 PM PDT 24
Peak memory 233808 kb
Host smart-bbe513ef-6c6a-4a65-ab06-adeac3af1485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374254814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2374254814
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.574902515
Short name T395
Test name
Test status
Simulation time 118408562 ps
CPU time 2.4 seconds
Started Aug 12 06:24:49 PM PDT 24
Finished Aug 12 06:24:52 PM PDT 24
Peak memory 225508 kb
Host smart-87a10d4d-e155-4040-a4c9-21a91e45f10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574902515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.574902515
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2997712948
Short name T699
Test name
Test status
Simulation time 4114341435 ps
CPU time 8.07 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:24:59 PM PDT 24
Peak memory 223220 kb
Host smart-f2e4297f-0d14-4ffb-8466-a3863ac1b77d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2997712948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2997712948
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2922610146
Short name T43
Test name
Test status
Simulation time 357879768055 ps
CPU time 777.18 seconds
Started Aug 12 06:24:56 PM PDT 24
Finished Aug 12 06:37:53 PM PDT 24
Peak memory 291004 kb
Host smart-51d465f6-9f64-4074-b293-0661b03c1b86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922610146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2922610146
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.126059585
Short name T900
Test name
Test status
Simulation time 1841863122 ps
CPU time 10.55 seconds
Started Aug 12 06:24:51 PM PDT 24
Finished Aug 12 06:25:02 PM PDT 24
Peak memory 217280 kb
Host smart-0700fc3d-3f53-45dd-a786-422958f6ffe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126059585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.126059585
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.4118224788
Short name T908
Test name
Test status
Simulation time 2016974813 ps
CPU time 3.55 seconds
Started Aug 12 06:24:47 PM PDT 24
Finished Aug 12 06:24:50 PM PDT 24
Peak memory 217276 kb
Host smart-108dfe56-2bf1-4e38-a92e-b0e14cdb50ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118224788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.4118224788
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1107943208
Short name T646
Test name
Test status
Simulation time 48859029 ps
CPU time 0.95 seconds
Started Aug 12 06:24:37 PM PDT 24
Finished Aug 12 06:24:38 PM PDT 24
Peak memory 208028 kb
Host smart-b61aa604-e946-4606-b447-67cc8d8b6c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107943208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1107943208
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.4140422820
Short name T642
Test name
Test status
Simulation time 160124191 ps
CPU time 0.87 seconds
Started Aug 12 06:24:51 PM PDT 24
Finished Aug 12 06:24:52 PM PDT 24
Peak memory 206980 kb
Host smart-f609e5ec-3881-4e25-b7cc-7efe23158e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140422820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.4140422820
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1391818987
Short name T890
Test name
Test status
Simulation time 13525537380 ps
CPU time 26.53 seconds
Started Aug 12 06:24:48 PM PDT 24
Finished Aug 12 06:25:15 PM PDT 24
Peak memory 241524 kb
Host smart-dd3cdd88-2e7c-421d-8245-67771aab6e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391818987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1391818987
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2114310627
Short name T692
Test name
Test status
Simulation time 20755601 ps
CPU time 0.74 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:24:50 PM PDT 24
Peak memory 206432 kb
Host smart-de8462d3-db0b-4555-b44f-6a26dc38b83c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114310627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2114310627
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.463806796
Short name T812
Test name
Test status
Simulation time 665739617 ps
CPU time 4.26 seconds
Started Aug 12 06:25:00 PM PDT 24
Finished Aug 12 06:25:04 PM PDT 24
Peak memory 233788 kb
Host smart-fdc4523a-8c3a-4f1d-9543-b02904ed03ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463806796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.463806796
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2372895490
Short name T499
Test name
Test status
Simulation time 50266598 ps
CPU time 0.71 seconds
Started Aug 12 06:24:51 PM PDT 24
Finished Aug 12 06:24:52 PM PDT 24
Peak memory 206556 kb
Host smart-3226ef08-ae14-41cf-9620-4ab01b27a77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372895490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2372895490
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2534454362
Short name T191
Test name
Test status
Simulation time 3794493257 ps
CPU time 48.55 seconds
Started Aug 12 06:24:46 PM PDT 24
Finished Aug 12 06:25:34 PM PDT 24
Peak memory 250244 kb
Host smart-1bc82b6f-e50b-4d26-a7a0-84a03a1f9efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534454362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2534454362
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3898481021
Short name T124
Test name
Test status
Simulation time 37206573235 ps
CPU time 192.02 seconds
Started Aug 12 06:24:40 PM PDT 24
Finished Aug 12 06:27:52 PM PDT 24
Peak memory 254116 kb
Host smart-1fc1885e-8c23-4b69-b627-98471048fbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898481021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3898481021
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3268710696
Short name T546
Test name
Test status
Simulation time 539202848 ps
CPU time 6.39 seconds
Started Aug 12 06:24:43 PM PDT 24
Finished Aug 12 06:24:50 PM PDT 24
Peak memory 233824 kb
Host smart-71c88205-0a69-4378-9762-35d22e7c7355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268710696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3268710696
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1616498068
Short name T761
Test name
Test status
Simulation time 4938708854 ps
CPU time 57.85 seconds
Started Aug 12 06:24:44 PM PDT 24
Finished Aug 12 06:25:42 PM PDT 24
Peak memory 254880 kb
Host smart-2f3d3dbb-cba3-4e6d-86cb-47967321f0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616498068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1616498068
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2317110655
Short name T203
Test name
Test status
Simulation time 923407453 ps
CPU time 4.11 seconds
Started Aug 12 06:24:44 PM PDT 24
Finished Aug 12 06:24:48 PM PDT 24
Peak memory 225744 kb
Host smart-6777e248-8ea0-44b6-84b2-164337179808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317110655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2317110655
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2444529110
Short name T631
Test name
Test status
Simulation time 5575100841 ps
CPU time 10.76 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:25:06 PM PDT 24
Peak memory 233860 kb
Host smart-9ce63671-e759-42e2-9102-db17a6a4e788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444529110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2444529110
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.172492784
Short name T792
Test name
Test status
Simulation time 677177229 ps
CPU time 3.32 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:24:53 PM PDT 24
Peak memory 225520 kb
Host smart-106fc2da-3352-464c-bb7d-936fe1425779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172492784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.172492784
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3327553587
Short name T774
Test name
Test status
Simulation time 637369221 ps
CPU time 3.95 seconds
Started Aug 12 06:24:47 PM PDT 24
Finished Aug 12 06:24:51 PM PDT 24
Peak memory 233800 kb
Host smart-231830d7-b5c3-4dba-83c2-7acf06160ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327553587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3327553587
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.988805934
Short name T1001
Test name
Test status
Simulation time 5666122124 ps
CPU time 10.57 seconds
Started Aug 12 06:24:53 PM PDT 24
Finished Aug 12 06:25:04 PM PDT 24
Peak memory 223208 kb
Host smart-6dc3f222-5495-4669-bcb5-6060c8d36b95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=988805934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.988805934
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1978129748
Short name T156
Test name
Test status
Simulation time 9068634714 ps
CPU time 87.16 seconds
Started Aug 12 06:24:56 PM PDT 24
Finished Aug 12 06:26:23 PM PDT 24
Peak memory 237628 kb
Host smart-627bf516-c8b0-4076-9b98-b84d63ce0ce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978129748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1978129748
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.549736049
Short name T888
Test name
Test status
Simulation time 7314362288 ps
CPU time 24.48 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:25:17 PM PDT 24
Peak memory 217476 kb
Host smart-89de5e1e-e2a3-40cf-ba51-1c4ab069ea89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549736049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.549736049
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3139911561
Short name T382
Test name
Test status
Simulation time 7408558214 ps
CPU time 7.9 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:24:58 PM PDT 24
Peak memory 217452 kb
Host smart-d92ee50e-5568-405d-a5ba-680d286e6b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139911561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3139911561
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.951598945
Short name T543
Test name
Test status
Simulation time 37505415 ps
CPU time 1.34 seconds
Started Aug 12 06:24:53 PM PDT 24
Finished Aug 12 06:24:55 PM PDT 24
Peak memory 217300 kb
Host smart-22998b1f-7129-4db3-972b-7ad46d014b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951598945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.951598945
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4267361727
Short name T975
Test name
Test status
Simulation time 133915292 ps
CPU time 0.89 seconds
Started Aug 12 06:24:48 PM PDT 24
Finished Aug 12 06:24:49 PM PDT 24
Peak memory 207448 kb
Host smart-a7f65068-7f8c-43f1-aeec-bf2f83e4f10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267361727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4267361727
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3667041317
Short name T670
Test name
Test status
Simulation time 222791807 ps
CPU time 4.94 seconds
Started Aug 12 06:24:53 PM PDT 24
Finished Aug 12 06:24:58 PM PDT 24
Peak memory 233780 kb
Host smart-63f73b5a-fb39-4af6-b8b6-7221adb50ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667041317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3667041317
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2911003998
Short name T664
Test name
Test status
Simulation time 35445573 ps
CPU time 0.71 seconds
Started Aug 12 06:24:48 PM PDT 24
Finished Aug 12 06:24:48 PM PDT 24
Peak memory 205908 kb
Host smart-096d3b7c-76c0-4d1a-b371-22843fca81bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911003998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2911003998
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3942466069
Short name T551
Test name
Test status
Simulation time 56139047 ps
CPU time 2.61 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:24:53 PM PDT 24
Peak memory 233728 kb
Host smart-dac90559-3a80-4463-8fdb-191d91c0840b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942466069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3942466069
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.4186373382
Short name T397
Test name
Test status
Simulation time 71613472 ps
CPU time 0.8 seconds
Started Aug 12 06:24:53 PM PDT 24
Finished Aug 12 06:24:54 PM PDT 24
Peak memory 207636 kb
Host smart-c35079b2-a92a-4500-9ea2-dd514fed5842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186373382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4186373382
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2611637985
Short name T429
Test name
Test status
Simulation time 5641820260 ps
CPU time 53.58 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:25:46 PM PDT 24
Peak memory 263336 kb
Host smart-ffa83ae4-a3b1-42b9-967a-ba2f71fb6fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611637985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2611637985
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.4205126649
Short name T903
Test name
Test status
Simulation time 98425186446 ps
CPU time 202.25 seconds
Started Aug 12 06:24:51 PM PDT 24
Finished Aug 12 06:28:14 PM PDT 24
Peak memory 250344 kb
Host smart-d31768c6-953e-48bf-bbbc-e4213ed132a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205126649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.4205126649
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1103225377
Short name T685
Test name
Test status
Simulation time 16849539006 ps
CPU time 100.21 seconds
Started Aug 12 06:24:48 PM PDT 24
Finished Aug 12 06:26:28 PM PDT 24
Peak memory 256300 kb
Host smart-1cde083a-e240-4f97-900c-cd5b21b35624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103225377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1103225377
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1088189985
Short name T53
Test name
Test status
Simulation time 1987431942 ps
CPU time 18.59 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:25:09 PM PDT 24
Peak memory 233796 kb
Host smart-88218771-5336-4e1e-835d-66662019853f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088189985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1088189985
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2719992841
Short name T777
Test name
Test status
Simulation time 49582790837 ps
CPU time 96.45 seconds
Started Aug 12 06:24:36 PM PDT 24
Finished Aug 12 06:26:13 PM PDT 24
Peak memory 233920 kb
Host smart-43a9abcc-85e9-4ece-b900-955a42162d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719992841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2719992841
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3290064755
Short name T35
Test name
Test status
Simulation time 25825264937 ps
CPU time 13.87 seconds
Started Aug 12 06:24:51 PM PDT 24
Finished Aug 12 06:25:05 PM PDT 24
Peak memory 225728 kb
Host smart-88c3fe58-284e-4742-a949-365531e716d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290064755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3290064755
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3131558467
Short name T483
Test name
Test status
Simulation time 5188994113 ps
CPU time 6.95 seconds
Started Aug 12 06:24:36 PM PDT 24
Finished Aug 12 06:24:43 PM PDT 24
Peak memory 225664 kb
Host smart-dfc5ac68-829d-42be-9e00-39a7a20bb6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131558467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3131558467
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4122634186
Short name T971
Test name
Test status
Simulation time 1348710202 ps
CPU time 11.04 seconds
Started Aug 12 06:24:44 PM PDT 24
Finished Aug 12 06:24:55 PM PDT 24
Peak memory 223680 kb
Host smart-0c61f3fd-8fab-431e-a445-f9b9325158a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4122634186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4122634186
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.624876291
Short name T436
Test name
Test status
Simulation time 17506988863 ps
CPU time 28.93 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:25:21 PM PDT 24
Peak memory 217388 kb
Host smart-8f1e8f75-e804-41c0-b4da-56cfc8ac9011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624876291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.624876291
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2411465945
Short name T722
Test name
Test status
Simulation time 1885084143 ps
CPU time 3.3 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:24:59 PM PDT 24
Peak memory 217328 kb
Host smart-26b73a94-6b48-411a-8e2e-057019ed2767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411465945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2411465945
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1001066112
Short name T50
Test name
Test status
Simulation time 42142676 ps
CPU time 0.97 seconds
Started Aug 12 06:24:43 PM PDT 24
Finished Aug 12 06:24:45 PM PDT 24
Peak memory 208220 kb
Host smart-5c593f00-a18e-4261-affb-8f39df9bf820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001066112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1001066112
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2745214653
Short name T697
Test name
Test status
Simulation time 29537646 ps
CPU time 0.9 seconds
Started Aug 12 06:24:41 PM PDT 24
Finished Aug 12 06:24:42 PM PDT 24
Peak memory 206956 kb
Host smart-8fcf005c-f84e-4e9f-ba8d-36f880054abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745214653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2745214653
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1759868331
Short name T649
Test name
Test status
Simulation time 1385849383 ps
CPU time 5.49 seconds
Started Aug 12 06:24:36 PM PDT 24
Finished Aug 12 06:24:42 PM PDT 24
Peak memory 225540 kb
Host smart-075df214-606a-420e-b71b-8783d8a44c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759868331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1759868331
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4159912157
Short name T957
Test name
Test status
Simulation time 297047389 ps
CPU time 2.52 seconds
Started Aug 12 06:24:47 PM PDT 24
Finished Aug 12 06:24:50 PM PDT 24
Peak memory 233736 kb
Host smart-bed9b929-cf9a-4fbb-aa7e-c8331ec4d78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159912157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4159912157
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3882460771
Short name T635
Test name
Test status
Simulation time 82533619 ps
CPU time 0.78 seconds
Started Aug 12 06:24:40 PM PDT 24
Finished Aug 12 06:24:41 PM PDT 24
Peak memory 207604 kb
Host smart-2383aa5f-36a3-4008-aae7-fa49c466b8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882460771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3882460771
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3554611117
Short name T763
Test name
Test status
Simulation time 13135732680 ps
CPU time 112.55 seconds
Started Aug 12 06:24:53 PM PDT 24
Finished Aug 12 06:26:46 PM PDT 24
Peak memory 258488 kb
Host smart-23da8663-b888-49b6-9ef2-88a551a507c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554611117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3554611117
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.380447406
Short name T45
Test name
Test status
Simulation time 36644128439 ps
CPU time 360.48 seconds
Started Aug 12 06:24:46 PM PDT 24
Finished Aug 12 06:30:47 PM PDT 24
Peak memory 266728 kb
Host smart-1f0ab0b3-5bef-418a-91ba-66c3b5dd223b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380447406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.380447406
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1786589022
Short name T597
Test name
Test status
Simulation time 22620642900 ps
CPU time 83.97 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:26:15 PM PDT 24
Peak memory 258688 kb
Host smart-f8500a1d-6838-46b0-a3fd-f67b3badc537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786589022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1786589022
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1534151254
Short name T630
Test name
Test status
Simulation time 269174924 ps
CPU time 3.02 seconds
Started Aug 12 06:24:57 PM PDT 24
Finished Aug 12 06:25:00 PM PDT 24
Peak memory 225592 kb
Host smart-ae2786a6-b427-4fcb-b857-099c0825eaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534151254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1534151254
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3209390159
Short name T744
Test name
Test status
Simulation time 8921579212 ps
CPU time 59.39 seconds
Started Aug 12 06:24:39 PM PDT 24
Finished Aug 12 06:25:39 PM PDT 24
Peak memory 250420 kb
Host smart-3155672c-0feb-42a9-b4db-c71e89f2c877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209390159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3209390159
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.187327262
Short name T414
Test name
Test status
Simulation time 456104661 ps
CPU time 7.53 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:25:02 PM PDT 24
Peak memory 225600 kb
Host smart-67389158-b165-4f05-8b35-87bc627382f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187327262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.187327262
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2221717914
Short name T378
Test name
Test status
Simulation time 28768317 ps
CPU time 2.02 seconds
Started Aug 12 06:24:39 PM PDT 24
Finished Aug 12 06:24:41 PM PDT 24
Peak memory 225068 kb
Host smart-5542087a-a243-4607-b3ac-351855a1a2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221717914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2221717914
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3458352983
Short name T760
Test name
Test status
Simulation time 57083057 ps
CPU time 2.31 seconds
Started Aug 12 06:24:47 PM PDT 24
Finished Aug 12 06:24:49 PM PDT 24
Peak memory 233460 kb
Host smart-8660e5c9-8cca-4c5d-bb89-aca6c155e0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458352983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3458352983
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3294615653
Short name T828
Test name
Test status
Simulation time 1221140400 ps
CPU time 10.13 seconds
Started Aug 12 06:24:42 PM PDT 24
Finished Aug 12 06:24:52 PM PDT 24
Peak memory 234644 kb
Host smart-af90d1a6-27bd-428d-9f81-9790278943f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294615653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3294615653
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.796503125
Short name T441
Test name
Test status
Simulation time 3126806218 ps
CPU time 8.76 seconds
Started Aug 12 06:24:48 PM PDT 24
Finished Aug 12 06:24:57 PM PDT 24
Peak memory 224348 kb
Host smart-b03a96dc-3c8e-44af-a9c2-8090d61b8d42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=796503125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.796503125
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1712845232
Short name T520
Test name
Test status
Simulation time 76666893508 ps
CPU time 172.07 seconds
Started Aug 12 06:24:48 PM PDT 24
Finished Aug 12 06:27:41 PM PDT 24
Peak memory 251616 kb
Host smart-51b3ca4e-b676-4260-b23f-cebc0ed96609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712845232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1712845232
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.4032783998
Short name T452
Test name
Test status
Simulation time 10001805757 ps
CPU time 16.99 seconds
Started Aug 12 06:24:40 PM PDT 24
Finished Aug 12 06:24:57 PM PDT 24
Peak memory 217364 kb
Host smart-ca9bd807-ec54-497c-9fa4-1879a12639c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032783998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.4032783998
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.726053468
Short name T342
Test name
Test status
Simulation time 8796071310 ps
CPU time 13.6 seconds
Started Aug 12 06:24:46 PM PDT 24
Finished Aug 12 06:25:00 PM PDT 24
Peak memory 217420 kb
Host smart-8389b39d-9d34-41b4-94e7-b09eca352b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726053468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.726053468
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2733103648
Short name T821
Test name
Test status
Simulation time 17573155 ps
CPU time 0.79 seconds
Started Aug 12 06:24:47 PM PDT 24
Finished Aug 12 06:24:48 PM PDT 24
Peak memory 207028 kb
Host smart-fe7735dc-d747-4d46-a79d-7550fe13124b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733103648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2733103648
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2107972691
Short name T522
Test name
Test status
Simulation time 99474588 ps
CPU time 0.81 seconds
Started Aug 12 06:24:30 PM PDT 24
Finished Aug 12 06:24:31 PM PDT 24
Peak memory 207004 kb
Host smart-eef65232-1fee-4fa8-9f0c-9ac5c3d463e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107972691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2107972691
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2724543725
Short name T185
Test name
Test status
Simulation time 2030111782 ps
CPU time 7.87 seconds
Started Aug 12 06:24:43 PM PDT 24
Finished Aug 12 06:24:51 PM PDT 24
Peak memory 225552 kb
Host smart-8eef0b5a-e611-4a26-be51-8ddaa148dfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724543725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2724543725
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.742440251
Short name T724
Test name
Test status
Simulation time 81022326 ps
CPU time 0.72 seconds
Started Aug 12 06:24:49 PM PDT 24
Finished Aug 12 06:24:49 PM PDT 24
Peak memory 206808 kb
Host smart-584a8558-9c8b-46d2-b311-593d3d024830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742440251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.742440251
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3258160544
Short name T462
Test name
Test status
Simulation time 320306065 ps
CPU time 6.41 seconds
Started Aug 12 06:24:46 PM PDT 24
Finished Aug 12 06:24:52 PM PDT 24
Peak memory 233760 kb
Host smart-51ab598a-ae2c-4fa7-b572-3a40f7db8ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258160544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3258160544
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.698473293
Short name T488
Test name
Test status
Simulation time 14897675 ps
CPU time 0.82 seconds
Started Aug 12 06:24:46 PM PDT 24
Finished Aug 12 06:24:52 PM PDT 24
Peak memory 207528 kb
Host smart-087fdd3a-d2c8-4dab-81f9-2ccac81610b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698473293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.698473293
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3688058878
Short name T553
Test name
Test status
Simulation time 606134941 ps
CPU time 15.51 seconds
Started Aug 12 06:24:51 PM PDT 24
Finished Aug 12 06:25:06 PM PDT 24
Peak memory 256396 kb
Host smart-c122cb6f-079f-4f83-b201-d0e710e00e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688058878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3688058878
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2857435142
Short name T134
Test name
Test status
Simulation time 209381010860 ps
CPU time 488.33 seconds
Started Aug 12 06:24:53 PM PDT 24
Finished Aug 12 06:33:02 PM PDT 24
Peak memory 255456 kb
Host smart-c7c08233-75a8-4219-8eed-2494bb3f3ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857435142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2857435142
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.608306538
Short name T773
Test name
Test status
Simulation time 14552955503 ps
CPU time 56.84 seconds
Started Aug 12 06:24:40 PM PDT 24
Finished Aug 12 06:25:37 PM PDT 24
Peak memory 225748 kb
Host smart-6441d9c7-d048-4ff9-8052-31296dc20507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608306538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.608306538
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2139971796
Short name T268
Test name
Test status
Simulation time 276348379 ps
CPU time 4.05 seconds
Started Aug 12 06:24:47 PM PDT 24
Finished Aug 12 06:24:51 PM PDT 24
Peak memory 233752 kb
Host smart-8baf9652-37c8-4878-9a58-d4530a73ff30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139971796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2139971796
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1128921956
Short name T916
Test name
Test status
Simulation time 40057807 ps
CPU time 0.73 seconds
Started Aug 12 06:24:51 PM PDT 24
Finished Aug 12 06:24:52 PM PDT 24
Peak memory 216816 kb
Host smart-a62761e6-9e17-4101-a645-7054c47a653e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128921956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1128921956
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.934965528
Short name T896
Test name
Test status
Simulation time 1791228169 ps
CPU time 8.03 seconds
Started Aug 12 06:24:43 PM PDT 24
Finished Aug 12 06:24:51 PM PDT 24
Peak memory 233776 kb
Host smart-d4d87d34-05e0-47a4-acbc-64e55327a8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934965528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.934965528
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1147288029
Short name T403
Test name
Test status
Simulation time 900873037 ps
CPU time 12.82 seconds
Started Aug 12 06:24:56 PM PDT 24
Finished Aug 12 06:25:09 PM PDT 24
Peak memory 251020 kb
Host smart-29605bec-b968-4d79-ad7f-d2925aecbb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147288029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1147288029
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.82057349
Short name T177
Test name
Test status
Simulation time 398834671 ps
CPU time 2.33 seconds
Started Aug 12 06:24:44 PM PDT 24
Finished Aug 12 06:24:46 PM PDT 24
Peak memory 225548 kb
Host smart-03598adc-4093-471b-8825-0edaf8c11bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82057349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.82057349
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2969953200
Short name T652
Test name
Test status
Simulation time 874845531 ps
CPU time 4.39 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:25:00 PM PDT 24
Peak memory 233784 kb
Host smart-26814779-9334-41a7-8cab-d1cdfab62312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969953200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2969953200
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3656652345
Short name T743
Test name
Test status
Simulation time 356224111 ps
CPU time 4.31 seconds
Started Aug 12 06:24:56 PM PDT 24
Finished Aug 12 06:25:01 PM PDT 24
Peak memory 220228 kb
Host smart-513efc3e-8a44-4b31-8aed-6aa6c6446fa7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3656652345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3656652345
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1040598108
Short name T721
Test name
Test status
Simulation time 3006484211 ps
CPU time 29.21 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:25:21 PM PDT 24
Peak memory 217444 kb
Host smart-fe857a35-689b-4193-9bbb-0366ba9d83fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040598108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1040598108
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3203857860
Short name T72
Test name
Test status
Simulation time 349195624 ps
CPU time 1.19 seconds
Started Aug 12 06:24:47 PM PDT 24
Finished Aug 12 06:24:49 PM PDT 24
Peak memory 208908 kb
Host smart-e22af253-062b-4830-be56-d98071e4e002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203857860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3203857860
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3001308145
Short name T275
Test name
Test status
Simulation time 54872547 ps
CPU time 1.18 seconds
Started Aug 12 06:24:34 PM PDT 24
Finished Aug 12 06:24:35 PM PDT 24
Peak memory 208920 kb
Host smart-eeda641f-0ff6-4847-affc-1ba9214e4aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001308145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3001308145
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4135392726
Short name T556
Test name
Test status
Simulation time 219953637 ps
CPU time 0.87 seconds
Started Aug 12 06:24:49 PM PDT 24
Finished Aug 12 06:24:50 PM PDT 24
Peak memory 206992 kb
Host smart-1de27524-260e-4003-9827-db13fa9bc418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135392726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4135392726
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.390797862
Short name T194
Test name
Test status
Simulation time 6137438525 ps
CPU time 11.72 seconds
Started Aug 12 06:24:56 PM PDT 24
Finished Aug 12 06:25:08 PM PDT 24
Peak memory 233872 kb
Host smart-67739db2-ed3a-48c1-899a-30bf3f05ce71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390797862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.390797862
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.663472260
Short name T322
Test name
Test status
Simulation time 31946202 ps
CPU time 0.78 seconds
Started Aug 12 06:24:03 PM PDT 24
Finished Aug 12 06:24:04 PM PDT 24
Peak memory 205900 kb
Host smart-e1e56f7c-c978-4a56-b910-8cd51efd1f9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663472260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.663472260
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3672166947
Short name T883
Test name
Test status
Simulation time 1169759282 ps
CPU time 7.69 seconds
Started Aug 12 06:24:12 PM PDT 24
Finished Aug 12 06:24:19 PM PDT 24
Peak memory 233832 kb
Host smart-f4793a11-f140-4457-970d-9353d760827f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672166947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3672166947
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1881226148
Short name T572
Test name
Test status
Simulation time 55331400 ps
CPU time 0.81 seconds
Started Aug 12 06:24:11 PM PDT 24
Finished Aug 12 06:24:12 PM PDT 24
Peak memory 207632 kb
Host smart-c144fadb-b267-42d6-8aef-05a2d9aaf777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881226148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1881226148
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.81249339
Short name T468
Test name
Test status
Simulation time 36604887443 ps
CPU time 103.4 seconds
Started Aug 12 06:24:08 PM PDT 24
Finished Aug 12 06:25:51 PM PDT 24
Peak memory 266444 kb
Host smart-baf0b280-9757-4708-b02a-fe22ba1a7240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81249339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.81249339
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2469334252
Short name T853
Test name
Test status
Simulation time 229661271444 ps
CPU time 396.6 seconds
Started Aug 12 06:24:06 PM PDT 24
Finished Aug 12 06:30:43 PM PDT 24
Peak memory 257416 kb
Host smart-35ab5bb5-dc13-484e-a706-957351aaa01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469334252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2469334252
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2418055466
Short name T511
Test name
Test status
Simulation time 21239978391 ps
CPU time 96.64 seconds
Started Aug 12 06:23:58 PM PDT 24
Finished Aug 12 06:25:34 PM PDT 24
Peak memory 250292 kb
Host smart-670dafc5-24f1-4b64-909b-93c19dd21fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418055466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2418055466
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3596356211
Short name T865
Test name
Test status
Simulation time 7770844206 ps
CPU time 25.9 seconds
Started Aug 12 06:24:17 PM PDT 24
Finished Aug 12 06:24:43 PM PDT 24
Peak memory 225780 kb
Host smart-7682b4db-9212-46d1-862e-10d34d890695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596356211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3596356211
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1943041343
Short name T920
Test name
Test status
Simulation time 79312434952 ps
CPU time 202.44 seconds
Started Aug 12 06:24:08 PM PDT 24
Finished Aug 12 06:27:30 PM PDT 24
Peak memory 250224 kb
Host smart-3d2b226e-6ec1-4f24-944b-9100aa3bdfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943041343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1943041343
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.4131746979
Short name T193
Test name
Test status
Simulation time 560697278 ps
CPU time 5.3 seconds
Started Aug 12 06:24:01 PM PDT 24
Finished Aug 12 06:24:06 PM PDT 24
Peak memory 225528 kb
Host smart-ab1206dc-e2e1-4e22-b146-cf440fc8510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131746979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.4131746979
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.859923138
Short name T336
Test name
Test status
Simulation time 449193690 ps
CPU time 2.46 seconds
Started Aug 12 06:24:08 PM PDT 24
Finished Aug 12 06:24:11 PM PDT 24
Peak memory 219896 kb
Host smart-efaee595-fc1c-45b3-8fd8-d4e75ca146f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859923138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.859923138
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.484513143
Short name T611
Test name
Test status
Simulation time 118367268020 ps
CPU time 24.37 seconds
Started Aug 12 06:24:06 PM PDT 24
Finished Aug 12 06:24:30 PM PDT 24
Peak memory 225712 kb
Host smart-5a75fac2-0bc9-4254-8995-d975c283b244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484513143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
484513143
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.887012378
Short name T421
Test name
Test status
Simulation time 1433394363 ps
CPU time 7.16 seconds
Started Aug 12 06:23:51 PM PDT 24
Finished Aug 12 06:23:59 PM PDT 24
Peak memory 241920 kb
Host smart-268ee187-2c32-45a2-a33d-bc858ed5e293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887012378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.887012378
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.4257170372
Short name T399
Test name
Test status
Simulation time 600772261 ps
CPU time 4.86 seconds
Started Aug 12 06:23:59 PM PDT 24
Finished Aug 12 06:24:04 PM PDT 24
Peak memory 219944 kb
Host smart-fb172fa2-52d3-4e14-9947-742e14079c6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4257170372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.4257170372
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3713247903
Short name T255
Test name
Test status
Simulation time 4680291458 ps
CPU time 58.14 seconds
Started Aug 12 06:23:56 PM PDT 24
Finished Aug 12 06:24:54 PM PDT 24
Peak memory 250964 kb
Host smart-d9405329-f4c8-46c6-86f9-4eafd33e70a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713247903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3713247903
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3009423918
Short name T738
Test name
Test status
Simulation time 4844347720 ps
CPU time 19.51 seconds
Started Aug 12 06:24:09 PM PDT 24
Finished Aug 12 06:24:29 PM PDT 24
Peak memory 217776 kb
Host smart-f8ee778c-8d8c-4e95-b90b-fab5cf68ca91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009423918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3009423918
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3758341022
Short name T427
Test name
Test status
Simulation time 632882904 ps
CPU time 1.84 seconds
Started Aug 12 06:24:00 PM PDT 24
Finished Aug 12 06:24:02 PM PDT 24
Peak memory 208884 kb
Host smart-0ef992c0-e579-4f81-a6ff-b36a69c62bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758341022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3758341022
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3867829048
Short name T323
Test name
Test status
Simulation time 581605423 ps
CPU time 4.87 seconds
Started Aug 12 06:23:58 PM PDT 24
Finished Aug 12 06:24:04 PM PDT 24
Peak memory 217324 kb
Host smart-76c7e96b-e26f-4896-9dc5-712d356da9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867829048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3867829048
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4038846545
Short name T472
Test name
Test status
Simulation time 574373807 ps
CPU time 0.83 seconds
Started Aug 12 06:24:08 PM PDT 24
Finished Aug 12 06:24:10 PM PDT 24
Peak memory 207008 kb
Host smart-fa3abeab-ff8c-4c9f-899e-3cb0dd42241c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038846545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4038846545
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2770646318
Short name T230
Test name
Test status
Simulation time 9836545472 ps
CPU time 12.34 seconds
Started Aug 12 06:24:02 PM PDT 24
Finished Aug 12 06:24:15 PM PDT 24
Peak memory 233912 kb
Host smart-61f8678f-8e08-4783-ae43-2d78de622616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770646318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2770646318
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2908698003
Short name T571
Test name
Test status
Simulation time 14595880 ps
CPU time 0.74 seconds
Started Aug 12 06:25:01 PM PDT 24
Finished Aug 12 06:25:02 PM PDT 24
Peak memory 205924 kb
Host smart-19481257-1f25-4e06-bb5a-9c3c546eace0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908698003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2908698003
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.251122911
Short name T48
Test name
Test status
Simulation time 375227509 ps
CPU time 4.41 seconds
Started Aug 12 06:24:58 PM PDT 24
Finished Aug 12 06:25:03 PM PDT 24
Peak memory 225496 kb
Host smart-34b64357-aab8-4a8a-ae2c-4a61e8c5a787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251122911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.251122911
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2561773211
Short name T998
Test name
Test status
Simulation time 65182001 ps
CPU time 0.76 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:24:53 PM PDT 24
Peak memory 207968 kb
Host smart-755a1149-a938-4415-bc6d-8b0e6d0da7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561773211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2561773211
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.151088194
Short name T294
Test name
Test status
Simulation time 82474303303 ps
CPU time 126.2 seconds
Started Aug 12 06:24:46 PM PDT 24
Finished Aug 12 06:26:52 PM PDT 24
Peak memory 263728 kb
Host smart-d291b78b-6131-4f4c-a7be-1c4ce7979f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151088194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.151088194
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3960581324
Short name T396
Test name
Test status
Simulation time 151005626 ps
CPU time 2.39 seconds
Started Aug 12 06:24:58 PM PDT 24
Finished Aug 12 06:25:00 PM PDT 24
Peak memory 218584 kb
Host smart-77d0023f-df75-470e-8054-4f99f2018c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960581324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3960581324
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3439919682
Short name T439
Test name
Test status
Simulation time 99413072158 ps
CPU time 177.96 seconds
Started Aug 12 06:25:01 PM PDT 24
Finished Aug 12 06:28:00 PM PDT 24
Peak memory 239292 kb
Host smart-8f22183b-5f79-45c4-9a17-ec2b304d29de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439919682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3439919682
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3903456464
Short name T137
Test name
Test status
Simulation time 125747008 ps
CPU time 3.14 seconds
Started Aug 12 06:24:53 PM PDT 24
Finished Aug 12 06:24:57 PM PDT 24
Peak memory 233704 kb
Host smart-e6e4acc6-4be2-4b1d-8131-d1ded50b5912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903456464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3903456464
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.815919180
Short name T567
Test name
Test status
Simulation time 13947776288 ps
CPU time 21.21 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:25:16 PM PDT 24
Peak memory 251296 kb
Host smart-9473db6a-e24d-42d7-ad3e-dd1e74a9dbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815919180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.815919180
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.954623432
Short name T303
Test name
Test status
Simulation time 723916152 ps
CPU time 4.52 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:24:55 PM PDT 24
Peak memory 225648 kb
Host smart-ab871433-6015-4cdb-af21-37ede1ec9d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954623432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.954623432
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2423664569
Short name T338
Test name
Test status
Simulation time 110250243 ps
CPU time 2.37 seconds
Started Aug 12 06:24:49 PM PDT 24
Finished Aug 12 06:24:51 PM PDT 24
Peak memory 232320 kb
Host smart-8b2e5955-ae51-4552-90c6-f1682fdd0803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423664569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2423664569
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2219318519
Short name T830
Test name
Test status
Simulation time 83664411 ps
CPU time 2.19 seconds
Started Aug 12 06:24:59 PM PDT 24
Finished Aug 12 06:25:01 PM PDT 24
Peak memory 225180 kb
Host smart-7298fc93-7301-49e6-aaec-f7adc6975022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219318519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2219318519
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.235236658
Short name T507
Test name
Test status
Simulation time 9904110195 ps
CPU time 19.65 seconds
Started Aug 12 06:25:03 PM PDT 24
Finished Aug 12 06:25:23 PM PDT 24
Peak memory 242132 kb
Host smart-aafa16b3-3396-4668-80a0-1ed46e264acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235236658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.235236658
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1125804635
Short name T22
Test name
Test status
Simulation time 175953976 ps
CPU time 1 seconds
Started Aug 12 06:24:44 PM PDT 24
Finished Aug 12 06:24:45 PM PDT 24
Peak memory 208724 kb
Host smart-74738d2d-d4fb-48eb-8f12-0c91e159740a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125804635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1125804635
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2037806842
Short name T854
Test name
Test status
Simulation time 3838251267 ps
CPU time 24.61 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:25:20 PM PDT 24
Peak memory 217408 kb
Host smart-9c049480-ea6f-4a99-9368-ba8d3d21686f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037806842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2037806842
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1990085163
Short name T475
Test name
Test status
Simulation time 2690284549 ps
CPU time 10.91 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:25:03 PM PDT 24
Peak memory 217584 kb
Host smart-684d80cb-7462-404e-8561-5b15571921c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990085163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1990085163
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.318942139
Short name T936
Test name
Test status
Simulation time 18622172 ps
CPU time 0.89 seconds
Started Aug 12 06:25:01 PM PDT 24
Finished Aug 12 06:25:02 PM PDT 24
Peak memory 208400 kb
Host smart-cea54ab1-614e-4d98-9c6e-b04dc9b53486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318942139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.318942139
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3916933514
Short name T640
Test name
Test status
Simulation time 61472275 ps
CPU time 0.72 seconds
Started Aug 12 06:24:44 PM PDT 24
Finished Aug 12 06:24:45 PM PDT 24
Peak memory 206980 kb
Host smart-80557c0f-316b-4567-bc56-a449daa3fcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916933514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3916933514
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2555012545
Short name T982
Test name
Test status
Simulation time 551957298 ps
CPU time 4.1 seconds
Started Aug 12 06:24:53 PM PDT 24
Finished Aug 12 06:24:57 PM PDT 24
Peak memory 225612 kb
Host smart-1b09dc26-bd81-4c3b-ab71-431fb5351dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555012545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2555012545
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.219268526
Short name T657
Test name
Test status
Simulation time 23399800 ps
CPU time 0.69 seconds
Started Aug 12 06:25:06 PM PDT 24
Finished Aug 12 06:25:07 PM PDT 24
Peak memory 206452 kb
Host smart-eec3cccd-ce78-466b-b181-5bc15be67a94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219268526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.219268526
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1763346863
Short name T681
Test name
Test status
Simulation time 1537108091 ps
CPU time 6.32 seconds
Started Aug 12 06:24:53 PM PDT 24
Finished Aug 12 06:25:00 PM PDT 24
Peak memory 233912 kb
Host smart-0b9b36c1-8fd1-4e4f-99b7-121f72c4be80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763346863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1763346863
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.4181741371
Short name T392
Test name
Test status
Simulation time 20909223 ps
CPU time 0.82 seconds
Started Aug 12 06:24:39 PM PDT 24
Finished Aug 12 06:24:40 PM PDT 24
Peak memory 207968 kb
Host smart-fdadef93-1009-4a11-95a8-42fd3e6e2afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181741371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4181741371
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1208794128
Short name T34
Test name
Test status
Simulation time 5768971919 ps
CPU time 47.09 seconds
Started Aug 12 06:24:47 PM PDT 24
Finished Aug 12 06:25:35 PM PDT 24
Peak memory 242116 kb
Host smart-0da21828-e388-42b7-99f7-1d7353d966eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208794128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1208794128
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.377977740
Short name T662
Test name
Test status
Simulation time 22619742869 ps
CPU time 214.69 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:28:27 PM PDT 24
Peak memory 262492 kb
Host smart-03851a7e-5820-4ce9-bff3-6fb83ad86812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377977740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.377977740
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.312933710
Short name T476
Test name
Test status
Simulation time 22492936995 ps
CPU time 170.72 seconds
Started Aug 12 06:24:49 PM PDT 24
Finished Aug 12 06:27:40 PM PDT 24
Peak memory 266108 kb
Host smart-4ac8b59f-9e4d-4638-82ba-25756eb1b852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312933710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.312933710
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1854976393
Short name T602
Test name
Test status
Simulation time 207454810 ps
CPU time 4.77 seconds
Started Aug 12 06:24:45 PM PDT 24
Finished Aug 12 06:24:50 PM PDT 24
Peak memory 233828 kb
Host smart-6826bf2a-6b71-4ba8-b3a1-0b4050f06465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854976393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1854976393
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1410713847
Short name T915
Test name
Test status
Simulation time 2115671697 ps
CPU time 17.36 seconds
Started Aug 12 06:24:45 PM PDT 24
Finished Aug 12 06:25:02 PM PDT 24
Peak memory 224380 kb
Host smart-070ecf31-c3cb-44e8-abf3-c25b138a643e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410713847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1410713847
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.80878306
Short name T932
Test name
Test status
Simulation time 485763636 ps
CPU time 5.04 seconds
Started Aug 12 06:24:48 PM PDT 24
Finished Aug 12 06:24:53 PM PDT 24
Peak memory 233792 kb
Host smart-ad73abdc-2168-4d2c-89fe-4b4255e6f61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80878306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.80878306
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1991740209
Short name T609
Test name
Test status
Simulation time 10126607333 ps
CPU time 31.72 seconds
Started Aug 12 06:24:57 PM PDT 24
Finished Aug 12 06:25:29 PM PDT 24
Peak memory 250796 kb
Host smart-ca39527c-48af-4b72-98c0-605ca485b032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991740209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1991740209
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2468009732
Short name T701
Test name
Test status
Simulation time 389809426 ps
CPU time 6.32 seconds
Started Aug 12 06:24:53 PM PDT 24
Finished Aug 12 06:24:59 PM PDT 24
Peak memory 222732 kb
Host smart-94812ede-aa08-4a8a-ab26-7ad64af7240e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2468009732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2468009732
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1308678881
Short name T27
Test name
Test status
Simulation time 2821886313 ps
CPU time 41.47 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:25:32 PM PDT 24
Peak memory 253840 kb
Host smart-7d119841-95a3-42f8-818a-8c1a7849a916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308678881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1308678881
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3570610851
Short name T895
Test name
Test status
Simulation time 663000603 ps
CPU time 8.33 seconds
Started Aug 12 06:24:46 PM PDT 24
Finished Aug 12 06:24:54 PM PDT 24
Peak memory 216216 kb
Host smart-4a6538e7-f40c-431c-8f92-e0c1c3c91736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570610851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3570610851
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1916417223
Short name T370
Test name
Test status
Simulation time 1081415223 ps
CPU time 7.36 seconds
Started Aug 12 06:24:59 PM PDT 24
Finished Aug 12 06:25:06 PM PDT 24
Peak memory 217336 kb
Host smart-7e99584b-f8db-4168-a146-8f54096d7b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916417223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1916417223
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2312580725
Short name T527
Test name
Test status
Simulation time 12856509 ps
CPU time 0.71 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:24:55 PM PDT 24
Peak memory 206608 kb
Host smart-817bb085-90a0-4a8a-83fd-00d81114e8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312580725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2312580725
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2929987202
Short name T568
Test name
Test status
Simulation time 39442244 ps
CPU time 0.65 seconds
Started Aug 12 06:24:59 PM PDT 24
Finished Aug 12 06:25:00 PM PDT 24
Peak memory 206636 kb
Host smart-caea50d5-5970-4c9c-bccc-737644ed7749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929987202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2929987202
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.746758952
Short name T906
Test name
Test status
Simulation time 875484318 ps
CPU time 3.21 seconds
Started Aug 12 06:24:53 PM PDT 24
Finished Aug 12 06:24:56 PM PDT 24
Peak memory 233860 kb
Host smart-6bfd7549-66de-4c7b-ba6a-29a59a567b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746758952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.746758952
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1501064676
Short name T585
Test name
Test status
Simulation time 20602394 ps
CPU time 0.74 seconds
Started Aug 12 06:24:56 PM PDT 24
Finished Aug 12 06:24:57 PM PDT 24
Peak memory 206480 kb
Host smart-1a3485d2-8b32-4632-8e57-827dfbb91c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501064676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1501064676
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.501284350
Short name T227
Test name
Test status
Simulation time 245231888 ps
CPU time 4.14 seconds
Started Aug 12 06:25:09 PM PDT 24
Finished Aug 12 06:25:13 PM PDT 24
Peak memory 225532 kb
Host smart-e350bb5e-aa4d-401a-98f8-e85d1cd9ce21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501284350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.501284350
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.615943625
Short name T814
Test name
Test status
Simulation time 14244328 ps
CPU time 0.78 seconds
Started Aug 12 06:25:00 PM PDT 24
Finished Aug 12 06:25:01 PM PDT 24
Peak memory 206852 kb
Host smart-bb7f0369-7f3b-4c2f-9106-828fb1792c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615943625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.615943625
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3918433643
Short name T1004
Test name
Test status
Simulation time 51816685782 ps
CPU time 76.11 seconds
Started Aug 12 06:25:00 PM PDT 24
Finished Aug 12 06:26:16 PM PDT 24
Peak memory 250332 kb
Host smart-eb527ce7-4236-49ff-be16-27665f420636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918433643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3918433643
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3819308141
Short name T484
Test name
Test status
Simulation time 60156826100 ps
CPU time 280.3 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:29:35 PM PDT 24
Peak memory 252760 kb
Host smart-310bea1c-bb8f-4b7a-9760-c4f996b9bf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819308141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3819308141
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3824987535
Short name T541
Test name
Test status
Simulation time 2511248603 ps
CPU time 8.58 seconds
Started Aug 12 06:24:48 PM PDT 24
Finished Aug 12 06:24:57 PM PDT 24
Peak memory 233936 kb
Host smart-b707e637-e05f-4ad7-9a2d-e4ada5604616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824987535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3824987535
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1188212453
Short name T169
Test name
Test status
Simulation time 22747521431 ps
CPU time 180.64 seconds
Started Aug 12 06:24:59 PM PDT 24
Finished Aug 12 06:28:00 PM PDT 24
Peak memory 258488 kb
Host smart-faee71f5-604b-44b8-9b7f-8ca1e0ecee2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188212453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1188212453
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3535399792
Short name T912
Test name
Test status
Simulation time 7922959130 ps
CPU time 13.53 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:25:09 PM PDT 24
Peak memory 225648 kb
Host smart-1cbed18b-f79a-4733-97c4-3e4af98cc5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535399792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3535399792
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1022725389
Short name T604
Test name
Test status
Simulation time 3862750715 ps
CPU time 38.56 seconds
Started Aug 12 06:24:58 PM PDT 24
Finished Aug 12 06:25:37 PM PDT 24
Peak memory 233916 kb
Host smart-bfc4cb0b-7373-42d8-a9c5-7b6ebf82ce5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022725389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1022725389
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1390055977
Short name T667
Test name
Test status
Simulation time 2604012260 ps
CPU time 6.74 seconds
Started Aug 12 06:24:56 PM PDT 24
Finished Aug 12 06:25:03 PM PDT 24
Peak memory 233904 kb
Host smart-8ff807e5-82d9-46ec-80f1-27a917329d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390055977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1390055977
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2238188878
Short name T753
Test name
Test status
Simulation time 46660735798 ps
CPU time 11.17 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:25:04 PM PDT 24
Peak memory 233912 kb
Host smart-bc17c676-4d1c-4bd5-9732-4f6800da5a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238188878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2238188878
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3792049994
Short name T335
Test name
Test status
Simulation time 471432816 ps
CPU time 3.69 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:24:56 PM PDT 24
Peak memory 224308 kb
Host smart-92f7b30e-293d-494c-a208-4eed7078c7fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3792049994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3792049994
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3436550743
Short name T868
Test name
Test status
Simulation time 7346210574 ps
CPU time 162.94 seconds
Started Aug 12 06:24:47 PM PDT 24
Finished Aug 12 06:27:30 PM PDT 24
Peak memory 274920 kb
Host smart-a4f12527-69a5-4946-a9ca-f258ac4aad68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436550743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3436550743
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2842134953
Short name T995
Test name
Test status
Simulation time 11226125554 ps
CPU time 29.29 seconds
Started Aug 12 06:24:58 PM PDT 24
Finished Aug 12 06:25:28 PM PDT 24
Peak memory 217444 kb
Host smart-bcafef72-7bc0-4f12-99cc-8344aa7831b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842134953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2842134953
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3844093503
Short name T951
Test name
Test status
Simulation time 1963573287 ps
CPU time 7.35 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:25:05 PM PDT 24
Peak memory 217356 kb
Host smart-2db84743-37e6-4480-a2d4-73ab1f20872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844093503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3844093503
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.119618292
Short name T10
Test name
Test status
Simulation time 62648698 ps
CPU time 2.15 seconds
Started Aug 12 06:24:57 PM PDT 24
Finished Aug 12 06:25:00 PM PDT 24
Peak memory 217288 kb
Host smart-11188f58-d9ee-42da-a8b8-cdb7eea513c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119618292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.119618292
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1800401809
Short name T331
Test name
Test status
Simulation time 38454449 ps
CPU time 0.86 seconds
Started Aug 12 06:24:58 PM PDT 24
Finished Aug 12 06:24:59 PM PDT 24
Peak memory 206972 kb
Host smart-225aa936-d856-4706-9483-56cbdc5dd37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800401809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1800401809
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1174284818
Short name T688
Test name
Test status
Simulation time 88248520 ps
CPU time 2.73 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:24:53 PM PDT 24
Peak memory 233764 kb
Host smart-d9a351cf-59c6-4dfb-acd4-35a3b085624b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174284818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1174284818
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.595112523
Short name T56
Test name
Test status
Simulation time 18265965 ps
CPU time 0.69 seconds
Started Aug 12 06:25:06 PM PDT 24
Finished Aug 12 06:25:07 PM PDT 24
Peak memory 206808 kb
Host smart-7241f6ff-273e-4711-ad01-45a4d3d482d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595112523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.595112523
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1230364385
Short name T279
Test name
Test status
Simulation time 280735322 ps
CPU time 2.21 seconds
Started Aug 12 06:24:58 PM PDT 24
Finished Aug 12 06:25:00 PM PDT 24
Peak memory 225520 kb
Host smart-173f5e61-a984-4e63-a2da-e66dff44f411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230364385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1230364385
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.540923636
Short name T324
Test name
Test status
Simulation time 26615033 ps
CPU time 0.77 seconds
Started Aug 12 06:24:58 PM PDT 24
Finished Aug 12 06:24:59 PM PDT 24
Peak memory 207868 kb
Host smart-51c9636c-62ff-4154-9417-df5555b00eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540923636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.540923636
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3787794224
Short name T805
Test name
Test status
Simulation time 112638029247 ps
CPU time 182.91 seconds
Started Aug 12 06:25:01 PM PDT 24
Finished Aug 12 06:28:04 PM PDT 24
Peak memory 250304 kb
Host smart-0f93626d-de78-49b1-8f99-4c5b2fe59b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787794224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3787794224
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1837563476
Short name T746
Test name
Test status
Simulation time 2123930051 ps
CPU time 24.77 seconds
Started Aug 12 06:24:58 PM PDT 24
Finished Aug 12 06:25:23 PM PDT 24
Peak memory 233856 kb
Host smart-1a6d36ba-5cc2-407b-9392-91ee33e98cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837563476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1837563476
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2010321527
Short name T426
Test name
Test status
Simulation time 2680698384 ps
CPU time 29.55 seconds
Started Aug 12 06:24:54 PM PDT 24
Finished Aug 12 06:25:24 PM PDT 24
Peak memory 240216 kb
Host smart-8d767b48-883f-46f2-a195-7e5c2f9bdff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010321527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2010321527
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3213839385
Short name T199
Test name
Test status
Simulation time 284118124 ps
CPU time 3.51 seconds
Started Aug 12 06:24:53 PM PDT 24
Finished Aug 12 06:24:57 PM PDT 24
Peak memory 234636 kb
Host smart-c063c69f-9e2b-4ae0-b8af-0eb3b8e632ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213839385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3213839385
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.619908474
Short name T565
Test name
Test status
Simulation time 532468990 ps
CPU time 10.1 seconds
Started Aug 12 06:24:57 PM PDT 24
Finished Aug 12 06:25:08 PM PDT 24
Peak memory 241960 kb
Host smart-52a4d14c-7340-4bd3-b003-8a5452f37675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619908474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.619908474
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2486239738
Short name T289
Test name
Test status
Simulation time 196889913 ps
CPU time 2.43 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:24:52 PM PDT 24
Peak memory 225528 kb
Host smart-00a85a78-82bc-4a0d-ad84-177aee72875a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486239738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2486239738
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3366425562
Short name T147
Test name
Test status
Simulation time 34588271 ps
CPU time 2.56 seconds
Started Aug 12 06:25:09 PM PDT 24
Finished Aug 12 06:25:12 PM PDT 24
Peak memory 233456 kb
Host smart-3098706f-f37b-4534-8bf7-540592c0833d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366425562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3366425562
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.488626719
Short name T902
Test name
Test status
Simulation time 259727333 ps
CPU time 4.84 seconds
Started Aug 12 06:24:58 PM PDT 24
Finished Aug 12 06:25:03 PM PDT 24
Peak memory 233760 kb
Host smart-5281e11b-750c-435c-827f-a186d4248142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488626719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.488626719
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4012392895
Short name T942
Test name
Test status
Simulation time 3752822233 ps
CPU time 9.33 seconds
Started Aug 12 06:24:49 PM PDT 24
Finished Aug 12 06:24:59 PM PDT 24
Peak memory 225664 kb
Host smart-7bbb6468-10e4-4ec8-abce-c9bbf8b8be4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012392895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4012392895
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3467714344
Short name T330
Test name
Test status
Simulation time 133846386 ps
CPU time 4.34 seconds
Started Aug 12 06:24:57 PM PDT 24
Finished Aug 12 06:25:02 PM PDT 24
Peak memory 221488 kb
Host smart-29ae626d-7bb5-4098-9097-7917beeb9844
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3467714344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3467714344
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.221338206
Short name T796
Test name
Test status
Simulation time 1500163423 ps
CPU time 23.42 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:25:15 PM PDT 24
Peak memory 242160 kb
Host smart-41c01855-4c7f-4bdd-9f0a-61bddd24b809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221338206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.221338206
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1349466317
Short name T730
Test name
Test status
Simulation time 1194125028 ps
CPU time 8 seconds
Started Aug 12 06:24:59 PM PDT 24
Finished Aug 12 06:25:07 PM PDT 24
Peak memory 217260 kb
Host smart-0433fe03-31ce-43bd-a0b5-4a79de423076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349466317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1349466317
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2821649806
Short name T318
Test name
Test status
Simulation time 23504445 ps
CPU time 0.71 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:24:55 PM PDT 24
Peak memory 206724 kb
Host smart-625d2009-02a5-4074-885b-d9ff3e540fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821649806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2821649806
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.489790065
Short name T390
Test name
Test status
Simulation time 37809913 ps
CPU time 0.66 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:24:53 PM PDT 24
Peak memory 206680 kb
Host smart-0505c1a6-781c-401e-9ca5-f7c896fc11ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489790065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.489790065
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1982579136
Short name T346
Test name
Test status
Simulation time 80429144 ps
CPU time 0.83 seconds
Started Aug 12 06:24:53 PM PDT 24
Finished Aug 12 06:24:54 PM PDT 24
Peak memory 207000 kb
Host smart-2619e9d1-001e-4970-a5d2-fa37b642c270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982579136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1982579136
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2985896830
Short name T355
Test name
Test status
Simulation time 9872776509 ps
CPU time 18.57 seconds
Started Aug 12 06:24:53 PM PDT 24
Finished Aug 12 06:25:12 PM PDT 24
Peak memory 239840 kb
Host smart-513c5c54-55b4-4bba-8aff-c9341fa6f334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985896830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2985896830
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1946398800
Short name T490
Test name
Test status
Simulation time 43130937 ps
CPU time 0.73 seconds
Started Aug 12 06:24:54 PM PDT 24
Finished Aug 12 06:24:55 PM PDT 24
Peak memory 206496 kb
Host smart-0126c320-e9fa-47ce-bce2-99c96fc188f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946398800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1946398800
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1393135879
Short name T73
Test name
Test status
Simulation time 302859132 ps
CPU time 5.95 seconds
Started Aug 12 06:24:55 PM PDT 24
Finished Aug 12 06:25:01 PM PDT 24
Peak memory 225500 kb
Host smart-00dc7871-4f01-4b37-abc9-56abfe76aeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393135879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1393135879
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3924846562
Short name T286
Test name
Test status
Simulation time 15983560 ps
CPU time 0.74 seconds
Started Aug 12 06:24:57 PM PDT 24
Finished Aug 12 06:24:58 PM PDT 24
Peak memory 206936 kb
Host smart-2632213a-892d-4276-88b2-eb9daeb2f0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924846562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3924846562
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1793001670
Short name T879
Test name
Test status
Simulation time 73084683187 ps
CPU time 143.1 seconds
Started Aug 12 06:25:14 PM PDT 24
Finished Aug 12 06:27:38 PM PDT 24
Peak memory 242080 kb
Host smart-97f58797-8caf-442c-88d6-6ca030df70bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793001670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1793001670
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3406272535
Short name T44
Test name
Test status
Simulation time 3573987023 ps
CPU time 44.38 seconds
Started Aug 12 06:24:59 PM PDT 24
Finished Aug 12 06:25:44 PM PDT 24
Peak memory 250288 kb
Host smart-2352dc11-6aae-4cd0-a1b3-7d5b90d349e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406272535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3406272535
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2958930907
Short name T922
Test name
Test status
Simulation time 40589894687 ps
CPU time 111.03 seconds
Started Aug 12 06:25:04 PM PDT 24
Finished Aug 12 06:26:55 PM PDT 24
Peak memory 251812 kb
Host smart-0a62118f-db94-4776-9bf9-95e55cdc6bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958930907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2958930907
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1624958840
Short name T518
Test name
Test status
Simulation time 3587004836 ps
CPU time 29.39 seconds
Started Aug 12 06:24:56 PM PDT 24
Finished Aug 12 06:25:25 PM PDT 24
Peak memory 242084 kb
Host smart-cce05361-b359-4dc2-94e9-be8aa50ff7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624958840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1624958840
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3119520804
Short name T822
Test name
Test status
Simulation time 4466085235 ps
CPU time 60.22 seconds
Started Aug 12 06:24:58 PM PDT 24
Finished Aug 12 06:25:59 PM PDT 24
Peak memory 251316 kb
Host smart-a5b36dd0-4fd0-410d-b40a-334fc7c84869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119520804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3119520804
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2442181013
Short name T557
Test name
Test status
Simulation time 9525535955 ps
CPU time 27.6 seconds
Started Aug 12 06:24:54 PM PDT 24
Finished Aug 12 06:25:22 PM PDT 24
Peak memory 225732 kb
Host smart-a641886f-1c07-430c-a67a-a7684b3452ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442181013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2442181013
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2397070549
Short name T121
Test name
Test status
Simulation time 2587799613 ps
CPU time 10.51 seconds
Started Aug 12 06:24:57 PM PDT 24
Finished Aug 12 06:25:07 PM PDT 24
Peak memory 225724 kb
Host smart-d6d86520-064d-4898-8880-c83d4b968021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397070549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2397070549
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3007602067
Short name T376
Test name
Test status
Simulation time 3227528821 ps
CPU time 13.53 seconds
Started Aug 12 06:24:49 PM PDT 24
Finished Aug 12 06:25:03 PM PDT 24
Peak memory 233956 kb
Host smart-0e16b887-610d-40a8-b9b7-a89a48520b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007602067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3007602067
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2801755302
Short name T713
Test name
Test status
Simulation time 37428544301 ps
CPU time 15.03 seconds
Started Aug 12 06:24:56 PM PDT 24
Finished Aug 12 06:25:11 PM PDT 24
Peak memory 239984 kb
Host smart-c44e29d2-f29b-4a94-81ce-3ef7bf8e9a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801755302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2801755302
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2020623916
Short name T341
Test name
Test status
Simulation time 1337799990 ps
CPU time 6.91 seconds
Started Aug 12 06:24:54 PM PDT 24
Finished Aug 12 06:25:01 PM PDT 24
Peak memory 219808 kb
Host smart-7daa3b53-d06a-4d40-a1c8-aa6372b397d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2020623916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2020623916
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3026929942
Short name T272
Test name
Test status
Simulation time 4923581409 ps
CPU time 9.85 seconds
Started Aug 12 06:24:49 PM PDT 24
Finished Aug 12 06:24:59 PM PDT 24
Peak memory 217476 kb
Host smart-be61a0ea-1bb8-4101-b2f9-36befe5bf682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026929942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3026929942
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3874167493
Short name T628
Test name
Test status
Simulation time 1770474416 ps
CPU time 3.45 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:24:56 PM PDT 24
Peak memory 217292 kb
Host smart-bde384d0-333a-4ff9-8933-9e13cfb04160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874167493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3874167493
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.265528335
Short name T943
Test name
Test status
Simulation time 141540831 ps
CPU time 1.61 seconds
Started Aug 12 06:24:50 PM PDT 24
Finished Aug 12 06:24:51 PM PDT 24
Peak memory 217256 kb
Host smart-5db96a6c-131f-44d0-8a5b-6572b996bd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265528335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.265528335
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2616794272
Short name T348
Test name
Test status
Simulation time 46571820 ps
CPU time 0.85 seconds
Started Aug 12 06:24:54 PM PDT 24
Finished Aug 12 06:24:55 PM PDT 24
Peak memory 206996 kb
Host smart-b2a899eb-454a-4353-abd7-07aae3947b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616794272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2616794272
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1635445966
Short name T581
Test name
Test status
Simulation time 984817050 ps
CPU time 4.41 seconds
Started Aug 12 06:24:56 PM PDT 24
Finished Aug 12 06:25:00 PM PDT 24
Peak memory 225564 kb
Host smart-1296da9c-1f3f-4ee7-bf00-d1bc9ad47a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635445966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1635445966
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4131224602
Short name T576
Test name
Test status
Simulation time 30786947 ps
CPU time 0.71 seconds
Started Aug 12 06:24:59 PM PDT 24
Finished Aug 12 06:25:00 PM PDT 24
Peak memory 206472 kb
Host smart-6f1dc10f-683d-45b1-9af0-e171958e95b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131224602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4131224602
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1589456612
Short name T839
Test name
Test status
Simulation time 796867930 ps
CPU time 3.2 seconds
Started Aug 12 06:25:07 PM PDT 24
Finished Aug 12 06:25:11 PM PDT 24
Peak memory 225588 kb
Host smart-b18d1f1f-2167-4e74-bf5b-99a153c7287b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589456612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1589456612
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4230987154
Short name T351
Test name
Test status
Simulation time 17262383 ps
CPU time 0.79 seconds
Started Aug 12 06:25:08 PM PDT 24
Finished Aug 12 06:25:09 PM PDT 24
Peak memory 207644 kb
Host smart-9d4c7cdf-f639-483d-b767-2fdbd71c6f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230987154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4230987154
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2772590045
Short name T661
Test name
Test status
Simulation time 21597947497 ps
CPU time 142.89 seconds
Started Aug 12 06:25:07 PM PDT 24
Finished Aug 12 06:27:30 PM PDT 24
Peak memory 252048 kb
Host smart-86578199-ce54-42a0-9229-78350fb750fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772590045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2772590045
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2073398271
Short name T183
Test name
Test status
Simulation time 210135480874 ps
CPU time 463.33 seconds
Started Aug 12 06:24:58 PM PDT 24
Finished Aug 12 06:32:42 PM PDT 24
Peak memory 250352 kb
Host smart-98188d31-3113-46b8-8d04-f28d4b84a8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073398271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2073398271
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2760067397
Short name T980
Test name
Test status
Simulation time 14152293383 ps
CPU time 67.88 seconds
Started Aug 12 06:25:19 PM PDT 24
Finished Aug 12 06:26:27 PM PDT 24
Peak memory 253496 kb
Host smart-dcb85cc5-f722-40d1-b4e6-6f1822749f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760067397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2760067397
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2189862194
Short name T261
Test name
Test status
Simulation time 6264727214 ps
CPU time 22.75 seconds
Started Aug 12 06:25:08 PM PDT 24
Finished Aug 12 06:25:31 PM PDT 24
Peak memory 225724 kb
Host smart-813b4fa1-8b11-4832-b2e4-c790c5e33f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189862194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2189862194
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.252760830
Short name T924
Test name
Test status
Simulation time 13406741058 ps
CPU time 95.25 seconds
Started Aug 12 06:25:07 PM PDT 24
Finished Aug 12 06:26:43 PM PDT 24
Peak memory 258432 kb
Host smart-883135c1-9188-489f-af0b-9fc49f80252a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252760830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.252760830
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1088879054
Short name T126
Test name
Test status
Simulation time 2676844191 ps
CPU time 10.58 seconds
Started Aug 12 06:24:59 PM PDT 24
Finished Aug 12 06:25:10 PM PDT 24
Peak memory 233920 kb
Host smart-22a59303-e208-48dc-a06e-9eeace8204db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088879054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1088879054
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.61232121
Short name T885
Test name
Test status
Simulation time 912751194 ps
CPU time 13.64 seconds
Started Aug 12 06:24:59 PM PDT 24
Finished Aug 12 06:25:13 PM PDT 24
Peak memory 235388 kb
Host smart-d7de09e8-1933-4765-afb0-eb4425ae5eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61232121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.61232121
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.542560869
Short name T202
Test name
Test status
Simulation time 13713675380 ps
CPU time 21.52 seconds
Started Aug 12 06:25:07 PM PDT 24
Finished Aug 12 06:25:29 PM PDT 24
Peak memory 233932 kb
Host smart-2b10e6e5-d22f-4fc4-8795-82a76f8dd0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542560869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.542560869
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1376391926
Short name T381
Test name
Test status
Simulation time 102353759 ps
CPU time 2.51 seconds
Started Aug 12 06:25:18 PM PDT 24
Finished Aug 12 06:25:20 PM PDT 24
Peak memory 233452 kb
Host smart-101774a2-ed26-4691-bb10-2a8d8dae8ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376391926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1376391926
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2636734563
Short name T873
Test name
Test status
Simulation time 3566128383 ps
CPU time 9.91 seconds
Started Aug 12 06:24:57 PM PDT 24
Finished Aug 12 06:25:07 PM PDT 24
Peak memory 221404 kb
Host smart-49928ccb-742d-4398-b6b5-752b3ec0ad0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2636734563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2636734563
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3452208098
Short name T270
Test name
Test status
Simulation time 2760218786 ps
CPU time 15.83 seconds
Started Aug 12 06:24:51 PM PDT 24
Finished Aug 12 06:25:07 PM PDT 24
Peak memory 217436 kb
Host smart-1796882f-ffc0-4901-89fc-00953a8efe76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452208098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3452208098
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2387807135
Short name T478
Test name
Test status
Simulation time 6769956958 ps
CPU time 19.23 seconds
Started Aug 12 06:25:21 PM PDT 24
Finished Aug 12 06:25:40 PM PDT 24
Peak memory 217360 kb
Host smart-77ed37e0-cfee-4b1e-94eb-6e1f087cb201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387807135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2387807135
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2374964217
Short name T899
Test name
Test status
Simulation time 10335849 ps
CPU time 0.69 seconds
Started Aug 12 06:25:11 PM PDT 24
Finished Aug 12 06:25:12 PM PDT 24
Peak memory 206644 kb
Host smart-70b6fc2f-6cba-4c5c-8d64-b1c71dca1d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374964217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2374964217
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.757581419
Short name T434
Test name
Test status
Simulation time 70039771 ps
CPU time 0.86 seconds
Started Aug 12 06:25:01 PM PDT 24
Finished Aug 12 06:25:02 PM PDT 24
Peak memory 206928 kb
Host smart-f5c7f836-8117-4747-9c34-4aba5567c013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757581419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.757581419
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.934622049
Short name T749
Test name
Test status
Simulation time 384201922 ps
CPU time 4.44 seconds
Started Aug 12 06:25:19 PM PDT 24
Finished Aug 12 06:25:23 PM PDT 24
Peak memory 225604 kb
Host smart-8b650278-94bb-457c-a54f-e9c2df1dd33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934622049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.934622049
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3337727560
Short name T869
Test name
Test status
Simulation time 13395514 ps
CPU time 0.72 seconds
Started Aug 12 06:25:19 PM PDT 24
Finished Aug 12 06:25:20 PM PDT 24
Peak memory 206768 kb
Host smart-8ece42f4-cc84-4da8-b791-75ff1d681e4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337727560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3337727560
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3028858336
Short name T74
Test name
Test status
Simulation time 154089732 ps
CPU time 3.85 seconds
Started Aug 12 06:25:14 PM PDT 24
Finished Aug 12 06:25:18 PM PDT 24
Peak memory 233752 kb
Host smart-93569e15-b802-4a6d-86b3-d2beea524b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028858336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3028858336
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3406275300
Short name T523
Test name
Test status
Simulation time 50647280 ps
CPU time 0.75 seconds
Started Aug 12 06:25:05 PM PDT 24
Finished Aug 12 06:25:11 PM PDT 24
Peak memory 207624 kb
Host smart-5df0dc83-a7f2-4321-a077-adf56b03da0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406275300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3406275300
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1062941723
Short name T696
Test name
Test status
Simulation time 1296849362 ps
CPU time 16.49 seconds
Started Aug 12 06:24:58 PM PDT 24
Finished Aug 12 06:25:15 PM PDT 24
Peak memory 225604 kb
Host smart-ab377a83-4a12-4825-8fa4-17614fdb6eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062941723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1062941723
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2879991599
Short name T443
Test name
Test status
Simulation time 1047039897 ps
CPU time 14.59 seconds
Started Aug 12 06:25:27 PM PDT 24
Finished Aug 12 06:25:42 PM PDT 24
Peak memory 225444 kb
Host smart-c5b5e446-3f9a-4869-b709-63f5dfebd8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879991599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2879991599
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3856010480
Short name T931
Test name
Test status
Simulation time 2032212638 ps
CPU time 15.59 seconds
Started Aug 12 06:24:52 PM PDT 24
Finished Aug 12 06:25:08 PM PDT 24
Peak memory 233752 kb
Host smart-bdc3a2ed-178f-48e5-a9ad-0238eb639f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856010480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3856010480
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2391604929
Short name T823
Test name
Test status
Simulation time 13008854136 ps
CPU time 40.67 seconds
Started Aug 12 06:25:06 PM PDT 24
Finished Aug 12 06:25:47 PM PDT 24
Peak memory 250292 kb
Host smart-8ed50c7b-fca7-453a-8dc9-83b7bf72679e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391604929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2391604929
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1298955619
Short name T996
Test name
Test status
Simulation time 618152215 ps
CPU time 15.82 seconds
Started Aug 12 06:25:09 PM PDT 24
Finished Aug 12 06:25:25 PM PDT 24
Peak memory 241976 kb
Host smart-50225640-7db9-471e-846d-9f7e8a8239f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298955619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1298955619
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4110464178
Short name T229
Test name
Test status
Simulation time 605952003 ps
CPU time 6.58 seconds
Started Aug 12 06:25:36 PM PDT 24
Finished Aug 12 06:25:43 PM PDT 24
Peak memory 233788 kb
Host smart-8de70f1a-e6d4-4b8f-8495-d76b38a67560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110464178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4110464178
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1670431535
Short name T215
Test name
Test status
Simulation time 16927050363 ps
CPU time 43.24 seconds
Started Aug 12 06:25:17 PM PDT 24
Finished Aug 12 06:26:00 PM PDT 24
Peak memory 240208 kb
Host smart-f01375a4-72ec-4a8b-aca1-5ec4d325dbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670431535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1670431535
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2360675334
Short name T595
Test name
Test status
Simulation time 105847953 ps
CPU time 2.34 seconds
Started Aug 12 06:25:08 PM PDT 24
Finished Aug 12 06:25:11 PM PDT 24
Peak memory 225148 kb
Host smart-d89e5f41-3325-46d4-b181-55cf5074c452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360675334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2360675334
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2482129847
Short name T767
Test name
Test status
Simulation time 14028980018 ps
CPU time 14.81 seconds
Started Aug 12 06:25:01 PM PDT 24
Finished Aug 12 06:25:16 PM PDT 24
Peak memory 233924 kb
Host smart-ce04025a-5d08-48d3-b653-9a39b4e732ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482129847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2482129847
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2374558177
Short name T540
Test name
Test status
Simulation time 74257775 ps
CPU time 3.82 seconds
Started Aug 12 06:25:02 PM PDT 24
Finished Aug 12 06:25:06 PM PDT 24
Peak memory 224256 kb
Host smart-61ddec93-b843-4ce7-a67d-15232131723f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2374558177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2374558177
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3824530451
Short name T375
Test name
Test status
Simulation time 4212975825 ps
CPU time 28.3 seconds
Started Aug 12 06:25:08 PM PDT 24
Finished Aug 12 06:25:37 PM PDT 24
Peak memory 217668 kb
Host smart-a8cd61db-1e60-42f4-b8c6-8ed0397ce849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824530451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3824530451
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.736427269
Short name T638
Test name
Test status
Simulation time 927972178 ps
CPU time 1.95 seconds
Started Aug 12 06:25:17 PM PDT 24
Finished Aug 12 06:25:19 PM PDT 24
Peak memory 208836 kb
Host smart-e4498190-89cd-4902-8be7-783d56d332ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736427269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.736427269
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.387375759
Short name T857
Test name
Test status
Simulation time 102141391 ps
CPU time 2.2 seconds
Started Aug 12 06:24:54 PM PDT 24
Finished Aug 12 06:24:56 PM PDT 24
Peak memory 217332 kb
Host smart-44ed1e9e-0761-4966-b436-4fdab9f5c01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387375759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.387375759
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3560623239
Short name T326
Test name
Test status
Simulation time 103629752 ps
CPU time 0.78 seconds
Started Aug 12 06:25:09 PM PDT 24
Finished Aug 12 06:25:10 PM PDT 24
Peak memory 206996 kb
Host smart-f8ca94b5-fab3-4770-8014-a51e102ae792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560623239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3560623239
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.109099910
Short name T201
Test name
Test status
Simulation time 1731957811 ps
CPU time 7.22 seconds
Started Aug 12 06:25:13 PM PDT 24
Finished Aug 12 06:25:20 PM PDT 24
Peak memory 250164 kb
Host smart-66141d9f-2e67-4a3a-8f41-a46a1eb46807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109099910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.109099910
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1705697386
Short name T480
Test name
Test status
Simulation time 14129830 ps
CPU time 0.71 seconds
Started Aug 12 06:25:15 PM PDT 24
Finished Aug 12 06:25:15 PM PDT 24
Peak memory 206812 kb
Host smart-77b00cbb-331d-4c52-b9e7-7e677453d0af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705697386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1705697386
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.75654597
Short name T966
Test name
Test status
Simulation time 6408246043 ps
CPU time 20.82 seconds
Started Aug 12 06:25:11 PM PDT 24
Finished Aug 12 06:25:37 PM PDT 24
Peak memory 225712 kb
Host smart-ddd42136-f36f-4be4-9895-55df9758ceba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75654597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.75654597
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1186941057
Short name T632
Test name
Test status
Simulation time 40125596 ps
CPU time 0.75 seconds
Started Aug 12 06:25:19 PM PDT 24
Finished Aug 12 06:25:20 PM PDT 24
Peak memory 207924 kb
Host smart-37965473-6be6-4fb2-b5a7-5cafd0218e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186941057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1186941057
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3292236144
Short name T704
Test name
Test status
Simulation time 20565815872 ps
CPU time 164.62 seconds
Started Aug 12 06:25:07 PM PDT 24
Finished Aug 12 06:27:52 PM PDT 24
Peak memory 250324 kb
Host smart-d8f2143a-8352-4b3a-ac29-1b3c3e8133b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292236144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3292236144
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.458212962
Short name T517
Test name
Test status
Simulation time 12323919179 ps
CPU time 68.92 seconds
Started Aug 12 06:25:11 PM PDT 24
Finished Aug 12 06:26:20 PM PDT 24
Peak memory 263352 kb
Host smart-1fbb311e-d2ff-4e83-99a5-2b3169d8bf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458212962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.458212962
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2720944511
Short name T367
Test name
Test status
Simulation time 17270453961 ps
CPU time 65.31 seconds
Started Aug 12 06:25:19 PM PDT 24
Finished Aug 12 06:26:25 PM PDT 24
Peak memory 257284 kb
Host smart-9c30faf3-d21d-43cb-a3e0-cdd994537ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720944511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2720944511
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.289350270
Short name T264
Test name
Test status
Simulation time 18761929744 ps
CPU time 50.93 seconds
Started Aug 12 06:24:54 PM PDT 24
Finished Aug 12 06:25:45 PM PDT 24
Peak memory 225744 kb
Host smart-ea8c86d5-bcff-483c-a5f7-5244ac388dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289350270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.289350270
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.692004380
Short name T287
Test name
Test status
Simulation time 49603158 ps
CPU time 0.75 seconds
Started Aug 12 06:25:10 PM PDT 24
Finished Aug 12 06:25:11 PM PDT 24
Peak memory 216792 kb
Host smart-796447bc-65bd-4bd5-beb5-8482e39c38c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692004380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.692004380
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2717211648
Short name T208
Test name
Test status
Simulation time 1244340706 ps
CPU time 9.61 seconds
Started Aug 12 06:25:07 PM PDT 24
Finished Aug 12 06:25:16 PM PDT 24
Peak memory 233776 kb
Host smart-779028a9-78fb-4dd3-9f79-ab20cf2103a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717211648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2717211648
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2312359425
Short name T619
Test name
Test status
Simulation time 1291260981 ps
CPU time 18.57 seconds
Started Aug 12 06:24:58 PM PDT 24
Finished Aug 12 06:25:17 PM PDT 24
Peak memory 241536 kb
Host smart-23e0494a-6ebf-46bb-a26d-30e484a31fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312359425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2312359425
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.524706399
Short name T222
Test name
Test status
Simulation time 1126677586 ps
CPU time 6.12 seconds
Started Aug 12 06:24:59 PM PDT 24
Finished Aug 12 06:25:05 PM PDT 24
Peak memory 225592 kb
Host smart-f1cbd2b4-c38b-4360-ac82-09bf599a638b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524706399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.524706399
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2658924949
Short name T493
Test name
Test status
Simulation time 8331868824 ps
CPU time 17.49 seconds
Started Aug 12 06:24:58 PM PDT 24
Finished Aug 12 06:25:15 PM PDT 24
Peak memory 235296 kb
Host smart-13bb348a-c911-428b-ae9e-a0cca76cb3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658924949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2658924949
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1606218298
Short name T988
Test name
Test status
Simulation time 11072099554 ps
CPU time 6.82 seconds
Started Aug 12 06:25:19 PM PDT 24
Finished Aug 12 06:25:26 PM PDT 24
Peak memory 224396 kb
Host smart-ffed9563-a859-4b1f-b2b2-3a8eea5f14ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1606218298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1606218298
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1911773421
Short name T368
Test name
Test status
Simulation time 1572383461 ps
CPU time 36.9 seconds
Started Aug 12 06:25:17 PM PDT 24
Finished Aug 12 06:25:54 PM PDT 24
Peak memory 251264 kb
Host smart-f62e311a-785b-458e-9239-9ca89e370677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911773421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1911773421
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.205629120
Short name T824
Test name
Test status
Simulation time 16296650749 ps
CPU time 21.48 seconds
Started Aug 12 06:25:06 PM PDT 24
Finished Aug 12 06:25:28 PM PDT 24
Peak memory 222032 kb
Host smart-60be9b43-29d8-4352-8165-ee39e84d84fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205629120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.205629120
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3850308193
Short name T545
Test name
Test status
Simulation time 4996865209 ps
CPU time 5.3 seconds
Started Aug 12 06:25:00 PM PDT 24
Finished Aug 12 06:25:06 PM PDT 24
Peak memory 217448 kb
Host smart-171eddb6-f0ed-4856-864d-9d70db5926c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850308193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3850308193
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1656221937
Short name T782
Test name
Test status
Simulation time 137079146 ps
CPU time 1.25 seconds
Started Aug 12 06:25:13 PM PDT 24
Finished Aug 12 06:25:15 PM PDT 24
Peak memory 217332 kb
Host smart-a983db7f-3901-4874-b894-0c957289c8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656221937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1656221937
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.295315041
Short name T455
Test name
Test status
Simulation time 35634433 ps
CPU time 0.77 seconds
Started Aug 12 06:24:59 PM PDT 24
Finished Aug 12 06:25:00 PM PDT 24
Peak memory 206972 kb
Host smart-d657a72f-a6d7-453f-a1c0-711fa0064e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295315041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.295315041
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1903999896
Short name T593
Test name
Test status
Simulation time 257787482 ps
CPU time 3.73 seconds
Started Aug 12 06:25:00 PM PDT 24
Finished Aug 12 06:25:04 PM PDT 24
Peak memory 233816 kb
Host smart-47eb0fac-aa3b-41ab-b7c1-f3c31fe22cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903999896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1903999896
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1788609678
Short name T325
Test name
Test status
Simulation time 15654680 ps
CPU time 0.7 seconds
Started Aug 12 06:25:16 PM PDT 24
Finished Aug 12 06:25:16 PM PDT 24
Peak memory 206492 kb
Host smart-6b952174-224f-4098-be80-b008bb8e92e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788609678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1788609678
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3149712860
Short name T779
Test name
Test status
Simulation time 355782317 ps
CPU time 6.96 seconds
Started Aug 12 06:25:17 PM PDT 24
Finished Aug 12 06:25:24 PM PDT 24
Peak memory 233704 kb
Host smart-d6e70780-dfeb-43ec-adb6-8cf643d62751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149712860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3149712860
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3452255586
Short name T445
Test name
Test status
Simulation time 14016767 ps
CPU time 0.74 seconds
Started Aug 12 06:25:19 PM PDT 24
Finished Aug 12 06:25:20 PM PDT 24
Peak memory 207972 kb
Host smart-d63d1148-4b7e-46dc-9b2f-6b105d12e0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452255586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3452255586
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2082061613
Short name T283
Test name
Test status
Simulation time 27192629 ps
CPU time 0.85 seconds
Started Aug 12 06:25:27 PM PDT 24
Finished Aug 12 06:25:28 PM PDT 24
Peak memory 216808 kb
Host smart-012e7276-5078-409d-a461-2ee4c09c2d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082061613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2082061613
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4172064501
Short name T176
Test name
Test status
Simulation time 18822451647 ps
CPU time 231.49 seconds
Started Aug 12 06:25:18 PM PDT 24
Finished Aug 12 06:29:10 PM PDT 24
Peak memory 265332 kb
Host smart-9fdeeb7c-d225-4f70-8668-240e9729909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172064501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4172064501
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2482452181
Short name T765
Test name
Test status
Simulation time 182573253824 ps
CPU time 92.67 seconds
Started Aug 12 06:25:07 PM PDT 24
Finished Aug 12 06:26:40 PM PDT 24
Peak memory 242148 kb
Host smart-2dee389a-6ac6-4a37-ad7c-7447cf6fa9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482452181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2482452181
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4197859333
Short name T999
Test name
Test status
Simulation time 251463458 ps
CPU time 5.64 seconds
Started Aug 12 06:25:20 PM PDT 24
Finished Aug 12 06:25:25 PM PDT 24
Peak memory 233692 kb
Host smart-7bfaddfd-0fa7-458a-b4da-7bb7e1f045da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197859333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4197859333
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2265755933
Short name T503
Test name
Test status
Simulation time 2901964278 ps
CPU time 6.87 seconds
Started Aug 12 06:25:23 PM PDT 24
Finished Aug 12 06:25:30 PM PDT 24
Peak memory 225716 kb
Host smart-10b5a1a4-75c3-4d14-9a83-25d5d5fd6b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265755933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2265755933
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.140521617
Short name T190
Test name
Test status
Simulation time 138457309 ps
CPU time 2.8 seconds
Started Aug 12 06:25:14 PM PDT 24
Finished Aug 12 06:25:16 PM PDT 24
Peak memory 225616 kb
Host smart-673b6fa2-75eb-4a58-b1e7-88249e5cc0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140521617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.140521617
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3308844375
Short name T836
Test name
Test status
Simulation time 7674661137 ps
CPU time 40.02 seconds
Started Aug 12 06:25:21 PM PDT 24
Finished Aug 12 06:26:01 PM PDT 24
Peak memory 251384 kb
Host smart-6c0b1eb1-8050-4b16-b56b-614967e160a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308844375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3308844375
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.874453097
Short name T1002
Test name
Test status
Simulation time 3508441649 ps
CPU time 11.59 seconds
Started Aug 12 06:25:14 PM PDT 24
Finished Aug 12 06:25:25 PM PDT 24
Peak memory 233932 kb
Host smart-3e9aecea-98f7-4c66-a098-52bd17ac1ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874453097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.874453097
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3279925613
Short name T878
Test name
Test status
Simulation time 27746642625 ps
CPU time 34.28 seconds
Started Aug 12 06:25:13 PM PDT 24
Finished Aug 12 06:25:47 PM PDT 24
Peak memory 232264 kb
Host smart-d8482df5-b305-4958-b9ee-7f2c0bc08bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279925613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3279925613
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3684342801
Short name T145
Test name
Test status
Simulation time 5606024620 ps
CPU time 12.46 seconds
Started Aug 12 06:25:15 PM PDT 24
Finished Aug 12 06:25:28 PM PDT 24
Peak memory 220120 kb
Host smart-593d68dc-9319-4075-98eb-d60eb6cc526d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3684342801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3684342801
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2773370267
Short name T566
Test name
Test status
Simulation time 6925232633 ps
CPU time 145.25 seconds
Started Aug 12 06:25:20 PM PDT 24
Finished Aug 12 06:27:45 PM PDT 24
Peak memory 257068 kb
Host smart-f6d2485f-6b78-4538-8241-bec0733d7d45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773370267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2773370267
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.853439873
Short name T485
Test name
Test status
Simulation time 2575222103 ps
CPU time 8.61 seconds
Started Aug 12 06:25:13 PM PDT 24
Finished Aug 12 06:25:21 PM PDT 24
Peak memory 217452 kb
Host smart-ebe72eec-0bc7-40b9-8d7a-473a1de90bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853439873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.853439873
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.26994503
Short name T307
Test name
Test status
Simulation time 12695100 ps
CPU time 0.72 seconds
Started Aug 12 06:25:10 PM PDT 24
Finished Aug 12 06:25:11 PM PDT 24
Peak memory 206700 kb
Host smart-6b7439c8-25c3-4966-a2a2-560541ccd3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26994503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.26994503
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1743498256
Short name T290
Test name
Test status
Simulation time 126471147 ps
CPU time 0.69 seconds
Started Aug 12 06:25:12 PM PDT 24
Finished Aug 12 06:25:13 PM PDT 24
Peak memory 206672 kb
Host smart-d298bef0-7e21-4162-a18c-00f1c652938b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743498256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1743498256
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3506130989
Short name T536
Test name
Test status
Simulation time 39747343 ps
CPU time 0.74 seconds
Started Aug 12 06:25:17 PM PDT 24
Finished Aug 12 06:25:18 PM PDT 24
Peak memory 206952 kb
Host smart-ca406f1e-5ecb-4691-a799-5785a6141d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506130989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3506130989
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2733108977
Short name T574
Test name
Test status
Simulation time 14275660353 ps
CPU time 13.17 seconds
Started Aug 12 06:25:21 PM PDT 24
Finished Aug 12 06:25:35 PM PDT 24
Peak memory 233896 kb
Host smart-b80029e9-2975-4e6c-bc16-d0c32e2a7ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733108977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2733108977
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.750365298
Short name T776
Test name
Test status
Simulation time 21159034 ps
CPU time 0.73 seconds
Started Aug 12 06:25:27 PM PDT 24
Finished Aug 12 06:25:28 PM PDT 24
Peak memory 206500 kb
Host smart-f082ebc9-6991-42fc-ab32-df35e2432382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750365298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.750365298
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3215347050
Short name T417
Test name
Test status
Simulation time 45784767 ps
CPU time 2.72 seconds
Started Aug 12 06:25:16 PM PDT 24
Finished Aug 12 06:25:19 PM PDT 24
Peak memory 233712 kb
Host smart-3a6da7c2-6ef9-43eb-8703-d648f525313a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215347050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3215347050
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3393790168
Short name T772
Test name
Test status
Simulation time 25816137 ps
CPU time 0.78 seconds
Started Aug 12 06:25:17 PM PDT 24
Finished Aug 12 06:25:18 PM PDT 24
Peak memory 207584 kb
Host smart-62b4734d-6852-45ef-9983-f25d789693e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393790168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3393790168
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1513982381
Short name T459
Test name
Test status
Simulation time 1119653150 ps
CPU time 13.49 seconds
Started Aug 12 06:25:15 PM PDT 24
Finished Aug 12 06:25:29 PM PDT 24
Peak memory 233704 kb
Host smart-f7a94860-2130-46cd-94ec-3c715339b176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513982381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1513982381
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2947630124
Short name T136
Test name
Test status
Simulation time 122440557916 ps
CPU time 258.44 seconds
Started Aug 12 06:25:22 PM PDT 24
Finished Aug 12 06:29:40 PM PDT 24
Peak memory 256724 kb
Host smart-c89a320f-f070-42be-be18-969420e2b461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947630124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2947630124
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3053037045
Short name T424
Test name
Test status
Simulation time 2178359919 ps
CPU time 29.78 seconds
Started Aug 12 06:25:22 PM PDT 24
Finished Aug 12 06:25:52 PM PDT 24
Peak memory 220480 kb
Host smart-0bfe828f-6dc6-4bf2-aab7-17c3f00f4820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053037045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3053037045
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3106379752
Short name T689
Test name
Test status
Simulation time 22273257897 ps
CPU time 103.53 seconds
Started Aug 12 06:25:24 PM PDT 24
Finished Aug 12 06:27:08 PM PDT 24
Peak memory 266688 kb
Host smart-9c3cc81f-4eb0-45fe-b462-2c4ca557fdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106379752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3106379752
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2128329110
Short name T1000
Test name
Test status
Simulation time 405385399 ps
CPU time 4.45 seconds
Started Aug 12 06:25:17 PM PDT 24
Finished Aug 12 06:25:22 PM PDT 24
Peak memory 233788 kb
Host smart-080f45c1-1e55-4245-913f-094d6d464e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128329110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2128329110
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3690939592
Short name T917
Test name
Test status
Simulation time 7008046684 ps
CPU time 72.43 seconds
Started Aug 12 06:25:20 PM PDT 24
Finished Aug 12 06:26:33 PM PDT 24
Peak memory 250008 kb
Host smart-4ac68bce-ea5a-4b2c-aeb9-2ceefd74b122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690939592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3690939592
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2827316771
Short name T329
Test name
Test status
Simulation time 516451806 ps
CPU time 2.36 seconds
Started Aug 12 06:25:13 PM PDT 24
Finished Aug 12 06:25:16 PM PDT 24
Peak memory 224980 kb
Host smart-89f5a707-b407-4f8a-b490-2a3c97e92d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827316771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2827316771
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.819379249
Short name T726
Test name
Test status
Simulation time 509067237 ps
CPU time 3.69 seconds
Started Aug 12 06:25:19 PM PDT 24
Finished Aug 12 06:25:23 PM PDT 24
Peak memory 225596 kb
Host smart-6806ff49-eecc-4c64-820a-5602ed473c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819379249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.819379249
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2761493342
Short name T945
Test name
Test status
Simulation time 1759404380 ps
CPU time 5.35 seconds
Started Aug 12 06:25:07 PM PDT 24
Finished Aug 12 06:25:12 PM PDT 24
Peak memory 221292 kb
Host smart-0194a8e3-ac12-44dd-ba02-8e1cbf8448fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2761493342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2761493342
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4274182973
Short name T241
Test name
Test status
Simulation time 24010347128 ps
CPU time 85.47 seconds
Started Aug 12 06:25:13 PM PDT 24
Finished Aug 12 06:26:38 PM PDT 24
Peak memory 250648 kb
Host smart-ba1ed4d7-f324-4263-bec5-0171e78ef4f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274182973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4274182973
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1003288823
Short name T525
Test name
Test status
Simulation time 10739710516 ps
CPU time 50.67 seconds
Started Aug 12 06:25:04 PM PDT 24
Finished Aug 12 06:25:55 PM PDT 24
Peak memory 217400 kb
Host smart-8458cdac-53da-4abf-9f52-b46766d894c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003288823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1003288823
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2052373810
Short name T925
Test name
Test status
Simulation time 18109055648 ps
CPU time 12.23 seconds
Started Aug 12 06:25:17 PM PDT 24
Finished Aug 12 06:25:29 PM PDT 24
Peak memory 217420 kb
Host smart-3c719eb0-b156-4069-b3c2-0280626d342b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052373810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2052373810
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.646513059
Short name T433
Test name
Test status
Simulation time 237469947 ps
CPU time 1.72 seconds
Started Aug 12 06:25:21 PM PDT 24
Finished Aug 12 06:25:23 PM PDT 24
Peak memory 217400 kb
Host smart-ff58876a-a5c0-49cc-935c-ce3ff35e70de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646513059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.646513059
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2334150370
Short name T989
Test name
Test status
Simulation time 90984620 ps
CPU time 0.8 seconds
Started Aug 12 06:25:19 PM PDT 24
Finished Aug 12 06:25:20 PM PDT 24
Peak memory 206996 kb
Host smart-212e2c81-ccab-45d0-94a8-ee0be32b82cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334150370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2334150370
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1962733114
Short name T512
Test name
Test status
Simulation time 21762521635 ps
CPU time 12.3 seconds
Started Aug 12 06:25:14 PM PDT 24
Finished Aug 12 06:25:27 PM PDT 24
Peak memory 225684 kb
Host smart-cd55ee65-2363-416d-8551-28119c8f9a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962733114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1962733114
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1434769918
Short name T314
Test name
Test status
Simulation time 19865702 ps
CPU time 0.72 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:24:06 PM PDT 24
Peak memory 206488 kb
Host smart-e8750c58-5a79-461d-93e3-81f412cb4572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434769918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
434769918
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3795398922
Short name T586
Test name
Test status
Simulation time 682542506 ps
CPU time 4.7 seconds
Started Aug 12 06:23:54 PM PDT 24
Finished Aug 12 06:23:59 PM PDT 24
Peak memory 233720 kb
Host smart-f97f4479-e212-45b2-8890-1c5edc9dc326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795398922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3795398922
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1522866969
Short name T946
Test name
Test status
Simulation time 60767440 ps
CPU time 0.81 seconds
Started Aug 12 06:24:11 PM PDT 24
Finished Aug 12 06:24:12 PM PDT 24
Peak memory 207784 kb
Host smart-4eb7ca68-6b47-4f60-b15e-c0a7c878d1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522866969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1522866969
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2948360294
Short name T711
Test name
Test status
Simulation time 14223443581 ps
CPU time 69.98 seconds
Started Aug 12 06:23:58 PM PDT 24
Finished Aug 12 06:25:08 PM PDT 24
Peak memory 255808 kb
Host smart-052ffb20-89b0-4b19-9831-34228f5f4f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948360294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2948360294
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2267751441
Short name T238
Test name
Test status
Simulation time 2543342556 ps
CPU time 75.67 seconds
Started Aug 12 06:24:04 PM PDT 24
Finished Aug 12 06:25:20 PM PDT 24
Peak memory 265960 kb
Host smart-c492ab99-853f-47bc-b5df-5841d150769f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267751441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2267751441
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2137925115
Short name T267
Test name
Test status
Simulation time 189145279 ps
CPU time 5.12 seconds
Started Aug 12 06:23:56 PM PDT 24
Finished Aug 12 06:24:07 PM PDT 24
Peak memory 233808 kb
Host smart-cff1763e-3b72-4104-a538-7b6d6dfd89be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137925115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2137925115
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1869040150
Short name T897
Test name
Test status
Simulation time 1939715840 ps
CPU time 18.6 seconds
Started Aug 12 06:24:13 PM PDT 24
Finished Aug 12 06:24:31 PM PDT 24
Peak memory 237464 kb
Host smart-464903a4-0aa4-4402-bb6f-c78861141a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869040150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1869040150
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.569978008
Short name T882
Test name
Test status
Simulation time 766052002 ps
CPU time 11.32 seconds
Started Aug 12 06:23:47 PM PDT 24
Finished Aug 12 06:23:59 PM PDT 24
Peak memory 225584 kb
Host smart-99b4356e-f6d0-4bbf-8e68-9ae1683f3e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569978008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.569978008
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.4047805451
Short name T205
Test name
Test status
Simulation time 4572278640 ps
CPU time 12.19 seconds
Started Aug 12 06:24:00 PM PDT 24
Finished Aug 12 06:24:12 PM PDT 24
Peak memory 233868 kb
Host smart-6bd9ddcb-a874-406e-b41f-10985d96b357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047805451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.4047805451
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3897039036
Short name T502
Test name
Test status
Simulation time 5785931542 ps
CPU time 19.46 seconds
Started Aug 12 06:24:01 PM PDT 24
Finished Aug 12 06:24:20 PM PDT 24
Peak memory 233908 kb
Host smart-096dbadb-e1f2-4b0e-9af5-63dd41eae962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897039036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3897039036
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2368875310
Short name T756
Test name
Test status
Simulation time 860137746 ps
CPU time 4.98 seconds
Started Aug 12 06:24:03 PM PDT 24
Finished Aug 12 06:24:08 PM PDT 24
Peak memory 233772 kb
Host smart-86063110-ebe5-43f2-95cd-68f473130b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368875310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2368875310
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2787875890
Short name T559
Test name
Test status
Simulation time 240343695 ps
CPU time 3.66 seconds
Started Aug 12 06:24:13 PM PDT 24
Finished Aug 12 06:24:17 PM PDT 24
Peak memory 221864 kb
Host smart-b9ae5437-f47c-45c8-b0fb-70c216dca5ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2787875890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2787875890
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3745811981
Short name T20
Test name
Test status
Simulation time 392871127 ps
CPU time 1.12 seconds
Started Aug 12 06:24:13 PM PDT 24
Finished Aug 12 06:24:14 PM PDT 24
Peak memory 237412 kb
Host smart-d3f41692-6f6b-476a-bc4d-7dacf4c15709
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745811981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3745811981
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1932891710
Short name T374
Test name
Test status
Simulation time 55228338887 ps
CPU time 27.36 seconds
Started Aug 12 06:24:03 PM PDT 24
Finished Aug 12 06:24:31 PM PDT 24
Peak memory 217472 kb
Host smart-db1fdc8f-0996-42a7-a479-a388792a48bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932891710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1932891710
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2417247658
Short name T282
Test name
Test status
Simulation time 11308135 ps
CPU time 0.72 seconds
Started Aug 12 06:24:16 PM PDT 24
Finished Aug 12 06:24:17 PM PDT 24
Peak memory 206740 kb
Host smart-6be62be1-fd92-4d4e-9b20-df8919f759e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417247658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2417247658
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1508885546
Short name T795
Test name
Test status
Simulation time 84313396 ps
CPU time 1.56 seconds
Started Aug 12 06:24:09 PM PDT 24
Finished Aug 12 06:24:11 PM PDT 24
Peak memory 217356 kb
Host smart-8fbcfe75-870f-43c1-85fa-ae83c24424b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508885546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1508885546
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.868944961
Short name T633
Test name
Test status
Simulation time 36984212 ps
CPU time 0.79 seconds
Started Aug 12 06:23:53 PM PDT 24
Finished Aug 12 06:23:54 PM PDT 24
Peak memory 207152 kb
Host smart-c63770c6-29bf-4886-99d3-df97ce918829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868944961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.868944961
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2165457703
Short name T592
Test name
Test status
Simulation time 37093821 ps
CPU time 2.31 seconds
Started Aug 12 06:24:01 PM PDT 24
Finished Aug 12 06:24:03 PM PDT 24
Peak memory 225232 kb
Host smart-f08fe592-cd84-46b8-bb47-bcb32508318b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165457703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2165457703
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1167241415
Short name T637
Test name
Test status
Simulation time 55498422 ps
CPU time 0.73 seconds
Started Aug 12 06:25:14 PM PDT 24
Finished Aug 12 06:25:14 PM PDT 24
Peak memory 206452 kb
Host smart-b7fdbf0e-3363-49b7-ba52-0702fff22d86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167241415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1167241415
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3116705596
Short name T218
Test name
Test status
Simulation time 206926232 ps
CPU time 2.86 seconds
Started Aug 12 06:25:23 PM PDT 24
Finished Aug 12 06:25:26 PM PDT 24
Peak memory 225536 kb
Host smart-1fc212ff-e99e-4b9d-af5f-461b1b2ff1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116705596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3116705596
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3250284672
Short name T914
Test name
Test status
Simulation time 16368834 ps
CPU time 0.81 seconds
Started Aug 12 06:25:16 PM PDT 24
Finished Aug 12 06:25:17 PM PDT 24
Peak memory 207632 kb
Host smart-534357a9-de88-44a4-8382-a24621f88e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250284672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3250284672
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2340547422
Short name T803
Test name
Test status
Simulation time 78876917396 ps
CPU time 299.73 seconds
Started Aug 12 06:25:27 PM PDT 24
Finished Aug 12 06:30:27 PM PDT 24
Peak memory 258244 kb
Host smart-df32e476-57ca-4ef6-9502-0f0116a25d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340547422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2340547422
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1649788029
Short name T533
Test name
Test status
Simulation time 2611691488 ps
CPU time 61.37 seconds
Started Aug 12 06:25:29 PM PDT 24
Finished Aug 12 06:26:31 PM PDT 24
Peak memory 250368 kb
Host smart-3dfb750e-3467-48d7-9a55-e0d8cf1ce86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649788029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1649788029
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1053990767
Short name T250
Test name
Test status
Simulation time 10165470553 ps
CPU time 96.55 seconds
Started Aug 12 06:25:16 PM PDT 24
Finished Aug 12 06:26:58 PM PDT 24
Peak memory 253908 kb
Host smart-65ba2843-321f-4b71-9a75-6277febc222e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053990767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1053990767
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.963453315
Short name T473
Test name
Test status
Simulation time 1108642093 ps
CPU time 5.53 seconds
Started Aug 12 06:25:22 PM PDT 24
Finished Aug 12 06:25:28 PM PDT 24
Peak memory 233832 kb
Host smart-3f8a61b0-d51f-4fe2-a87c-de6151bb2149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963453315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.963453315
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1172545475
Short name T723
Test name
Test status
Simulation time 9714695975 ps
CPU time 55.79 seconds
Started Aug 12 06:25:34 PM PDT 24
Finished Aug 12 06:26:30 PM PDT 24
Peak memory 258468 kb
Host smart-c18d5885-30b7-475b-b1ff-57ba05365a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172545475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1172545475
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.366270245
Short name T372
Test name
Test status
Simulation time 5658774486 ps
CPU time 25.26 seconds
Started Aug 12 06:25:10 PM PDT 24
Finished Aug 12 06:25:36 PM PDT 24
Peak memory 225696 kb
Host smart-b3288692-0a56-4e48-b836-13f8f4c11160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366270245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.366270245
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1774054362
Short name T284
Test name
Test status
Simulation time 107293702 ps
CPU time 2.29 seconds
Started Aug 12 06:25:16 PM PDT 24
Finished Aug 12 06:25:18 PM PDT 24
Peak memory 225108 kb
Host smart-287963e2-4474-42c2-bbe0-96ebbd93ca95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774054362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1774054362
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.4161834949
Short name T733
Test name
Test status
Simulation time 6382698728 ps
CPU time 9.84 seconds
Started Aug 12 06:25:18 PM PDT 24
Finished Aug 12 06:25:28 PM PDT 24
Peak memory 233912 kb
Host smart-daf3eab3-7a70-4fa4-9c7d-777c71331873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161834949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.4161834949
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.250083825
Short name T78
Test name
Test status
Simulation time 8106126551 ps
CPU time 16.99 seconds
Started Aug 12 06:25:19 PM PDT 24
Finished Aug 12 06:25:36 PM PDT 24
Peak memory 219932 kb
Host smart-a016941d-f877-45f2-b12f-27826acf24fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250083825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.250083825
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.732131494
Short name T435
Test name
Test status
Simulation time 1068579250 ps
CPU time 5.23 seconds
Started Aug 12 06:25:29 PM PDT 24
Finished Aug 12 06:25:35 PM PDT 24
Peak memory 224220 kb
Host smart-c5b6b7b4-c526-4462-ba04-6e38eed739ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=732131494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.732131494
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.833324260
Short name T817
Test name
Test status
Simulation time 3881960495 ps
CPU time 71.73 seconds
Started Aug 12 06:25:21 PM PDT 24
Finished Aug 12 06:26:33 PM PDT 24
Peak memory 250684 kb
Host smart-236b02d3-6da2-42db-b0dd-3c0365fedb07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833324260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.833324260
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3660801022
Short name T458
Test name
Test status
Simulation time 1846118514 ps
CPU time 9.26 seconds
Started Aug 12 06:25:17 PM PDT 24
Finished Aug 12 06:25:27 PM PDT 24
Peak memory 217208 kb
Host smart-d36d0c49-d1c0-4677-9ecb-519d628dd82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660801022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3660801022
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1601250190
Short name T794
Test name
Test status
Simulation time 861950505 ps
CPU time 3.13 seconds
Started Aug 12 06:25:16 PM PDT 24
Finished Aug 12 06:25:20 PM PDT 24
Peak memory 217408 kb
Host smart-92e829b4-84e7-44ea-89a8-fe8f9b848b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601250190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1601250190
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2285580512
Short name T859
Test name
Test status
Simulation time 1215529262 ps
CPU time 5.19 seconds
Started Aug 12 06:25:22 PM PDT 24
Finished Aug 12 06:25:28 PM PDT 24
Peak memory 217292 kb
Host smart-41d4f908-fc1d-4796-8f53-83432567db75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285580512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2285580512
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3677761691
Short name T319
Test name
Test status
Simulation time 70421597 ps
CPU time 0.74 seconds
Started Aug 12 06:25:23 PM PDT 24
Finished Aug 12 06:25:23 PM PDT 24
Peak memory 207060 kb
Host smart-7fd5a786-c2bd-4054-89a1-822e9fb7783d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677761691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3677761691
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.4261112412
Short name T616
Test name
Test status
Simulation time 2669919127 ps
CPU time 11.06 seconds
Started Aug 12 06:25:21 PM PDT 24
Finished Aug 12 06:25:33 PM PDT 24
Peak memory 238464 kb
Host smart-3ee71eaf-283f-45b9-a416-3a8adb7db4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261112412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.4261112412
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3528503123
Short name T285
Test name
Test status
Simulation time 19395480 ps
CPU time 0.75 seconds
Started Aug 12 06:25:20 PM PDT 24
Finished Aug 12 06:25:20 PM PDT 24
Peak memory 206392 kb
Host smart-f53bce4f-7acd-4a97-a75d-005d954c4f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528503123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3528503123
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1513538622
Short name T506
Test name
Test status
Simulation time 719595375 ps
CPU time 7.24 seconds
Started Aug 12 06:25:17 PM PDT 24
Finished Aug 12 06:25:25 PM PDT 24
Peak memory 225500 kb
Host smart-6bd3cc28-9153-4723-a304-40cda69269f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513538622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1513538622
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.4014651611
Short name T958
Test name
Test status
Simulation time 36562621 ps
CPU time 0.85 seconds
Started Aug 12 06:25:25 PM PDT 24
Finished Aug 12 06:25:26 PM PDT 24
Peak memory 207620 kb
Host smart-5a11a2c9-736b-446c-a2f3-4af4152473e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014651611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.4014651611
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.141296150
Short name T880
Test name
Test status
Simulation time 20412655092 ps
CPU time 113.15 seconds
Started Aug 12 06:25:18 PM PDT 24
Finished Aug 12 06:27:11 PM PDT 24
Peak memory 256328 kb
Host smart-547c549b-a7d3-4cd1-aa00-326e0fb0b1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141296150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.141296150
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3400798449
Short name T901
Test name
Test status
Simulation time 2613836540 ps
CPU time 51.02 seconds
Started Aug 12 06:25:17 PM PDT 24
Finished Aug 12 06:26:08 PM PDT 24
Peak memory 252488 kb
Host smart-272872c3-a12e-46a7-98bb-e6a8b4359710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400798449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3400798449
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2765031355
Short name T788
Test name
Test status
Simulation time 23063544716 ps
CPU time 73.89 seconds
Started Aug 12 06:25:19 PM PDT 24
Finished Aug 12 06:26:33 PM PDT 24
Peak memory 258556 kb
Host smart-befbcf26-ae20-454a-a817-3536109704d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765031355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2765031355
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3191530559
Short name T291
Test name
Test status
Simulation time 753869783 ps
CPU time 4.85 seconds
Started Aug 12 06:25:28 PM PDT 24
Finished Aug 12 06:25:33 PM PDT 24
Peak memory 225612 kb
Host smart-940bd48d-9dde-4b71-9dab-20d363521af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191530559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3191530559
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.282105185
Short name T666
Test name
Test status
Simulation time 10316370382 ps
CPU time 70.71 seconds
Started Aug 12 06:25:18 PM PDT 24
Finished Aug 12 06:26:29 PM PDT 24
Peak memory 251576 kb
Host smart-e16a8c57-7cbf-45cf-9889-36872be84526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282105185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.282105185
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2234518056
Short name T509
Test name
Test status
Simulation time 4123324230 ps
CPU time 9.27 seconds
Started Aug 12 06:25:09 PM PDT 24
Finished Aug 12 06:25:19 PM PDT 24
Peak memory 233864 kb
Host smart-02eaaf04-7159-4c1f-baa7-0dac53fcf5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234518056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2234518056
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.86680872
Short name T234
Test name
Test status
Simulation time 6615546450 ps
CPU time 48.08 seconds
Started Aug 12 06:25:16 PM PDT 24
Finished Aug 12 06:26:05 PM PDT 24
Peak memory 237960 kb
Host smart-fe54fd5d-5b52-46a7-bdc9-827509d7eb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86680872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.86680872
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.225249729
Short name T676
Test name
Test status
Simulation time 24124773222 ps
CPU time 18.57 seconds
Started Aug 12 06:25:26 PM PDT 24
Finished Aug 12 06:25:45 PM PDT 24
Peak memory 233888 kb
Host smart-daed64e9-6ca5-442f-9cdb-cd9e8c71ae8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225249729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.225249729
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.4268856272
Short name T784
Test name
Test status
Simulation time 8980392053 ps
CPU time 8.32 seconds
Started Aug 12 06:25:13 PM PDT 24
Finished Aug 12 06:25:21 PM PDT 24
Peak memory 225656 kb
Host smart-51ce5162-844b-4618-9c46-315e38cb0e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268856272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4268856272
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3240924860
Short name T937
Test name
Test status
Simulation time 2142684425 ps
CPU time 5.56 seconds
Started Aug 12 06:25:19 PM PDT 24
Finished Aug 12 06:25:25 PM PDT 24
Peak memory 221628 kb
Host smart-1be0c240-a1d2-452e-b38f-e192db2832eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3240924860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3240924860
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1255333181
Short name T870
Test name
Test status
Simulation time 3407907221 ps
CPU time 30 seconds
Started Aug 12 06:25:28 PM PDT 24
Finished Aug 12 06:25:58 PM PDT 24
Peak memory 217352 kb
Host smart-764a20ea-6121-41d6-ae65-45861115f4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255333181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1255333181
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1498191715
Short name T460
Test name
Test status
Simulation time 9197241467 ps
CPU time 15.06 seconds
Started Aug 12 06:25:12 PM PDT 24
Finished Aug 12 06:25:27 PM PDT 24
Peak memory 217456 kb
Host smart-27ddf16f-6b4b-48a7-9b52-34d8dec47ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498191715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1498191715
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.4240976322
Short name T9
Test name
Test status
Simulation time 644670458 ps
CPU time 5.18 seconds
Started Aug 12 06:25:17 PM PDT 24
Finished Aug 12 06:25:23 PM PDT 24
Peak memory 217304 kb
Host smart-266ddf4c-475b-49d0-a883-0fc2f8e75b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240976322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4240976322
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3710937503
Short name T337
Test name
Test status
Simulation time 95208569 ps
CPU time 0.97 seconds
Started Aug 12 06:25:16 PM PDT 24
Finished Aug 12 06:25:17 PM PDT 24
Peak memory 206964 kb
Host smart-203e07e6-e980-4295-a46f-92cc895325b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710937503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3710937503
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1040837673
Short name T621
Test name
Test status
Simulation time 200381401 ps
CPU time 2.67 seconds
Started Aug 12 06:25:17 PM PDT 24
Finished Aug 12 06:25:20 PM PDT 24
Peak memory 225492 kb
Host smart-62c768f9-f431-4c54-a7b7-10552385557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040837673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1040837673
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2054161553
Short name T589
Test name
Test status
Simulation time 30853780 ps
CPU time 0.67 seconds
Started Aug 12 06:25:23 PM PDT 24
Finished Aug 12 06:25:24 PM PDT 24
Peak memory 206824 kb
Host smart-919f9f51-2d22-4ef3-ae9a-7ff922e5efae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054161553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2054161553
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1350465983
Short name T584
Test name
Test status
Simulation time 642083201 ps
CPU time 6.02 seconds
Started Aug 12 06:25:27 PM PDT 24
Finished Aug 12 06:25:33 PM PDT 24
Peak memory 225536 kb
Host smart-52434817-b403-4859-b3b5-b7babba418c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350465983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1350465983
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.258713928
Short name T923
Test name
Test status
Simulation time 23174697 ps
CPU time 0.74 seconds
Started Aug 12 06:25:33 PM PDT 24
Finished Aug 12 06:25:34 PM PDT 24
Peak memory 206584 kb
Host smart-a681e240-4e7d-44bc-b56c-8ad1f2eb0077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258713928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.258713928
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.608504583
Short name T849
Test name
Test status
Simulation time 33844503817 ps
CPU time 250.52 seconds
Started Aug 12 06:25:21 PM PDT 24
Finished Aug 12 06:29:32 PM PDT 24
Peak memory 258500 kb
Host smart-8d41bcb5-33e0-41cc-ad40-690d0cbcb602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608504583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.608504583
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1433322450
Short name T244
Test name
Test status
Simulation time 14119355436 ps
CPU time 84.82 seconds
Started Aug 12 06:25:18 PM PDT 24
Finished Aug 12 06:26:43 PM PDT 24
Peak memory 254156 kb
Host smart-668f6a8f-1fa2-4dac-a5c4-16e9a10ecc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433322450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1433322450
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.4006606591
Short name T564
Test name
Test status
Simulation time 85766267635 ps
CPU time 215.81 seconds
Started Aug 12 06:25:29 PM PDT 24
Finished Aug 12 06:29:05 PM PDT 24
Peak memory 256020 kb
Host smart-0a5ebf7d-8653-4e7e-bc77-3ea6aea9ba79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006606591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.4006606591
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3621582489
Short name T660
Test name
Test status
Simulation time 160043170 ps
CPU time 6.46 seconds
Started Aug 12 06:25:41 PM PDT 24
Finished Aug 12 06:25:48 PM PDT 24
Peak memory 233824 kb
Host smart-0a086609-384a-400b-8ee1-083c15b462dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621582489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3621582489
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2712350039
Short name T683
Test name
Test status
Simulation time 6951751107 ps
CPU time 70.43 seconds
Started Aug 12 06:25:35 PM PDT 24
Finished Aug 12 06:26:46 PM PDT 24
Peak memory 252872 kb
Host smart-9ad086ae-48e5-4857-b5e9-dd89929f3e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712350039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2712350039
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.74563374
Short name T192
Test name
Test status
Simulation time 1191602619 ps
CPU time 4.67 seconds
Started Aug 12 06:25:09 PM PDT 24
Finished Aug 12 06:25:14 PM PDT 24
Peak memory 225552 kb
Host smart-3ebcd141-db91-41b3-a985-88d0aaf5ec19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74563374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.74563374
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.384898937
Short name T422
Test name
Test status
Simulation time 417450355 ps
CPU time 3.88 seconds
Started Aug 12 06:25:22 PM PDT 24
Finished Aug 12 06:25:26 PM PDT 24
Peak memory 233784 kb
Host smart-5130be3f-e752-4b14-a4de-d61b435e5abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384898937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.384898937
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3528657792
Short name T785
Test name
Test status
Simulation time 2802632545 ps
CPU time 4.34 seconds
Started Aug 12 06:25:18 PM PDT 24
Finished Aug 12 06:25:22 PM PDT 24
Peak memory 225664 kb
Host smart-00a9125a-dda7-4360-98ce-a7687369c928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528657792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3528657792
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1720692874
Short name T978
Test name
Test status
Simulation time 59960054322 ps
CPU time 14.54 seconds
Started Aug 12 06:25:16 PM PDT 24
Finished Aug 12 06:25:30 PM PDT 24
Peak memory 239736 kb
Host smart-9a168dbe-4927-491b-b465-aa3c46a04697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720692874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1720692874
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.347039806
Short name T950
Test name
Test status
Simulation time 6665930211 ps
CPU time 16.46 seconds
Started Aug 12 06:25:22 PM PDT 24
Finished Aug 12 06:25:38 PM PDT 24
Peak memory 220028 kb
Host smart-9f4e4896-ec39-486a-ae87-68f0bb38f4bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=347039806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.347039806
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3918058458
Short name T610
Test name
Test status
Simulation time 3398990104 ps
CPU time 8.84 seconds
Started Aug 12 06:25:20 PM PDT 24
Finished Aug 12 06:25:29 PM PDT 24
Peak memory 217452 kb
Host smart-e7693d8f-e035-4f79-8e1b-32e43e4f451b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918058458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3918058458
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2141991871
Short name T555
Test name
Test status
Simulation time 2482420351 ps
CPU time 1.56 seconds
Started Aug 12 06:25:22 PM PDT 24
Finished Aug 12 06:25:24 PM PDT 24
Peak memory 209004 kb
Host smart-7805fb74-8b65-43ba-9991-3656c4dccbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141991871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2141991871
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3762062637
Short name T148
Test name
Test status
Simulation time 72488990 ps
CPU time 1.39 seconds
Started Aug 12 06:25:22 PM PDT 24
Finished Aug 12 06:25:33 PM PDT 24
Peak memory 217292 kb
Host smart-4c56a30c-419c-420b-a958-3dd0c85ba888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762062637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3762062637
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1831325609
Short name T804
Test name
Test status
Simulation time 17316668 ps
CPU time 0.73 seconds
Started Aug 12 06:25:27 PM PDT 24
Finished Aug 12 06:25:28 PM PDT 24
Peak memory 206956 kb
Host smart-945f3cf4-6bc4-43a6-be7c-3537d6a07bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831325609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1831325609
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.116090207
Short name T800
Test name
Test status
Simulation time 35041247561 ps
CPU time 41.18 seconds
Started Aug 12 06:25:23 PM PDT 24
Finished Aug 12 06:26:04 PM PDT 24
Peak memory 233792 kb
Host smart-9d1006c4-d91a-4f03-976e-1b61f145f526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116090207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.116090207
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3319562727
Short name T531
Test name
Test status
Simulation time 36736423 ps
CPU time 0.71 seconds
Started Aug 12 06:25:49 PM PDT 24
Finished Aug 12 06:25:49 PM PDT 24
Peak memory 206844 kb
Host smart-4914e99d-e295-42e9-90bb-789afbb83709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319562727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3319562727
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2027218278
Short name T801
Test name
Test status
Simulation time 5239070367 ps
CPU time 22.36 seconds
Started Aug 12 06:25:21 PM PDT 24
Finished Aug 12 06:25:43 PM PDT 24
Peak memory 225720 kb
Host smart-bd18b79d-7dbf-49c0-9144-59bc8152b1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027218278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2027218278
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3227158388
Short name T465
Test name
Test status
Simulation time 108809407 ps
CPU time 0.75 seconds
Started Aug 12 06:25:15 PM PDT 24
Finished Aug 12 06:25:16 PM PDT 24
Peak memory 206580 kb
Host smart-0c938b20-b522-45bd-98ba-57ca43e5106a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227158388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3227158388
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1741797020
Short name T198
Test name
Test status
Simulation time 10262414055 ps
CPU time 53.35 seconds
Started Aug 12 06:25:38 PM PDT 24
Finished Aug 12 06:26:32 PM PDT 24
Peak memory 254316 kb
Host smart-1426d791-2038-4e08-9499-d56e8a704a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741797020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1741797020
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3658276099
Short name T120
Test name
Test status
Simulation time 14487062022 ps
CPU time 59.9 seconds
Started Aug 12 06:25:40 PM PDT 24
Finished Aug 12 06:26:40 PM PDT 24
Peak memory 250604 kb
Host smart-abcd9e94-b16d-47b7-a074-70d609f45dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658276099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3658276099
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2390962134
Short name T552
Test name
Test status
Simulation time 5677613211 ps
CPU time 29.91 seconds
Started Aug 12 06:25:25 PM PDT 24
Finished Aug 12 06:25:55 PM PDT 24
Peak memory 220424 kb
Host smart-f7e4ac41-8174-4f4f-b818-0b98f0a2264c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390962134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2390962134
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2006917175
Short name T974
Test name
Test status
Simulation time 37733776 ps
CPU time 2.86 seconds
Started Aug 12 06:25:27 PM PDT 24
Finished Aug 12 06:25:30 PM PDT 24
Peak memory 233804 kb
Host smart-8ca612b7-5e80-4ceb-baf3-999344e01c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006917175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2006917175
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1735253298
Short name T167
Test name
Test status
Simulation time 6551082099 ps
CPU time 17.76 seconds
Started Aug 12 06:25:45 PM PDT 24
Finished Aug 12 06:26:03 PM PDT 24
Peak memory 239404 kb
Host smart-67e5d82f-c29e-49c1-9aa8-ae5d20167a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735253298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1735253298
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1692523020
Short name T412
Test name
Test status
Simulation time 1584408568 ps
CPU time 16.97 seconds
Started Aug 12 06:25:35 PM PDT 24
Finished Aug 12 06:25:52 PM PDT 24
Peak memory 225612 kb
Host smart-bb349e29-e77d-4a50-b9dc-661bfc3fcc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692523020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1692523020
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3766412300
Short name T768
Test name
Test status
Simulation time 6156683219 ps
CPU time 31.79 seconds
Started Aug 12 06:25:43 PM PDT 24
Finished Aug 12 06:26:15 PM PDT 24
Peak memory 242040 kb
Host smart-e68dc410-01cf-4311-b253-59712bc9540c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766412300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3766412300
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.769928033
Short name T561
Test name
Test status
Simulation time 75488234 ps
CPU time 2.42 seconds
Started Aug 12 06:25:28 PM PDT 24
Finished Aug 12 06:25:30 PM PDT 24
Peak memory 225484 kb
Host smart-4a54e29d-d8e1-4153-a595-cfbe016fbb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769928033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.769928033
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2735538703
Short name T599
Test name
Test status
Simulation time 877099445 ps
CPU time 9.52 seconds
Started Aug 12 06:25:28 PM PDT 24
Finished Aug 12 06:25:37 PM PDT 24
Peak memory 233812 kb
Host smart-6790c485-12d8-48b0-8011-e7ef47fd94b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735538703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2735538703
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1289451554
Short name T948
Test name
Test status
Simulation time 3324784219 ps
CPU time 3.9 seconds
Started Aug 12 06:25:31 PM PDT 24
Finished Aug 12 06:25:36 PM PDT 24
Peak memory 220112 kb
Host smart-f51fef46-6829-44ca-9dca-0e49396a3520
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1289451554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1289451554
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3826474123
Short name T457
Test name
Test status
Simulation time 6659939735 ps
CPU time 40.04 seconds
Started Aug 12 06:25:23 PM PDT 24
Finished Aug 12 06:26:03 PM PDT 24
Peak memory 217680 kb
Host smart-74189e9c-5717-4fa7-b4a6-9f1d852cc49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826474123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3826474123
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1555992976
Short name T354
Test name
Test status
Simulation time 25916697611 ps
CPU time 7.43 seconds
Started Aug 12 06:25:22 PM PDT 24
Finished Aug 12 06:25:30 PM PDT 24
Peak memory 217440 kb
Host smart-c59940e9-c334-44b3-8f37-16794f17b6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555992976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1555992976
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4086479470
Short name T669
Test name
Test status
Simulation time 904017739 ps
CPU time 2.66 seconds
Started Aug 12 06:25:29 PM PDT 24
Finished Aug 12 06:25:32 PM PDT 24
Peak memory 217304 kb
Host smart-e88bdbf5-2553-4297-b0c4-77be67ce926f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086479470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4086479470
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1281421641
Short name T411
Test name
Test status
Simulation time 313442387 ps
CPU time 0.82 seconds
Started Aug 12 06:25:24 PM PDT 24
Finished Aug 12 06:25:25 PM PDT 24
Peak memory 206984 kb
Host smart-0072d270-e91b-42d5-933f-3393e4074889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281421641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1281421641
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2452726132
Short name T15
Test name
Test status
Simulation time 9589180405 ps
CPU time 13.6 seconds
Started Aug 12 06:25:21 PM PDT 24
Finished Aug 12 06:25:35 PM PDT 24
Peak memory 231084 kb
Host smart-c9af6d08-28c5-404c-8909-0aead41a1174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452726132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2452726132
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.606548597
Short name T2
Test name
Test status
Simulation time 19998496 ps
CPU time 0.71 seconds
Started Aug 12 06:25:27 PM PDT 24
Finished Aug 12 06:25:27 PM PDT 24
Peak memory 206500 kb
Host smart-89b377fa-e2b3-4761-a634-658b2eb17371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606548597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.606548597
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.4264848652
Short name T877
Test name
Test status
Simulation time 137411672 ps
CPU time 2.2 seconds
Started Aug 12 06:25:34 PM PDT 24
Finished Aug 12 06:25:36 PM PDT 24
Peak memory 225500 kb
Host smart-a3e9e718-47c8-4d24-9125-932797a11384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264848652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.4264848652
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3500024995
Short name T356
Test name
Test status
Simulation time 203624626 ps
CPU time 0.8 seconds
Started Aug 12 06:25:41 PM PDT 24
Finished Aug 12 06:25:42 PM PDT 24
Peak memory 207584 kb
Host smart-a2807b14-5c33-4469-9778-9a1bf7b8cff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500024995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3500024995
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3373735354
Short name T984
Test name
Test status
Simulation time 2338443296 ps
CPU time 38.08 seconds
Started Aug 12 06:25:29 PM PDT 24
Finished Aug 12 06:26:07 PM PDT 24
Peak memory 251792 kb
Host smart-fce909c1-0b41-4330-9ee7-e78ceaa375d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373735354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3373735354
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1521838251
Short name T235
Test name
Test status
Simulation time 5405043682 ps
CPU time 75.12 seconds
Started Aug 12 06:25:20 PM PDT 24
Finished Aug 12 06:26:35 PM PDT 24
Peak memory 266136 kb
Host smart-84085644-c883-4491-801c-38c045cca1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521838251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1521838251
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3935934085
Short name T246
Test name
Test status
Simulation time 146099885978 ps
CPU time 190.65 seconds
Started Aug 12 06:25:37 PM PDT 24
Finished Aug 12 06:28:48 PM PDT 24
Peak memory 250356 kb
Host smart-5e9d1dd0-5254-4141-93d2-376d75c66247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935934085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3935934085
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3979697712
Short name T965
Test name
Test status
Simulation time 1916750540 ps
CPU time 14.29 seconds
Started Aug 12 06:25:30 PM PDT 24
Finished Aug 12 06:25:45 PM PDT 24
Peak memory 225536 kb
Host smart-2dc112de-7e5a-45c3-bcaa-bb3afb7a97bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979697712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3979697712
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3581716702
Short name T170
Test name
Test status
Simulation time 12129874632 ps
CPU time 84.53 seconds
Started Aug 12 06:25:19 PM PDT 24
Finished Aug 12 06:26:43 PM PDT 24
Peak memory 250708 kb
Host smart-05ac592d-0e1a-43b5-a36a-1418ad831b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581716702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3581716702
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3484756791
Short name T963
Test name
Test status
Simulation time 11482169037 ps
CPU time 36.65 seconds
Started Aug 12 06:25:32 PM PDT 24
Finished Aug 12 06:26:09 PM PDT 24
Peak memory 225728 kb
Host smart-dba736cd-a40b-469b-aa5f-9db83251f0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484756791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3484756791
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2967476039
Short name T418
Test name
Test status
Simulation time 1104726412 ps
CPU time 17.15 seconds
Started Aug 12 06:25:20 PM PDT 24
Finished Aug 12 06:25:37 PM PDT 24
Peak memory 241376 kb
Host smart-573fb1f4-8d02-4a79-8eb9-92e140222b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967476039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2967476039
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3908377960
Short name T825
Test name
Test status
Simulation time 4086587594 ps
CPU time 7.19 seconds
Started Aug 12 06:25:26 PM PDT 24
Finished Aug 12 06:25:33 PM PDT 24
Peak memory 225668 kb
Host smart-9d46642a-6d53-4586-9164-14de6df2d75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908377960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3908377960
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1072511198
Short name T530
Test name
Test status
Simulation time 13240640414 ps
CPU time 20.79 seconds
Started Aug 12 06:25:22 PM PDT 24
Finished Aug 12 06:25:43 PM PDT 24
Peak memory 225692 kb
Host smart-9bf14f6e-865c-4203-8b98-3ff9f5cab3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072511198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1072511198
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3046426174
Short name T138
Test name
Test status
Simulation time 8652683136 ps
CPU time 15.27 seconds
Started Aug 12 06:25:32 PM PDT 24
Finished Aug 12 06:25:47 PM PDT 24
Peak memory 221132 kb
Host smart-ff3f5612-a01a-4e37-8505-eeb398f0f05c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3046426174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3046426174
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1971150532
Short name T809
Test name
Test status
Simulation time 56894524 ps
CPU time 1 seconds
Started Aug 12 06:25:22 PM PDT 24
Finished Aug 12 06:25:23 PM PDT 24
Peak memory 207840 kb
Host smart-1156d844-ec19-4448-a922-6cf556bab671
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971150532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1971150532
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3706164169
Short name T960
Test name
Test status
Simulation time 30702696583 ps
CPU time 30.12 seconds
Started Aug 12 06:25:36 PM PDT 24
Finished Aug 12 06:26:06 PM PDT 24
Peak memory 217868 kb
Host smart-363a4259-cf53-4f51-9a74-80cb4c7fb655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706164169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3706164169
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3999650878
Short name T125
Test name
Test status
Simulation time 1191014865 ps
CPU time 6.58 seconds
Started Aug 12 06:25:19 PM PDT 24
Finished Aug 12 06:25:26 PM PDT 24
Peak memory 217260 kb
Host smart-d610e3e9-25f4-404c-a841-5f702d016baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999650878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3999650878
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3827213504
Short name T293
Test name
Test status
Simulation time 31680241 ps
CPU time 1 seconds
Started Aug 12 06:25:18 PM PDT 24
Finished Aug 12 06:25:19 PM PDT 24
Peak memory 208268 kb
Host smart-e27d9ecb-5c04-473c-97d9-60eb66f58dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827213504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3827213504
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.110454282
Short name T309
Test name
Test status
Simulation time 30152386 ps
CPU time 0.75 seconds
Started Aug 12 06:25:20 PM PDT 24
Finished Aug 12 06:25:21 PM PDT 24
Peak memory 206980 kb
Host smart-2c5464fd-d46e-4409-9919-7e8704dd8400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110454282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.110454282
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3466567521
Short name T505
Test name
Test status
Simulation time 1196053429 ps
CPU time 3.08 seconds
Started Aug 12 06:25:31 PM PDT 24
Finished Aug 12 06:25:34 PM PDT 24
Peak memory 233784 kb
Host smart-1b597e9b-c379-4d3f-be07-e5ae7684d948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466567521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3466567521
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2783716119
Short name T735
Test name
Test status
Simulation time 13616550 ps
CPU time 0.7 seconds
Started Aug 12 06:25:49 PM PDT 24
Finished Aug 12 06:25:50 PM PDT 24
Peak memory 205908 kb
Host smart-2a31515c-3aad-40cb-acea-8318990696e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783716119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2783716119
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2270997634
Short name T913
Test name
Test status
Simulation time 339967569 ps
CPU time 4.05 seconds
Started Aug 12 06:25:48 PM PDT 24
Finished Aug 12 06:25:52 PM PDT 24
Peak memory 233768 kb
Host smart-b4cceaf5-51d4-429d-9aad-f6cf6d6b0554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270997634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2270997634
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1360129701
Short name T614
Test name
Test status
Simulation time 61838019 ps
CPU time 0.78 seconds
Started Aug 12 06:25:29 PM PDT 24
Finished Aug 12 06:25:30 PM PDT 24
Peak memory 207656 kb
Host smart-75c17cd8-3586-47a8-b1dc-c23e1858ef49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360129701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1360129701
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3213036500
Short name T961
Test name
Test status
Simulation time 60014685045 ps
CPU time 52.7 seconds
Started Aug 12 06:25:39 PM PDT 24
Finished Aug 12 06:26:32 PM PDT 24
Peak memory 239848 kb
Host smart-06947573-2bea-4dc9-b51c-ab06befa1e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213036500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3213036500
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1985934333
Short name T213
Test name
Test status
Simulation time 31426213078 ps
CPU time 125.48 seconds
Started Aug 12 06:25:42 PM PDT 24
Finished Aug 12 06:27:47 PM PDT 24
Peak memory 240800 kb
Host smart-1ca672e4-4517-4d09-986f-834f91dab754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985934333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1985934333
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4092041030
Short name T871
Test name
Test status
Simulation time 2718872552 ps
CPU time 22.37 seconds
Started Aug 12 06:25:35 PM PDT 24
Finished Aug 12 06:25:58 PM PDT 24
Peak memory 225652 kb
Host smart-87c1a10e-1998-48e4-be78-627027185a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092041030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.4092041030
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.313988647
Short name T140
Test name
Test status
Simulation time 3828962210 ps
CPU time 32.43 seconds
Started Aug 12 06:25:40 PM PDT 24
Finished Aug 12 06:26:13 PM PDT 24
Peak memory 250316 kb
Host smart-1c815de3-9710-4d65-abfe-f4ee6030d389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313988647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.313988647
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.149615709
Short name T179
Test name
Test status
Simulation time 148567491304 ps
CPU time 296.1 seconds
Started Aug 12 06:25:46 PM PDT 24
Finished Aug 12 06:30:43 PM PDT 24
Peak memory 266640 kb
Host smart-5cc6a19c-1fba-4c56-bed8-fac25c185c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149615709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.149615709
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3513281348
Short name T487
Test name
Test status
Simulation time 9956945364 ps
CPU time 13.58 seconds
Started Aug 12 06:25:49 PM PDT 24
Finished Aug 12 06:26:03 PM PDT 24
Peak memory 225636 kb
Host smart-6ed30578-2bd4-4c6b-8b6c-d4f81f731ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513281348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3513281348
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3815676930
Short name T492
Test name
Test status
Simulation time 1395853500 ps
CPU time 15.4 seconds
Started Aug 12 06:25:44 PM PDT 24
Finished Aug 12 06:25:59 PM PDT 24
Peak memory 233780 kb
Host smart-6f7b48d8-c7aa-4339-b5ba-23a792481928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815676930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3815676930
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2454065311
Short name T391
Test name
Test status
Simulation time 5785369156 ps
CPU time 7.42 seconds
Started Aug 12 06:25:36 PM PDT 24
Finished Aug 12 06:25:43 PM PDT 24
Peak memory 233900 kb
Host smart-ade689b2-d3a7-4eb2-8d38-46dd261ba564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454065311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2454065311
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2178393006
Short name T219
Test name
Test status
Simulation time 739577278 ps
CPU time 5.22 seconds
Started Aug 12 06:25:37 PM PDT 24
Finished Aug 12 06:25:42 PM PDT 24
Peak memory 233784 kb
Host smart-cb106961-d3c4-4aac-9902-6842443e6433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178393006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2178393006
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1884225284
Short name T742
Test name
Test status
Simulation time 563247799 ps
CPU time 4.36 seconds
Started Aug 12 06:25:43 PM PDT 24
Finished Aug 12 06:25:47 PM PDT 24
Peak memory 224116 kb
Host smart-060d163f-d6a4-474c-9d5e-17ad76e0dbe5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1884225284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1884225284
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3528267675
Short name T245
Test name
Test status
Simulation time 52837135858 ps
CPU time 149.37 seconds
Started Aug 12 06:25:51 PM PDT 24
Finished Aug 12 06:28:21 PM PDT 24
Peak memory 272468 kb
Host smart-ffa3e98c-2723-45c3-97be-e86ced12b464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528267675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3528267675
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.447505053
Short name T997
Test name
Test status
Simulation time 1664426626 ps
CPU time 14.27 seconds
Started Aug 12 06:25:25 PM PDT 24
Finished Aug 12 06:25:40 PM PDT 24
Peak memory 217480 kb
Host smart-e116364f-c0e8-496a-a75e-dd6b07870799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447505053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.447505053
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2019638649
Short name T347
Test name
Test status
Simulation time 2557953171 ps
CPU time 7.96 seconds
Started Aug 12 06:25:28 PM PDT 24
Finished Aug 12 06:25:36 PM PDT 24
Peak memory 217392 kb
Host smart-5f8851cb-e00f-4f7e-9fcc-cbc17e00ba2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019638649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2019638649
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1405570159
Short name T407
Test name
Test status
Simulation time 376338301 ps
CPU time 2.75 seconds
Started Aug 12 06:25:42 PM PDT 24
Finished Aug 12 06:25:45 PM PDT 24
Peak memory 217428 kb
Host smart-1697e60e-74d6-44ff-896d-9fd149d16c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405570159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1405570159
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.51926348
Short name T682
Test name
Test status
Simulation time 891740234 ps
CPU time 0.97 seconds
Started Aug 12 06:25:22 PM PDT 24
Finished Aug 12 06:25:23 PM PDT 24
Peak memory 207996 kb
Host smart-e0071d30-8fbf-4b1b-9f6d-5be21c52be76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51926348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.51926348
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4008680281
Short name T993
Test name
Test status
Simulation time 1707979332 ps
CPU time 7.5 seconds
Started Aug 12 06:25:36 PM PDT 24
Finished Aug 12 06:25:44 PM PDT 24
Peak memory 225536 kb
Host smart-4128ee77-a8f3-4af8-b28f-71f165af8b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008680281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4008680281
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1216611478
Short name T55
Test name
Test status
Simulation time 30902799 ps
CPU time 0.72 seconds
Started Aug 12 06:25:43 PM PDT 24
Finished Aug 12 06:25:44 PM PDT 24
Peak memory 206820 kb
Host smart-9f7a2428-64aa-4c54-9d72-0a6336e99255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216611478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1216611478
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1726637932
Short name T491
Test name
Test status
Simulation time 3279644624 ps
CPU time 9.36 seconds
Started Aug 12 06:25:44 PM PDT 24
Finished Aug 12 06:25:54 PM PDT 24
Peak memory 225704 kb
Host smart-0f7ff29a-bbda-4f9b-9382-08727c39f939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726637932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1726637932
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2538289248
Short name T653
Test name
Test status
Simulation time 17908771 ps
CPU time 0.77 seconds
Started Aug 12 06:25:45 PM PDT 24
Finished Aug 12 06:25:46 PM PDT 24
Peak memory 207604 kb
Host smart-56494832-7c16-47c8-b463-0c526c64b671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538289248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2538289248
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2735589066
Short name T813
Test name
Test status
Simulation time 2382998286 ps
CPU time 48.48 seconds
Started Aug 12 06:25:30 PM PDT 24
Finished Aug 12 06:26:19 PM PDT 24
Peak memory 258460 kb
Host smart-79245688-03ee-41a9-a302-a7ba70f340a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735589066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2735589066
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1035839888
Short name T972
Test name
Test status
Simulation time 4987003721 ps
CPU time 47.56 seconds
Started Aug 12 06:25:42 PM PDT 24
Finished Aug 12 06:26:30 PM PDT 24
Peak memory 250384 kb
Host smart-a3de96eb-130b-4753-860c-ccaa3ac2feae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035839888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1035839888
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2255846666
Short name T918
Test name
Test status
Simulation time 5625583722 ps
CPU time 18.82 seconds
Started Aug 12 06:25:32 PM PDT 24
Finished Aug 12 06:25:51 PM PDT 24
Peak memory 242088 kb
Host smart-002640ac-262c-41ba-a851-898cec3cfc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255846666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2255846666
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.4004361880
Short name T157
Test name
Test status
Simulation time 3456623498 ps
CPU time 31.32 seconds
Started Aug 12 06:25:48 PM PDT 24
Finished Aug 12 06:26:20 PM PDT 24
Peak memory 256084 kb
Host smart-e8cd091d-133e-4de3-b171-37e2a86b7f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004361880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.4004361880
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.4193205832
Short name T8
Test name
Test status
Simulation time 17164676373 ps
CPU time 23.87 seconds
Started Aug 12 06:25:43 PM PDT 24
Finished Aug 12 06:26:07 PM PDT 24
Peak memory 225608 kb
Host smart-93a7d48e-1653-497e-bf91-2d4225bfedda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193205832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.4193205832
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3299367791
Short name T952
Test name
Test status
Simulation time 18004140573 ps
CPU time 41.28 seconds
Started Aug 12 06:25:31 PM PDT 24
Finished Aug 12 06:26:18 PM PDT 24
Peak memory 233884 kb
Host smart-79b9272b-2e86-4a52-a72e-95a6a851d3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299367791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3299367791
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1303864791
Short name T962
Test name
Test status
Simulation time 30313222307 ps
CPU time 12.38 seconds
Started Aug 12 06:25:27 PM PDT 24
Finished Aug 12 06:25:40 PM PDT 24
Peak memory 225624 kb
Host smart-253619d4-72a1-418b-902f-769b8a389e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303864791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1303864791
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2944884620
Short name T694
Test name
Test status
Simulation time 6572910419 ps
CPU time 11.84 seconds
Started Aug 12 06:25:48 PM PDT 24
Finished Aug 12 06:26:00 PM PDT 24
Peak memory 225700 kb
Host smart-aa47357e-04bc-4e8c-a774-17eeb4823785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944884620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2944884620
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3788892729
Short name T519
Test name
Test status
Simulation time 511802538 ps
CPU time 8.67 seconds
Started Aug 12 06:25:49 PM PDT 24
Finished Aug 12 06:25:57 PM PDT 24
Peak memory 222620 kb
Host smart-86c831d2-46d1-4055-b9ff-f2e93ad112b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3788892729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3788892729
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3859805204
Short name T154
Test name
Test status
Simulation time 1646754382 ps
CPU time 25 seconds
Started Aug 12 06:25:34 PM PDT 24
Finished Aug 12 06:25:59 PM PDT 24
Peak memory 237636 kb
Host smart-dd70be80-689e-402f-a210-c96bde8198ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859805204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3859805204
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.575190868
Short name T46
Test name
Test status
Simulation time 5653999247 ps
CPU time 19.79 seconds
Started Aug 12 06:25:45 PM PDT 24
Finished Aug 12 06:26:05 PM PDT 24
Peak memory 218116 kb
Host smart-b9796854-e931-4530-8130-1fa2db77bfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575190868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.575190868
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3358759855
Short name T987
Test name
Test status
Simulation time 1117235625 ps
CPU time 4.17 seconds
Started Aug 12 06:25:44 PM PDT 24
Finished Aug 12 06:25:48 PM PDT 24
Peak memory 217376 kb
Host smart-85431606-5219-4510-874c-7136392b15d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358759855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3358759855
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1264256677
Short name T308
Test name
Test status
Simulation time 1111378460 ps
CPU time 5.18 seconds
Started Aug 12 06:25:43 PM PDT 24
Finished Aug 12 06:25:48 PM PDT 24
Peak memory 217324 kb
Host smart-03ca9132-c684-4b66-b2c0-877fe286728d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264256677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1264256677
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.292942666
Short name T928
Test name
Test status
Simulation time 134597836 ps
CPU time 0.9 seconds
Started Aug 12 06:25:38 PM PDT 24
Finished Aug 12 06:25:39 PM PDT 24
Peak memory 207152 kb
Host smart-2958c50e-993b-4bd7-82e9-e6ddf0e8a2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292942666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.292942666
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1587484480
Short name T419
Test name
Test status
Simulation time 2506733911 ps
CPU time 5.45 seconds
Started Aug 12 06:25:33 PM PDT 24
Finished Aug 12 06:25:39 PM PDT 24
Peak memory 225660 kb
Host smart-88fa236c-ecbb-471f-ad8d-4c74cbd508c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587484480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1587484480
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3412475204
Short name T709
Test name
Test status
Simulation time 43161059 ps
CPU time 0.69 seconds
Started Aug 12 06:25:41 PM PDT 24
Finished Aug 12 06:25:42 PM PDT 24
Peak memory 206400 kb
Host smart-2e29589f-45c3-459c-85f2-f6d07ef72554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412475204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3412475204
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.744093770
Short name T986
Test name
Test status
Simulation time 2346259129 ps
CPU time 8.43 seconds
Started Aug 12 06:25:51 PM PDT 24
Finished Aug 12 06:26:00 PM PDT 24
Peak memory 225616 kb
Host smart-f6b89b8a-347c-43f1-b4ac-3de4da6f79e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744093770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.744093770
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3412170414
Short name T934
Test name
Test status
Simulation time 18094420 ps
CPU time 0.83 seconds
Started Aug 12 06:25:48 PM PDT 24
Finished Aug 12 06:25:49 PM PDT 24
Peak memory 207960 kb
Host smart-152606fb-a641-469c-ab0a-e585cfa1feeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412170414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3412170414
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2273429772
Short name T49
Test name
Test status
Simulation time 193014207658 ps
CPU time 397.46 seconds
Started Aug 12 06:25:46 PM PDT 24
Finished Aug 12 06:32:24 PM PDT 24
Peak memory 251356 kb
Host smart-a9514221-04c2-47da-9c21-83253881b5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273429772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2273429772
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.814381318
Short name T129
Test name
Test status
Simulation time 23686316689 ps
CPU time 128.26 seconds
Started Aug 12 06:25:43 PM PDT 24
Finished Aug 12 06:27:51 PM PDT 24
Peak memory 264316 kb
Host smart-9e1a70d5-9ade-47f8-a59c-cc296f197225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814381318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.814381318
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2271354025
Short name T188
Test name
Test status
Simulation time 32239899681 ps
CPU time 334.57 seconds
Started Aug 12 06:25:47 PM PDT 24
Finished Aug 12 06:31:22 PM PDT 24
Peak memory 255048 kb
Host smart-6c4a205b-2a2b-45d4-9c5d-a97e4117088f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271354025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2271354025
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1349189233
Short name T442
Test name
Test status
Simulation time 285114093 ps
CPU time 9.08 seconds
Started Aug 12 06:25:44 PM PDT 24
Finished Aug 12 06:25:53 PM PDT 24
Peak memory 251224 kb
Host smart-33b1a006-457a-44f3-8211-f906af85c0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349189233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1349189233
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1946087634
Short name T855
Test name
Test status
Simulation time 27716845184 ps
CPU time 141.04 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:28:15 PM PDT 24
Peak memory 259092 kb
Host smart-d9225d4d-f0f7-4ce1-bf0c-ea2db19d6488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946087634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1946087634
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3722478993
Short name T461
Test name
Test status
Simulation time 6354711170 ps
CPU time 22.93 seconds
Started Aug 12 06:25:44 PM PDT 24
Finished Aug 12 06:26:07 PM PDT 24
Peak memory 225680 kb
Host smart-918170d3-eb1a-49e2-a51d-e8a4d590daaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722478993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3722478993
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3455131243
Short name T623
Test name
Test status
Simulation time 2446759569 ps
CPU time 10.34 seconds
Started Aug 12 06:25:38 PM PDT 24
Finished Aug 12 06:25:49 PM PDT 24
Peak memory 225704 kb
Host smart-afe350ae-d6dc-478d-9b36-6c7aad5e8e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455131243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3455131243
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2870301138
Short name T919
Test name
Test status
Simulation time 3342098174 ps
CPU time 7.47 seconds
Started Aug 12 06:25:50 PM PDT 24
Finished Aug 12 06:25:57 PM PDT 24
Peak memory 233844 kb
Host smart-b62155b3-a35e-4e3b-9ac5-e62c8aa83aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870301138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2870301138
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2230634988
Short name T720
Test name
Test status
Simulation time 1682996389 ps
CPU time 9.44 seconds
Started Aug 12 06:25:41 PM PDT 24
Finished Aug 12 06:25:51 PM PDT 24
Peak memory 241724 kb
Host smart-ac28547c-bc09-4a18-8fa8-c3e408db0beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230634988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2230634988
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3968674696
Short name T332
Test name
Test status
Simulation time 1273005878 ps
CPU time 5.41 seconds
Started Aug 12 06:25:48 PM PDT 24
Finished Aug 12 06:25:53 PM PDT 24
Peak memory 224124 kb
Host smart-b4561405-e627-4323-ba18-d7029f02daed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3968674696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3968674696
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2928759675
Short name T257
Test name
Test status
Simulation time 26758237826 ps
CPU time 320.67 seconds
Started Aug 12 06:25:43 PM PDT 24
Finished Aug 12 06:31:04 PM PDT 24
Peak memory 263484 kb
Host smart-89c406a9-6dee-4fcf-b21e-d0e9d9f25a57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928759675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2928759675
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.4020425539
Short name T684
Test name
Test status
Simulation time 386474984 ps
CPU time 4.71 seconds
Started Aug 12 06:25:42 PM PDT 24
Finished Aug 12 06:25:47 PM PDT 24
Peak memory 217288 kb
Host smart-034d6a4f-92ec-4937-ab84-63638e90d5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020425539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4020425539
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4244670105
Short name T301
Test name
Test status
Simulation time 5864024188 ps
CPU time 13.48 seconds
Started Aug 12 06:25:42 PM PDT 24
Finished Aug 12 06:25:56 PM PDT 24
Peak memory 217592 kb
Host smart-252e8f31-4e25-4527-a94f-9305e1fb4035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244670105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4244670105
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.381472863
Short name T313
Test name
Test status
Simulation time 27569212 ps
CPU time 1.71 seconds
Started Aug 12 06:25:42 PM PDT 24
Finished Aug 12 06:25:44 PM PDT 24
Peak memory 217264 kb
Host smart-07c9033e-ef54-42c0-9e5e-e9d55a1287b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381472863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.381472863
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.4070201401
Short name T353
Test name
Test status
Simulation time 125813210 ps
CPU time 0.8 seconds
Started Aug 12 06:25:21 PM PDT 24
Finished Aug 12 06:25:22 PM PDT 24
Peak memory 206948 kb
Host smart-4704e0dd-24a7-4941-92db-3a41c5c45347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070201401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.4070201401
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2276917165
Short name T905
Test name
Test status
Simulation time 9471695801 ps
CPU time 8.41 seconds
Started Aug 12 06:25:40 PM PDT 24
Finished Aug 12 06:25:49 PM PDT 24
Peak memory 233868 kb
Host smart-103d898e-fbd9-4811-942f-5a2b3b96cb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276917165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2276917165
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2848937641
Short name T605
Test name
Test status
Simulation time 11694579 ps
CPU time 0.7 seconds
Started Aug 12 06:25:47 PM PDT 24
Finished Aug 12 06:25:48 PM PDT 24
Peak memory 206788 kb
Host smart-81701795-b718-492c-8c6b-d1bd72307b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848937641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2848937641
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.299780287
Short name T811
Test name
Test status
Simulation time 75033316 ps
CPU time 3.04 seconds
Started Aug 12 06:25:44 PM PDT 24
Finished Aug 12 06:25:47 PM PDT 24
Peak memory 233728 kb
Host smart-742db5f7-f9a7-4d4b-8796-204bfed25eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299780287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.299780287
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1701623801
Short name T549
Test name
Test status
Simulation time 56478029 ps
CPU time 0.76 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:25:54 PM PDT 24
Peak memory 207588 kb
Host smart-eb429284-1517-4b3d-ab74-c53b6c2df034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701623801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1701623801
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1853044134
Short name T1
Test name
Test status
Simulation time 10614332384 ps
CPU time 32.25 seconds
Started Aug 12 06:25:49 PM PDT 24
Finished Aug 12 06:26:22 PM PDT 24
Peak memory 251564 kb
Host smart-c58fde47-ceeb-4020-9e29-f69e55fba6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853044134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1853044134
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1941795222
Short name T339
Test name
Test status
Simulation time 2399837494 ps
CPU time 23.63 seconds
Started Aug 12 06:25:45 PM PDT 24
Finished Aug 12 06:26:09 PM PDT 24
Peak memory 225640 kb
Host smart-dad6dd5c-c1a1-47a9-bf6f-d23370affc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941795222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1941795222
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.4167700347
Short name T840
Test name
Test status
Simulation time 6661664608 ps
CPU time 22.02 seconds
Started Aug 12 06:25:45 PM PDT 24
Finished Aug 12 06:26:07 PM PDT 24
Peak memory 239080 kb
Host smart-5d80dd53-411e-409b-811e-a74bce80f36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167700347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.4167700347
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3790058187
Short name T260
Test name
Test status
Simulation time 531652574 ps
CPU time 3.6 seconds
Started Aug 12 06:25:44 PM PDT 24
Finished Aug 12 06:25:47 PM PDT 24
Peak memory 225624 kb
Host smart-2424d3a4-1e7d-4fb9-b46b-84d96394df09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790058187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3790058187
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.635682779
Short name T690
Test name
Test status
Simulation time 7860506781 ps
CPU time 52.26 seconds
Started Aug 12 06:25:42 PM PDT 24
Finished Aug 12 06:26:35 PM PDT 24
Peak memory 255696 kb
Host smart-863b26d4-76fb-4aa6-b1bb-2ebd38a58710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635682779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.635682779
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2152784801
Short name T469
Test name
Test status
Simulation time 3008942143 ps
CPU time 6.3 seconds
Started Aug 12 06:25:49 PM PDT 24
Finished Aug 12 06:25:55 PM PDT 24
Peak memory 225648 kb
Host smart-65c8e178-6616-450e-8e95-f97bc6f52b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152784801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2152784801
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4017350395
Short name T703
Test name
Test status
Simulation time 7484022922 ps
CPU time 6.56 seconds
Started Aug 12 06:25:45 PM PDT 24
Finished Aug 12 06:25:51 PM PDT 24
Peak memory 225696 kb
Host smart-5bcd26e8-0f14-47bd-b5a9-8c784fd2de12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017350395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4017350395
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2906139269
Short name T451
Test name
Test status
Simulation time 3254905959 ps
CPU time 11.86 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:26:05 PM PDT 24
Peak memory 233876 kb
Host smart-013a1792-b607-4708-a02c-def643257a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906139269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2906139269
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1526897483
Short name T994
Test name
Test status
Simulation time 477672566 ps
CPU time 3.7 seconds
Started Aug 12 06:25:50 PM PDT 24
Finished Aug 12 06:25:54 PM PDT 24
Peak memory 225584 kb
Host smart-1f17be95-ba34-4c65-8ebc-a35a3dcce893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526897483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1526897483
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.702681008
Short name T941
Test name
Test status
Simulation time 653203189 ps
CPU time 4.06 seconds
Started Aug 12 06:25:50 PM PDT 24
Finished Aug 12 06:25:55 PM PDT 24
Peak memory 219952 kb
Host smart-93da9207-e7d1-4af4-89d2-b6797512ae65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=702681008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.702681008
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.4243800673
Short name T651
Test name
Test status
Simulation time 191399432 ps
CPU time 1 seconds
Started Aug 12 06:25:50 PM PDT 24
Finished Aug 12 06:25:51 PM PDT 24
Peak memory 208812 kb
Host smart-53d00262-944b-4452-bad4-3179d8094d96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243800673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.4243800673
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3012898136
Short name T26
Test name
Test status
Simulation time 22378503771 ps
CPU time 35.83 seconds
Started Aug 12 06:25:48 PM PDT 24
Finished Aug 12 06:26:24 PM PDT 24
Peak memory 217444 kb
Host smart-c28e1fbb-b681-41a5-bca8-5073438c3fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012898136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3012898136
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3374654167
Short name T373
Test name
Test status
Simulation time 2617737168 ps
CPU time 1.64 seconds
Started Aug 12 06:25:44 PM PDT 24
Finished Aug 12 06:25:46 PM PDT 24
Peak memory 209052 kb
Host smart-36346c9e-0461-4716-9eec-cf5caa92b982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374654167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3374654167
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1496167971
Short name T867
Test name
Test status
Simulation time 504608840 ps
CPU time 2.73 seconds
Started Aug 12 06:25:34 PM PDT 24
Finished Aug 12 06:25:37 PM PDT 24
Peak memory 217352 kb
Host smart-82d30cf0-a128-4cd9-b484-2650f12dd9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496167971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1496167971
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3752471089
Short name T964
Test name
Test status
Simulation time 42421256 ps
CPU time 0.82 seconds
Started Aug 12 06:25:43 PM PDT 24
Finished Aug 12 06:25:44 PM PDT 24
Peak memory 207016 kb
Host smart-aaa51564-a5d1-43ac-bb01-50d5824e837c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752471089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3752471089
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2006100632
Short name T618
Test name
Test status
Simulation time 2637508022 ps
CPU time 9.64 seconds
Started Aug 12 06:25:44 PM PDT 24
Finished Aug 12 06:25:54 PM PDT 24
Peak memory 233816 kb
Host smart-5123a240-ae2b-4d29-aca1-cb8d019fe0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006100632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2006100632
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2023270683
Short name T820
Test name
Test status
Simulation time 158050498 ps
CPU time 0.71 seconds
Started Aug 12 06:25:38 PM PDT 24
Finished Aug 12 06:25:39 PM PDT 24
Peak memory 205904 kb
Host smart-48911560-3db7-4f8b-ad45-064115030fc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023270683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2023270683
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1259157474
Short name T209
Test name
Test status
Simulation time 64443025 ps
CPU time 2.5 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:25:55 PM PDT 24
Peak memory 233708 kb
Host smart-43cad977-3ba2-4fa6-90fa-79e3ce9c5643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259157474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1259157474
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.408697274
Short name T358
Test name
Test status
Simulation time 49716695 ps
CPU time 0.83 seconds
Started Aug 12 06:25:41 PM PDT 24
Finished Aug 12 06:25:42 PM PDT 24
Peak memory 207076 kb
Host smart-c77c5743-0f46-4f6f-b7c7-192336453a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408697274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.408697274
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3876565491
Short name T940
Test name
Test status
Simulation time 77627155937 ps
CPU time 191.56 seconds
Started Aug 12 06:25:45 PM PDT 24
Finished Aug 12 06:28:56 PM PDT 24
Peak memory 252476 kb
Host smart-fc50775c-6ea1-40fb-b11f-5c94ae7aad02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876565491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3876565491
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3394692222
Short name T180
Test name
Test status
Simulation time 10526857160 ps
CPU time 126.06 seconds
Started Aug 12 06:25:55 PM PDT 24
Finished Aug 12 06:28:01 PM PDT 24
Peak memory 264452 kb
Host smart-3d9eeb73-ae6c-478d-9a40-8bb3554c1265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394692222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3394692222
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4183011672
Short name T887
Test name
Test status
Simulation time 3191312403 ps
CPU time 33.95 seconds
Started Aug 12 06:25:51 PM PDT 24
Finished Aug 12 06:26:25 PM PDT 24
Peak memory 233928 kb
Host smart-dfbe7a1d-08c2-4c46-9351-5b000569d476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183011672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4183011672
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.4063013989
Short name T717
Test name
Test status
Simulation time 315231737 ps
CPU time 4.17 seconds
Started Aug 12 06:25:41 PM PDT 24
Finished Aug 12 06:25:45 PM PDT 24
Peak memory 225492 kb
Host smart-5957555b-c81a-4254-b57c-3660646714aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063013989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4063013989
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1690588191
Short name T122
Test name
Test status
Simulation time 10170911494 ps
CPU time 52.87 seconds
Started Aug 12 06:25:52 PM PDT 24
Finished Aug 12 06:26:45 PM PDT 24
Peak memory 255236 kb
Host smart-2887cb42-cf0f-4313-a96e-02a7c3c71056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690588191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1690588191
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2121304535
Short name T718
Test name
Test status
Simulation time 39669926 ps
CPU time 2.65 seconds
Started Aug 12 06:25:42 PM PDT 24
Finished Aug 12 06:25:44 PM PDT 24
Peak memory 233752 kb
Host smart-225d0db6-1560-43cc-a968-094f4d6fa275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121304535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2121304535
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4157457160
Short name T881
Test name
Test status
Simulation time 35355378 ps
CPU time 2.56 seconds
Started Aug 12 06:25:47 PM PDT 24
Finished Aug 12 06:25:50 PM PDT 24
Peak memory 233756 kb
Host smart-bf739fe4-46bc-48c0-a92a-1da2fe2d0685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157457160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4157457160
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3115119542
Short name T384
Test name
Test status
Simulation time 4975949010 ps
CPU time 13.07 seconds
Started Aug 12 06:25:41 PM PDT 24
Finished Aug 12 06:25:54 PM PDT 24
Peak memory 225532 kb
Host smart-c844a274-49c4-4025-9f61-bda5d8584042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115119542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3115119542
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2606013866
Short name T970
Test name
Test status
Simulation time 8574183206 ps
CPU time 7.41 seconds
Started Aug 12 06:25:43 PM PDT 24
Finished Aug 12 06:25:51 PM PDT 24
Peak memory 225652 kb
Host smart-5b3ec503-0c96-4152-9e75-bb95880c03d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606013866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2606013866
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.483293157
Short name T408
Test name
Test status
Simulation time 1417687601 ps
CPU time 4.5 seconds
Started Aug 12 06:25:46 PM PDT 24
Finished Aug 12 06:25:51 PM PDT 24
Peak memory 224232 kb
Host smart-5bebf076-be59-4856-99b1-9e327dcef4d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=483293157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.483293157
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3278576271
Short name T28
Test name
Test status
Simulation time 284340023179 ps
CPU time 663.64 seconds
Started Aug 12 06:25:42 PM PDT 24
Finished Aug 12 06:36:46 PM PDT 24
Peak memory 272228 kb
Host smart-a164068d-91da-4be6-a515-cb875731bc21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278576271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3278576271
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.4107698418
Short name T944
Test name
Test status
Simulation time 3556991379 ps
CPU time 8.96 seconds
Started Aug 12 06:25:38 PM PDT 24
Finished Aug 12 06:25:47 PM PDT 24
Peak memory 221372 kb
Host smart-d954a88e-5232-49d6-ae55-f2f283d3f265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107698418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4107698418
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2516388016
Short name T386
Test name
Test status
Simulation time 2057182036 ps
CPU time 7.85 seconds
Started Aug 12 06:25:46 PM PDT 24
Finished Aug 12 06:25:54 PM PDT 24
Peak memory 217328 kb
Host smart-310f3ae5-e4c9-4a36-809d-8ed7f517401f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516388016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2516388016
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2386427363
Short name T477
Test name
Test status
Simulation time 358485864 ps
CPU time 2.97 seconds
Started Aug 12 06:25:39 PM PDT 24
Finished Aug 12 06:25:42 PM PDT 24
Peak memory 217256 kb
Host smart-8477c41f-6abd-4692-94c7-f58acf9990ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386427363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2386427363
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3517427426
Short name T277
Test name
Test status
Simulation time 19510124 ps
CPU time 0.72 seconds
Started Aug 12 06:25:42 PM PDT 24
Finished Aug 12 06:25:43 PM PDT 24
Peak memory 207004 kb
Host smart-152d9e32-93d2-450e-bfbd-3d46bb48f6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517427426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3517427426
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3939765301
Short name T12
Test name
Test status
Simulation time 808567724 ps
CPU time 7.37 seconds
Started Aug 12 06:25:49 PM PDT 24
Finished Aug 12 06:25:57 PM PDT 24
Peak memory 233716 kb
Host smart-8c4e44f4-a319-41f1-a0bf-36ef9f1e479d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939765301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3939765301
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2687553235
Short name T977
Test name
Test status
Simulation time 66048571 ps
CPU time 0.7 seconds
Started Aug 12 06:24:13 PM PDT 24
Finished Aug 12 06:24:14 PM PDT 24
Peak memory 205944 kb
Host smart-0259cf6b-85a7-4b89-ab05-884f33a29c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687553235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
687553235
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1925219715
Short name T851
Test name
Test status
Simulation time 220153180 ps
CPU time 4.43 seconds
Started Aug 12 06:24:09 PM PDT 24
Finished Aug 12 06:24:14 PM PDT 24
Peak memory 233828 kb
Host smart-de74ca37-983b-4977-bd98-32f7a6a8ed5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925219715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1925219715
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1751068534
Short name T413
Test name
Test status
Simulation time 13868488 ps
CPU time 0.76 seconds
Started Aug 12 06:24:21 PM PDT 24
Finished Aug 12 06:24:23 PM PDT 24
Peak memory 206612 kb
Host smart-dde27f4c-bdd6-4e8c-83d5-4f4659491f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751068534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1751068534
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3724823201
Short name T171
Test name
Test status
Simulation time 11512273849 ps
CPU time 56.85 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:25:02 PM PDT 24
Peak memory 257964 kb
Host smart-fda65515-585f-45f0-9a82-fe393f3db069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724823201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3724823201
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1210971628
Short name T207
Test name
Test status
Simulation time 17449939339 ps
CPU time 66.44 seconds
Started Aug 12 06:24:13 PM PDT 24
Finished Aug 12 06:25:20 PM PDT 24
Peak memory 250288 kb
Host smart-23593651-4be6-4b15-bfb7-43fde058c60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210971628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1210971628
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1677249415
Short name T494
Test name
Test status
Simulation time 8318938992 ps
CPU time 64.25 seconds
Started Aug 12 06:24:03 PM PDT 24
Finished Aug 12 06:25:08 PM PDT 24
Peak memory 250284 kb
Host smart-170b69c7-90a6-446f-82b0-a3a6029f2df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677249415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1677249415
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2130432682
Short name T514
Test name
Test status
Simulation time 2393839980 ps
CPU time 6.73 seconds
Started Aug 12 06:24:19 PM PDT 24
Finished Aug 12 06:24:26 PM PDT 24
Peak memory 237172 kb
Host smart-3aead1d9-5e5d-426c-8c09-514501cc0186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130432682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2130432682
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3843718509
Short name T560
Test name
Test status
Simulation time 3934173418 ps
CPU time 36.53 seconds
Started Aug 12 06:24:04 PM PDT 24
Finished Aug 12 06:24:40 PM PDT 24
Peak memory 252788 kb
Host smart-882f0ea1-6c23-472c-882e-a3fb6942a623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843718509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3843718509
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.141896893
Short name T933
Test name
Test status
Simulation time 870981743 ps
CPU time 5.49 seconds
Started Aug 12 06:24:03 PM PDT 24
Finished Aug 12 06:24:09 PM PDT 24
Peak memory 233744 kb
Host smart-e0a4246b-a247-4f97-8be7-3097291e1c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141896893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.141896893
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.721153181
Short name T856
Test name
Test status
Simulation time 15440001000 ps
CPU time 58.75 seconds
Started Aug 12 06:24:13 PM PDT 24
Finished Aug 12 06:25:12 PM PDT 24
Peak memory 233808 kb
Host smart-42b0b9a0-df6d-4bad-bf2f-531b21251501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721153181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.721153181
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1938759596
Short name T474
Test name
Test status
Simulation time 325351242 ps
CPU time 4.62 seconds
Started Aug 12 06:24:02 PM PDT 24
Finished Aug 12 06:24:07 PM PDT 24
Peak memory 225584 kb
Host smart-d87b0592-20d0-4fe7-9c05-afbfdf7370aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938759596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1938759596
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.679172630
Short name T714
Test name
Test status
Simulation time 637912773 ps
CPU time 3.85 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:24:09 PM PDT 24
Peak memory 225456 kb
Host smart-30c595b1-022c-44f8-b850-b4f92332f2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679172630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.679172630
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1676642014
Short name T848
Test name
Test status
Simulation time 3409729848 ps
CPU time 7.99 seconds
Started Aug 12 06:24:14 PM PDT 24
Finished Aug 12 06:24:22 PM PDT 24
Peak memory 222220 kb
Host smart-9f2c929a-7ade-4053-8c28-38513deca5b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1676642014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1676642014
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2813144759
Short name T61
Test name
Test status
Simulation time 150942266 ps
CPU time 1.01 seconds
Started Aug 12 06:24:16 PM PDT 24
Finished Aug 12 06:24:17 PM PDT 24
Peak memory 236568 kb
Host smart-ba74c42f-b164-4b0e-8442-0ab77e168ee5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813144759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2813144759
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3792473076
Short name T18
Test name
Test status
Simulation time 20585914536 ps
CPU time 80.15 seconds
Started Aug 12 06:24:14 PM PDT 24
Finished Aug 12 06:25:34 PM PDT 24
Peak memory 256208 kb
Host smart-3776b947-3a08-44f6-8b26-6a6a0a51aaa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792473076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3792473076
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2673269864
Short name T891
Test name
Test status
Simulation time 9758006834 ps
CPU time 30.75 seconds
Started Aug 12 06:24:07 PM PDT 24
Finished Aug 12 06:24:38 PM PDT 24
Peak memory 221372 kb
Host smart-b3d9d091-a952-4c9c-af7a-8179dc753701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673269864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2673269864
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.783485352
Short name T359
Test name
Test status
Simulation time 1681928164 ps
CPU time 4.61 seconds
Started Aug 12 06:24:04 PM PDT 24
Finished Aug 12 06:24:08 PM PDT 24
Peak memory 217328 kb
Host smart-d9997b6d-790b-4d99-b0fd-cf208658a2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783485352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.783485352
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3463124742
Short name T428
Test name
Test status
Simulation time 112228412 ps
CPU time 1.19 seconds
Started Aug 12 06:24:28 PM PDT 24
Finished Aug 12 06:24:29 PM PDT 24
Peak memory 208904 kb
Host smart-237693aa-9350-4ab1-a358-ee544f7697f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463124742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3463124742
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1204316968
Short name T127
Test name
Test status
Simulation time 27672824 ps
CPU time 0.77 seconds
Started Aug 12 06:24:04 PM PDT 24
Finished Aug 12 06:24:05 PM PDT 24
Peak memory 206972 kb
Host smart-17b8e0db-9a12-479f-83c3-80cbfc78e785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204316968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1204316968
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3467904766
Short name T172
Test name
Test status
Simulation time 16374160159 ps
CPU time 12.79 seconds
Started Aug 12 06:24:03 PM PDT 24
Finished Aug 12 06:24:16 PM PDT 24
Peak memory 225616 kb
Host smart-45563bbd-663f-4f64-904d-e788d8b1e5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467904766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3467904766
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3100661332
Short name T387
Test name
Test status
Simulation time 47497859 ps
CPU time 0.72 seconds
Started Aug 12 06:25:55 PM PDT 24
Finished Aug 12 06:25:56 PM PDT 24
Peak memory 205832 kb
Host smart-ef1b821e-0b70-4de1-b576-28b04f762419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100661332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3100661332
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1222234193
Short name T967
Test name
Test status
Simulation time 133914689 ps
CPU time 2.49 seconds
Started Aug 12 06:25:47 PM PDT 24
Finished Aug 12 06:25:49 PM PDT 24
Peak memory 225552 kb
Host smart-804c7d7c-a60f-49e7-b3b1-687d06435dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222234193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1222234193
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2230523875
Short name T842
Test name
Test status
Simulation time 94564130 ps
CPU time 0.75 seconds
Started Aug 12 06:25:51 PM PDT 24
Finished Aug 12 06:25:52 PM PDT 24
Peak memory 206572 kb
Host smart-50db95de-5bdb-4fd1-aca9-eb4a187c88a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230523875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2230523875
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.733810230
Short name T771
Test name
Test status
Simulation time 50023295666 ps
CPU time 218.89 seconds
Started Aug 12 06:26:10 PM PDT 24
Finished Aug 12 06:29:49 PM PDT 24
Peak memory 257360 kb
Host smart-353b9733-7cf1-4c91-ac4b-b12fe2d70d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733810230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.733810230
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.44637423
Short name T197
Test name
Test status
Simulation time 34638753956 ps
CPU time 346.49 seconds
Started Aug 12 06:25:51 PM PDT 24
Finished Aug 12 06:31:37 PM PDT 24
Peak memory 258404 kb
Host smart-4edbdf0e-4614-454d-bd70-0ffbf8027f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44637423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.44637423
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1145217403
Short name T580
Test name
Test status
Simulation time 116229287525 ps
CPU time 245.13 seconds
Started Aug 12 06:25:51 PM PDT 24
Finished Aug 12 06:29:56 PM PDT 24
Peak memory 250332 kb
Host smart-84f96ab9-f1d4-4fbb-9af8-d24243309013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145217403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1145217403
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1928232575
Short name T607
Test name
Test status
Simulation time 1175276974 ps
CPU time 5.14 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:25:59 PM PDT 24
Peak memory 233808 kb
Host smart-562d8a64-fbec-4625-8b3f-9459b753d735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928232575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1928232575
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.647895779
Short name T496
Test name
Test status
Simulation time 5931953206 ps
CPU time 60.76 seconds
Started Aug 12 06:25:46 PM PDT 24
Finished Aug 12 06:26:47 PM PDT 24
Peak memory 255616 kb
Host smart-196aaee1-7d66-4387-bb2e-82fc92d2c26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647895779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.647895779
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.95343093
Short name T79
Test name
Test status
Simulation time 623432001 ps
CPU time 4.95 seconds
Started Aug 12 06:26:09 PM PDT 24
Finished Aug 12 06:26:15 PM PDT 24
Peak memory 233836 kb
Host smart-999c014b-3692-4db3-af12-e8b8b07ce26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95343093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.95343093
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1077964203
Short name T195
Test name
Test status
Simulation time 8903010362 ps
CPU time 63.52 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:26:57 PM PDT 24
Peak memory 241916 kb
Host smart-91ce08bd-e40a-4e0d-a7d6-857d7a57a15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077964203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1077964203
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.4237031153
Short name T736
Test name
Test status
Simulation time 812050125 ps
CPU time 4.36 seconds
Started Aug 12 06:25:46 PM PDT 24
Finished Aug 12 06:25:51 PM PDT 24
Peak memory 233800 kb
Host smart-d204461a-e0bc-43f6-b26d-ff96b24ba1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237031153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.4237031153
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2608566742
Short name T858
Test name
Test status
Simulation time 12058046570 ps
CPU time 8.44 seconds
Started Aug 12 06:25:46 PM PDT 24
Finished Aug 12 06:25:54 PM PDT 24
Peak memory 225664 kb
Host smart-383e7056-d03d-43ba-85d4-f1139a7aab1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608566742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2608566742
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.63117706
Short name T141
Test name
Test status
Simulation time 1233917170 ps
CPU time 8.97 seconds
Started Aug 12 06:25:52 PM PDT 24
Finished Aug 12 06:26:01 PM PDT 24
Peak memory 223468 kb
Host smart-353fe4f6-9990-4ae2-a974-00ecdf1d9ae5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=63117706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direc
t.63117706
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2825919474
Short name T17
Test name
Test status
Simulation time 72912272 ps
CPU time 0.98 seconds
Started Aug 12 06:25:59 PM PDT 24
Finished Aug 12 06:26:00 PM PDT 24
Peak memory 208116 kb
Host smart-bcf075a1-83c1-4bae-b0b9-4527a2d027a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825919474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2825919474
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3669012137
Short name T274
Test name
Test status
Simulation time 3743358512 ps
CPU time 12.05 seconds
Started Aug 12 06:25:40 PM PDT 24
Finished Aug 12 06:25:53 PM PDT 24
Peak memory 217688 kb
Host smart-8a70141d-62ab-406f-b0ef-51ba2a97c663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669012137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3669012137
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.381568003
Short name T874
Test name
Test status
Simulation time 287539279 ps
CPU time 2.29 seconds
Started Aug 12 06:25:59 PM PDT 24
Finished Aug 12 06:26:01 PM PDT 24
Peak memory 217316 kb
Host smart-dd57c8a5-5f0b-4d3c-840b-9a1191603667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381568003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.381568003
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.284323106
Short name T658
Test name
Test status
Simulation time 179938388 ps
CPU time 1.32 seconds
Started Aug 12 06:25:46 PM PDT 24
Finished Aug 12 06:25:48 PM PDT 24
Peak memory 217364 kb
Host smart-07dc3bb7-e0d9-4144-a214-468395d65388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284323106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.284323106
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1681513292
Short name T333
Test name
Test status
Simulation time 66160220 ps
CPU time 0.85 seconds
Started Aug 12 06:25:43 PM PDT 24
Finished Aug 12 06:25:44 PM PDT 24
Peak memory 207016 kb
Host smart-60402e13-f175-499a-babd-4732c3858258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681513292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1681513292
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2720632879
Short name T212
Test name
Test status
Simulation time 9760737861 ps
CPU time 9.23 seconds
Started Aug 12 06:25:52 PM PDT 24
Finished Aug 12 06:26:02 PM PDT 24
Peak memory 219740 kb
Host smart-f82b63cc-12a6-410f-aeaa-f558803a5763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720632879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2720632879
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3070432967
Short name T558
Test name
Test status
Simulation time 72722053 ps
CPU time 0.72 seconds
Started Aug 12 06:25:56 PM PDT 24
Finished Aug 12 06:25:57 PM PDT 24
Peak memory 206424 kb
Host smart-ba8da1d9-02fe-450f-983c-6ad1bf0352f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070432967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3070432967
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1411753006
Short name T734
Test name
Test status
Simulation time 49437880 ps
CPU time 2.4 seconds
Started Aug 12 06:25:47 PM PDT 24
Finished Aug 12 06:25:50 PM PDT 24
Peak memory 225592 kb
Host smart-6ae0711a-97f2-429c-a6c3-2dc3a9cfd5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411753006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1411753006
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1868473880
Short name T360
Test name
Test status
Simulation time 24306477 ps
CPU time 0.78 seconds
Started Aug 12 06:25:48 PM PDT 24
Finished Aug 12 06:25:49 PM PDT 24
Peak memory 207632 kb
Host smart-8d1a5c82-dde7-4261-9dcb-469cd0daadf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868473880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1868473880
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1915902110
Short name T65
Test name
Test status
Simulation time 29771125687 ps
CPU time 56.71 seconds
Started Aug 12 06:25:52 PM PDT 24
Finished Aug 12 06:26:49 PM PDT 24
Peak memory 263212 kb
Host smart-d0ab765a-2c8c-4959-910e-eb15060ae9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915902110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1915902110
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2325265554
Short name T410
Test name
Test status
Simulation time 11335534194 ps
CPU time 106.63 seconds
Started Aug 12 06:25:54 PM PDT 24
Finished Aug 12 06:27:41 PM PDT 24
Peak memory 250988 kb
Host smart-ee91c335-872f-4c71-863f-31bce88d2f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325265554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2325265554
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3438303872
Short name T864
Test name
Test status
Simulation time 6800427082 ps
CPU time 106.12 seconds
Started Aug 12 06:25:57 PM PDT 24
Finished Aug 12 06:27:43 PM PDT 24
Peak memory 258576 kb
Host smart-29023f95-52bf-4367-b72f-7ccf9ed2547b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438303872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3438303872
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.83759821
Short name T562
Test name
Test status
Simulation time 251371871 ps
CPU time 5.62 seconds
Started Aug 12 06:25:55 PM PDT 24
Finished Aug 12 06:26:00 PM PDT 24
Peak memory 234836 kb
Host smart-2137540d-b363-4162-aaa4-4697ac580ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83759821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.83759821
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1330603535
Short name T423
Test name
Test status
Simulation time 9651185640 ps
CPU time 57.65 seconds
Started Aug 12 06:25:58 PM PDT 24
Finished Aug 12 06:26:56 PM PDT 24
Peak memory 250484 kb
Host smart-87846c63-165b-442b-8fda-081aa3c4c081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330603535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1330603535
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.895579130
Short name T320
Test name
Test status
Simulation time 100873468 ps
CPU time 2.68 seconds
Started Aug 12 06:26:08 PM PDT 24
Finished Aug 12 06:26:11 PM PDT 24
Peak memory 225572 kb
Host smart-a3908df3-ca73-4d15-a52a-c852504ece10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895579130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.895579130
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1774811753
Short name T762
Test name
Test status
Simulation time 1905317554 ps
CPU time 21.87 seconds
Started Aug 12 06:25:55 PM PDT 24
Finished Aug 12 06:26:17 PM PDT 24
Peak memory 233728 kb
Host smart-35cb2d88-73af-465d-a417-6307d769f7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774811753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1774811753
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1027664928
Short name T832
Test name
Test status
Simulation time 754350758 ps
CPU time 3.6 seconds
Started Aug 12 06:25:44 PM PDT 24
Finished Aug 12 06:25:48 PM PDT 24
Peak memory 233756 kb
Host smart-8cd6ac3e-5d60-4eb2-a905-4878c461608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027664928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1027664928
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3771799091
Short name T608
Test name
Test status
Simulation time 2518390329 ps
CPU time 2.56 seconds
Started Aug 12 06:25:52 PM PDT 24
Finished Aug 12 06:25:54 PM PDT 24
Peak memory 225652 kb
Host smart-c947dd77-e82f-4717-b035-4322dcd49acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771799091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3771799091
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1783024655
Short name T983
Test name
Test status
Simulation time 6689373240 ps
CPU time 13.54 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:26:06 PM PDT 24
Peak memory 221336 kb
Host smart-f46b2e3a-ca08-4244-b248-79fbc4d3f78a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1783024655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1783024655
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4244045584
Short name T242
Test name
Test status
Simulation time 109163845014 ps
CPU time 110.98 seconds
Started Aug 12 06:25:54 PM PDT 24
Finished Aug 12 06:27:45 PM PDT 24
Peak memory 262716 kb
Host smart-b9bf86fb-a3bc-4cbf-a0c1-6b5ed3239779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244045584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4244045584
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1562867823
Short name T781
Test name
Test status
Simulation time 5805181768 ps
CPU time 10.99 seconds
Started Aug 12 06:25:49 PM PDT 24
Finished Aug 12 06:26:01 PM PDT 24
Peak memory 217380 kb
Host smart-fdaabd08-4293-47c0-a4c0-7e4473397d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562867823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1562867823
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3403497596
Short name T357
Test name
Test status
Simulation time 18705255749 ps
CPU time 13.22 seconds
Started Aug 12 06:25:45 PM PDT 24
Finished Aug 12 06:25:59 PM PDT 24
Peak memory 217452 kb
Host smart-cdb371e5-cdf1-4187-addd-88cff1adff9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403497596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3403497596
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2333456010
Short name T831
Test name
Test status
Simulation time 177176927 ps
CPU time 2.1 seconds
Started Aug 12 06:25:49 PM PDT 24
Finished Aug 12 06:25:51 PM PDT 24
Peak memory 217288 kb
Host smart-aed99c07-4bdd-4780-9a55-54961bf62888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333456010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2333456010
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3753606327
Short name T737
Test name
Test status
Simulation time 141934748 ps
CPU time 0.94 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:25:54 PM PDT 24
Peak memory 208012 kb
Host smart-5cc49471-96fa-4fa6-904a-8a79f0ab580b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753606327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3753606327
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.467711511
Short name T750
Test name
Test status
Simulation time 295362309 ps
CPU time 2.36 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:25:55 PM PDT 24
Peak memory 225212 kb
Host smart-61900172-8294-4298-8ee8-066a6547eb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467711511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.467711511
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3988647499
Short name T769
Test name
Test status
Simulation time 54806604 ps
CPU time 0.73 seconds
Started Aug 12 06:25:49 PM PDT 24
Finished Aug 12 06:25:50 PM PDT 24
Peak memory 205868 kb
Host smart-299a7fd5-e366-425c-8a53-6025dcec110b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988647499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3988647499
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2465837595
Short name T577
Test name
Test status
Simulation time 103753321 ps
CPU time 3.11 seconds
Started Aug 12 06:25:55 PM PDT 24
Finished Aug 12 06:26:03 PM PDT 24
Peak memory 233708 kb
Host smart-f3f2aa89-1d7f-4a04-8248-41bf00050ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465837595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2465837595
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.684288988
Short name T695
Test name
Test status
Simulation time 53735629 ps
CPU time 0.77 seconds
Started Aug 12 06:25:51 PM PDT 24
Finished Aug 12 06:25:52 PM PDT 24
Peak memory 207952 kb
Host smart-a4ccc460-8be5-4672-8360-4ca65d8feff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684288988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.684288988
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.4287486863
Short name T206
Test name
Test status
Simulation time 82733299487 ps
CPU time 149.94 seconds
Started Aug 12 06:25:54 PM PDT 24
Finished Aug 12 06:28:24 PM PDT 24
Peak memory 258508 kb
Host smart-2b2f4f4e-513f-462c-af82-7d84a7d0bbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287486863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.4287486863
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2979038578
Short name T780
Test name
Test status
Simulation time 32660321868 ps
CPU time 101.93 seconds
Started Aug 12 06:25:48 PM PDT 24
Finished Aug 12 06:27:30 PM PDT 24
Peak memory 250352 kb
Host smart-d690f072-aa21-4b95-b96f-e8bda3f3d64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979038578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2979038578
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2938892201
Short name T707
Test name
Test status
Simulation time 5913021396 ps
CPU time 35.45 seconds
Started Aug 12 06:25:52 PM PDT 24
Finished Aug 12 06:26:28 PM PDT 24
Peak memory 225772 kb
Host smart-c4d5de79-e39a-4bbc-9677-f6e481057476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938892201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2938892201
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2224038921
Short name T625
Test name
Test status
Simulation time 205865160 ps
CPU time 4.65 seconds
Started Aug 12 06:25:55 PM PDT 24
Finished Aug 12 06:26:00 PM PDT 24
Peak memory 224580 kb
Host smart-1214fa70-06d8-41b0-bc73-0e1ca92fae39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224038921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2224038921
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.567406291
Short name T5
Test name
Test status
Simulation time 6790819407 ps
CPU time 14.2 seconds
Started Aug 12 06:25:57 PM PDT 24
Finished Aug 12 06:26:12 PM PDT 24
Peak memory 242112 kb
Host smart-ad43a93f-30aa-47d8-b082-224aa31038a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567406291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.567406291
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1761040776
Short name T200
Test name
Test status
Simulation time 4475756559 ps
CPU time 18.83 seconds
Started Aug 12 06:25:46 PM PDT 24
Finished Aug 12 06:26:05 PM PDT 24
Peak memory 225688 kb
Host smart-6f8cbc3e-1126-4e25-b576-8daec8669563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761040776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1761040776
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1962993440
Short name T875
Test name
Test status
Simulation time 2538432196 ps
CPU time 19.52 seconds
Started Aug 12 06:25:55 PM PDT 24
Finished Aug 12 06:26:15 PM PDT 24
Peak memory 233904 kb
Host smart-1bbff131-4dda-4cdd-8069-9d8542b71ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962993440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1962993440
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2931960823
Short name T807
Test name
Test status
Simulation time 6046960182 ps
CPU time 19.06 seconds
Started Aug 12 06:25:46 PM PDT 24
Finished Aug 12 06:26:05 PM PDT 24
Peak memory 234044 kb
Host smart-7f5239a6-3132-4d71-8b0d-cd8b9107c96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931960823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2931960823
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.4222196118
Short name T570
Test name
Test status
Simulation time 4435259539 ps
CPU time 15.34 seconds
Started Aug 12 06:25:46 PM PDT 24
Finished Aug 12 06:26:02 PM PDT 24
Peak memory 233928 kb
Host smart-08589391-262f-4b9d-a42a-142fb314da06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222196118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.4222196118
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3715587855
Short name T508
Test name
Test status
Simulation time 2075458835 ps
CPU time 6.77 seconds
Started Aug 12 06:25:51 PM PDT 24
Finished Aug 12 06:25:58 PM PDT 24
Peak memory 224176 kb
Host smart-4d393f42-372e-45f9-b621-36487cb3d3b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3715587855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3715587855
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3523744111
Short name T153
Test name
Test status
Simulation time 32074771994 ps
CPU time 149.59 seconds
Started Aug 12 06:25:54 PM PDT 24
Finished Aug 12 06:28:24 PM PDT 24
Peak memory 282680 kb
Host smart-99e7425f-9982-4f12-ae10-c96f378db378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523744111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3523744111
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.836673571
Short name T269
Test name
Test status
Simulation time 2683679979 ps
CPU time 19.27 seconds
Started Aug 12 06:25:55 PM PDT 24
Finished Aug 12 06:26:15 PM PDT 24
Peak memory 217480 kb
Host smart-55ee83e5-a8a9-4e67-bef7-5baa3033b5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836673571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.836673571
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3044993647
Short name T554
Test name
Test status
Simulation time 11293125190 ps
CPU time 9.71 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:26:03 PM PDT 24
Peak memory 217660 kb
Host smart-3e301891-27df-4573-92f0-0024c6d61fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044993647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3044993647
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3942565691
Short name T542
Test name
Test status
Simulation time 324750802 ps
CPU time 1.26 seconds
Started Aug 12 06:26:02 PM PDT 24
Finished Aug 12 06:26:03 PM PDT 24
Peak memory 209140 kb
Host smart-7218c10d-63fb-4513-838e-39d4337f6552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942565691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3942565691
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2399964425
Short name T910
Test name
Test status
Simulation time 792751764 ps
CPU time 0.97 seconds
Started Aug 12 06:25:49 PM PDT 24
Finished Aug 12 06:25:50 PM PDT 24
Peak memory 207996 kb
Host smart-b83e1500-9616-49e5-96e7-039cc746f30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399964425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2399964425
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.313641987
Short name T404
Test name
Test status
Simulation time 16197504952 ps
CPU time 15.26 seconds
Started Aug 12 06:25:46 PM PDT 24
Finished Aug 12 06:26:02 PM PDT 24
Peak memory 233876 kb
Host smart-e05b126d-23ce-4f39-a586-9f9a5b5e257f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313641987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.313641987
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3552171080
Short name T292
Test name
Test status
Simulation time 37070602 ps
CPU time 0.7 seconds
Started Aug 12 06:25:56 PM PDT 24
Finished Aug 12 06:25:57 PM PDT 24
Peak memory 206812 kb
Host smart-d90d4bca-856a-40dc-93b0-b5a1b5632ebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552171080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3552171080
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1992324312
Short name T889
Test name
Test status
Simulation time 1278382181 ps
CPU time 16.75 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:26:10 PM PDT 24
Peak memory 233796 kb
Host smart-82799175-7b18-49de-9a67-ba3255f46f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992324312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1992324312
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1282450188
Short name T539
Test name
Test status
Simulation time 36111856 ps
CPU time 0.77 seconds
Started Aug 12 06:25:47 PM PDT 24
Finished Aug 12 06:25:48 PM PDT 24
Peak memory 207956 kb
Host smart-b0ed459a-e7e6-484f-8744-cf58c4a41da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282450188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1282450188
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.266454315
Short name T187
Test name
Test status
Simulation time 59052371076 ps
CPU time 418.56 seconds
Started Aug 12 06:25:55 PM PDT 24
Finished Aug 12 06:32:53 PM PDT 24
Peak memory 258468 kb
Host smart-c2b88262-f0c1-4ce4-9141-dfad8ef1d84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266454315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.266454315
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1769394952
Short name T725
Test name
Test status
Simulation time 57316861189 ps
CPU time 483.75 seconds
Started Aug 12 06:25:52 PM PDT 24
Finished Aug 12 06:33:56 PM PDT 24
Peak memory 267724 kb
Host smart-1a80a8b1-82b0-4777-9b30-f73b2489ad85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769394952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1769394952
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2528155274
Short name T256
Test name
Test status
Simulation time 143527729285 ps
CPU time 563.61 seconds
Started Aug 12 06:25:55 PM PDT 24
Finished Aug 12 06:35:19 PM PDT 24
Peak memory 271244 kb
Host smart-63dd483e-9ebe-4487-bd99-8f6cba86e831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528155274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2528155274
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.267259930
Short name T315
Test name
Test status
Simulation time 4280795214 ps
CPU time 15.3 seconds
Started Aug 12 06:25:46 PM PDT 24
Finished Aug 12 06:26:01 PM PDT 24
Peak memory 236252 kb
Host smart-c6549b49-4cee-4c21-a521-7d2917e596d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267259930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.267259930
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3382249249
Short name T535
Test name
Test status
Simulation time 814627640 ps
CPU time 4.75 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:25:58 PM PDT 24
Peak memory 220524 kb
Host smart-984b702c-abf2-4ce8-bfef-999dd4ecee2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382249249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3382249249
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.27057428
Short name T406
Test name
Test status
Simulation time 962696130 ps
CPU time 6.12 seconds
Started Aug 12 06:26:05 PM PDT 24
Finished Aug 12 06:26:11 PM PDT 24
Peak memory 233812 kb
Host smart-00268169-2113-42a7-9f30-161c560ea48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27057428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.27057428
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3158464193
Short name T534
Test name
Test status
Simulation time 2730421858 ps
CPU time 29.72 seconds
Started Aug 12 06:26:00 PM PDT 24
Finished Aug 12 06:26:30 PM PDT 24
Peak memory 233480 kb
Host smart-ac17c5e6-b9ae-4425-a383-b97a18bc3387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158464193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3158464193
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3606142441
Short name T705
Test name
Test status
Simulation time 3940427882 ps
CPU time 8.72 seconds
Started Aug 12 06:25:45 PM PDT 24
Finished Aug 12 06:25:54 PM PDT 24
Peak memory 242040 kb
Host smart-92d2cb52-7cd2-487e-84bf-eb8503541fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606142441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3606142441
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3720689892
Short name T791
Test name
Test status
Simulation time 35277422106 ps
CPU time 27.43 seconds
Started Aug 12 06:25:51 PM PDT 24
Finished Aug 12 06:26:18 PM PDT 24
Peak memory 233904 kb
Host smart-fed33c21-879d-474f-b021-48fa9af25b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720689892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3720689892
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1522053044
Short name T139
Test name
Test status
Simulation time 2729685820 ps
CPU time 5.45 seconds
Started Aug 12 06:26:01 PM PDT 24
Finished Aug 12 06:26:07 PM PDT 24
Peak memory 221632 kb
Host smart-a341b3dc-bb72-4a1e-88d8-97e1be6c7e0e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1522053044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1522053044
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.282256008
Short name T248
Test name
Test status
Simulation time 5365846178 ps
CPU time 49.49 seconds
Started Aug 12 06:25:57 PM PDT 24
Finished Aug 12 06:26:46 PM PDT 24
Peak memory 257988 kb
Host smart-9f55114a-ed58-41de-861f-7e8cc2b7230e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282256008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.282256008
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.4238580965
Short name T691
Test name
Test status
Simulation time 18014358573 ps
CPU time 35.87 seconds
Started Aug 12 06:25:58 PM PDT 24
Finished Aug 12 06:26:35 PM PDT 24
Peak memory 217372 kb
Host smart-92dfdfee-3764-41a7-aeeb-eda02489f272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238580965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4238580965
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2612071651
Short name T590
Test name
Test status
Simulation time 555573177 ps
CPU time 4.31 seconds
Started Aug 12 06:25:51 PM PDT 24
Finished Aug 12 06:25:55 PM PDT 24
Peak memory 217352 kb
Host smart-dd874d6f-bfd2-46b2-abfe-04ae6b740a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612071651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2612071651
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3342002718
Short name T702
Test name
Test status
Simulation time 374538008 ps
CPU time 1.72 seconds
Started Aug 12 06:25:47 PM PDT 24
Finished Aug 12 06:25:49 PM PDT 24
Peak memory 217212 kb
Host smart-9fcb5586-ad52-423f-a45a-96fb595e4dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342002718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3342002718
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.659409131
Short name T819
Test name
Test status
Simulation time 104195147 ps
CPU time 0.79 seconds
Started Aug 12 06:25:46 PM PDT 24
Finished Aug 12 06:25:47 PM PDT 24
Peak memory 206992 kb
Host smart-d0101e37-fa9b-4f2e-814d-05f9154e20d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659409131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.659409131
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.4236370829
Short name T402
Test name
Test status
Simulation time 246775488 ps
CPU time 4.45 seconds
Started Aug 12 06:25:57 PM PDT 24
Finished Aug 12 06:26:01 PM PDT 24
Peak memory 233272 kb
Host smart-f6088e50-8752-4b45-8bf1-d2f700f1293c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236370829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.4236370829
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1380073037
Short name T311
Test name
Test status
Simulation time 14034114 ps
CPU time 0.72 seconds
Started Aug 12 06:25:58 PM PDT 24
Finished Aug 12 06:25:59 PM PDT 24
Peak memory 205940 kb
Host smart-c3e80833-f5fe-4c0e-8df2-4f33f27f5fc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380073037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1380073037
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.986418196
Short name T361
Test name
Test status
Simulation time 139358502 ps
CPU time 2.39 seconds
Started Aug 12 06:25:52 PM PDT 24
Finished Aug 12 06:25:55 PM PDT 24
Peak memory 225536 kb
Host smart-30fba3c8-a679-44cd-8096-b14837782475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986418196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.986418196
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.380870521
Short name T365
Test name
Test status
Simulation time 77658206 ps
CPU time 0.78 seconds
Started Aug 12 06:25:58 PM PDT 24
Finished Aug 12 06:25:59 PM PDT 24
Peak memory 207556 kb
Host smart-a161e1ab-be59-4e34-b100-609c7bc82289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380870521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.380870521
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.818209686
Short name T947
Test name
Test status
Simulation time 16377823029 ps
CPU time 96.25 seconds
Started Aug 12 06:26:07 PM PDT 24
Finished Aug 12 06:27:43 PM PDT 24
Peak memory 250336 kb
Host smart-ecedc85e-16cc-48ff-992e-53687f20efe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818209686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.818209686
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2547320318
Short name T102
Test name
Test status
Simulation time 6641558339 ps
CPU time 32.97 seconds
Started Aug 12 06:25:54 PM PDT 24
Finished Aug 12 06:26:28 PM PDT 24
Peak memory 242172 kb
Host smart-a4b3e482-a9cc-40f7-a15a-1263802ca818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547320318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2547320318
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.228149820
Short name T254
Test name
Test status
Simulation time 451762527427 ps
CPU time 326.84 seconds
Started Aug 12 06:26:22 PM PDT 24
Finished Aug 12 06:31:49 PM PDT 24
Peak memory 252436 kb
Host smart-52323ac2-a0ba-4ec7-b720-e701e0f0306d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228149820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.228149820
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3194093567
Short name T679
Test name
Test status
Simulation time 1895039947 ps
CPU time 14.57 seconds
Started Aug 12 06:25:59 PM PDT 24
Finished Aug 12 06:26:14 PM PDT 24
Peak memory 241568 kb
Host smart-aa02698f-9c65-41ff-83f1-efc81ae4a5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194093567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3194093567
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2838624724
Short name T678
Test name
Test status
Simulation time 8497289584 ps
CPU time 53.54 seconds
Started Aug 12 06:26:22 PM PDT 24
Finished Aug 12 06:27:15 PM PDT 24
Peak memory 256524 kb
Host smart-367c56c0-6526-4e5c-84aa-3fd90e2c34f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838624724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2838624724
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.38762983
Short name T808
Test name
Test status
Simulation time 299602607 ps
CPU time 3.19 seconds
Started Aug 12 06:25:58 PM PDT 24
Finished Aug 12 06:26:01 PM PDT 24
Peak memory 225528 kb
Host smart-ddd67ecb-ebca-4b5b-867f-218ea52c39a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38762983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.38762983
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2783696712
Short name T843
Test name
Test status
Simulation time 461633513 ps
CPU time 3.94 seconds
Started Aug 12 06:25:50 PM PDT 24
Finished Aug 12 06:25:55 PM PDT 24
Peak memory 225520 kb
Host smart-16bbaa09-da76-4ce3-bdb7-1f60d1207f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783696712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2783696712
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.4245106248
Short name T650
Test name
Test status
Simulation time 7792385780 ps
CPU time 10.13 seconds
Started Aug 12 06:25:52 PM PDT 24
Finished Aug 12 06:26:03 PM PDT 24
Peak memory 225164 kb
Host smart-0b900719-d287-406b-ab63-91e36eacb054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245106248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.4245106248
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1694101856
Short name T578
Test name
Test status
Simulation time 35099945119 ps
CPU time 22.09 seconds
Started Aug 12 06:26:11 PM PDT 24
Finished Aug 12 06:26:33 PM PDT 24
Peak memory 240668 kb
Host smart-98e2b880-e9aa-448c-b811-4336899cf8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694101856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1694101856
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3795391470
Short name T32
Test name
Test status
Simulation time 433579320 ps
CPU time 4.23 seconds
Started Aug 12 06:26:10 PM PDT 24
Finished Aug 12 06:26:14 PM PDT 24
Peak memory 224148 kb
Host smart-da309471-e489-49c6-babb-cdfc9a4a9f5a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3795391470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3795391470
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1319616614
Short name T237
Test name
Test status
Simulation time 10403460356 ps
CPU time 141.04 seconds
Started Aug 12 06:25:59 PM PDT 24
Finished Aug 12 06:28:20 PM PDT 24
Peak memory 258432 kb
Host smart-e4027f6a-99e9-4c9d-97ac-aa1ff7a6c72b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319616614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1319616614
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2128224552
Short name T379
Test name
Test status
Simulation time 8643505203 ps
CPU time 24.83 seconds
Started Aug 12 06:26:13 PM PDT 24
Finished Aug 12 06:26:38 PM PDT 24
Peak memory 222288 kb
Host smart-cd727fcb-5ac0-402b-8401-d19f5d9b804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128224552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2128224552
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.623605216
Short name T393
Test name
Test status
Simulation time 1679826279 ps
CPU time 4.68 seconds
Started Aug 12 06:25:58 PM PDT 24
Finished Aug 12 06:26:02 PM PDT 24
Peak memory 217336 kb
Host smart-25168d9b-1e8c-45fd-9b06-c3c886eefe89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623605216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.623605216
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.4072067687
Short name T778
Test name
Test status
Simulation time 101432802 ps
CPU time 0.93 seconds
Started Aug 12 06:26:13 PM PDT 24
Finished Aug 12 06:26:14 PM PDT 24
Peak memory 208448 kb
Host smart-ac7d8929-74cd-41e3-a62e-56e3a95ba65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072067687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4072067687
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.56762069
Short name T806
Test name
Test status
Simulation time 57555896 ps
CPU time 0.8 seconds
Started Aug 12 06:26:18 PM PDT 24
Finished Aug 12 06:26:19 PM PDT 24
Peak memory 207016 kb
Host smart-3bb475ab-aea6-478a-be2d-71d8f7d195d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56762069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.56762069
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.83103674
Short name T949
Test name
Test status
Simulation time 202776301 ps
CPU time 4.28 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:25:58 PM PDT 24
Peak memory 225516 kb
Host smart-6e7bcffc-d503-4b85-bd34-6ea17f62a2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83103674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.83103674
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1459017079
Short name T23
Test name
Test status
Simulation time 22009006 ps
CPU time 0.72 seconds
Started Aug 12 06:26:09 PM PDT 24
Finished Aug 12 06:26:10 PM PDT 24
Peak memory 206452 kb
Host smart-b17ddff2-722c-4959-9eed-8b034614d9db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459017079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1459017079
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2579837124
Short name T231
Test name
Test status
Simulation time 217329562 ps
CPU time 2.35 seconds
Started Aug 12 06:25:55 PM PDT 24
Finished Aug 12 06:25:58 PM PDT 24
Peak memory 225404 kb
Host smart-13a23fbc-cfa3-4455-a6af-38c3b1bb0b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579837124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2579837124
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.239527915
Short name T991
Test name
Test status
Simulation time 269720508 ps
CPU time 0.8 seconds
Started Aug 12 06:25:57 PM PDT 24
Finished Aug 12 06:25:59 PM PDT 24
Peak memory 207564 kb
Host smart-95cf74e4-810b-4ac4-95c5-9a66c0ca0c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239527915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.239527915
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1457315668
Short name T51
Test name
Test status
Simulation time 30296795867 ps
CPU time 154.5 seconds
Started Aug 12 06:25:56 PM PDT 24
Finished Aug 12 06:28:31 PM PDT 24
Peak memory 256612 kb
Host smart-47fdbdbc-0772-422a-824a-afd2ad113516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457315668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1457315668
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2023851327
Short name T186
Test name
Test status
Simulation time 57632853024 ps
CPU time 158.51 seconds
Started Aug 12 06:26:08 PM PDT 24
Finished Aug 12 06:28:47 PM PDT 24
Peak memory 253492 kb
Host smart-658ec386-b6f5-463f-9f1a-87aa7358631d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023851327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2023851327
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1359887676
Short name T181
Test name
Test status
Simulation time 48885491485 ps
CPU time 270.04 seconds
Started Aug 12 06:26:09 PM PDT 24
Finished Aug 12 06:30:39 PM PDT 24
Peak memory 266644 kb
Host smart-c89e70f2-0b45-471c-b0bd-a56dbf52b002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359887676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1359887676
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3977922654
Short name T366
Test name
Test status
Simulation time 419964213 ps
CPU time 3.1 seconds
Started Aug 12 06:26:07 PM PDT 24
Finished Aug 12 06:26:11 PM PDT 24
Peak memory 225584 kb
Host smart-b5511d84-955e-4e94-b5f0-184adfee845c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977922654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3977922654
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1599672782
Short name T866
Test name
Test status
Simulation time 122963940263 ps
CPU time 226.18 seconds
Started Aug 12 06:25:54 PM PDT 24
Finished Aug 12 06:29:40 PM PDT 24
Peak memory 250312 kb
Host smart-380a5302-44f2-4197-b679-902120df4d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599672782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1599672782
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.411303741
Short name T976
Test name
Test status
Simulation time 1050766445 ps
CPU time 10.68 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:26:04 PM PDT 24
Peak memory 233812 kb
Host smart-9a11f765-6b9f-40c7-b577-39c1bf5cc370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411303741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.411303741
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2035212255
Short name T634
Test name
Test status
Simulation time 929255241 ps
CPU time 15.18 seconds
Started Aug 12 06:26:04 PM PDT 24
Finished Aug 12 06:26:20 PM PDT 24
Peak memory 233784 kb
Host smart-df65c589-1a33-4706-8c46-c9aa30b67217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035212255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2035212255
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1104230980
Short name T641
Test name
Test status
Simulation time 59703907624 ps
CPU time 14.16 seconds
Started Aug 12 06:25:59 PM PDT 24
Finished Aug 12 06:26:13 PM PDT 24
Peak memory 233908 kb
Host smart-91e83929-8211-4463-b969-a43b2c45e4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104230980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1104230980
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3619230208
Short name T617
Test name
Test status
Simulation time 1483150608 ps
CPU time 5.05 seconds
Started Aug 12 06:26:04 PM PDT 24
Finished Aug 12 06:26:09 PM PDT 24
Peak memory 225524 kb
Host smart-4ab3c717-33cb-48bd-934e-d970feec4d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619230208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3619230208
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1279317862
Short name T142
Test name
Test status
Simulation time 1069749039 ps
CPU time 9.5 seconds
Started Aug 12 06:26:05 PM PDT 24
Finished Aug 12 06:26:15 PM PDT 24
Peak memory 220324 kb
Host smart-abf5ff20-59da-4be5-9ef9-7f0eea04fa5d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1279317862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1279317862
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2852157897
Short name T133
Test name
Test status
Simulation time 90590165033 ps
CPU time 287.68 seconds
Started Aug 12 06:25:56 PM PDT 24
Finished Aug 12 06:30:44 PM PDT 24
Peak memory 273816 kb
Host smart-72a98923-4006-4c9a-976b-47533eac0854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852157897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2852157897
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1903786242
Short name T754
Test name
Test status
Simulation time 23021435849 ps
CPU time 31.16 seconds
Started Aug 12 06:26:05 PM PDT 24
Finished Aug 12 06:26:36 PM PDT 24
Peak memory 217352 kb
Host smart-d7ee770e-3ee5-43e5-afc2-af4af5ef345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903786242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1903786242
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2516888292
Short name T299
Test name
Test status
Simulation time 12095068 ps
CPU time 0.72 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:26:14 PM PDT 24
Peak memory 206748 kb
Host smart-01810581-7482-46bf-9f75-10f9f605f90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516888292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2516888292
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3462885433
Short name T501
Test name
Test status
Simulation time 13235920 ps
CPU time 0.69 seconds
Started Aug 12 06:26:12 PM PDT 24
Finished Aug 12 06:26:12 PM PDT 24
Peak memory 206644 kb
Host smart-7b8cfb3f-cc2d-4ce4-bb36-962d9022d8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462885433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3462885433
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3900693481
Short name T629
Test name
Test status
Simulation time 100766739 ps
CPU time 0.84 seconds
Started Aug 12 06:26:01 PM PDT 24
Finished Aug 12 06:26:02 PM PDT 24
Peak memory 206956 kb
Host smart-5ce425ab-2488-4cf8-ab73-4013d874f9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900693481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3900693481
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3701337528
Short name T298
Test name
Test status
Simulation time 7900787076 ps
CPU time 9.97 seconds
Started Aug 12 06:25:56 PM PDT 24
Finished Aug 12 06:26:06 PM PDT 24
Peak memory 225772 kb
Host smart-3ffa740d-c412-49f1-9449-04deefa30750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701337528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3701337528
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2216864128
Short name T288
Test name
Test status
Simulation time 21323356 ps
CPU time 0.7 seconds
Started Aug 12 06:26:26 PM PDT 24
Finished Aug 12 06:26:27 PM PDT 24
Peak memory 206804 kb
Host smart-516c0659-3c79-49f9-863c-ef261a555dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216864128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2216864128
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3206412022
Short name T500
Test name
Test status
Simulation time 885827312 ps
CPU time 3.11 seconds
Started Aug 12 06:26:03 PM PDT 24
Finished Aug 12 06:26:06 PM PDT 24
Peak memory 225508 kb
Host smart-b6ede92a-13e1-4f5f-b22c-27d7dd35befc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206412022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3206412022
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1806081302
Short name T394
Test name
Test status
Simulation time 41939913 ps
CPU time 0.72 seconds
Started Aug 12 06:25:55 PM PDT 24
Finished Aug 12 06:25:56 PM PDT 24
Peak memory 205800 kb
Host smart-a2a62c2e-e6c3-44c2-89cd-e62f0103e3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806081302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1806081302
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1610147368
Short name T383
Test name
Test status
Simulation time 2010082567 ps
CPU time 31.83 seconds
Started Aug 12 06:26:05 PM PDT 24
Finished Aug 12 06:26:37 PM PDT 24
Peak memory 253352 kb
Host smart-9853073f-1971-4f94-b78a-6d2b95e453b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610147368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1610147368
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2709674491
Short name T304
Test name
Test status
Simulation time 13776054766 ps
CPU time 23.51 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:26:17 PM PDT 24
Peak memory 233872 kb
Host smart-58399aa3-ff17-4230-a524-d6b749edd4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709674491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2709674491
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1507061345
Short name T598
Test name
Test status
Simulation time 24116408644 ps
CPU time 31.59 seconds
Started Aug 12 06:26:19 PM PDT 24
Finished Aug 12 06:26:51 PM PDT 24
Peak memory 218612 kb
Host smart-1b765c49-fcce-4819-b00b-468598aa0465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507061345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1507061345
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.636617542
Short name T990
Test name
Test status
Simulation time 208053902 ps
CPU time 4.89 seconds
Started Aug 12 06:26:06 PM PDT 24
Finished Aug 12 06:26:16 PM PDT 24
Peak memory 225752 kb
Host smart-4236a504-8d87-45da-845f-971de2fa2be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636617542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.636617542
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4249251984
Short name T77
Test name
Test status
Simulation time 26892197031 ps
CPU time 195.34 seconds
Started Aug 12 06:26:11 PM PDT 24
Finished Aug 12 06:29:26 PM PDT 24
Peak memory 253112 kb
Host smart-143a0ae5-9a50-46a5-ba68-1ca49c54d695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249251984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4249251984
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1889192438
Short name T606
Test name
Test status
Simulation time 1545486869 ps
CPU time 17.02 seconds
Started Aug 12 06:25:56 PM PDT 24
Finished Aug 12 06:26:13 PM PDT 24
Peak memory 225516 kb
Host smart-fb7c60f7-5344-4b83-8899-f0b2e5534861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889192438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1889192438
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3734473467
Short name T644
Test name
Test status
Simulation time 501162482 ps
CPU time 14.56 seconds
Started Aug 12 06:25:55 PM PDT 24
Finished Aug 12 06:26:10 PM PDT 24
Peak memory 225604 kb
Host smart-b727f64e-86d7-4b5e-8752-d08b15d08048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734473467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3734473467
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2686369551
Short name T221
Test name
Test status
Simulation time 8892391634 ps
CPU time 10.2 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:26:24 PM PDT 24
Peak memory 225684 kb
Host smart-d9e25746-9eea-4bb9-83ac-92b52094a40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686369551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2686369551
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3069491278
Short name T444
Test name
Test status
Simulation time 683240988 ps
CPU time 3.82 seconds
Started Aug 12 06:26:09 PM PDT 24
Finished Aug 12 06:26:13 PM PDT 24
Peak memory 233796 kb
Host smart-c10a315a-ff4a-48e1-bd73-29bcb88ebb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069491278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3069491278
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3423845165
Short name T510
Test name
Test status
Simulation time 3295798666 ps
CPU time 9.29 seconds
Started Aug 12 06:25:53 PM PDT 24
Finished Aug 12 06:26:03 PM PDT 24
Peak memory 221708 kb
Host smart-dca239b5-418b-48ad-bdd2-c6afe258f719
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3423845165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3423845165
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1605685389
Short name T131
Test name
Test status
Simulation time 361780944982 ps
CPU time 842.62 seconds
Started Aug 12 06:26:09 PM PDT 24
Finished Aug 12 06:40:12 PM PDT 24
Peak memory 274208 kb
Host smart-794497bb-f3f7-4daa-bafa-5a9883576fd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605685389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1605685389
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2294771710
Short name T278
Test name
Test status
Simulation time 4551618433 ps
CPU time 19.78 seconds
Started Aug 12 06:26:02 PM PDT 24
Finished Aug 12 06:26:22 PM PDT 24
Peak memory 217708 kb
Host smart-c011669a-f69a-43fd-b995-590bfc3f9576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294771710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2294771710
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2123570837
Short name T764
Test name
Test status
Simulation time 2652762759 ps
CPU time 3.32 seconds
Started Aug 12 06:25:54 PM PDT 24
Finished Aug 12 06:25:57 PM PDT 24
Peak memory 217396 kb
Host smart-eb73e0d1-93cb-40de-bb6b-169179980cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123570837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2123570837
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1560566620
Short name T1006
Test name
Test status
Simulation time 339173547 ps
CPU time 1.71 seconds
Started Aug 12 06:26:08 PM PDT 24
Finished Aug 12 06:26:10 PM PDT 24
Peak memory 217256 kb
Host smart-0b39044a-19b7-4497-bfb3-49ea826a5970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560566620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1560566620
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.225247212
Short name T985
Test name
Test status
Simulation time 333953840 ps
CPU time 0.8 seconds
Started Aug 12 06:25:55 PM PDT 24
Finished Aug 12 06:25:56 PM PDT 24
Peak memory 206960 kb
Host smart-523d4d46-bf3c-44e2-9b37-2c684064a92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225247212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.225247212
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1347022191
Short name T1007
Test name
Test status
Simulation time 15203401422 ps
CPU time 13.86 seconds
Started Aug 12 06:25:58 PM PDT 24
Finished Aug 12 06:26:12 PM PDT 24
Peak memory 225656 kb
Host smart-36051365-933c-499e-bf9c-872df2030397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347022191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1347022191
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1804895706
Short name T398
Test name
Test status
Simulation time 12997624 ps
CPU time 0.68 seconds
Started Aug 12 06:26:09 PM PDT 24
Finished Aug 12 06:26:10 PM PDT 24
Peak memory 205928 kb
Host smart-ddb8fbb2-a987-43a4-8d2e-4d14cea0a056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804895706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1804895706
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3462245284
Short name T532
Test name
Test status
Simulation time 9006944264 ps
CPU time 11.1 seconds
Started Aug 12 06:26:12 PM PDT 24
Finished Aug 12 06:26:24 PM PDT 24
Peak memory 233848 kb
Host smart-a5f61851-caaf-4437-be55-e48fa648f2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462245284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3462245284
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3496707410
Short name T1005
Test name
Test status
Simulation time 15806907 ps
CPU time 0.78 seconds
Started Aug 12 06:25:58 PM PDT 24
Finished Aug 12 06:25:59 PM PDT 24
Peak memory 206896 kb
Host smart-38569f7e-4b95-4eb8-8464-0b7476b083e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496707410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3496707410
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4005838310
Short name T904
Test name
Test status
Simulation time 28345198436 ps
CPU time 196.33 seconds
Started Aug 12 06:26:11 PM PDT 24
Finished Aug 12 06:29:28 PM PDT 24
Peak memory 251300 kb
Host smart-bae3977b-823f-4d98-951b-fb1c1edfd6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005838310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4005838310
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1586387703
Short name T786
Test name
Test status
Simulation time 68490904271 ps
CPU time 201.77 seconds
Started Aug 12 06:26:01 PM PDT 24
Finished Aug 12 06:29:22 PM PDT 24
Peak memory 258508 kb
Host smart-b109956c-6f3b-4039-b2b0-a326ef9a44b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586387703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1586387703
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3205698047
Short name T968
Test name
Test status
Simulation time 27643162447 ps
CPU time 186.48 seconds
Started Aug 12 06:26:03 PM PDT 24
Finished Aug 12 06:29:10 PM PDT 24
Peak memory 258348 kb
Host smart-816ad1b8-dbba-4422-ae93-1ddb84bb60a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205698047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3205698047
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.373455431
Short name T793
Test name
Test status
Simulation time 1360322214 ps
CPU time 11.26 seconds
Started Aug 12 06:26:08 PM PDT 24
Finished Aug 12 06:26:24 PM PDT 24
Peak memory 225560 kb
Host smart-56cd4638-0829-4fba-82a5-d983b98c1912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373455431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.373455431
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1010668863
Short name T907
Test name
Test status
Simulation time 2027564604 ps
CPU time 50.68 seconds
Started Aug 12 06:26:09 PM PDT 24
Finished Aug 12 06:27:00 PM PDT 24
Peak memory 256360 kb
Host smart-e64862fd-1e93-4e18-9dd2-d649dfac12b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010668863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1010668863
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.683227805
Short name T775
Test name
Test status
Simulation time 4091561998 ps
CPU time 9.76 seconds
Started Aug 12 06:26:05 PM PDT 24
Finished Aug 12 06:26:15 PM PDT 24
Peak memory 219980 kb
Host smart-7eae6836-bec4-48eb-8e80-91c90247d028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683227805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.683227805
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2256136495
Short name T216
Test name
Test status
Simulation time 26269542101 ps
CPU time 74.62 seconds
Started Aug 12 06:26:00 PM PDT 24
Finished Aug 12 06:27:14 PM PDT 24
Peak memory 242104 kb
Host smart-e6dc4c82-416a-48f9-9ffb-ca7857725705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256136495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2256136495
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3810295481
Short name T935
Test name
Test status
Simulation time 6662616445 ps
CPU time 10.76 seconds
Started Aug 12 06:26:16 PM PDT 24
Finished Aug 12 06:26:27 PM PDT 24
Peak memory 233892 kb
Host smart-6541e744-c10b-4046-b114-ad25973be9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810295481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3810295481
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4074927913
Short name T498
Test name
Test status
Simulation time 32172469 ps
CPU time 2.42 seconds
Started Aug 12 06:25:58 PM PDT 24
Finished Aug 12 06:26:01 PM PDT 24
Peak memory 233476 kb
Host smart-6b3e0862-1938-44a0-800c-7ebec013260f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074927913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4074927913
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.659356454
Short name T54
Test name
Test status
Simulation time 1724005940 ps
CPU time 10.91 seconds
Started Aug 12 06:26:00 PM PDT 24
Finished Aug 12 06:26:11 PM PDT 24
Peak memory 224092 kb
Host smart-b566e039-0eb6-42f5-82bb-f942b83ba703
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=659356454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.659356454
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3999373583
Short name T884
Test name
Test status
Simulation time 25387407360 ps
CPU time 83.58 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:27:38 PM PDT 24
Peak memory 259588 kb
Host smart-04c517be-132c-4550-b4cf-81939307e79c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999373583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3999373583
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.273630462
Short name T273
Test name
Test status
Simulation time 2629481592 ps
CPU time 9.72 seconds
Started Aug 12 06:26:12 PM PDT 24
Finished Aug 12 06:26:22 PM PDT 24
Peak memory 217588 kb
Host smart-13eb9d57-e2e8-48f8-a7fa-4ec08005a477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273630462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.273630462
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2240627549
Short name T316
Test name
Test status
Simulation time 992447875 ps
CPU time 1.48 seconds
Started Aug 12 06:25:57 PM PDT 24
Finished Aug 12 06:25:59 PM PDT 24
Peak memory 208004 kb
Host smart-999f625d-678b-41b2-961f-7cc152289197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240627549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2240627549
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2100627654
Short name T38
Test name
Test status
Simulation time 679856976 ps
CPU time 1.59 seconds
Started Aug 12 06:26:02 PM PDT 24
Finished Aug 12 06:26:04 PM PDT 24
Peak memory 209100 kb
Host smart-726610ae-c29e-49d4-8cd4-6fd43dbb8930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100627654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2100627654
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2043385833
Short name T886
Test name
Test status
Simulation time 33943795 ps
CPU time 0.7 seconds
Started Aug 12 06:26:09 PM PDT 24
Finished Aug 12 06:26:10 PM PDT 24
Peak memory 206884 kb
Host smart-fbc535bf-5ac0-436d-aa3b-b5b141cf67e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043385833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2043385833
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.4160852500
Short name T686
Test name
Test status
Simulation time 912374556 ps
CPU time 7.34 seconds
Started Aug 12 06:26:11 PM PDT 24
Finished Aug 12 06:26:18 PM PDT 24
Peak memory 233792 kb
Host smart-51b4687c-b977-4b1c-a4b9-970de117c8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160852500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4160852500
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.648684760
Short name T281
Test name
Test status
Simulation time 33627897 ps
CPU time 0.71 seconds
Started Aug 12 06:26:21 PM PDT 24
Finished Aug 12 06:26:22 PM PDT 24
Peak memory 205932 kb
Host smart-40a8c075-0b9e-4705-bbd5-7d2e9b92995a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648684760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.648684760
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.4281069094
Short name T677
Test name
Test status
Simulation time 343074419 ps
CPU time 2.53 seconds
Started Aug 12 06:26:14 PM PDT 24
Finished Aug 12 06:26:17 PM PDT 24
Peak memory 233740 kb
Host smart-7f003ba1-552d-405b-99db-0a5ef4b52a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281069094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.4281069094
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3222363856
Short name T389
Test name
Test status
Simulation time 24329131 ps
CPU time 0.8 seconds
Started Aug 12 06:26:01 PM PDT 24
Finished Aug 12 06:26:02 PM PDT 24
Peak memory 207628 kb
Host smart-4bea55d0-b3ee-4474-a46d-820ef3b85306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222363856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3222363856
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3125057025
Short name T668
Test name
Test status
Simulation time 120984440145 ps
CPU time 231.41 seconds
Started Aug 12 06:25:59 PM PDT 24
Finished Aug 12 06:29:51 PM PDT 24
Peak memory 268416 kb
Host smart-0192e156-b990-46a6-a956-e703622df15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125057025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3125057025
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2717068889
Short name T829
Test name
Test status
Simulation time 2096464768 ps
CPU time 50.68 seconds
Started Aug 12 06:26:10 PM PDT 24
Finished Aug 12 06:27:01 PM PDT 24
Peak memory 251284 kb
Host smart-2db5b9be-db09-4ae0-b784-73c17ae457df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717068889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2717068889
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1370763315
Short name T893
Test name
Test status
Simulation time 5049523050 ps
CPU time 69.69 seconds
Started Aug 12 06:26:04 PM PDT 24
Finished Aug 12 06:27:14 PM PDT 24
Peak memory 252468 kb
Host smart-4c1fb5c0-c501-406b-a986-1a574d652caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370763315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1370763315
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.957632391
Short name T266
Test name
Test status
Simulation time 2138034252 ps
CPU time 21.63 seconds
Started Aug 12 06:26:15 PM PDT 24
Finished Aug 12 06:26:36 PM PDT 24
Peak memory 233756 kb
Host smart-5145e2d1-4483-4b92-8870-b56d2ad5135b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957632391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.957632391
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3304427371
Short name T409
Test name
Test status
Simulation time 42394533089 ps
CPU time 284.37 seconds
Started Aug 12 06:26:16 PM PDT 24
Finished Aug 12 06:31:01 PM PDT 24
Peak memory 250304 kb
Host smart-770ffc27-37f3-4496-bb8a-d98182d96c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304427371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3304427371
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2704311535
Short name T184
Test name
Test status
Simulation time 2164169360 ps
CPU time 16.06 seconds
Started Aug 12 06:26:12 PM PDT 24
Finished Aug 12 06:26:28 PM PDT 24
Peak memory 233920 kb
Host smart-8e631aa2-3aa1-4e91-88e9-9e48e70ad2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704311535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2704311535
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3001071910
Short name T471
Test name
Test status
Simulation time 15754231330 ps
CPU time 49.38 seconds
Started Aug 12 06:26:13 PM PDT 24
Finished Aug 12 06:27:02 PM PDT 24
Peak memory 233836 kb
Host smart-0b8b23da-9d53-4bd0-9ab9-6ac3e2440ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001071910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3001071910
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.718282817
Short name T223
Test name
Test status
Simulation time 1241161953 ps
CPU time 6.11 seconds
Started Aug 12 06:25:58 PM PDT 24
Finished Aug 12 06:26:04 PM PDT 24
Peak memory 233816 kb
Host smart-b2a1dd74-ea35-4004-a192-58720bb760c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718282817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.718282817
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.472106388
Short name T680
Test name
Test status
Simulation time 34410347355 ps
CPU time 12.62 seconds
Started Aug 12 06:26:13 PM PDT 24
Finished Aug 12 06:26:26 PM PDT 24
Peak memory 233896 kb
Host smart-ac51d6b8-c95d-4bec-ba37-f109e682ed3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472106388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.472106388
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1666643275
Short name T876
Test name
Test status
Simulation time 6729809592 ps
CPU time 5.94 seconds
Started Aug 12 06:26:09 PM PDT 24
Finished Aug 12 06:26:15 PM PDT 24
Peak memory 220944 kb
Host smart-97bc17da-21eb-4a58-befd-5e29510bd0c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1666643275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1666643275
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1189388490
Short name T799
Test name
Test status
Simulation time 1854559862 ps
CPU time 20.78 seconds
Started Aug 12 06:26:00 PM PDT 24
Finished Aug 12 06:26:21 PM PDT 24
Peak memory 220816 kb
Host smart-38936e4a-ff3b-4798-a32e-9cdf544f6807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189388490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1189388490
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2907764451
Short name T969
Test name
Test status
Simulation time 26404150366 ps
CPU time 19.49 seconds
Started Aug 12 06:26:03 PM PDT 24
Finished Aug 12 06:26:23 PM PDT 24
Peak memory 217492 kb
Host smart-7ac69efd-f24b-4b28-8be4-66e89b46e670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907764451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2907764451
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2260799450
Short name T470
Test name
Test status
Simulation time 47754017 ps
CPU time 2.66 seconds
Started Aug 12 06:25:58 PM PDT 24
Finished Aug 12 06:26:01 PM PDT 24
Peak memory 217312 kb
Host smart-a720437d-d02c-4ee9-9ff7-1b027c7069fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260799450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2260799450
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.849283045
Short name T306
Test name
Test status
Simulation time 46159227 ps
CPU time 0.84 seconds
Started Aug 12 06:26:09 PM PDT 24
Finished Aug 12 06:26:10 PM PDT 24
Peak memory 206956 kb
Host smart-366909f6-c4e8-474e-a1b2-155f486ba8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849283045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.849283045
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2833092208
Short name T591
Test name
Test status
Simulation time 23284139483 ps
CPU time 21.87 seconds
Started Aug 12 06:26:00 PM PDT 24
Finished Aug 12 06:26:22 PM PDT 24
Peak memory 241964 kb
Host smart-185e7c25-93b5-4e28-a9e8-8fdb0702781e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833092208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2833092208
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.455658035
Short name T312
Test name
Test status
Simulation time 60460962 ps
CPU time 0.75 seconds
Started Aug 12 06:26:13 PM PDT 24
Finished Aug 12 06:26:14 PM PDT 24
Peak memory 206456 kb
Host smart-85ab0bcc-7bb6-4511-9a97-29ae25a9e14e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455658035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.455658035
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.947528812
Short name T588
Test name
Test status
Simulation time 2027890359 ps
CPU time 18.92 seconds
Started Aug 12 06:26:07 PM PDT 24
Finished Aug 12 06:26:26 PM PDT 24
Peak memory 225580 kb
Host smart-1c42867f-9bea-4186-9461-1e143ddc2af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947528812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.947528812
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.48670610
Short name T513
Test name
Test status
Simulation time 121779249 ps
CPU time 0.77 seconds
Started Aug 12 06:26:11 PM PDT 24
Finished Aug 12 06:26:12 PM PDT 24
Peak memory 207928 kb
Host smart-9810cb47-c157-471e-bd96-99325a581bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48670610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.48670610
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2578438449
Short name T253
Test name
Test status
Simulation time 83185902816 ps
CPU time 507.23 seconds
Started Aug 12 06:26:18 PM PDT 24
Finished Aug 12 06:34:45 PM PDT 24
Peak memory 268512 kb
Host smart-6a8d2ed4-14d5-4061-a1f5-981f26af7438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578438449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2578438449
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3846848093
Short name T440
Test name
Test status
Simulation time 1007756275 ps
CPU time 2.8 seconds
Started Aug 12 06:26:15 PM PDT 24
Finished Aug 12 06:26:18 PM PDT 24
Peak memory 225188 kb
Host smart-3135d160-84e2-487e-aec7-4949760fab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846848093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3846848093
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1830045471
Short name T143
Test name
Test status
Simulation time 1202430513 ps
CPU time 20.44 seconds
Started Aug 12 06:26:27 PM PDT 24
Finished Aug 12 06:26:47 PM PDT 24
Peak memory 225488 kb
Host smart-dfefb469-2fc2-497f-9838-01dbc4d07cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830045471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1830045471
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1241942563
Short name T852
Test name
Test status
Simulation time 1624690776 ps
CPU time 16.6 seconds
Started Aug 12 06:26:07 PM PDT 24
Finished Aug 12 06:26:24 PM PDT 24
Peak memory 241968 kb
Host smart-dd9ca25b-fcbf-487c-99a3-bfbbffd70f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241942563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1241942563
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2387430966
Short name T655
Test name
Test status
Simulation time 5472537988 ps
CPU time 5.81 seconds
Started Aug 12 06:26:15 PM PDT 24
Finished Aug 12 06:26:21 PM PDT 24
Peak memory 225632 kb
Host smart-cd1e2401-3903-4219-a623-8a680a3e00b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387430966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2387430966
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2737101824
Short name T671
Test name
Test status
Simulation time 3573379241 ps
CPU time 33.32 seconds
Started Aug 12 06:26:13 PM PDT 24
Finished Aug 12 06:26:46 PM PDT 24
Peak memory 233900 kb
Host smart-5bb61bd3-9e9c-4f47-9743-00b9447cb36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737101824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2737101824
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1030017579
Short name T939
Test name
Test status
Simulation time 88094073765 ps
CPU time 18.05 seconds
Started Aug 12 06:26:08 PM PDT 24
Finished Aug 12 06:26:26 PM PDT 24
Peak memory 234888 kb
Host smart-c457f730-1e8d-4085-8500-f886f454dea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030017579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1030017579
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.449566204
Short name T489
Test name
Test status
Simulation time 5156649402 ps
CPU time 5.18 seconds
Started Aug 12 06:26:16 PM PDT 24
Finished Aug 12 06:26:21 PM PDT 24
Peak memory 225688 kb
Host smart-0f724c86-c8ca-43a1-a010-65f19868a6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449566204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.449566204
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.11297058
Short name T953
Test name
Test status
Simulation time 364686594 ps
CPU time 4.64 seconds
Started Aug 12 06:26:12 PM PDT 24
Finished Aug 12 06:26:17 PM PDT 24
Peak memory 224084 kb
Host smart-e001a02d-eb47-4aa9-8c09-6e56216477a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=11297058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direc
t.11297058
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4145689566
Short name T334
Test name
Test status
Simulation time 23447905685 ps
CPU time 102.84 seconds
Started Aug 12 06:26:31 PM PDT 24
Finished Aug 12 06:28:14 PM PDT 24
Peak memory 252228 kb
Host smart-a62eaf14-3fac-4ecc-92fd-9f8e2f732e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145689566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4145689566
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3653858168
Short name T693
Test name
Test status
Simulation time 9136280035 ps
CPU time 23.81 seconds
Started Aug 12 06:26:12 PM PDT 24
Finished Aug 12 06:26:36 PM PDT 24
Peak memory 221012 kb
Host smart-dd425ca4-5576-44e2-bae4-13fe1d164d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653858168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3653858168
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3887487561
Short name T123
Test name
Test status
Simulation time 3635340135 ps
CPU time 11.93 seconds
Started Aug 12 06:26:01 PM PDT 24
Finished Aug 12 06:26:13 PM PDT 24
Peak memory 217360 kb
Host smart-ff26b841-e721-46ea-b5bb-90aa442c19d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887487561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3887487561
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3153133371
Short name T317
Test name
Test status
Simulation time 22081494 ps
CPU time 0.84 seconds
Started Aug 12 06:26:13 PM PDT 24
Finished Aug 12 06:26:14 PM PDT 24
Peak memory 207896 kb
Host smart-bbf5b40e-a656-431c-be9f-b11d20f10f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153133371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3153133371
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2855252727
Short name T575
Test name
Test status
Simulation time 76359210 ps
CPU time 0.75 seconds
Started Aug 12 06:26:06 PM PDT 24
Finished Aug 12 06:26:07 PM PDT 24
Peak memory 206972 kb
Host smart-a809e210-2dcf-4e22-bbb0-a09b09f2231c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855252727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2855252727
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3031623468
Short name T295
Test name
Test status
Simulation time 147609881 ps
CPU time 2.34 seconds
Started Aug 12 06:26:32 PM PDT 24
Finished Aug 12 06:26:34 PM PDT 24
Peak memory 233468 kb
Host smart-891a1dc2-8067-406b-8aaa-2c2cd9439898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031623468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3031623468
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1917559210
Short name T280
Test name
Test status
Simulation time 23978906 ps
CPU time 0.7 seconds
Started Aug 12 06:24:04 PM PDT 24
Finished Aug 12 06:24:05 PM PDT 24
Peak memory 206472 kb
Host smart-095050a8-8764-4058-ad8e-695b5f540ae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917559210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
917559210
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.962293652
Short name T834
Test name
Test status
Simulation time 213250405 ps
CPU time 2.78 seconds
Started Aug 12 06:24:14 PM PDT 24
Finished Aug 12 06:24:17 PM PDT 24
Peak memory 233800 kb
Host smart-91407371-ecdc-4524-b105-4370ade13d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962293652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.962293652
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2199742185
Short name T639
Test name
Test status
Simulation time 64059053 ps
CPU time 0.77 seconds
Started Aug 12 06:24:25 PM PDT 24
Finished Aug 12 06:24:25 PM PDT 24
Peak memory 206596 kb
Host smart-3145cd80-0fc2-4bc4-b849-e4447059467f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199742185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2199742185
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.129217237
Short name T898
Test name
Test status
Simulation time 33707599465 ps
CPU time 106.86 seconds
Started Aug 12 06:24:34 PM PDT 24
Finished Aug 12 06:26:21 PM PDT 24
Peak memory 260072 kb
Host smart-3426adde-2667-47c8-86e3-b8fe588eda45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129217237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.129217237
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2722586808
Short name T740
Test name
Test status
Simulation time 39197201735 ps
CPU time 227.58 seconds
Started Aug 12 06:24:14 PM PDT 24
Finished Aug 12 06:28:02 PM PDT 24
Peak memory 254712 kb
Host smart-3fe07b51-87cb-4cc7-b8c2-b55b5e4a730e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722586808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2722586808
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1566534611
Short name T243
Test name
Test status
Simulation time 320795240475 ps
CPU time 779.16 seconds
Started Aug 12 06:24:16 PM PDT 24
Finished Aug 12 06:37:15 PM PDT 24
Peak memory 274164 kb
Host smart-958d0f4a-6401-4968-98f9-1a035b95a636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566534611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1566534611
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3469429342
Short name T537
Test name
Test status
Simulation time 197751369 ps
CPU time 6.31 seconds
Started Aug 12 06:24:22 PM PDT 24
Finished Aug 12 06:24:28 PM PDT 24
Peak memory 233820 kb
Host smart-6c6ad517-8435-40ee-993c-448cc798b2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469429342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3469429342
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2966072180
Short name T467
Test name
Test status
Simulation time 28077120072 ps
CPU time 58.43 seconds
Started Aug 12 06:24:04 PM PDT 24
Finished Aug 12 06:25:03 PM PDT 24
Peak memory 250688 kb
Host smart-21135838-bba6-471c-8539-1d095349e968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966072180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2966072180
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2379224824
Short name T550
Test name
Test status
Simulation time 1368156405 ps
CPU time 10.28 seconds
Started Aug 12 06:24:02 PM PDT 24
Finished Aug 12 06:24:13 PM PDT 24
Peak memory 225548 kb
Host smart-616b4b2a-b64b-4598-979c-423f672f1f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379224824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2379224824
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2083359901
Short name T835
Test name
Test status
Simulation time 77312560 ps
CPU time 2.21 seconds
Started Aug 12 06:24:17 PM PDT 24
Finished Aug 12 06:24:19 PM PDT 24
Peak memory 225008 kb
Host smart-a4e46aaf-a15a-4e8c-884e-1ed880e2a036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083359901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2083359901
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2002782153
Short name T643
Test name
Test status
Simulation time 636240025 ps
CPU time 5.62 seconds
Started Aug 12 06:24:17 PM PDT 24
Finished Aug 12 06:24:22 PM PDT 24
Peak memory 233744 kb
Host smart-7a831749-7469-4093-b334-808799627ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002782153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2002782153
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1176383547
Short name T526
Test name
Test status
Simulation time 1757288227 ps
CPU time 6.57 seconds
Started Aug 12 06:24:16 PM PDT 24
Finished Aug 12 06:24:23 PM PDT 24
Peak memory 225576 kb
Host smart-d884cd8d-e506-421e-ac53-23dc1e31a744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176383547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1176383547
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1875747106
Short name T544
Test name
Test status
Simulation time 3643301545 ps
CPU time 17.09 seconds
Started Aug 12 06:24:04 PM PDT 24
Finished Aug 12 06:24:22 PM PDT 24
Peak memory 220288 kb
Host smart-6a0081de-29e9-47bc-b803-b37c31132772
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1875747106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1875747106
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3255215484
Short name T350
Test name
Test status
Simulation time 216758091954 ps
CPU time 198.76 seconds
Started Aug 12 06:24:04 PM PDT 24
Finished Aug 12 06:27:23 PM PDT 24
Peak memory 257000 kb
Host smart-3969724b-2b86-4c37-907f-c5b0b952d2e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255215484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3255215484
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3936745710
Short name T815
Test name
Test status
Simulation time 160757598962 ps
CPU time 40.69 seconds
Started Aug 12 06:24:11 PM PDT 24
Finished Aug 12 06:24:52 PM PDT 24
Peak memory 217384 kb
Host smart-26ba51a9-107b-4162-8368-166165137dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936745710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3936745710
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.574463083
Short name T596
Test name
Test status
Simulation time 153694072 ps
CPU time 0.98 seconds
Started Aug 12 06:24:43 PM PDT 24
Finished Aug 12 06:24:44 PM PDT 24
Peak memory 207848 kb
Host smart-1d83a0a5-74e8-4d27-87f4-773d9ff767b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574463083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.574463083
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1551792944
Short name T612
Test name
Test status
Simulation time 34224944 ps
CPU time 1.23 seconds
Started Aug 12 06:24:15 PM PDT 24
Finished Aug 12 06:24:16 PM PDT 24
Peak memory 217304 kb
Host smart-da8ebb8b-07a7-43a2-be11-5470ee543d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551792944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1551792944
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2239112384
Short name T438
Test name
Test status
Simulation time 148757583 ps
CPU time 0.9 seconds
Started Aug 12 06:24:21 PM PDT 24
Finished Aug 12 06:24:23 PM PDT 24
Peak memory 207536 kb
Host smart-ba59c535-c868-4475-aba4-891c39738ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239112384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2239112384
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.4273615092
Short name T675
Test name
Test status
Simulation time 1806714982 ps
CPU time 12.17 seconds
Started Aug 12 06:24:20 PM PDT 24
Finished Aug 12 06:24:34 PM PDT 24
Peak memory 233764 kb
Host smart-2cf407a8-5765-4cd0-87e0-eb3d479765cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273615092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4273615092
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.304100194
Short name T447
Test name
Test status
Simulation time 13307444 ps
CPU time 0.73 seconds
Started Aug 12 06:24:03 PM PDT 24
Finished Aug 12 06:24:04 PM PDT 24
Peak memory 205896 kb
Host smart-7cc6796b-ca01-46c6-bc7a-ea03bbc2e1a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304100194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.304100194
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1145482335
Short name T955
Test name
Test status
Simulation time 905823474 ps
CPU time 8.63 seconds
Started Aug 12 06:24:02 PM PDT 24
Finished Aug 12 06:24:12 PM PDT 24
Peak memory 233784 kb
Host smart-52e99eda-5415-409d-bb66-6999c7316973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145482335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1145482335
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2359372571
Short name T343
Test name
Test status
Simulation time 35288764 ps
CPU time 0.74 seconds
Started Aug 12 06:24:16 PM PDT 24
Finished Aug 12 06:24:17 PM PDT 24
Peak memory 206592 kb
Host smart-cbeebb45-825b-49ac-865c-10c0a30d17c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359372571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2359372571
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3078983977
Short name T938
Test name
Test status
Simulation time 8511730992 ps
CPU time 77.47 seconds
Started Aug 12 06:24:26 PM PDT 24
Finished Aug 12 06:25:44 PM PDT 24
Peak memory 254700 kb
Host smart-0b52f8b1-7839-456e-b8a7-96a36d847e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078983977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3078983977
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.967293059
Short name T271
Test name
Test status
Simulation time 73381456424 ps
CPU time 149.4 seconds
Started Aug 12 06:24:04 PM PDT 24
Finished Aug 12 06:26:34 PM PDT 24
Peak memory 250364 kb
Host smart-f3ce96ab-c66e-4181-a40c-f20209b824a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967293059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.967293059
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.202673434
Short name T766
Test name
Test status
Simulation time 30225467458 ps
CPU time 304.86 seconds
Started Aug 12 06:24:25 PM PDT 24
Finished Aug 12 06:29:30 PM PDT 24
Peak memory 254484 kb
Host smart-fcce347c-0a32-4921-ad31-0b5bb578ba0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202673434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
202673434
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3712156421
Short name T259
Test name
Test status
Simulation time 211927952 ps
CPU time 3.9 seconds
Started Aug 12 06:24:13 PM PDT 24
Finished Aug 12 06:24:17 PM PDT 24
Peak memory 233748 kb
Host smart-baec2132-9c06-45c2-91a4-fdd890985e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712156421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3712156421
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.697750553
Short name T603
Test name
Test status
Simulation time 2770554995 ps
CPU time 55.31 seconds
Started Aug 12 06:24:15 PM PDT 24
Finished Aug 12 06:25:10 PM PDT 24
Peak memory 253020 kb
Host smart-47581864-1906-42d5-a222-1f77cc776e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697750553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
697750553
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1208224802
Short name T911
Test name
Test status
Simulation time 3159296576 ps
CPU time 31.28 seconds
Started Aug 12 06:24:07 PM PDT 24
Finished Aug 12 06:24:39 PM PDT 24
Peak memory 233880 kb
Host smart-eb2ff596-5299-41e0-bdd2-4d67479c11c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208224802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1208224802
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1620354728
Short name T844
Test name
Test status
Simulation time 3506473875 ps
CPU time 16.49 seconds
Started Aug 12 06:24:23 PM PDT 24
Finished Aug 12 06:24:39 PM PDT 24
Peak memory 234896 kb
Host smart-7be89c25-1bee-4159-ad08-b8679f80fafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620354728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1620354728
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.420202458
Short name T239
Test name
Test status
Simulation time 12495046415 ps
CPU time 21.23 seconds
Started Aug 12 06:24:04 PM PDT 24
Finished Aug 12 06:24:25 PM PDT 24
Peak memory 241872 kb
Host smart-22f4d7cb-ace7-415e-aece-9c874f31b9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420202458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
420202458
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.608710380
Short name T926
Test name
Test status
Simulation time 1840011331 ps
CPU time 9.54 seconds
Started Aug 12 06:24:03 PM PDT 24
Finished Aug 12 06:24:13 PM PDT 24
Peak memory 233744 kb
Host smart-71132707-7ef7-429c-ac95-73c672db34bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608710380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.608710380
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1774775756
Short name T405
Test name
Test status
Simulation time 2252523995 ps
CPU time 10.72 seconds
Started Aug 12 06:24:06 PM PDT 24
Finished Aug 12 06:24:17 PM PDT 24
Peak memory 222692 kb
Host smart-2192c983-d43b-4ea8-8ec1-08cb053cad5b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1774775756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1774775756
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2562497414
Short name T103
Test name
Test status
Simulation time 2275829410 ps
CPU time 11.39 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:24:16 PM PDT 24
Peak memory 217460 kb
Host smart-9655a527-cc88-4253-8de2-3b1c37c16d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562497414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2562497414
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2787990064
Short name T481
Test name
Test status
Simulation time 1319164072 ps
CPU time 5.11 seconds
Started Aug 12 06:24:14 PM PDT 24
Finished Aug 12 06:24:19 PM PDT 24
Peak memory 217292 kb
Host smart-dd411314-2bb9-4583-af90-743f8cc3e765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787990064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2787990064
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1195618734
Short name T149
Test name
Test status
Simulation time 19502321 ps
CPU time 0.8 seconds
Started Aug 12 06:24:23 PM PDT 24
Finished Aug 12 06:24:24 PM PDT 24
Peak memory 208000 kb
Host smart-94566400-f32e-4487-8467-eaf88a34a484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195618734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1195618734
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3302273659
Short name T296
Test name
Test status
Simulation time 39859637 ps
CPU time 0.83 seconds
Started Aug 12 06:24:13 PM PDT 24
Finished Aug 12 06:24:15 PM PDT 24
Peak memory 206968 kb
Host smart-fc85ffa1-6d64-4272-8beb-26e57e96b5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302273659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3302273659
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.103624707
Short name T86
Test name
Test status
Simulation time 693731357 ps
CPU time 8.03 seconds
Started Aug 12 06:24:24 PM PDT 24
Finished Aug 12 06:24:32 PM PDT 24
Peak memory 233772 kb
Host smart-0d659115-4fe4-4e94-a082-86453d71b5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103624707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.103624707
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3698496235
Short name T300
Test name
Test status
Simulation time 53522700 ps
CPU time 0.73 seconds
Started Aug 12 06:24:04 PM PDT 24
Finished Aug 12 06:24:05 PM PDT 24
Peak memory 206520 kb
Host smart-71b4cff3-72de-433b-ac93-4e5d649b990b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698496235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
698496235
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3740842725
Short name T463
Test name
Test status
Simulation time 383829025 ps
CPU time 2.27 seconds
Started Aug 12 06:24:17 PM PDT 24
Finished Aug 12 06:24:19 PM PDT 24
Peak memory 225624 kb
Host smart-a68d08a9-1973-4e6b-9a51-e84192770eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740842725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3740842725
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2810433775
Short name T727
Test name
Test status
Simulation time 21819802 ps
CPU time 0.76 seconds
Started Aug 12 06:24:21 PM PDT 24
Finished Aug 12 06:24:22 PM PDT 24
Peak memory 207576 kb
Host smart-ae07163b-3f81-4443-be22-a327c934cc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810433775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2810433775
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2210566961
Short name T663
Test name
Test status
Simulation time 32380472496 ps
CPU time 134.76 seconds
Started Aug 12 06:24:10 PM PDT 24
Finished Aug 12 06:26:25 PM PDT 24
Peak memory 253316 kb
Host smart-43aa9416-dd01-4de3-9084-a5e80da0b21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210566961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2210566961
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1246332688
Short name T515
Test name
Test status
Simulation time 51199555367 ps
CPU time 216.1 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:27:41 PM PDT 24
Peak memory 258480 kb
Host smart-7ca84d0e-ca64-44d2-9240-37abbbc9c552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246332688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1246332688
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1560567956
Short name T416
Test name
Test status
Simulation time 6193019579 ps
CPU time 22.32 seconds
Started Aug 12 06:24:06 PM PDT 24
Finished Aug 12 06:24:29 PM PDT 24
Peak memory 233964 kb
Host smart-6bf3e8ad-5892-454e-946f-1bab0b2c4da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560567956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1560567956
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3159565771
Short name T220
Test name
Test status
Simulation time 7158910480 ps
CPU time 79.1 seconds
Started Aug 12 06:24:17 PM PDT 24
Finished Aug 12 06:25:36 PM PDT 24
Peak memory 267028 kb
Host smart-5c79b5f6-8922-4e48-b6a9-ab1b93456e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159565771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3159565771
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.323633423
Short name T327
Test name
Test status
Simulation time 4013950400 ps
CPU time 10.67 seconds
Started Aug 12 06:24:02 PM PDT 24
Finished Aug 12 06:24:14 PM PDT 24
Peak memory 230488 kb
Host smart-2fb1be39-033b-4bf8-af53-9decb0e7476e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323633423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.323633423
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2175699430
Short name T363
Test name
Test status
Simulation time 13239427546 ps
CPU time 102.83 seconds
Started Aug 12 06:24:16 PM PDT 24
Finished Aug 12 06:25:59 PM PDT 24
Peak memory 238444 kb
Host smart-a07005c1-0461-416d-8275-0bd791928ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175699430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2175699430
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2579545534
Short name T827
Test name
Test status
Simulation time 8417595102 ps
CPU time 8.94 seconds
Started Aug 12 06:24:15 PM PDT 24
Finished Aug 12 06:24:24 PM PDT 24
Peak memory 228316 kb
Host smart-cc5aa480-828c-4e46-bbe3-600145871f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579545534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2579545534
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.38863824
Short name T847
Test name
Test status
Simulation time 1235686175 ps
CPU time 6.34 seconds
Started Aug 12 06:24:24 PM PDT 24
Finished Aug 12 06:24:30 PM PDT 24
Peak memory 225492 kb
Host smart-335e2ccd-d348-479a-a2cb-affc94d05874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38863824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.38863824
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1580559904
Short name T846
Test name
Test status
Simulation time 234984622 ps
CPU time 3.65 seconds
Started Aug 12 06:24:10 PM PDT 24
Finished Aug 12 06:24:14 PM PDT 24
Peak memory 220068 kb
Host smart-8b303944-3a60-4f7f-bfef-5c07d30df964
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1580559904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1580559904
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3303241713
Short name T24
Test name
Test status
Simulation time 1163633739 ps
CPU time 7.64 seconds
Started Aug 12 06:24:26 PM PDT 24
Finished Aug 12 06:24:34 PM PDT 24
Peak memory 217264 kb
Host smart-2e430528-4161-41be-813d-3875b4fc2dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303241713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3303241713
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3459505272
Short name T992
Test name
Test status
Simulation time 2067891604 ps
CPU time 6.24 seconds
Started Aug 12 06:24:03 PM PDT 24
Finished Aug 12 06:24:09 PM PDT 24
Peak memory 217332 kb
Host smart-cd92c18a-ec04-4c5d-a344-668d90a5f2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459505272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3459505272
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2448857973
Short name T302
Test name
Test status
Simulation time 349922104 ps
CPU time 1.9 seconds
Started Aug 12 06:24:13 PM PDT 24
Finished Aug 12 06:24:15 PM PDT 24
Peak memory 217336 kb
Host smart-7e0030fa-b0c5-4695-a32f-ae15ea452312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448857973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2448857973
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2362731400
Short name T921
Test name
Test status
Simulation time 97930164 ps
CPU time 0.83 seconds
Started Aug 12 06:24:07 PM PDT 24
Finished Aug 12 06:24:08 PM PDT 24
Peak memory 207000 kb
Host smart-00bed558-6306-4b5d-9c67-8bce53fb6d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362731400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2362731400
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.533375033
Short name T752
Test name
Test status
Simulation time 17787165072 ps
CPU time 13.73 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:24:19 PM PDT 24
Peak memory 225632 kb
Host smart-3ecef349-98e1-4f76-9971-a4084cd46c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533375033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.533375033
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.664500089
Short name T529
Test name
Test status
Simulation time 111016548 ps
CPU time 0.68 seconds
Started Aug 12 06:24:08 PM PDT 24
Finished Aug 12 06:24:09 PM PDT 24
Peak memory 206496 kb
Host smart-e049519b-3f39-4938-9d22-4bbe5425c6cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664500089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.664500089
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1709685495
Short name T758
Test name
Test status
Simulation time 1075006412 ps
CPU time 2.77 seconds
Started Aug 12 06:24:12 PM PDT 24
Finished Aug 12 06:24:15 PM PDT 24
Peak memory 225532 kb
Host smart-395b8e4a-e87e-453b-8ffa-bcd23e9be7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709685495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1709685495
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2392851544
Short name T328
Test name
Test status
Simulation time 15668398 ps
CPU time 0.75 seconds
Started Aug 12 06:24:17 PM PDT 24
Finished Aug 12 06:24:18 PM PDT 24
Peak memory 207880 kb
Host smart-e5cae615-4b1d-40de-9b37-7c53a74177bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392851544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2392851544
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3161436347
Short name T104
Test name
Test status
Simulation time 7119815056 ps
CPU time 39.08 seconds
Started Aug 12 06:24:08 PM PDT 24
Finished Aug 12 06:24:47 PM PDT 24
Peak memory 250252 kb
Host smart-1303e071-2861-4059-a724-69afe1acfcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161436347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3161436347
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1289447439
Short name T647
Test name
Test status
Simulation time 69396833516 ps
CPU time 171.83 seconds
Started Aug 12 06:24:13 PM PDT 24
Finished Aug 12 06:27:05 PM PDT 24
Peak memory 266740 kb
Host smart-23f93039-c712-41e8-aa57-78d22c10b4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289447439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1289447439
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2374961085
Short name T739
Test name
Test status
Simulation time 25272548261 ps
CPU time 123.41 seconds
Started Aug 12 06:24:14 PM PDT 24
Finished Aug 12 06:26:18 PM PDT 24
Peak memory 266740 kb
Host smart-cd7dddbe-044a-418e-94cf-c09d664e2bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374961085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2374961085
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.596988769
Short name T401
Test name
Test status
Simulation time 358643407 ps
CPU time 2.83 seconds
Started Aug 12 06:24:29 PM PDT 24
Finished Aug 12 06:24:32 PM PDT 24
Peak memory 225628 kb
Host smart-efd8901c-aa66-4d88-beb5-0c3ab7d26833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596988769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.596988769
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2347910387
Short name T716
Test name
Test status
Simulation time 2800598555 ps
CPU time 34.9 seconds
Started Aug 12 06:24:15 PM PDT 24
Finished Aug 12 06:24:50 PM PDT 24
Peak memory 242112 kb
Host smart-d301cd03-3de5-463d-9afd-9451006aa9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347910387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2347910387
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3610345568
Short name T894
Test name
Test status
Simulation time 247018734 ps
CPU time 4.58 seconds
Started Aug 12 06:24:24 PM PDT 24
Finished Aug 12 06:24:29 PM PDT 24
Peak memory 225560 kb
Host smart-bd1ee1c8-fba5-48e3-88ff-77c3fe50bedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610345568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3610345568
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2886792805
Short name T497
Test name
Test status
Simulation time 136649666 ps
CPU time 4.46 seconds
Started Aug 12 06:24:04 PM PDT 24
Finished Aug 12 06:24:09 PM PDT 24
Peak memory 233732 kb
Host smart-a4aac213-2ca6-44d4-b0b4-b2dc58d19b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886792805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2886792805
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2627962591
Short name T232
Test name
Test status
Simulation time 670421653 ps
CPU time 4.42 seconds
Started Aug 12 06:24:24 PM PDT 24
Finished Aug 12 06:24:28 PM PDT 24
Peak memory 225628 kb
Host smart-487d1325-da0d-478f-adc6-3115313593ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627962591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2627962591
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3278468065
Short name T388
Test name
Test status
Simulation time 9065692291 ps
CPU time 22.64 seconds
Started Aug 12 06:24:20 PM PDT 24
Finished Aug 12 06:24:43 PM PDT 24
Peak memory 233832 kb
Host smart-c6fb58f5-c3e5-4380-9599-7f0ff0e37395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278468065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3278468065
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3931602283
Short name T594
Test name
Test status
Simulation time 392570134 ps
CPU time 7.19 seconds
Started Aug 12 06:24:05 PM PDT 24
Finished Aug 12 06:24:13 PM PDT 24
Peak memory 224248 kb
Host smart-cc3158ec-4551-4dc4-bf6c-fad70d63e9d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3931602283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3931602283
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1919224957
Short name T130
Test name
Test status
Simulation time 44499258777 ps
CPU time 423.42 seconds
Started Aug 12 06:24:21 PM PDT 24
Finished Aug 12 06:31:25 PM PDT 24
Peak memory 266748 kb
Host smart-ac6e2b20-c8f6-447a-9a90-4dc21100ee8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919224957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1919224957
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2736769073
Short name T783
Test name
Test status
Simulation time 2446906057 ps
CPU time 24.09 seconds
Started Aug 12 06:24:12 PM PDT 24
Finished Aug 12 06:24:36 PM PDT 24
Peak memory 217460 kb
Host smart-bf0fd90b-5b12-4955-a681-c9f6d1b45e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736769073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2736769073
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1994272377
Short name T349
Test name
Test status
Simulation time 3956525883 ps
CPU time 12.51 seconds
Started Aug 12 06:24:24 PM PDT 24
Finished Aug 12 06:24:36 PM PDT 24
Peak memory 217500 kb
Host smart-123c055b-d3d7-48e6-8920-a5e18e62e825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994272377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1994272377
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3429487894
Short name T454
Test name
Test status
Simulation time 30572885 ps
CPU time 0.97 seconds
Started Aug 12 06:24:12 PM PDT 24
Finished Aug 12 06:24:14 PM PDT 24
Peak memory 208112 kb
Host smart-e98ec753-2a07-4d96-9b89-8979fe43918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429487894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3429487894
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1796012368
Short name T954
Test name
Test status
Simulation time 102449565 ps
CPU time 0.8 seconds
Started Aug 12 06:24:20 PM PDT 24
Finished Aug 12 06:24:21 PM PDT 24
Peak memory 207008 kb
Host smart-b4876983-1850-4547-b021-e93201482c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796012368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1796012368
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2255728945
Short name T297
Test name
Test status
Simulation time 28215675784 ps
CPU time 20.25 seconds
Started Aug 12 06:24:32 PM PDT 24
Finished Aug 12 06:24:53 PM PDT 24
Peak memory 241900 kb
Host smart-739dc72c-3eb2-449e-a955-11865afa4c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255728945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2255728945
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2130090376
Short name T981
Test name
Test status
Simulation time 43202871 ps
CPU time 0.76 seconds
Started Aug 12 06:24:23 PM PDT 24
Finished Aug 12 06:24:24 PM PDT 24
Peak memory 206804 kb
Host smart-c989bf36-0653-4340-aa28-9ae3a8a06934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130090376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
130090376
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2695671548
Short name T624
Test name
Test status
Simulation time 11868885625 ps
CPU time 13.58 seconds
Started Aug 12 06:24:16 PM PDT 24
Finished Aug 12 06:24:30 PM PDT 24
Peak memory 225652 kb
Host smart-4eda0d69-12b6-44d6-9edb-1c42d78dc2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695671548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2695671548
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2132573634
Short name T420
Test name
Test status
Simulation time 79811885 ps
CPU time 0.79 seconds
Started Aug 12 06:24:19 PM PDT 24
Finished Aug 12 06:24:24 PM PDT 24
Peak memory 207584 kb
Host smart-4a492d4f-3efb-4271-b3f2-94c81f4537e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132573634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2132573634
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2781232185
Short name T860
Test name
Test status
Simulation time 242091472622 ps
CPU time 197.49 seconds
Started Aug 12 06:24:27 PM PDT 24
Finished Aug 12 06:27:44 PM PDT 24
Peak memory 265984 kb
Host smart-6000089b-2d93-4be2-bd1c-990578181f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781232185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2781232185
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3751658861
Short name T228
Test name
Test status
Simulation time 78359616045 ps
CPU time 162.25 seconds
Started Aug 12 06:24:16 PM PDT 24
Finished Aug 12 06:26:58 PM PDT 24
Peak memory 242160 kb
Host smart-5aa10b94-1e83-41e1-9641-2c4338e0f9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751658861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3751658861
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4068985716
Short name T728
Test name
Test status
Simulation time 33516203560 ps
CPU time 295.59 seconds
Started Aug 12 06:24:06 PM PDT 24
Finished Aug 12 06:29:01 PM PDT 24
Peak memory 266548 kb
Host smart-ddabfe20-572f-430f-b755-f357fe6b8bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068985716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4068985716
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1780029830
Short name T850
Test name
Test status
Simulation time 1125597884 ps
CPU time 4.25 seconds
Started Aug 12 06:24:22 PM PDT 24
Finished Aug 12 06:24:27 PM PDT 24
Peak memory 225616 kb
Host smart-d689b37a-b94e-4e7a-b602-5d6a421adfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780029830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1780029830
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2747696052
Short name T909
Test name
Test status
Simulation time 1243446828 ps
CPU time 11.32 seconds
Started Aug 12 06:24:20 PM PDT 24
Finished Aug 12 06:24:37 PM PDT 24
Peak memory 233776 kb
Host smart-bbb017e3-3da2-40ed-9848-6881b653a7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747696052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2747696052
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1032854450
Short name T547
Test name
Test status
Simulation time 850406465 ps
CPU time 6.76 seconds
Started Aug 12 06:24:23 PM PDT 24
Finished Aug 12 06:24:30 PM PDT 24
Peak memory 238364 kb
Host smart-ef70e718-e4de-4066-b520-8b9984c1bdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032854450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1032854450
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1000236724
Short name T528
Test name
Test status
Simulation time 941698963 ps
CPU time 3.05 seconds
Started Aug 12 06:24:21 PM PDT 24
Finished Aug 12 06:24:24 PM PDT 24
Peak memory 225564 kb
Host smart-57b8e466-dd46-4e1a-8ddb-ff38b45b70a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000236724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1000236724
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.386168232
Short name T892
Test name
Test status
Simulation time 8521332743 ps
CPU time 21.09 seconds
Started Aug 12 06:24:07 PM PDT 24
Finished Aug 12 06:24:28 PM PDT 24
Peak memory 233760 kb
Host smart-654dbe6c-bf6b-467d-9fe5-7f357a69dcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386168232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.386168232
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3153664781
Short name T710
Test name
Test status
Simulation time 1066266492 ps
CPU time 6.31 seconds
Started Aug 12 06:24:14 PM PDT 24
Finished Aug 12 06:24:20 PM PDT 24
Peak memory 221500 kb
Host smart-c15fe396-32bd-4d9a-a5ba-61ff3e8a84e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3153664781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3153664781
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1792573143
Short name T52
Test name
Test status
Simulation time 34592286 ps
CPU time 0.72 seconds
Started Aug 12 06:24:32 PM PDT 24
Finished Aug 12 06:24:33 PM PDT 24
Peak memory 206748 kb
Host smart-402af84f-aa73-4f42-8e29-d0940ff856f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792573143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1792573143
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1306991349
Short name T626
Test name
Test status
Simulation time 1347750600 ps
CPU time 4.28 seconds
Started Aug 12 06:24:14 PM PDT 24
Finished Aug 12 06:24:18 PM PDT 24
Peak memory 217336 kb
Host smart-1508e242-fbe7-4bd6-83e6-ab2677278b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306991349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1306991349
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2086905715
Short name T826
Test name
Test status
Simulation time 1350801733 ps
CPU time 1.53 seconds
Started Aug 12 06:24:27 PM PDT 24
Finished Aug 12 06:24:29 PM PDT 24
Peak memory 217360 kb
Host smart-9b5e1fd0-18bd-430a-9c68-34c8f4242956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086905715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2086905715
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1149376508
Short name T431
Test name
Test status
Simulation time 102049163 ps
CPU time 1.04 seconds
Started Aug 12 06:24:06 PM PDT 24
Finished Aug 12 06:24:07 PM PDT 24
Peak memory 207992 kb
Host smart-7d3fd524-6b6b-4d86-aaf4-b19533f15531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149376508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1149376508
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2019193485
Short name T645
Test name
Test status
Simulation time 796125460 ps
CPU time 9.11 seconds
Started Aug 12 06:24:08 PM PDT 24
Finished Aug 12 06:24:17 PM PDT 24
Peak memory 241292 kb
Host smart-d81a8505-7d75-4a0e-96be-8610fda97c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019193485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2019193485
Directory /workspace/9.spi_device_upload/latest
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