Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3057652	1			T1	1		T2	1		T3	1
all_values[1]	3057652	1			T1	1		T2	1		T3	1
all_values[2]	3057652	1			T1	1		T2	1		T3	1
all_values[3]	3057652	1			T1	1		T2	1		T3	1
all_values[4]	3057652	1			T1	1		T2	1		T3	1
all_values[5]	3057652	1			T1	1		T2	1		T3	1
all_values[6]	3057652	1			T1	1		T2	1		T3	1
all_values[7]	3057652	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23724928

1

T1

8

T2

8

T3

8

auto[1]

736288

1

T19

14

T20

2961

T31

68335

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24430966

1

T1

8

T2

8

T3

8

auto[1]

30250

1

T13

2

T41

337

T19

85

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2954129	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	13974	1			T13	1		T41	213		T19	43
all_values[0]	auto[1]	auto[0]	88692	1			T31	13430		T32	3		T33	2
all_values[0]	auto[1]	auto[1]	857	1			T19	1		T31	236		T32	1
all_values[1]	auto[0]	auto[0]	2978660	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	9374	1			T13	1		T41	120		T19	18
all_values[1]	auto[1]	auto[0]	68911	1			T19	3		T20	722		T31	13460
all_values[1]	auto[1]	auto[1]	707	1			T20	18		T31	206		T33	2
all_values[2]	auto[0]	auto[0]	2944600	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	3243	1			T41	4		T19	16		T89	9
all_values[2]	auto[1]	auto[0]	109489	1			T19	2		T31	13600		T33	40939
all_values[2]	auto[1]	auto[1]	320	1			T19	1		T31	61		T32	1
all_values[3]	auto[0]	auto[0]	2928570	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	180	1			T19	1		T20	3		T31	2
all_values[3]	auto[1]	auto[0]	128714	1			T19	2		T31	13657		T33	40941
all_values[3]	auto[1]	auto[1]	188	1			T20	1		T31	3		T33	1
all_values[4]	auto[0]	auto[0]	2931543	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	198	1			T19	1		T31	2		T32	1
all_values[4]	auto[1]	auto[0]	125750	1			T20	740		T31	3		T32	3
all_values[4]	auto[1]	auto[1]	161	1			T19	1		T31	2		T33	1
all_values[5]	auto[0]	auto[0]	2971251	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	175	1			T19	2		T20	2		T31	3
all_values[5]	auto[1]	auto[0]	86076	1			T20	1		T31	2		T32	2
all_values[5]	auto[1]	auto[1]	150	1			T31	3		T32	1		T33	1
all_values[6]	auto[0]	auto[0]	3008617	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	186	1			T20	2		T31	2		T33	1
all_values[6]	auto[1]	auto[0]	48674	1			T20	737		T31	8		T32	2
all_values[6]	auto[1]	auto[1]	175	1			T20	2		T31	4		T32	2
all_values[7]	auto[0]	auto[0]	2980041	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	187	1			T31	4		T32	3		T33	3
all_values[7]	auto[1]	auto[0]	77249	1			T19	3		T20	740		T31	13656
all_values[7]	auto[1]	auto[1]	175	1			T19	1		T31	4		T32	1