Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34030	1			T3	2		T6	35		T10	26
auto[SpiFlashAddrCfg]	7760	1			T6	19		T10	4		T11	43
auto[SpiFlashAddr3b]	9243	1			T6	18		T11	43		T13	5
auto[SpiFlashAddr4b]	7688	1			T6	8		T10	2		T11	35

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33179

1

T3

2

T6

44

T10

32

auto[1]

25542

1

T6

36

T11

366

T13

7

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31567

1

T3

2

T6

53

T10

28

auto[1]

27154

1

T6

27

T10

4

T11

237

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38742	1			T3	2		T6	36		T10	24
values[1]	1076	1			T6	3		T11	2		T16	1
values[2]	1476	1			T6	4		T11	4		T16	1
values[3]	1480	1			T6	4		T10	2		T11	2
values[4]	1556	1			T6	7		T10	2		T11	8
values[5]	1429	1			T6	4		T10	2		T11	7
values[6]	1493	1			T11	6		T13	2		T16	3
values[7]	1415	1			T6	4		T11	7		T36	4
values[8]	10054	1			T6	18		T10	2		T11	55

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30239

1

T3

2

T10

32

T13

22

auto[1]

28482

1

T6

80

T11

524

T17

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55359

1

T3

2

T6

78

T10

32

write

3362

1

T6

2

T11

15

T13

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19421

1

T6

50

T10

8

T11

92

valids[0x1]

39300

1

T3

2

T6

30

T10

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1629	1			T6	4		T11	11		T16	1
internal_process_ops[0x5a]	1575	1			T6	2		T11	11		T36	1
internal_process_ops[0x05]	19942	1			T3	2		T6	4		T10	20
internal_process_ops[0x35]	1621	1			T6	2		T11	5		T36	1
internal_process_ops[0x15]	1569	1			T11	4		T13	1		T36	1
internal_process_ops[0x03]	1022	1			T6	1		T11	3		T16	1
internal_process_ops[0x0b]	1027	1			T6	1		T11	5		T13	1
internal_process_ops[0x3b]	1048	1			T6	2		T11	4		T13	1
internal_process_ops[0x6b]	1021	1			T11	1		T13	2		T36	1
internal_process_ops[0xbb]	1066	1			T6	2		T11	4		T36	2
internal_process_ops[0xeb]	1043	1			T6	1		T11	4		T13	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57074

1

T3

2

T6

79

T10

32

auto[1]

1647

1

T6

1

T11

6

T36

8

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56248

1

T3

2

T6

80

T10

28

auto[1]

2473

1

T10

4

T11

14

T13

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9839

1

T3

2

T10

26

T13

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6814

1

T13

2

T16

2

T37

36

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2105

1

T10

4

T13

1

T16

1

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1743

1

T13

4

T16

1

T37

31

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2389

1

T13

4

T16

2

T18

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2052

1

T16

3

T37

24

T19

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1981

1

T10

2

T13

3

T16

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1773

1

T16

1

T37

18

T19

10

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

95

1

T43

2

T53

1

T170

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

84

1

T49

5

T52

2

T20

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

100

1

T37

1

T49

7

T171

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

114

1

T37

1

T49

1

T52

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

100

1

T19

1

T49

1

T52

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

104

1

T49

1

T53

2

T56

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

91

1

T43

1

T53

1

T56

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

80

1

T37

4

T52

2

T53

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

99

1

T13

1

T47

2

T19

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

89

1

T49

3

T53

1

T123

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

97

1

T16

1

T37

2

T43

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

120

1

T43

3

T49

1

T52

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

106

1

T48

2

T43

2

T49

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

89

1

T43

1

T49

1

T52

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

85

1

T13

1

T49

2

T52

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

90

1

T37

1

T19

1

T43

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9979

1

T6

28

T11

99

T36

17

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6530

1

T6

6

T11

300

T36

7

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1525

1

T6

3

T11

18

T36

5

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1578

1

T6

16

T11

22

T36

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2046

1

T6

8

T11

21

T36

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1897

1

T6

10

T11

17

T36

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1611

1

T6

3

T11

12

T17

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1497

1

T6

4

T11

20

T36

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

153

1

T6

1

T11

3

T41

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

100

1

T11

1

T36

4

T41

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

124

1

T40

1

T57

3

T64

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

98

1

T41

6

T64

2

T172

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

116

1

T11

1

T57

2

T172

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

120

1

T11

1

T41

3

T57

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

89

1

T36

1

T41

3

T57

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

109

1

T11

1

T36

3

T41

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

116

1

T11

1

T41

1

T95

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

108

1

T40

1

T64

2

T95

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

130

1

T11

3

T41

1

T57

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

100

1

T11

1

T95

2

T173

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

119

1

T36

1

T40

1

T57

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

106

1

T6

1

T11

1

T36

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

95

1

T11

1

T36

1

T40

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

136

1

T11

1

T41

1

T57

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3702	1			T10	4		T13	6		T16	3
auto[0]	values[0]	valids[0x1]	15702	1			T3	2		T10	20		T13	5
auto[0]	values[1]	valids[0x1]	504	1			T16	1		T37	7		T19	2
auto[0]	values[2]	valids[0x0]	526	1			T37	3		T58	2		T19	1
auto[0]	values[2]	valids[0x1]	271	1			T16	1		T37	2		T43	1
auto[0]	values[3]	valids[0x0]	481	1			T47	2		T37	4		T65	2
auto[0]	values[3]	valids[0x1]	306	1			T10	2		T13	2		T37	3
auto[0]	values[4]	valids[0x0]	539	1			T16	3		T37	12		T50	2
auto[0]	values[4]	valids[0x1]	307	1			T10	2		T37	5		T19	4
auto[0]	values[5]	valids[0x0]	484	1			T10	2		T37	7		T50	2
auto[0]	values[5]	valids[0x1]	275	1			T16	2		T37	2		T43	7
auto[0]	values[6]	valids[0x0]	530	1			T13	2		T37	8		T19	7
auto[0]	values[6]	valids[0x1]	285	1			T16	3		T37	1		T43	4
auto[0]	values[7]	valids[0x0]	457	1			T37	2		T19	2		T43	4
auto[0]	values[7]	valids[0x1]	314	1			T37	3		T19	2		T43	4
auto[0]	values[8]	valids[0x0]	3506	1			T10	2		T13	6		T16	3
auto[0]	values[8]	valids[0x1]	2050	1			T13	1		T48	4		T37	20
auto[1]	values[0]	valids[0x0]	4062	1			T6	22		T11	42		T36	14
auto[1]	values[0]	valids[0x1]	15276	1			T6	14		T11	391		T36	22
auto[1]	values[1]	valids[0x1]	572	1			T6	3		T11	2		T40	2
auto[1]	values[2]	valids[0x0]	411	1			T6	1		T40	3		T57	2
auto[1]	values[2]	valids[0x1]	268	1			T6	3		T11	4		T40	7
auto[1]	values[3]	valids[0x0]	415	1			T6	3		T40	2		T41	5
auto[1]	values[3]	valids[0x1]	278	1			T6	1		T11	2		T17	1
auto[1]	values[4]	valids[0x0]	444	1			T6	5		T11	6		T36	2
auto[1]	values[4]	valids[0x1]	266	1			T6	2		T11	2		T41	1
auto[1]	values[5]	valids[0x0]	401	1			T6	4		T11	2		T36	2
auto[1]	values[5]	valids[0x1]	269	1			T11	5		T40	1		T41	5
auto[1]	values[6]	valids[0x0]	400	1			T11	2		T36	4		T40	1
auto[1]	values[6]	valids[0x1]	278	1			T11	4		T40	4		T41	13
auto[1]	values[7]	valids[0x0]	377	1			T6	4		T11	4		T36	2
auto[1]	values[7]	valids[0x1]	267	1			T11	3		T36	2		T40	2
auto[1]	values[8]	valids[0x0]	2686	1			T6	11		T11	36		T17	2
auto[1]	values[8]	valids[0x1]	1812	1			T6	7		T11	19		T17	3