Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3323984

1

T2

775

T3

1922

T6

2294

auto[1]

36743

1

T10

16

T11

324

T13

2

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

783522

1

T2

775

T3

1922

T6

20

auto[1]

2577205

1

T6

2274

T10

784

T11

7839

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	576156	1			T2	377		T3	251		T7	1
auto[524288:1048575]	397574	1			T2	117		T3	124		T11	780
auto[1048576:1572863]	350606	1			T2	3		T3	3		T6	1901
auto[1572864:2097151]	421402	1			T2	49		T3	699		T6	2
auto[2097152:2621439]	388005	1			T2	117		T11	132		T13	2
auto[2621440:3145727]	403351	1			T3	400		T11	15		T36	2899
auto[3145728:3670015]	384850	1			T2	112		T3	218		T6	256
auto[3670016:4194303]	438783	1			T3	227		T6	135		T11	1165

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2612062

1

T2

17

T3

23

T6

2294

auto[1]

748665

1

T2

758

T3

1899

T10

4

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2838419

1

T2

775

T3

1922

T6

526

auto[1]

522308

1

T6

1768

T11

615

T13

8

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	159579	1			T2	377		T3	251		T7	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	346146	1			T10	772		T11	513		T13	512
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	87912	1			T2	117		T3	124		T11	7
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	244885	1			T11	516		T37	5001		T41	261
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	80148	1			T2	3		T3	3		T6	8
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	215567	1			T6	256		T11	5		T36	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	75726	1			T2	49		T3	699		T6	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	275761	1			T11	2894		T16	1		T37	2094
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	64987	1			T2	117		T11	1		T13	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	242681	1			T11	1		T36	1913		T37	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	91804	1			T3	400		T11	5		T37	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	250223	1			T11	1		T37	3763		T40	395
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	93250	1			T2	112		T3	218		T11	16
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	225436	1			T6	256		T11	1932		T37	512
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	116067	1			T3	227		T6	4		T11	9
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	237384	1			T11	1153		T37	2986		T40	1664
auto[0]	auto[1]	auto[0:524287]	auto[0]	904	1			T11	1		T13	1		T36	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	62301	1			T11	1		T40	512		T57	897
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2564	1			T11	1		T36	9		T40	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	57980	1			T11	256		T40	128		T41	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1568	1			T6	3		T11	2		T36	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	49897	1			T6	1634		T11	1		T41	32
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1909	1			T11	2		T37	1		T40	23
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	63598	1			T11	128		T37	2735		T40	721
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	608	1			T11	1		T13	1		T36	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	73714	1			T11	128		T57	896		T95	128
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	558	1			T36	36		T40	6		T41	8
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	55859	1			T36	2792		T41	434		T172	1385
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	810	1			T11	3		T37	1		T40	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	61778	1			T49	256		T85	154		T89	499
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	668	1			T6	3		T13	2		T40	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	81712	1			T6	128		T13	2		T40	4
auto[1]	auto[0]	auto[0:524287]	auto[0]	541	1			T10	4		T11	1		T37	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	6077	1			T10	12		T11	28		T37	71
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	464	1			T37	3		T41	3		T57	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3210	1			T37	62		T41	7		T57	19
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	397	1			T36	10		T37	4		T41	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2063	1			T36	13		T37	62		T41	9
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	510	1			T11	3		T16	1		T36	12
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3148	1			T11	64		T37	1		T41	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	484	1			T11	1		T37	1		T40	6
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	4657	1			T37	11		T64	128		T95	187
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	432	1			T11	1		T40	3		T41	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3539	1			T11	8		T57	47		T64	256
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	403	1			T11	5		T40	4		T41	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2650	1			T11	119		T40	212		T41	18
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	452	1			T11	1		T37	4		T57	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1836	1			T11	2		T37	51		T57	2
auto[1]	auto[1]	auto[0:524287]	auto[0]	77	1			T11	1		T40	4		T57	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	531	1			T11	76		T42	10		T52	6
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	97	1			T41	1		T43	1		T93	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	462	1			T41	5		T43	37		T171	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	120	1			T11	1		T57	1		T89	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	846	1			T11	13		T57	14		T89	19
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	66	1			T57	1		T53	1		T93	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	684	1			T57	9		T53	2		T31	6
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	89	1			T85	1		T89	1		T173	6
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	785	1			T85	12		T89	2		T173	18
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	111	1			T36	16		T41	5		T172	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	825	1			T36	55		T41	17		T43	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	90	1			T89	1		T21	2		T31	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	433	1			T89	2		T21	3		T31	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	127	1			T13	2		T41	1		T19	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	537	1			T41	3		T19	3		T85	18

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2064390	1			T2	17		T3	23		T6	526
auto[0]	auto[0]	auto[1]	743166	1			T2	758		T3	1899		T10	1
auto[0]	auto[1]	auto[0]	511589	1			T6	1768		T11	523		T13	6
auto[0]	auto[1]	auto[1]	4839	1			T11	1		T57	2		T172	1
auto[1]	auto[0]	auto[0]	30328	1			T10	13		T11	233		T16	1
auto[1]	auto[0]	auto[1]	535	1			T10	3		T36	3		T37	1
auto[1]	auto[1]	auto[0]	5755	1			T11	91		T13	2		T36	67
auto[1]	auto[1]	auto[1]	125	1			T36	4		T19	1		T42	1