Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3057652	1			T1	1		T2	1		T3	1
all_pins[1]	3057652	1			T1	1		T2	1		T3	1
all_pins[2]	3057652	1			T1	1		T2	1		T3	1
all_pins[3]	3057652	1			T1	1		T2	1		T3	1
all_pins[4]	3057652	1			T1	1		T2	1		T3	1
all_pins[5]	3057652	1			T1	1		T2	1		T3	1
all_pins[6]	3057652	1			T1	1		T2	1		T3	1
all_pins[7]	3057652	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	24409433	1			T1	8		T2	8		T3	8
values[0x1]	51783	1			T19	4		T20	759		T31	556
transitions[0x0=>0x1]	50733	1			T19	4		T20	759		T31	272
transitions[0x1=>0x0]	50742	1			T19	4		T20	759		T31	272

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3056737	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	915	1			T19	1		T31	255		T32	1
all_pins[0]	transitions[0x0=>0x1]	466	1			T19	1		T31	39		T32	1
all_pins[0]	transitions[0x1=>0x0]	299	1			T20	25		T31	4		T33	2
all_pins[1]	values[0x0]	3056904	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	748	1			T20	25		T31	220		T33	2
all_pins[1]	transitions[0x0=>0x1]	547	1			T20	25		T31	157		T167	4
all_pins[1]	transitions[0x1=>0x0]	131	1			T19	1		T31	2		T32	1
all_pins[2]	values[0x0]	3057320	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	332	1			T19	1		T31	65		T32	1
all_pins[2]	transitions[0x0=>0x1]	282	1			T19	1		T31	65		T32	1
all_pins[2]	transitions[0x1=>0x0]	138	1			T20	1		T31	3		T33	1
all_pins[3]	values[0x0]	3057464	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	188	1			T20	1		T31	3		T33	1
all_pins[3]	transitions[0x0=>0x1]	149	1			T20	1		T31	3		T33	1
all_pins[3]	transitions[0x1=>0x0]	122	1			T19	1		T31	2		T33	1
all_pins[4]	values[0x0]	3057491	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	161	1			T19	1		T31	2		T33	1
all_pins[4]	transitions[0x0=>0x1]	128	1			T19	1		T31	1		T169	1
all_pins[4]	transitions[0x1=>0x0]	868	1			T31	2		T32	1		T33	159
all_pins[5]	values[0x0]	3056751	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	901	1			T31	3		T32	1		T33	160
all_pins[5]	transitions[0x0=>0x1]	715	1			T31	1		T33	4		T169	2
all_pins[5]	transitions[0x1=>0x0]	48177	1			T20	733		T31	2		T32	1
all_pins[6]	values[0x0]	3009289	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	48363	1			T20	733		T31	4		T32	2
all_pins[6]	transitions[0x0=>0x1]	48322	1			T20	733		T31	3		T32	2
all_pins[6]	transitions[0x1=>0x0]	134	1			T19	1		T31	3		T32	1
all_pins[7]	values[0x0]	3057477	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	175	1			T19	1		T31	4		T32	1
all_pins[7]	transitions[0x0=>0x1]	124	1			T19	1		T31	3		T32	1
all_pins[7]	transitions[0x1=>0x0]	873	1			T19	1		T31	254		T32	1