Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17080

1

T3

2

T10

32

T13

15

auto[1]

13159

1

T13

7

T16

8

T37

118

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4723	1			T48	12		T37	34		T43	20
values[1]	3676	1			T37	20		T19	21		T43	92
values[2]	3712	1			T13	22		T18	2		T37	56
values[3]	3615	1			T3	2		T47	12		T19	23
values[4]	3614	1			T37	47		T51	14		T52	40
values[5]	3730	1			T37	171		T19	26		T49	100
values[6]	3757	1			T16	21		T37	47		T50	16
values[7]	3412	1			T10	32		T37	118		T19	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3539	1			T18	2		T48	12		T37	138
values[1]	3427	1			T37	47		T49	40		T52	62
values[2]	4214	1			T37	79		T65	4		T19	23
values[3]	3516	1			T10	32		T37	20		T19	26
values[4]	3945	1			T47	12		T50	16		T43	20
values[5]	3317	1			T37	74		T19	21		T43	162
values[6]	4238	1			T3	2		T16	21		T37	56
values[7]	4043	1			T13	22		T37	79		T174	16

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	316	1			T48	12		T43	11		T56	7
auto[0]	values[0]	values[1]	327	1			T193	10		T169	11		T186	11
auto[0]	values[0]	values[2]	457	1			T52	8		T53	13		T181	16
auto[0]	values[0]	values[3]	361	1			T273	10		T274	4		T156	9
auto[0]	values[0]	values[4]	267	1			T49	12		T171	9		T123	26
auto[0]	values[0]	values[5]	142	1			T37	9		T53	12		T175	13
auto[0]	values[0]	values[6]	511	1			T94	2		T33	14		T167	14
auto[0]	values[0]	values[7]	341	1			T195	6		T20	12		T159	16
auto[0]	values[1]	values[0]	447	1			T171	17		T176	4		T275	12
auto[0]	values[1]	values[1]	209	1			T200	2		T175	12		T212	13
auto[0]	values[1]	values[2]	222	1			T198	4		T123	14		T129	20
auto[0]	values[1]	values[3]	236	1			T129	14		T131	11		T23	7
auto[0]	values[1]	values[4]	208	1			T171	10		T23	43		T276	8
auto[0]	values[1]	values[5]	244	1			T37	14		T19	13		T49	4
auto[0]	values[1]	values[6]	290	1			T43	79		T49	9		T124	13
auto[0]	values[1]	values[7]	262	1			T171	16		T179	10		T128	12
auto[0]	values[2]	values[0]	213	1			T18	2		T43	8		T171	14
auto[0]	values[2]	values[1]	296	1			T49	12		T170	4		T277	51
auto[0]	values[2]	values[2]	225	1			T65	4		T92	6		T124	11
auto[0]	values[2]	values[3]	298	1			T189	24		T124	13		T129	20
auto[0]	values[2]	values[4]	183	1			T250	15		T209	12		T225	29
auto[0]	values[2]	values[5]	273	1			T53	16		T56	101		T192	10
auto[0]	values[2]	values[6]	405	1			T37	48		T58	6		T171	11
auto[0]	values[2]	values[7]	337	1			T13	15		T56	74		T33	21
auto[0]	values[3]	values[0]	254	1			T49	9		T179	9		T128	6
auto[0]	values[3]	values[1]	283	1			T52	8		T179	12		T123	20
auto[0]	values[3]	values[2]	183	1			T19	16		T49	11		T23	6
auto[0]	values[3]	values[3]	379	1			T20	11		T129	26		T175	13
auto[0]	values[3]	values[4]	269	1			T47	12		T20	11		T32	7
auto[0]	values[3]	values[5]	193	1			T43	12		T52	9		T20	12
auto[0]	values[3]	values[6]	206	1			T3	2		T185	8		T56	57
auto[0]	values[3]	values[7]	156	1			T20	10		T192	10		T33	14
auto[0]	values[4]	values[0]	121	1			T123	11		T129	12		T33	15
auto[0]	values[4]	values[1]	283	1			T37	39		T53	25		T192	11
auto[0]	values[4]	values[2]	334	1			T52	10		T53	12		T177	21
auto[0]	values[4]	values[3]	187	1			T51	14		T52	14		T129	32
auto[0]	values[4]	values[4]	299	1			T20	14		T192	13		T177	34
auto[0]	values[4]	values[5]	239	1			T206	4		T33	12		T177	9
auto[0]	values[4]	values[6]	215	1			T123	6		T23	8		T192	31
auto[0]	values[4]	values[7]	247	1			T131	6		T180	6		T169	28
auto[0]	values[5]	values[0]	166	1			T37	9		T179	8		T32	7
auto[0]	values[5]	values[1]	169	1			T49	7		T53	10		T188	8
auto[0]	values[5]	values[2]	374	1			T37	23		T49	13		T20	10
auto[0]	values[5]	values[3]	278	1			T37	10		T19	20		T52	21
auto[0]	values[5]	values[4]	289	1			T49	16		T178	2		T129	15
auto[0]	values[5]	values[5]	165	1			T37	5		T49	13		T129	15
auto[0]	values[5]	values[6]	289	1			T179	9		T128	12		T175	10
auto[0]	values[5]	values[7]	280	1			T37	73		T52	12		T171	13
auto[0]	values[6]	values[0]	136	1			T53	12		T171	6		T32	10
auto[0]	values[6]	values[1]	420	1			T53	11		T20	30		T23	12
auto[0]	values[6]	values[2]	262	1			T37	40		T43	10		T20	31
auto[0]	values[6]	values[3]	123	1			T56	11		T177	11		T278	2
auto[0]	values[6]	values[4]	248	1			T50	16		T128	16		T131	8
auto[0]	values[6]	values[5]	360	1			T53	25		T56	14		T23	8
auto[0]	values[6]	values[6]	204	1			T16	13		T124	14		T221	7
auto[0]	values[6]	values[7]	282	1			T53	13		T171	12		T169	11
auto[0]	values[7]	values[0]	383	1			T37	105		T56	12		T123	11
auto[0]	values[7]	values[1]	158	1			T56	78		T23	17		T217	13
auto[0]	values[7]	values[2]	237	1			T43	10		T53	15		T124	13
auto[0]	values[7]	values[3]	193	1			T10	32		T43	11		T52	11
auto[0]	values[7]	values[4]	367	1			T43	11		T53	8		T56	8
auto[0]	values[7]	values[5]	185	1			T52	25		T279	12		T175	13
auto[0]	values[7]	values[6]	283	1			T19	12		T23	17		T280	4
auto[0]	values[7]	values[7]	311	1			T49	17		T33	17		T250	11
auto[1]	values[0]	values[0]	302	1			T43	9		T56	61		T123	22
auto[1]	values[0]	values[1]	135	1			T169	14		T186	9		T250	10
auto[1]	values[0]	values[2]	223	1			T52	51		T53	9		T171	20
auto[1]	values[0]	values[3]	208	1			T281	2		T282	6		T156	26
auto[1]	values[0]	values[4]	358	1			T49	8		T171	16		T123	6
auto[1]	values[0]	values[5]	70	1			T37	25		T53	8		T175	7
auto[1]	values[0]	values[6]	266	1			T33	6		T167	6		T250	24
auto[1]	values[0]	values[7]	439	1			T20	8		T215	57		T191	21
auto[1]	values[1]	values[0]	108	1			T171	7		T186	8		T250	14
auto[1]	values[1]	values[1]	116	1			T175	8		T212	7		T233	8
auto[1]	values[1]	values[2]	334	1			T123	10		T129	6		T192	78
auto[1]	values[1]	values[3]	160	1			T129	6		T131	9		T23	14
auto[1]	values[1]	values[4]	237	1			T55	22		T171	10		T23	7
auto[1]	values[1]	values[5]	96	1			T37	6		T19	8		T49	16
auto[1]	values[1]	values[6]	286	1			T43	13		T49	11		T124	7
auto[1]	values[1]	values[7]	221	1			T174	16		T171	4		T179	10
auto[1]	values[2]	values[0]	206	1			T43	12		T171	6		T179	9
auto[1]	values[2]	values[1]	183	1			T49	8		T167	14		T168	11
auto[1]	values[2]	values[2]	136	1			T124	9		T192	13		T209	6
auto[1]	values[2]	values[3]	222	1			T124	7		T129	55		T192	10
auto[1]	values[2]	values[4]	109	1			T250	34		T209	11		T225	4
auto[1]	values[2]	values[5]	92	1			T53	12		T56	9		T192	10
auto[1]	values[2]	values[6]	432	1			T37	8		T171	9		T179	8
auto[1]	values[2]	values[7]	102	1			T13	7		T56	9		T33	11
auto[1]	values[3]	values[0]	164	1			T49	11		T179	11		T128	14
auto[1]	values[3]	values[1]	217	1			T52	54		T179	8		T123	22
auto[1]	values[3]	values[2]	250	1			T19	7		T49	9		T130	6
auto[1]	values[3]	values[3]	143	1			T20	9		T129	2		T175	7
auto[1]	values[3]	values[4]	256	1			T20	10		T32	17		T213	10
auto[1]	values[3]	values[5]	346	1			T43	150		T52	63		T20	8
auto[1]	values[3]	values[6]	154	1			T56	5		T124	11		T202	14
auto[1]	values[3]	values[7]	162	1			T20	10		T192	10		T33	13
auto[1]	values[4]	values[0]	115	1			T123	9		T129	12		T33	6
auto[1]	values[4]	values[1]	146	1			T37	8		T53	16		T192	23
auto[1]	values[4]	values[2]	193	1			T52	10		T53	8		T177	11
auto[1]	values[4]	values[3]	67	1			T52	6		T129	15		T220	5
auto[1]	values[4]	values[4]	303	1			T20	11		T192	8		T177	10
auto[1]	values[4]	values[5]	388	1			T33	8		T177	17		T221	5
auto[1]	values[4]	values[6]	196	1			T123	34		T23	73		T192	14
auto[1]	values[4]	values[7]	281	1			T131	14		T169	15		T183	2
auto[1]	values[5]	values[0]	124	1			T37	11		T179	12		T283	2
auto[1]	values[5]	values[1]	204	1			T49	13		T53	10		T179	7
auto[1]	values[5]	values[2]	293	1			T37	9		T49	7		T20	10
auto[1]	values[5]	values[3]	309	1			T37	10		T19	6		T52	33
auto[1]	values[5]	values[4]	158	1			T49	24		T54	12		T129	11
auto[1]	values[5]	values[5]	153	1			T37	15		T49	7		T129	9
auto[1]	values[5]	values[6]	161	1			T179	11		T128	27		T175	10
auto[1]	values[5]	values[7]	318	1			T37	6		T52	65		T171	10
auto[1]	values[6]	values[0]	270	1			T53	8		T171	14		T32	36
auto[1]	values[6]	values[1]	196	1			T53	9		T20	16		T23	10
auto[1]	values[6]	values[2]	303	1			T37	7		T43	10		T20	48
auto[1]	values[6]	values[3]	175	1			T56	9		T284	8		T177	114
auto[1]	values[6]	values[4]	189	1			T128	6		T131	12		T250	8
auto[1]	values[6]	values[5]	229	1			T53	18		T56	6		T23	13
auto[1]	values[6]	values[6]	185	1			T16	8		T124	6		T221	19
auto[1]	values[6]	values[7]	175	1			T53	7		T171	8		T169	9
auto[1]	values[7]	values[0]	214	1			T37	13		T56	8		T123	9
auto[1]	values[7]	values[1]	85	1			T56	6		T23	3		T217	7
auto[1]	values[7]	values[2]	188	1			T43	10		T53	8		T124	7
auto[1]	values[7]	values[3]	177	1			T43	17		T52	9		T228	10
auto[1]	values[7]	values[4]	205	1			T43	9		T53	13		T56	12
auto[1]	values[7]	values[5]	142	1			T52	22		T175	7		T177	5
auto[1]	values[7]	values[6]	155	1			T19	8		T23	52		T285	9
auto[1]	values[7]	values[7]	129	1			T49	3		T33	9		T250	9