Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	428	1			T37	8		T19	3		T51	8
auto[ReadAddrCrossIntoMailbox]	280	1			T37	1		T43	4		T49	5
auto[ReadAddrCrossOutOfMailbox]	315	1			T37	4		T19	2		T43	6
auto[ReadAddrCrossAllMailbox]	221	1			T37	7		T43	2		T49	1
auto[ReadAddrOutsideMailbox]	3390	1			T13	5		T16	5		T18	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2341

1

T13

3

T16

2

T18

1

auto[1]

2293

1

T13

2

T16

3

T18

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	741	1			T16	1		T37	7		T51	2
read_ops[0x0b]	777	1			T13	1		T16	1		T37	5
read_ops[0x3b]	773	1			T13	1		T16	1		T47	2
read_ops[0x6b]	778	1			T13	2		T37	12		T50	2
read_ops[0xbb]	791	1			T37	4		T50	2		T19	3
read_ops[0xeb]	774	1			T13	1		T16	2		T18	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T37	1		T51	1		T206	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T51	1		T206	1		T56	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T43	1		T53	1		T179	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T171	1		T123	1		T210	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T43	1		T49	1		T53	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T128	1		T33	1		T183	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T43	1		T53	1		T129	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T37	1		T20	1		T131	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	275	1			T16	1		T37	3		T43	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	263	1			T37	2		T43	1		T174	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T37	1		T43	1		T49	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T43	1		T199	3		T179	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T43	1		T171	1		T124	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T43	2		T123	3		T23	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T49	1		T20	2		T123	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T19	1		T43	1		T49	3
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T37	1		T43	1		T171	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T179	1		T129	1		T167	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	294	1			T13	1		T37	1		T43	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	273	1			T16	1		T37	2		T19	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T19	1		T171	1		T124	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T37	1		T43	2		T49	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T179	1		T124	2		T131	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T123	1		T169	2		T221	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T19	1		T52	1		T32	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T37	1		T49	1		T171	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T171	1		T56	1		T123	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T37	1		T53	1		T217	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T13	1		T16	1		T47	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	291	1			T47	1		T37	5		T19	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T37	1		T52	1		T20	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	20	1			T19	2		T179	1		T175	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T49	1		T20	2		T123	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T49	1		T179	1		T272	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T37	1		T171	1		T56	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T37	1		T43	2		T171	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T37	1		T49	1		T123	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T37	2		T123	1		T23	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	279	1			T37	3		T50	1		T65	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	292	1			T13	2		T37	3		T50	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T51	3		T43	1		T52	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T37	1		T51	3		T43	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T49	1		T52	1		T123	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T20	3		T179	1		T129	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T43	1		T179	1		T217	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T43	1		T56	1		T175	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T123	1		T210	1		T33	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T37	1		T210	1		T33	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	306	1			T37	1		T50	1		T49	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	271	1			T37	1		T50	1		T19	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T37	2		T49	2		T206	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T37	1		T43	1		T52	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T49	1		T171	1		T20	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T37	1		T49	1		T131	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T37	1		T49	1		T179	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T49	1		T20	1		T123	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T124	1		T23	1		T286	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T124	1		T286	1		T192	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	268	1			T13	1		T18	1		T37	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	291	1			T16	2		T18	1		T37	2