Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3456	1			T37	54		T50	16		T19	21
values[1]	3683	1			T43	132		T49	20		T53	71
values[2]	4529	1			T37	194		T19	23		T51	14
values[3]	3735	1			T16	21		T37	114		T58	6
values[4]	3546	1			T19	20		T43	48		T174	16
values[5]	3753	1			T10	32		T18	2		T37	79
values[6]	3499	1			T3	2		T13	22		T47	12
values[7]	4038	1			T37	52		T65	4		T49	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3978	1			T16	21		T43	40		T49	60
values[1]	4356	1			T13	22		T37	99		T65	4
values[2]	3952	1			T43	40		T52	74		T53	23
values[3]	2951	1			T37	32		T58	6		T19	23
values[4]	4429	1			T19	20		T43	254		T49	80
values[5]	3297	1			T3	2		T18	2		T37	56
values[6]	3595	1			T10	32		T37	67		T50	16
values[7]	3681	1			T47	12		T48	12		T37	239

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29469

1

T3

2

T10

32

T13

22

auto[1]

770

1

T37

6

T19

1

T43

5

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[5]]	[values[6]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	488	1			T52	26		T131	19		T175	20
auto[0]	values[0]	values[1]	656	1			T49	20		T176	4		T177	31
auto[0]	values[0]	values[2]	323	1			T56	19		T129	25		T23	20
auto[0]	values[0]	values[3]	365	1			T178	2		T131	19		T32	19
auto[0]	values[0]	values[4]	306	1			T55	18		T129	27		T23	71
auto[0]	values[0]	values[5]	385	1			T20	57		T179	20		T23	50
auto[0]	values[0]	values[6]	437	1			T50	16		T19	21		T53	22
auto[0]	values[0]	values[7]	397	1			T37	54		T180	6		T175	20
auto[0]	values[1]	values[0]	567	1			T43	20		T179	19		T23	81
auto[0]	values[1]	values[1]	592	1			T53	20		T170	4		T20	20
auto[0]	values[1]	values[2]	536	1			T56	20		T128	37		T23	20
auto[0]	values[1]	values[3]	423	1			T53	28		T171	20		T20	20
auto[0]	values[1]	values[4]	589	1			T43	90		T49	17		T181	16
auto[0]	values[1]	values[5]	233	1			T53	22		T171	20		T182	22
auto[0]	values[1]	values[6]	371	1			T129	23		T175	39		T183	22
auto[0]	values[1]	values[7]	283	1			T43	20		T56	68		T184	4
auto[0]	values[2]	values[0]	588	1			T49	18		T53	19		T23	22
auto[0]	values[2]	values[1]	578	1			T37	19		T185	8		T23	110
auto[0]	values[2]	values[2]	529	1			T23	32		T32	60		T33	23
auto[0]	values[2]	values[3]	226	1			T19	23		T186	20		T187	20
auto[0]	values[2]	values[4]	494	1			T52	20		T179	19		T123	52
auto[0]	values[2]	values[5]	490	1			T37	55		T51	14		T53	39
auto[0]	values[2]	values[6]	685	1			T53	20		T159	16		T179	19
auto[0]	values[2]	values[7]	788	1			T37	115		T56	20		T129	23
auto[0]	values[3]	values[0]	488	1			T16	21		T43	20		T49	37
auto[0]	values[3]	values[1]	322	1			T49	18		T188	8		T189	24
auto[0]	values[3]	values[2]	411	1			T124	20		T190	18		T191	19
auto[0]	values[3]	values[3]	477	1			T58	6		T52	70		T20	35
auto[0]	values[3]	values[4]	576	1			T49	19		T53	20		T56	108
auto[0]	values[3]	values[5]	410	1			T52	55		T129	25		T192	20
auto[0]	values[3]	values[6]	648	1			T37	47		T49	20		T128	20
auto[0]	values[3]	values[7]	315	1			T37	67		T23	19		T193	10
auto[0]	values[4]	values[0]	591	1			T52	18		T20	19		T168	20
auto[0]	values[4]	values[1]	650	1			T56	83		T33	30		T194	8
auto[0]	values[4]	values[2]	376	1			T43	20		T52	19		T56	60
auto[0]	values[4]	values[3]	265	1			T179	20		T192	20		T33	35
auto[0]	values[4]	values[4]	414	1			T19	20		T195	6		T124	19
auto[0]	values[4]	values[5]	359	1			T49	20		T20	20		T128	22
auto[0]	values[4]	values[6]	271	1			T174	16		T53	20		T186	58
auto[0]	values[4]	values[7]	546	1			T43	28		T171	23		T124	15
auto[0]	values[5]	values[0]	218	1			T23	40		T196	20		T197	12
auto[0]	values[5]	values[1]	459	1			T37	79		T131	20		T23	20
auto[0]	values[5]	values[2]	572	1			T43	20		T52	33		T53	21
auto[0]	values[5]	values[3]	265	1			T198	4		T49	20		T199	12
auto[0]	values[5]	values[4]	831	1			T43	159		T171	20		T192	40
auto[0]	values[5]	values[5]	522	1			T18	2		T92	6		T52	74
auto[0]	values[5]	values[6]	302	1			T10	32		T23	23		T32	20
auto[0]	values[5]	values[7]	513	1			T20	23		T200	2		T124	20
auto[0]	values[6]	values[0]	426	1			T52	20		T171	60		T131	20
auto[0]	values[6]	values[1]	646	1			T13	22		T53	19		T56	17
auto[0]	values[6]	values[2]	460	1			T52	20		T201	16		T169	23
auto[0]	values[6]	values[3]	472	1			T128	46		T202	14		T175	39
auto[0]	values[6]	values[4]	406	1			T49	20		T171	20		T169	24
auto[0]	values[6]	values[5]	344	1			T3	2		T19	25		T56	82
auto[0]	values[6]	values[6]	345	1			T203	16		T204	20		T205	18
auto[0]	values[6]	values[7]	307	1			T47	12		T48	12		T54	10
auto[0]	values[7]	values[0]	516	1			T53	18		T206	4		T20	41
auto[0]	values[7]	values[1]	331	1			T65	4		T23	19		T192	27
auto[0]	values[7]	values[2]	631	1			T207	10		T208	4		T209	27
auto[0]	values[7]	values[3]	394	1			T37	31		T20	21		T210	10
auto[0]	values[7]	values[4]	701	1			T49	19		T123	37		T129	23
auto[0]	values[7]	values[5]	449	1			T52	62		T129	22		T211	18
auto[0]	values[7]	values[6]	471	1			T37	20		T171	24		T167	24
auto[0]	values[7]	values[7]	440	1			T53	20		T192	33		T175	19
auto[1]	values[0]	values[0]	11	1			T52	1		T131	1		T212	2
auto[1]	values[0]	values[1]	12	1			T186	2		T213	1		T214	1
auto[1]	values[0]	values[2]	7	1			T56	1		T129	1		T23	1
auto[1]	values[0]	values[3]	16	1			T131	1		T32	1		T33	3
auto[1]	values[0]	values[4]	12	1			T55	4		T129	1		T23	1
auto[1]	values[0]	values[5]	8	1			T20	1		T215	2		T216	2
auto[1]	values[0]	values[6]	17	1			T20	1		T123	2		T217	1
auto[1]	values[0]	values[7]	16	1			T177	1		T187	3		T218	3
auto[1]	values[1]	values[0]	13	1			T179	1		T219	1		T220	3
auto[1]	values[1]	values[1]	15	1			T129	2		T192	3		T221	2
auto[1]	values[1]	values[2]	14	1			T128	2		T219	8		T222	2
auto[1]	values[1]	values[3]	7	1			T223	1		T196	1		T224	2
auto[1]	values[1]	values[4]	12	1			T43	2		T49	3		T225	1
auto[1]	values[1]	values[5]	11	1			T53	1		T131	2		T169	1
auto[1]	values[1]	values[6]	8	1			T175	1		T187	1		T226	2
auto[1]	values[1]	values[7]	9	1			T184	2		T169	1		T227	1
auto[1]	values[2]	values[0]	26	1			T49	2		T53	1		T175	5
auto[1]	values[2]	values[1]	22	1			T37	1		T23	4		T228	2
auto[1]	values[2]	values[2]	27	1			T23	1		T32	6		T33	4
auto[1]	values[2]	values[3]	2	1			T229	2		-	-		-	-
auto[1]	values[2]	values[4]	27	1			T179	1		T123	4		T175	1
auto[1]	values[2]	values[5]	12	1			T37	1		T53	1		T23	1
auto[1]	values[2]	values[6]	12	1			T179	1		T123	2		T221	1
auto[1]	values[2]	values[7]	23	1			T37	3		T129	1		T131	2
auto[1]	values[3]	values[0]	13	1			T49	3		T168	1		T191	3
auto[1]	values[3]	values[1]	10	1			T49	2		T177	1		T183	1
auto[1]	values[3]	values[2]	16	1			T191	1		T209	4		T230	2
auto[1]	values[3]	values[3]	11	1			T52	2		T192	2		T231	2
auto[1]	values[3]	values[4]	11	1			T49	1		T53	1		T56	2
auto[1]	values[3]	values[5]	14	1			T52	4		T129	1		T215	1
auto[1]	values[3]	values[6]	11	1			T217	2		T32	1		T219	1
auto[1]	values[3]	values[7]	2	1			T23	2		-	-		-	-
auto[1]	values[4]	values[0]	7	1			T52	2		T20	1		T168	1
auto[1]	values[4]	values[1]	9	1			T56	1		T33	2		T221	1
auto[1]	values[4]	values[2]	18	1			T52	1		T56	2		T232	2
auto[1]	values[4]	values[3]	3	1			T233	1		T234	2		-	-
auto[1]	values[4]	values[4]	9	1			T124	1		T192	1		T175	4
auto[1]	values[4]	values[5]	9	1			T183	1		T215	1		T235	1
auto[1]	values[4]	values[6]	3	1			T236	2		T237	1		-	-
auto[1]	values[4]	values[7]	16	1			T124	5		T23	1		T238	1
auto[1]	values[5]	values[0]	3	1			T239	1		T240	2		-	-
auto[1]	values[5]	values[1]	15	1			T209	4		T241	3		T242	1
auto[1]	values[5]	values[2]	9	1			T52	1		T53	2		T204	1
auto[1]	values[5]	values[3]	8	1			T129	1		T183	1		T233	2
auto[1]	values[5]	values[4]	12	1			T43	3		T33	2		T215	1
auto[1]	values[5]	values[5]	15	1			T52	3		T219	2		T187	2
auto[1]	values[5]	values[7]	9	1			T20	2		T23	4		T187	1
auto[1]	values[6]	values[0]	11	1			T171	4		T204	1		T243	2
auto[1]	values[6]	values[1]	29	1			T53	2		T56	3		T169	2
auto[1]	values[6]	values[2]	10	1			T196	3		T244	4		T245	2
auto[1]	values[6]	values[3]	6	1			T175	1		T238	2		T235	1
auto[1]	values[6]	values[4]	7	1			T169	1		T227	2		T246	1
auto[1]	values[6]	values[5]	14	1			T19	1		T56	1		T214	2
auto[1]	values[6]	values[6]	6	1			T247	2		T35	2		T248	2
auto[1]	values[6]	values[7]	10	1			T54	2		T20	1		T249	1
auto[1]	values[7]	values[0]	12	1			T53	2		T131	4		T191	1
auto[1]	values[7]	values[1]	10	1			T23	1		T192	2		T177	3
auto[1]	values[7]	values[2]	13	1			T209	2		T219	2		T214	2
auto[1]	values[7]	values[3]	11	1			T37	1		T192	1		T175	2
auto[1]	values[7]	values[4]	22	1			T49	1		T123	3		T129	1
auto[1]	values[7]	values[5]	22	1			T129	2		T250	1		T215	3
auto[1]	values[7]	values[6]	8	1			T171	1		T167	1		T156	2
auto[1]	values[7]	values[7]	7	1			T192	1		T175	1		T177	1