Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	784	1			T19	4		T20	4		T31	14
all_values[1]	784	1			T19	4		T20	4		T31	14
all_values[2]	784	1			T19	4		T20	4		T31	14
all_values[3]	784	1			T19	4		T20	4		T31	14
all_values[4]	784	1			T19	4		T20	4		T31	14
all_values[5]	784	1			T19	4		T20	4		T31	14
all_values[6]	784	1			T19	4		T20	4		T31	14
all_values[7]	784	1			T19	4		T20	4		T31	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3427

1

T19

20

T20

22

T31

63

auto[1]

2845

1

T19

12

T20

10

T31

49

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2577

1

T19

17

T20

16

T31

52

auto[1]

3695

1

T19

15

T20

16

T31

60

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3634

1

T19

22

T20

23

T31

66

auto[1]

2638

1

T19

10

T20

9

T31

46

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	174	1			T19	2		T20	4		T31	4
all_values[0]	auto[0]	auto[0]	auto[1]	81	1			T19	1		T31	1		T33	3
all_values[0]	auto[0]	auto[1]	auto[0]	127	1			T31	2		T32	1		T33	2
all_values[0]	auto[0]	auto[1]	auto[1]	82	1			T31	1		T167	1		T153	2
all_values[0]	auto[1]	auto[0]	auto[1]	172	1			T19	1		T31	1		T33	1
all_values[0]	auto[1]	auto[1]	auto[1]	148	1			T31	5		T32	2		T33	1
all_values[1]	auto[0]	auto[0]	auto[0]	163	1			T19	2		T20	1		T31	2
all_values[1]	auto[0]	auto[0]	auto[1]	75	1			T31	1		T153	1		T168	1
all_values[1]	auto[0]	auto[1]	auto[0]	134	1			T19	2		T20	2		T169	2
all_values[1]	auto[0]	auto[1]	auto[1]	88	1			T31	3		T169	1		T167	1
all_values[1]	auto[1]	auto[0]	auto[1]	181	1			T20	1		T31	3		T33	3
all_values[1]	auto[1]	auto[1]	auto[1]	143	1			T31	5		T33	1		T169	6
all_values[2]	auto[0]	auto[0]	auto[0]	165	1			T31	6		T33	1		T169	3
all_values[2]	auto[0]	auto[0]	auto[1]	79	1			T20	2		T31	1		T32	1
all_values[2]	auto[0]	auto[1]	auto[0]	140	1			T19	1		T31	2		T169	2
all_values[2]	auto[0]	auto[1]	auto[1]	70	1			T19	1		T31	1		T33	2
all_values[2]	auto[1]	auto[0]	auto[1]	187	1			T20	2		T31	3		T32	3
all_values[2]	auto[1]	auto[1]	auto[1]	143	1			T19	2		T31	1		T33	3
all_values[3]	auto[0]	auto[0]	auto[0]	176	1			T19	1		T31	6		T32	2
all_values[3]	auto[0]	auto[0]	auto[1]	67	1			T20	2		T32	1		T153	1
all_values[3]	auto[0]	auto[1]	auto[0]	120	1			T19	1		T31	2		T33	3
all_values[3]	auto[0]	auto[1]	auto[1]	78	1			T19	1		T31	1		T169	1
all_values[3]	auto[1]	auto[0]	auto[1]	179	1			T19	1		T20	2		T31	2
all_values[3]	auto[1]	auto[1]	auto[1]	164	1			T31	3		T33	1		T169	4
all_values[4]	auto[0]	auto[0]	auto[0]	162	1			T19	1		T20	2		T31	5
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T19	1		T31	2		T169	1
all_values[4]	auto[0]	auto[1]	auto[0]	149	1			T20	2		T31	2		T32	1
all_values[4]	auto[0]	auto[1]	auto[1]	59	1			T32	1		T153	1		T155	1
all_values[4]	auto[1]	auto[0]	auto[1]	184	1			T19	2		T31	3		T32	1
all_values[4]	auto[1]	auto[1]	auto[1]	146	1			T31	2		T33	1		T169	1
all_values[5]	auto[0]	auto[0]	auto[0]	275	1			T19	2		T20	2		T31	7
all_values[5]	auto[0]	auto[1]	auto[0]	184	1			T31	1		T32	1		T33	4
all_values[5]	auto[1]	auto[0]	auto[1]	183	1			T19	2		T20	1		T31	3
all_values[5]	auto[1]	auto[1]	auto[1]	142	1			T20	1		T31	3		T32	1
all_values[6]	auto[0]	auto[0]	auto[0]	166	1			T19	3		T31	4		T32	1
all_values[6]	auto[0]	auto[0]	auto[1]	76	1			T20	1		T169	2		T167	1
all_values[6]	auto[0]	auto[1]	auto[0]	140	1			T31	4		T32	1		T33	2
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T20	2		T31	1		T32	1
all_values[6]	auto[1]	auto[0]	auto[1]	172	1			T19	1		T20	1		T31	1
all_values[6]	auto[1]	auto[1]	auto[1]	155	1			T31	4		T32	1		T33	1
all_values[7]	auto[0]	auto[0]	auto[0]	166	1			T20	1		T31	3		T169	3
all_values[7]	auto[0]	auto[0]	auto[1]	66	1			T32	3		T33	1		T153	1
all_values[7]	auto[0]	auto[1]	auto[0]	136	1			T19	2		T20	2		T31	2
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T19	1		T31	2		T169	1
all_values[7]	auto[1]	auto[0]	auto[1]	194	1			T31	5		T32	1		T33	3
all_values[7]	auto[1]	auto[1]	auto[1]	145	1			T19	1		T20	1		T31	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal