Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1942

1

T5

2

T12

7

T13

9

auto[1]

1869

1

T5

6

T12

4

T13

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2206

1

T13

12

T16

5

T38

11

auto[1]

1605

1

T5

8

T12

11

T13

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2979

1

T5

8

T12

11

T13

10

auto[1]

832

1

T13

5

T16

1

T38

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	784	1			T12	2		T13	3		T25	3
valid[1]	782	1			T5	3		T12	1		T13	5
valid[2]	781	1			T5	2		T12	3		T13	3
valid[3]	719	1			T5	1		T12	1		T13	2
valid[4]	745	1			T5	2		T12	4		T13	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	173	1			T13	1		T38	1		T39	1
auto[0]	auto[0]	valid[0]	auto[1]	167	1			T12	2		T13	1		T25	1
auto[0]	auto[0]	valid[1]	auto[0]	140	1			T13	2		T38	1		T39	2
auto[0]	auto[0]	valid[1]	auto[1]	180	1			T14	2		T25	2		T29	4
auto[0]	auto[0]	valid[2]	auto[0]	152	1			T13	1		T39	2		T41	2
auto[0]	auto[0]	valid[2]	auto[1]	150	1			T12	2		T25	1		T29	6
auto[0]	auto[0]	valid[3]	auto[0]	135	1			T38	1		T39	1		T62	1
auto[0]	auto[0]	valid[3]	auto[1]	147	1			T5	1		T13	1		T14	1
auto[0]	auto[0]	valid[4]	auto[0]	122	1			T13	1		T39	1		T57	1
auto[0]	auto[0]	valid[4]	auto[1]	156	1			T5	1		T12	3		T14	1
auto[0]	auto[1]	valid[0]	auto[0]	132	1			T13	1		T16	1		T38	1
auto[0]	auto[1]	valid[0]	auto[1]	146	1			T25	2		T29	3		T30	3
auto[0]	auto[1]	valid[1]	auto[0]	135	1			T39	1		T61	1		T19	1
auto[0]	auto[1]	valid[1]	auto[1]	166	1			T5	3		T12	1		T29	2
auto[0]	auto[1]	valid[2]	auto[0]	117	1			T16	1		T41	2		T172	2
auto[0]	auto[1]	valid[2]	auto[1]	174	1			T5	2		T12	1		T13	1
auto[0]	auto[1]	valid[3]	auto[0]	140	1			T16	1		T38	3		T39	1
auto[0]	auto[1]	valid[3]	auto[1]	143	1			T12	1		T28	1		T29	5
auto[0]	auto[1]	valid[4]	auto[0]	128	1			T13	1		T16	1		T39	3
auto[0]	auto[1]	valid[4]	auto[1]	176	1			T5	1		T12	1		T25	3
auto[1]	auto[0]	valid[0]	auto[0]	86	1			T39	2		T61	2		T19	1
auto[1]	auto[0]	valid[1]	auto[0]	73	1			T13	2		T38	1		T39	2
auto[1]	auto[0]	valid[2]	auto[0]	100	1			T39	1		T41	2		T172	1
auto[1]	auto[0]	valid[3]	auto[0]	80	1			T41	2		T172	1		T90	1
auto[1]	auto[0]	valid[4]	auto[0]	81	1			T61	1		T19	1		T53	1
auto[1]	auto[1]	valid[0]	auto[0]	80	1			T90	1		T298	1		T161	1
auto[1]	auto[1]	valid[1]	auto[0]	88	1			T13	1		T38	2		T41	1
auto[1]	auto[1]	valid[2]	auto[0]	88	1			T13	1		T38	1		T39	1
auto[1]	auto[1]	valid[3]	auto[0]	74	1			T13	1		T16	1		T39	1
auto[1]	auto[1]	valid[4]	auto[0]	82	1			T39	1		T61	1		T89	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal