Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54402

1

T13

398

T16

147

T26

6

auto[1]

17050

1

T5

79

T12

102

T13

46

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51581

1

T5

79

T12

102

T13

300

auto[1]

19871

1

T13

144

T16

45

T26

3

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	36994	1			T5	44		T12	56		T13	226
others[1]	5974	1			T5	9		T12	9		T13	31
others[2]	5989	1			T5	5		T12	7		T13	42
others[3]	6794	1			T5	4		T12	3		T13	39
interest[1]	3790	1			T5	7		T12	6		T13	20
interest[4]	24300	1			T5	32		T12	41		T13	156
interest[64]	11911	1			T5	10		T12	21		T13	86

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17872	1			T13	133		T16	48		T38	86
auto[0]	auto[0]	others[1]	2918	1			T13	15		T16	12		T38	12
auto[0]	auto[0]	others[2]	2892	1			T13	26		T16	10		T26	1
auto[0]	auto[0]	others[3]	3289	1			T13	24		T16	13		T38	13
auto[0]	auto[0]	interest[1]	1866	1			T13	10		T16	8		T26	1
auto[0]	auto[0]	interest[4]	11648	1			T13	83		T16	29		T38	57
auto[0]	auto[0]	interest[64]	5694	1			T13	46		T16	11		T26	1
auto[0]	auto[1]	others[0]	8896	1			T5	44		T12	56		T13	18
auto[0]	auto[1]	others[1]	1451	1			T5	9		T12	9		T13	4
auto[0]	auto[1]	others[2]	1414	1			T5	5		T12	7		T13	4
auto[0]	auto[1]	others[3]	1636	1			T5	4		T12	3		T13	6
auto[0]	auto[1]	interest[1]	819	1			T5	7		T12	6		T25	10
auto[0]	auto[1]	interest[4]	5932	1			T5	32		T12	41		T13	11
auto[0]	auto[1]	interest[64]	2834	1			T5	10		T12	21		T13	14
auto[1]	auto[0]	others[0]	10226	1			T13	75		T16	25		T26	3
auto[1]	auto[0]	others[1]	1605	1			T13	12		T16	4		T38	11
auto[1]	auto[0]	others[2]	1683	1			T13	12		T16	2		T38	6
auto[1]	auto[0]	others[3]	1869	1			T13	9		T16	4		T38	4
auto[1]	auto[0]	interest[1]	1105	1			T13	10		T16	3		T38	8
auto[1]	auto[0]	interest[4]	6720	1			T13	62		T16	16		T26	3
auto[1]	auto[0]	interest[64]	3383	1			T13	26		T16	7		T38	24

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal