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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.02 98.38 93.99 98.62 89.36 97.19 95.45 99.16


Total test records in report: 1131
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T104 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3386122769 Aug 13 04:28:49 PM PDT 24 Aug 13 04:28:54 PM PDT 24 863603193 ps
T105 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2765666252 Aug 13 04:28:56 PM PDT 24 Aug 13 04:29:00 PM PDT 24 585485211 ps
T1024 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2461611281 Aug 13 04:29:00 PM PDT 24 Aug 13 04:29:01 PM PDT 24 17239233 ps
T1025 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.865617585 Aug 13 04:29:04 PM PDT 24 Aug 13 04:29:10 PM PDT 24 101463430 ps
T1026 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1837649165 Aug 13 04:29:10 PM PDT 24 Aug 13 04:29:14 PM PDT 24 166732267 ps
T103 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2208298022 Aug 13 04:28:55 PM PDT 24 Aug 13 04:28:57 PM PDT 24 245711607 ps
T1027 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2813790669 Aug 13 04:29:57 PM PDT 24 Aug 13 04:30:04 PM PDT 24 222918813 ps
T117 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2051257133 Aug 13 04:29:19 PM PDT 24 Aug 13 04:29:21 PM PDT 24 74954912 ps
T118 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1889601413 Aug 13 04:28:54 PM PDT 24 Aug 13 04:28:56 PM PDT 24 31162770 ps
T1028 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2632708305 Aug 13 04:29:22 PM PDT 24 Aug 13 04:29:26 PM PDT 24 65613285 ps
T1029 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2190541292 Aug 13 04:29:04 PM PDT 24 Aug 13 04:29:05 PM PDT 24 22393079 ps
T1030 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2603482225 Aug 13 04:28:58 PM PDT 24 Aug 13 04:28:59 PM PDT 24 196397438 ps
T119 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2611129706 Aug 13 04:28:54 PM PDT 24 Aug 13 04:29:02 PM PDT 24 790362077 ps
T1031 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1522589591 Aug 13 04:29:16 PM PDT 24 Aug 13 04:29:16 PM PDT 24 187130607 ps
T256 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2184655180 Aug 13 04:28:40 PM PDT 24 Aug 13 04:28:58 PM PDT 24 553397498 ps
T1032 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2999614480 Aug 13 04:28:58 PM PDT 24 Aug 13 04:29:00 PM PDT 24 54807621 ps
T148 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2814994856 Aug 13 04:28:58 PM PDT 24 Aug 13 04:29:01 PM PDT 24 107866860 ps
T149 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.734371151 Aug 13 04:29:07 PM PDT 24 Aug 13 04:29:08 PM PDT 24 759565642 ps
T1033 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2745094159 Aug 13 04:29:14 PM PDT 24 Aug 13 04:29:14 PM PDT 24 15701497 ps
T1034 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2888700848 Aug 13 04:29:13 PM PDT 24 Aug 13 04:29:14 PM PDT 24 48669049 ps
T1035 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.766173831 Aug 13 04:29:24 PM PDT 24 Aug 13 04:29:28 PM PDT 24 162571931 ps
T120 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2873625508 Aug 13 04:29:10 PM PDT 24 Aug 13 04:29:12 PM PDT 24 96443499 ps
T1036 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4248620672 Aug 13 04:28:43 PM PDT 24 Aug 13 04:28:45 PM PDT 24 30397002 ps
T106 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2612824481 Aug 13 04:28:57 PM PDT 24 Aug 13 04:29:01 PM PDT 24 201833604 ps
T150 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2631896147 Aug 13 04:29:07 PM PDT 24 Aug 13 04:29:11 PM PDT 24 141350238 ps
T1037 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3325247331 Aug 13 04:29:09 PM PDT 24 Aug 13 04:29:10 PM PDT 24 10928555 ps
T1038 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2452916840 Aug 13 04:29:08 PM PDT 24 Aug 13 04:29:09 PM PDT 24 45375168 ps
T1039 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3027507336 Aug 13 04:28:40 PM PDT 24 Aug 13 04:28:40 PM PDT 24 12753196 ps
T1040 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2507560137 Aug 13 04:28:50 PM PDT 24 Aug 13 04:28:51 PM PDT 24 48212892 ps
T1041 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.405829345 Aug 13 04:29:00 PM PDT 24 Aug 13 04:29:17 PM PDT 24 418316821 ps
T1042 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1209320994 Aug 13 04:29:14 PM PDT 24 Aug 13 04:29:18 PM PDT 24 58205777 ps
T121 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.231590772 Aug 13 04:28:48 PM PDT 24 Aug 13 04:28:50 PM PDT 24 94052828 ps
T1043 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3455633748 Aug 13 04:28:50 PM PDT 24 Aug 13 04:28:52 PM PDT 24 41076335 ps
T1044 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.23233698 Aug 13 04:29:04 PM PDT 24 Aug 13 04:29:05 PM PDT 24 24175554 ps
T107 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2129754500 Aug 13 04:29:16 PM PDT 24 Aug 13 04:29:21 PM PDT 24 3758562545 ps
T1045 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.58514239 Aug 13 04:29:11 PM PDT 24 Aug 13 04:29:13 PM PDT 24 55896335 ps
T1046 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3973924137 Aug 13 04:29:03 PM PDT 24 Aug 13 04:29:06 PM PDT 24 77666143 ps
T151 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2455625079 Aug 13 04:28:51 PM PDT 24 Aug 13 04:28:54 PM PDT 24 1775316797 ps
T1047 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.186090076 Aug 13 04:29:04 PM PDT 24 Aug 13 04:29:07 PM PDT 24 108574281 ps
T1048 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4071107631 Aug 13 04:29:13 PM PDT 24 Aug 13 04:29:14 PM PDT 24 95389006 ps
T1049 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3240742337 Aug 13 04:29:08 PM PDT 24 Aug 13 04:29:09 PM PDT 24 24519838 ps
T1050 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.850594069 Aug 13 04:29:06 PM PDT 24 Aug 13 04:29:07 PM PDT 24 42572588 ps
T1051 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2185948051 Aug 13 04:28:49 PM PDT 24 Aug 13 04:28:51 PM PDT 24 233137607 ps
T1052 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2135768368 Aug 13 04:29:07 PM PDT 24 Aug 13 04:29:08 PM PDT 24 45770341 ps
T1053 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4202033103 Aug 13 04:29:12 PM PDT 24 Aug 13 04:29:13 PM PDT 24 46143182 ps
T1054 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3929244677 Aug 13 04:29:18 PM PDT 24 Aug 13 04:29:19 PM PDT 24 25126682 ps
T1055 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1228797965 Aug 13 04:29:56 PM PDT 24 Aug 13 04:29:59 PM PDT 24 88232663 ps
T87 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2598511528 Aug 13 04:28:48 PM PDT 24 Aug 13 04:28:50 PM PDT 24 86628474 ps
T122 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.441641810 Aug 13 04:29:12 PM PDT 24 Aug 13 04:29:38 PM PDT 24 4409307921 ps
T166 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1412006577 Aug 13 04:29:20 PM PDT 24 Aug 13 04:29:23 PM PDT 24 198842790 ps
T1056 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.775315947 Aug 13 04:29:05 PM PDT 24 Aug 13 04:29:06 PM PDT 24 30961660 ps
T1057 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1327412883 Aug 13 04:28:57 PM PDT 24 Aug 13 04:29:01 PM PDT 24 999501884 ps
T1058 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3707744533 Aug 13 04:29:11 PM PDT 24 Aug 13 04:29:14 PM PDT 24 430699420 ps
T1059 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1587172290 Aug 13 04:28:59 PM PDT 24 Aug 13 04:29:01 PM PDT 24 77225060 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2900939286 Aug 13 04:28:52 PM PDT 24 Aug 13 04:29:06 PM PDT 24 218104337 ps
T1061 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.709202389 Aug 13 04:29:26 PM PDT 24 Aug 13 04:29:27 PM PDT 24 53082022 ps
T1062 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1194055878 Aug 13 04:28:54 PM PDT 24 Aug 13 04:28:54 PM PDT 24 11032752 ps
T1063 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1339471705 Aug 13 04:29:10 PM PDT 24 Aug 13 04:29:12 PM PDT 24 61160969 ps
T1064 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3170085685 Aug 13 04:29:02 PM PDT 24 Aug 13 04:29:04 PM PDT 24 491789872 ps
T1065 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1534834973 Aug 13 04:29:04 PM PDT 24 Aug 13 04:29:27 PM PDT 24 1071625951 ps
T1066 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.881592769 Aug 13 04:29:04 PM PDT 24 Aug 13 04:29:27 PM PDT 24 363199504 ps
T251 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1395283195 Aug 13 04:29:50 PM PDT 24 Aug 13 04:29:52 PM PDT 24 33051715 ps
T1067 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3413198491 Aug 13 04:29:54 PM PDT 24 Aug 13 04:29:59 PM PDT 24 383366905 ps
T1068 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.388336665 Aug 13 04:28:55 PM PDT 24 Aug 13 04:29:18 PM PDT 24 955361896 ps
T88 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.952505322 Aug 13 04:28:56 PM PDT 24 Aug 13 04:28:57 PM PDT 24 31460833 ps
T257 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2324739724 Aug 13 04:29:30 PM PDT 24 Aug 13 04:29:52 PM PDT 24 1034330181 ps
T1069 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.269181624 Aug 13 04:29:01 PM PDT 24 Aug 13 04:29:04 PM PDT 24 106035967 ps
T1070 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.217960371 Aug 13 04:28:58 PM PDT 24 Aug 13 04:29:00 PM PDT 24 54962242 ps
T1071 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1438045617 Aug 13 04:29:02 PM PDT 24 Aug 13 04:29:03 PM PDT 24 12261816 ps
T1072 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.439813973 Aug 13 04:29:14 PM PDT 24 Aug 13 04:29:15 PM PDT 24 15905286 ps
T1073 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.470053781 Aug 13 04:29:05 PM PDT 24 Aug 13 04:29:07 PM PDT 24 31294087 ps
T1074 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4061943449 Aug 13 04:29:05 PM PDT 24 Aug 13 04:29:06 PM PDT 24 19331092 ps
T1075 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1030331352 Aug 13 04:29:08 PM PDT 24 Aug 13 04:29:09 PM PDT 24 40987227 ps
T1076 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4289524464 Aug 13 04:28:56 PM PDT 24 Aug 13 04:28:58 PM PDT 24 103353635 ps
T1077 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3572046573 Aug 13 04:29:12 PM PDT 24 Aug 13 04:29:13 PM PDT 24 48767136 ps
T1078 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.24738527 Aug 13 04:28:52 PM PDT 24 Aug 13 04:28:53 PM PDT 24 231614331 ps
T1079 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.828211617 Aug 13 04:28:54 PM PDT 24 Aug 13 04:28:57 PM PDT 24 103265084 ps
T1080 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1718502072 Aug 13 04:28:41 PM PDT 24 Aug 13 04:28:43 PM PDT 24 262850797 ps
T1081 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1293820676 Aug 13 04:29:17 PM PDT 24 Aug 13 04:29:18 PM PDT 24 14044591 ps
T1082 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2382388186 Aug 13 04:29:04 PM PDT 24 Aug 13 04:29:10 PM PDT 24 43986383 ps
T1083 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2900798648 Aug 13 04:29:03 PM PDT 24 Aug 13 04:29:04 PM PDT 24 19628335 ps
T1084 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2469332482 Aug 13 04:28:56 PM PDT 24 Aug 13 04:29:07 PM PDT 24 186259854 ps
T1085 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1706248194 Aug 13 04:29:14 PM PDT 24 Aug 13 04:29:15 PM PDT 24 33398938 ps
T1086 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1250520350 Aug 13 04:28:55 PM PDT 24 Aug 13 04:28:59 PM PDT 24 65633734 ps
T1087 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1633377093 Aug 13 04:29:02 PM PDT 24 Aug 13 04:29:03 PM PDT 24 17843663 ps
T1088 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1931072604 Aug 13 04:29:11 PM PDT 24 Aug 13 04:29:13 PM PDT 24 55173101 ps
T1089 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2209482209 Aug 13 04:29:12 PM PDT 24 Aug 13 04:29:13 PM PDT 24 26396376 ps
T255 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3178123846 Aug 13 04:29:18 PM PDT 24 Aug 13 04:29:42 PM PDT 24 1681519576 ps
T1090 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1295791449 Aug 13 04:29:03 PM PDT 24 Aug 13 04:29:22 PM PDT 24 293326060 ps
T1091 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.330875272 Aug 13 04:28:48 PM PDT 24 Aug 13 04:28:48 PM PDT 24 12163053 ps
T1092 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3174734991 Aug 13 04:29:10 PM PDT 24 Aug 13 04:29:10 PM PDT 24 16662244 ps
T1093 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.266580788 Aug 13 04:28:44 PM PDT 24 Aug 13 04:28:58 PM PDT 24 928120643 ps
T1094 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3238817421 Aug 13 04:28:55 PM PDT 24 Aug 13 04:28:57 PM PDT 24 49876373 ps
T1095 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3061211847 Aug 13 04:29:12 PM PDT 24 Aug 13 04:29:13 PM PDT 24 58451460 ps
T1096 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1245963318 Aug 13 04:29:07 PM PDT 24 Aug 13 04:29:12 PM PDT 24 60169182 ps
T1097 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3344450 Aug 13 04:28:56 PM PDT 24 Aug 13 04:28:59 PM PDT 24 41631574 ps
T1098 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.461115422 Aug 13 04:29:01 PM PDT 24 Aug 13 04:29:03 PM PDT 24 313413974 ps
T1099 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2411354967 Aug 13 04:28:52 PM PDT 24 Aug 13 04:28:54 PM PDT 24 67219411 ps
T1100 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2006057132 Aug 13 04:29:24 PM PDT 24 Aug 13 04:29:25 PM PDT 24 14366390 ps
T1101 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4057468668 Aug 13 04:29:51 PM PDT 24 Aug 13 04:29:58 PM PDT 24 84894336 ps
T1102 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2473929461 Aug 13 04:29:11 PM PDT 24 Aug 13 04:29:14 PM PDT 24 209461396 ps
T1103 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.844258138 Aug 13 04:28:59 PM PDT 24 Aug 13 04:29:00 PM PDT 24 49998862 ps
T1104 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.346359463 Aug 13 04:28:52 PM PDT 24 Aug 13 04:28:54 PM PDT 24 107980469 ps
T1105 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3572854976 Aug 13 04:29:13 PM PDT 24 Aug 13 04:29:15 PM PDT 24 192476398 ps
T1106 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2666080955 Aug 13 04:29:18 PM PDT 24 Aug 13 04:29:19 PM PDT 24 13508178 ps
T1107 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1310275333 Aug 13 04:29:07 PM PDT 24 Aug 13 04:29:07 PM PDT 24 48242179 ps
T1108 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.82851042 Aug 13 04:29:15 PM PDT 24 Aug 13 04:29:18 PM PDT 24 103627196 ps
T1109 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3067439824 Aug 13 04:29:03 PM PDT 24 Aug 13 04:29:08 PM PDT 24 24950924 ps
T1110 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.208360807 Aug 13 04:28:54 PM PDT 24 Aug 13 04:29:12 PM PDT 24 7026184915 ps
T1111 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1341736303 Aug 13 04:29:08 PM PDT 24 Aug 13 04:29:10 PM PDT 24 53012242 ps
T1112 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1273434219 Aug 13 04:29:14 PM PDT 24 Aug 13 04:29:16 PM PDT 24 393164982 ps
T1113 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1489268771 Aug 13 04:28:54 PM PDT 24 Aug 13 04:28:56 PM PDT 24 49416678 ps
T1114 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1473918382 Aug 13 04:29:25 PM PDT 24 Aug 13 04:29:26 PM PDT 24 17156334 ps
T1115 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3335592004 Aug 13 04:29:13 PM PDT 24 Aug 13 04:29:14 PM PDT 24 17240900 ps
T1116 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2724604338 Aug 13 04:29:40 PM PDT 24 Aug 13 04:29:42 PM PDT 24 87701914 ps
T1117 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3379845113 Aug 13 04:29:05 PM PDT 24 Aug 13 04:29:08 PM PDT 24 489755539 ps
T1118 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2889101516 Aug 13 04:28:59 PM PDT 24 Aug 13 04:29:04 PM PDT 24 403925631 ps
T1119 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1341745171 Aug 13 04:29:00 PM PDT 24 Aug 13 04:29:02 PM PDT 24 161980625 ps
T1120 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.393357275 Aug 13 04:28:50 PM PDT 24 Aug 13 04:28:51 PM PDT 24 18004914 ps
T1121 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3670659440 Aug 13 04:29:21 PM PDT 24 Aug 13 04:29:22 PM PDT 24 10895219 ps
T1122 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3152195679 Aug 13 04:28:57 PM PDT 24 Aug 13 04:28:58 PM PDT 24 13598348 ps
T254 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1756630882 Aug 13 04:29:17 PM PDT 24 Aug 13 04:29:25 PM PDT 24 776924065 ps
T1123 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.55443270 Aug 13 04:29:06 PM PDT 24 Aug 13 04:29:07 PM PDT 24 13135299 ps
T1124 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1219432084 Aug 13 04:28:55 PM PDT 24 Aug 13 04:29:00 PM PDT 24 860596979 ps
T1125 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.754387813 Aug 13 04:29:05 PM PDT 24 Aug 13 04:29:06 PM PDT 24 18972813 ps
T1126 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3460976302 Aug 13 04:29:09 PM PDT 24 Aug 13 04:29:11 PM PDT 24 302885875 ps
T1127 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2045627791 Aug 13 04:29:01 PM PDT 24 Aug 13 04:29:02 PM PDT 24 65349605 ps
T1128 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4242438935 Aug 13 04:29:10 PM PDT 24 Aug 13 04:29:11 PM PDT 24 34347521 ps
T1129 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.388870242 Aug 13 04:29:15 PM PDT 24 Aug 13 04:29:19 PM PDT 24 207774959 ps
T1130 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.479544300 Aug 13 04:28:58 PM PDT 24 Aug 13 04:29:00 PM PDT 24 312844847 ps
T1131 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3280035841 Aug 13 04:29:11 PM PDT 24 Aug 13 04:29:20 PM PDT 24 704407090 ps

Test location /workspace/coverage/default/30.spi_device_flash_all.647532258
Short name T6
Test name
Test status
Simulation time 23329492483 ps
CPU time 20.62 seconds
Started Aug 13 04:32:17 PM PDT 24
Finished Aug 13 04:32:38 PM PDT 24
Peak memory 241784 kb
Host smart-23e3202f-bb2e-40ce-8394-0c553ae972be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647532258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.647532258
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.819445247
Short name T13
Test name
Test status
Simulation time 15438311033 ps
CPU time 57.33 seconds
Started Aug 13 04:32:33 PM PDT 24
Finished Aug 13 04:33:31 PM PDT 24
Peak memory 241928 kb
Host smart-0bb06d96-de23-4a7f-ba10-33f4aa5c3139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819445247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.819445247
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1380401086
Short name T37
Test name
Test status
Simulation time 19819258273 ps
CPU time 87.39 seconds
Started Aug 13 04:32:47 PM PDT 24
Finished Aug 13 04:34:15 PM PDT 24
Peak memory 258048 kb
Host smart-dc559bec-ff81-4d5a-8dcb-eaa36ecfac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380401086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1380401086
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.621063728
Short name T20
Test name
Test status
Simulation time 23359211760 ps
CPU time 295.19 seconds
Started Aug 13 04:32:45 PM PDT 24
Finished Aug 13 04:37:41 PM PDT 24
Peak memory 265048 kb
Host smart-0960d5fa-985e-4c96-a8bd-524a5c8ceddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621063728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.621063728
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2793613815
Short name T97
Test name
Test status
Simulation time 1165390937 ps
CPU time 23.17 seconds
Started Aug 13 04:28:56 PM PDT 24
Finished Aug 13 04:29:19 PM PDT 24
Peak memory 215120 kb
Host smart-fd11d8df-ca39-4513-93d9-cc7b9525170d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793613815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2793613815
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2265811998
Short name T19
Test name
Test status
Simulation time 117153348313 ps
CPU time 278.84 seconds
Started Aug 13 04:32:33 PM PDT 24
Finished Aug 13 04:37:11 PM PDT 24
Peak memory 248872 kb
Host smart-fc921bae-6766-400d-b0b1-fdfbcc8337fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265811998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2265811998
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1426284208
Short name T23
Test name
Test status
Simulation time 89173336773 ps
CPU time 299.07 seconds
Started Aug 13 04:31:26 PM PDT 24
Finished Aug 13 04:36:26 PM PDT 24
Peak memory 282852 kb
Host smart-2da38774-98f5-4062-85a9-f6d0bff8b3f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426284208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1426284208
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2798653616
Short name T71
Test name
Test status
Simulation time 52619876 ps
CPU time 0.69 seconds
Started Aug 13 04:30:32 PM PDT 24
Finished Aug 13 04:30:33 PM PDT 24
Peak memory 216704 kb
Host smart-8223c9ef-835e-4a30-a7ec-b6a35db1f8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798653616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2798653616
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.4086820896
Short name T33
Test name
Test status
Simulation time 284960199302 ps
CPU time 693.39 seconds
Started Aug 13 04:32:28 PM PDT 24
Finished Aug 13 04:44:02 PM PDT 24
Peak memory 273820 kb
Host smart-668d68a8-eea1-4393-9cc4-0e807c76494b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086820896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.4086820896
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2355720567
Short name T172
Test name
Test status
Simulation time 115775820779 ps
CPU time 254.27 seconds
Started Aug 13 04:31:49 PM PDT 24
Finished Aug 13 04:36:04 PM PDT 24
Peak memory 253236 kb
Host smart-b60e5d77-4efc-45e7-afb7-97cdb74e9116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355720567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2355720567
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2508246725
Short name T53
Test name
Test status
Simulation time 200322406506 ps
CPU time 548.69 seconds
Started Aug 13 04:30:56 PM PDT 24
Finished Aug 13 04:40:05 PM PDT 24
Peak memory 266128 kb
Host smart-75a89c29-68d6-4e19-9532-da6d3d5256d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508246725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2508246725
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3861858895
Short name T101
Test name
Test status
Simulation time 76099109 ps
CPU time 2.47 seconds
Started Aug 13 04:29:05 PM PDT 24
Finished Aug 13 04:29:08 PM PDT 24
Peak memory 215300 kb
Host smart-64a4c346-468d-4569-971f-6c1475e48d52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861858895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3861858895
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.110908566
Short name T209
Test name
Test status
Simulation time 101228970087 ps
CPU time 571.69 seconds
Started Aug 13 04:30:52 PM PDT 24
Finished Aug 13 04:40:24 PM PDT 24
Peak memory 290492 kb
Host smart-e749944f-4882-40e4-b7fa-0c689c5a46d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110908566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.110908566
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2113525831
Short name T24
Test name
Test status
Simulation time 67988323 ps
CPU time 1.14 seconds
Started Aug 13 04:30:56 PM PDT 24
Finished Aug 13 04:30:57 PM PDT 24
Peak memory 236596 kb
Host smart-adafa104-265f-4f4a-9fd8-91f2b66636ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113525831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2113525831
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2592115378
Short name T123
Test name
Test status
Simulation time 30069856906 ps
CPU time 124.76 seconds
Started Aug 13 04:31:30 PM PDT 24
Finished Aug 13 04:33:35 PM PDT 24
Peak memory 266192 kb
Host smart-218bc67e-a323-4876-a4a8-0d7a8571068d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592115378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2592115378
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.981010271
Short name T17
Test name
Test status
Simulation time 2678296886 ps
CPU time 21.39 seconds
Started Aug 13 04:33:07 PM PDT 24
Finished Aug 13 04:33:29 PM PDT 24
Peak memory 225368 kb
Host smart-e5bfb9b5-9de8-4f8d-951b-3244ce2213c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981010271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.981010271
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.696868990
Short name T235
Test name
Test status
Simulation time 147696827097 ps
CPU time 716.25 seconds
Started Aug 13 04:30:54 PM PDT 24
Finished Aug 13 04:42:50 PM PDT 24
Peak memory 258184 kb
Host smart-369834ce-c968-40b0-b97b-9e3c23467050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696868990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.696868990
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1117609809
Short name T21
Test name
Test status
Simulation time 79275287417 ps
CPU time 711.78 seconds
Started Aug 13 04:32:43 PM PDT 24
Finished Aug 13 04:44:35 PM PDT 24
Peak memory 274576 kb
Host smart-30f855d7-9597-44a3-b7c4-4f4d6189577f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117609809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1117609809
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.938241967
Short name T52
Test name
Test status
Simulation time 89588571151 ps
CPU time 203.6 seconds
Started Aug 13 04:31:53 PM PDT 24
Finished Aug 13 04:35:17 PM PDT 24
Peak memory 265428 kb
Host smart-72494b47-3a6d-407a-b1d9-22199372e54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938241967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.938241967
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2417669746
Short name T115
Test name
Test status
Simulation time 37568109 ps
CPU time 1.4 seconds
Started Aug 13 04:29:00 PM PDT 24
Finished Aug 13 04:29:02 PM PDT 24
Peak memory 214876 kb
Host smart-fd5fa2d6-c177-4882-b633-ce31bdf312a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417669746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2417669746
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1582110326
Short name T171
Test name
Test status
Simulation time 208031218538 ps
CPU time 332.23 seconds
Started Aug 13 04:31:27 PM PDT 24
Finished Aug 13 04:36:59 PM PDT 24
Peak memory 258296 kb
Host smart-2c86ef90-6a33-4fd3-a6ef-3473fbbbf8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582110326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1582110326
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1827593826
Short name T175
Test name
Test status
Simulation time 3302262343 ps
CPU time 72.55 seconds
Started Aug 13 04:31:21 PM PDT 24
Finished Aug 13 04:32:34 PM PDT 24
Peak memory 266356 kb
Host smart-0c171088-028a-46a4-98ad-659d9b8e35cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827593826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1827593826
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1555661431
Short name T250
Test name
Test status
Simulation time 73581667580 ps
CPU time 344.33 seconds
Started Aug 13 04:32:27 PM PDT 24
Finished Aug 13 04:38:11 PM PDT 24
Peak memory 267540 kb
Host smart-b5d9d64a-c7ee-4851-981a-ee2a4b2186d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555661431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1555661431
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.918278524
Short name T240
Test name
Test status
Simulation time 53233815906 ps
CPU time 446.26 seconds
Started Aug 13 04:32:14 PM PDT 24
Finished Aug 13 04:39:40 PM PDT 24
Peak memory 255264 kb
Host smart-23a80a85-abfb-490d-a232-71aed4b5debe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918278524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.918278524
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1004250382
Short name T49
Test name
Test status
Simulation time 266720564265 ps
CPU time 225.41 seconds
Started Aug 13 04:33:13 PM PDT 24
Finished Aug 13 04:36:58 PM PDT 24
Peak memory 263380 kb
Host smart-dbeb4748-396e-4f78-92b9-ef2176ab99f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004250382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1004250382
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2283967356
Short name T41
Test name
Test status
Simulation time 4119888504 ps
CPU time 96.74 seconds
Started Aug 13 04:32:04 PM PDT 24
Finished Aug 13 04:33:41 PM PDT 24
Peak memory 255516 kb
Host smart-e1333920-d95a-457f-8bdd-160ad750c53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283967356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2283967356
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1332019313
Short name T91
Test name
Test status
Simulation time 9249438821 ps
CPU time 15.55 seconds
Started Aug 13 04:31:37 PM PDT 24
Finished Aug 13 04:31:53 PM PDT 24
Peak memory 217136 kb
Host smart-d3b4a5a9-1b15-4118-ae52-be38e82d029b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332019313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1332019313
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2346410556
Short name T192
Test name
Test status
Simulation time 3477062614 ps
CPU time 88.58 seconds
Started Aug 13 04:32:23 PM PDT 24
Finished Aug 13 04:33:51 PM PDT 24
Peak memory 266488 kb
Host smart-1113c809-9578-4a61-934c-89524bdbdba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346410556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2346410556
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3838329088
Short name T77
Test name
Test status
Simulation time 39393985 ps
CPU time 0.75 seconds
Started Aug 13 04:30:46 PM PDT 24
Finished Aug 13 04:30:47 PM PDT 24
Peak memory 206128 kb
Host smart-7e123ac2-5554-4822-bd9b-42fc9769296a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838329088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
838329088
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1932973252
Short name T291
Test name
Test status
Simulation time 12429978191 ps
CPU time 41.93 seconds
Started Aug 13 04:31:28 PM PDT 24
Finished Aug 13 04:32:10 PM PDT 24
Peak memory 225324 kb
Host smart-992fdf5b-f932-471a-885b-514ef12d2c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932973252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1932973252
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.807875573
Short name T219
Test name
Test status
Simulation time 729844038673 ps
CPU time 825.11 seconds
Started Aug 13 04:30:58 PM PDT 24
Finished Aug 13 04:44:43 PM PDT 24
Peak memory 272960 kb
Host smart-b4f0f206-c50d-4ac9-a18f-da1acfc17687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807875573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.807875573
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3141004290
Short name T56
Test name
Test status
Simulation time 3673265121 ps
CPU time 75.4 seconds
Started Aug 13 04:31:06 PM PDT 24
Finished Aug 13 04:32:21 PM PDT 24
Peak memory 255984 kb
Host smart-7b5986b0-466d-4333-b031-054f9bd5e4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141004290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3141004290
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.159892412
Short name T253
Test name
Test status
Simulation time 1110760867 ps
CPU time 17.11 seconds
Started Aug 13 04:28:57 PM PDT 24
Finished Aug 13 04:29:14 PM PDT 24
Peak memory 215300 kb
Host smart-9fe730ee-f842-4b6c-b335-bb0878ff036b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159892412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.159892412
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1773785498
Short name T35
Test name
Test status
Simulation time 115191966893 ps
CPU time 546.81 seconds
Started Aug 13 04:31:06 PM PDT 24
Finished Aug 13 04:40:13 PM PDT 24
Peak memory 263796 kb
Host smart-7362f89b-3317-4366-b9bd-1a9bd57e5775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773785498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1773785498
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.762790920
Short name T102
Test name
Test status
Simulation time 136147994 ps
CPU time 2.08 seconds
Started Aug 13 04:28:57 PM PDT 24
Finished Aug 13 04:28:59 PM PDT 24
Peak memory 215120 kb
Host smart-8f1d01c8-98f2-434f-8788-bd7e11034fb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762790920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.762790920
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2859160119
Short name T129
Test name
Test status
Simulation time 16971285424 ps
CPU time 214.32 seconds
Started Aug 13 04:30:50 PM PDT 24
Finished Aug 13 04:34:24 PM PDT 24
Peak memory 254168 kb
Host smart-ff9f8216-e677-49a1-b090-dcbebc71b660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859160119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2859160119
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.4214848371
Short name T1000
Test name
Test status
Simulation time 10206082408 ps
CPU time 127.03 seconds
Started Aug 13 04:31:30 PM PDT 24
Finished Aug 13 04:33:37 PM PDT 24
Peak memory 266068 kb
Host smart-e8860355-086a-4116-83ed-ebe8faa47e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214848371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.4214848371
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.475783980
Short name T218
Test name
Test status
Simulation time 53557636429 ps
CPU time 347.06 seconds
Started Aug 13 04:32:52 PM PDT 24
Finished Aug 13 04:38:39 PM PDT 24
Peak memory 258284 kb
Host smart-0ff9e9dc-f0a4-48e3-995f-b00054f6340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475783980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.475783980
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.454037841
Short name T92
Test name
Test status
Simulation time 11089959409 ps
CPU time 27.01 seconds
Started Aug 13 04:32:59 PM PDT 24
Finished Aug 13 04:33:26 PM PDT 24
Peak memory 233536 kb
Host smart-dad97256-1f97-4aba-b782-4dd24b71b3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454037841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.454037841
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3537420214
Short name T264
Test name
Test status
Simulation time 176188354169 ps
CPU time 64.67 seconds
Started Aug 13 04:31:26 PM PDT 24
Finished Aug 13 04:32:31 PM PDT 24
Peak memory 233608 kb
Host smart-b372f86a-dd0a-4faa-802d-ff7e35215dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537420214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3537420214
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3094954253
Short name T140
Test name
Test status
Simulation time 399066894 ps
CPU time 5.26 seconds
Started Aug 13 04:30:44 PM PDT 24
Finished Aug 13 04:30:49 PM PDT 24
Peak memory 221612 kb
Host smart-bba85cef-1299-4bf7-9340-b18bfc1263c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3094954253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3094954253
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1250520350
Short name T1086
Test name
Test status
Simulation time 65633734 ps
CPU time 4.01 seconds
Started Aug 13 04:28:55 PM PDT 24
Finished Aug 13 04:28:59 PM PDT 24
Peak memory 215136 kb
Host smart-a0b04b7b-246e-4437-9873-5b6033c9468c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250520350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1250520350
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1542326285
Short name T147
Test name
Test status
Simulation time 326306139 ps
CPU time 7.43 seconds
Started Aug 13 04:28:50 PM PDT 24
Finished Aug 13 04:28:57 PM PDT 24
Peak memory 215008 kb
Host smart-a4120299-f5ba-4aee-8fee-49a6cdb482a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542326285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1542326285
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2184655180
Short name T256
Test name
Test status
Simulation time 553397498 ps
CPU time 17.95 seconds
Started Aug 13 04:28:40 PM PDT 24
Finished Aug 13 04:28:58 PM PDT 24
Peak memory 214980 kb
Host smart-4aa8314c-3e80-47c8-b228-0a4865d2fd97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184655180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2184655180
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2080546229
Short name T239
Test name
Test status
Simulation time 12236933759 ps
CPU time 82.65 seconds
Started Aug 13 04:31:16 PM PDT 24
Finished Aug 13 04:32:39 PM PDT 24
Peak memory 257980 kb
Host smart-c5d9653d-842b-4fd0-985b-9185984f82a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080546229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2080546229
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2616259555
Short name T300
Test name
Test status
Simulation time 8340129293 ps
CPU time 43.22 seconds
Started Aug 13 04:31:12 PM PDT 24
Finished Aug 13 04:31:56 PM PDT 24
Peak memory 220980 kb
Host smart-eb80db7b-91fa-4bc1-9f90-e5772fb73364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616259555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2616259555
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3702309670
Short name T293
Test name
Test status
Simulation time 2805667651 ps
CPU time 10.1 seconds
Started Aug 13 04:31:22 PM PDT 24
Finished Aug 13 04:31:33 PM PDT 24
Peak memory 233668 kb
Host smart-8114eb71-4653-4a4a-a96a-1c2803849a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702309670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3702309670
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4211477141
Short name T246
Test name
Test status
Simulation time 28739669504 ps
CPU time 266.76 seconds
Started Aug 13 04:31:44 PM PDT 24
Finished Aug 13 04:36:11 PM PDT 24
Peak memory 261688 kb
Host smart-185b54b8-d90b-456a-9163-759992450b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211477141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.4211477141
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1685627081
Short name T237
Test name
Test status
Simulation time 200345406781 ps
CPU time 489.24 seconds
Started Aug 13 04:31:49 PM PDT 24
Finished Aug 13 04:39:58 PM PDT 24
Peak memory 285964 kb
Host smart-dec8bf5b-1c99-45c5-8ff0-092a1e972210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685627081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1685627081
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1182251182
Short name T9
Test name
Test status
Simulation time 490050517 ps
CPU time 4.59 seconds
Started Aug 13 04:31:45 PM PDT 24
Finished Aug 13 04:31:50 PM PDT 24
Peak memory 225284 kb
Host smart-a1147f4e-90db-4227-ab10-fe817f4c2d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182251182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1182251182
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3668402944
Short name T260
Test name
Test status
Simulation time 1079179052 ps
CPU time 11.76 seconds
Started Aug 13 04:30:49 PM PDT 24
Finished Aug 13 04:31:01 PM PDT 24
Peak memory 233392 kb
Host smart-06a6cec5-6f8a-4476-b848-8f1a56f05518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668402944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3668402944
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3723865133
Short name T233
Test name
Test status
Simulation time 144987742385 ps
CPU time 392.8 seconds
Started Aug 13 04:32:40 PM PDT 24
Finished Aug 13 04:39:13 PM PDT 24
Peak memory 258212 kb
Host smart-c4a50259-d4aa-44b6-9113-e390c2e2df6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723865133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3723865133
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1149672582
Short name T229
Test name
Test status
Simulation time 19248541266 ps
CPU time 149.68 seconds
Started Aug 13 04:32:38 PM PDT 24
Finished Aug 13 04:35:08 PM PDT 24
Peak memory 257528 kb
Host smart-bfba4dd2-3e51-4801-b0f9-d234c0bc92b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149672582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1149672582
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2598511528
Short name T87
Test name
Test status
Simulation time 86628474 ps
CPU time 1.12 seconds
Started Aug 13 04:28:48 PM PDT 24
Finished Aug 13 04:28:50 PM PDT 24
Peak memory 206764 kb
Host smart-f3803d22-1a52-4280-bd34-0ddcfeba96dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598511528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2598511528
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3465005234
Short name T110
Test name
Test status
Simulation time 1868209187 ps
CPU time 21.04 seconds
Started Aug 13 04:28:49 PM PDT 24
Finished Aug 13 04:29:10 PM PDT 24
Peak memory 206680 kb
Host smart-19d088dd-2b8e-4514-9bd8-4a716d664343
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465005234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3465005234
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2737242857
Short name T1009
Test name
Test status
Simulation time 707174047 ps
CPU time 23.17 seconds
Started Aug 13 04:28:49 PM PDT 24
Finished Aug 13 04:29:12 PM PDT 24
Peak memory 215016 kb
Host smart-e844cb6f-0fc8-4d3a-a5e4-63c6539e49b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737242857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2737242857
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2999614480
Short name T1032
Test name
Test status
Simulation time 54807621 ps
CPU time 1.66 seconds
Started Aug 13 04:28:58 PM PDT 24
Finished Aug 13 04:29:00 PM PDT 24
Peak memory 215128 kb
Host smart-7fcf273f-d757-4a18-b07e-f7d0d64bc9db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999614480 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2999614480
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.231590772
Short name T121
Test name
Test status
Simulation time 94052828 ps
CPU time 1.51 seconds
Started Aug 13 04:28:48 PM PDT 24
Finished Aug 13 04:28:50 PM PDT 24
Peak memory 215016 kb
Host smart-de8f448a-57cc-439d-82b1-aa9908bbd323
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231590772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.231590772
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2461611281
Short name T1024
Test name
Test status
Simulation time 17239233 ps
CPU time 0.73 seconds
Started Aug 13 04:29:00 PM PDT 24
Finished Aug 13 04:29:01 PM PDT 24
Peak memory 204012 kb
Host smart-a9627d12-9418-4d33-a971-e7d5223164a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461611281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
461611281
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.479544300
Short name T1130
Test name
Test status
Simulation time 312844847 ps
CPU time 1.72 seconds
Started Aug 13 04:28:58 PM PDT 24
Finished Aug 13 04:29:00 PM PDT 24
Peak memory 215016 kb
Host smart-2b825e48-f182-4cd6-ac06-ee0f33d82756
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479544300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.479544300
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3027507336
Short name T1039
Test name
Test status
Simulation time 12753196 ps
CPU time 0.65 seconds
Started Aug 13 04:28:40 PM PDT 24
Finished Aug 13 04:28:40 PM PDT 24
Peak memory 203792 kb
Host smart-dba23cc5-7b82-4a0a-a464-c2b6428b30c6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027507336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3027507336
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1489268771
Short name T1113
Test name
Test status
Simulation time 49416678 ps
CPU time 1.56 seconds
Started Aug 13 04:28:54 PM PDT 24
Finished Aug 13 04:28:56 PM PDT 24
Peak memory 214856 kb
Host smart-393362c9-438f-4814-818a-142acc8f39ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489268771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1489268771
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.388336665
Short name T1068
Test name
Test status
Simulation time 955361896 ps
CPU time 23.07 seconds
Started Aug 13 04:28:55 PM PDT 24
Finished Aug 13 04:29:18 PM PDT 24
Peak memory 215000 kb
Host smart-025ec999-c7fe-43e8-ac21-40522de00629
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388336665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.388336665
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.881592769
Short name T1066
Test name
Test status
Simulation time 363199504 ps
CPU time 22.6 seconds
Started Aug 13 04:29:04 PM PDT 24
Finished Aug 13 04:29:27 PM PDT 24
Peak memory 206756 kb
Host smart-c175264c-3830-4d52-8827-2dc95d35523a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881592769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.881592769
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3089730579
Short name T86
Test name
Test status
Simulation time 57911176 ps
CPU time 1.13 seconds
Started Aug 13 04:28:56 PM PDT 24
Finished Aug 13 04:28:58 PM PDT 24
Peak memory 206904 kb
Host smart-388f0ba6-4b70-43ec-86a7-8ba369df2aff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089730579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3089730579
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2828828984
Short name T109
Test name
Test status
Simulation time 211524047 ps
CPU time 3.54 seconds
Started Aug 13 04:28:47 PM PDT 24
Finished Aug 13 04:28:50 PM PDT 24
Peak memory 217036 kb
Host smart-bc6a0078-85d4-4ad7-b60d-fb639eb0873b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828828984 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2828828984
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.470053781
Short name T1073
Test name
Test status
Simulation time 31294087 ps
CPU time 2 seconds
Started Aug 13 04:29:05 PM PDT 24
Finished Aug 13 04:29:07 PM PDT 24
Peak memory 214912 kb
Host smart-238c18a7-9f19-4df8-bfc2-50c76d2a9eaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470053781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.470053781
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3325247331
Short name T1037
Test name
Test status
Simulation time 10928555 ps
CPU time 0.72 seconds
Started Aug 13 04:29:09 PM PDT 24
Finished Aug 13 04:29:10 PM PDT 24
Peak memory 203564 kb
Host smart-f980061d-6c22-4f85-b4cd-f0f73ce4ac30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325247331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
325247331
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.24738527
Short name T1078
Test name
Test status
Simulation time 231614331 ps
CPU time 1.61 seconds
Started Aug 13 04:28:52 PM PDT 24
Finished Aug 13 04:28:53 PM PDT 24
Peak memory 215384 kb
Host smart-8cec3ce5-f460-4a4a-9c18-cad27bf51823
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24738527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_d
evice_mem_partial_access.24738527
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.680716184
Short name T1022
Test name
Test status
Simulation time 16141063 ps
CPU time 0.7 seconds
Started Aug 13 04:29:13 PM PDT 24
Finished Aug 13 04:29:13 PM PDT 24
Peak memory 203744 kb
Host smart-05208d7b-0a06-47da-9152-eaf87108a0cb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680716184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.680716184
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3344450
Short name T1097
Test name
Test status
Simulation time 41631574 ps
CPU time 2.71 seconds
Started Aug 13 04:28:56 PM PDT 24
Finished Aug 13 04:28:59 PM PDT 24
Peak memory 214928 kb
Host smart-35fb4d58-f7c1-4f87-98f8-4cbb5f8ba7a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_same_csr_outstanding.3344450
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.828211617
Short name T1079
Test name
Test status
Simulation time 103265084 ps
CPU time 2.74 seconds
Started Aug 13 04:28:54 PM PDT 24
Finished Aug 13 04:28:57 PM PDT 24
Peak memory 215164 kb
Host smart-a91fead9-4e19-4a31-8c3b-2b2e1aad6db9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828211617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.828211617
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1245963318
Short name T1096
Test name
Test status
Simulation time 60169182 ps
CPU time 3.92 seconds
Started Aug 13 04:29:07 PM PDT 24
Finished Aug 13 04:29:12 PM PDT 24
Peak memory 216688 kb
Host smart-022e2a9f-cdeb-4328-9cf5-dca2185e0266
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245963318 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1245963318
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1412006577
Short name T166
Test name
Test status
Simulation time 198842790 ps
CPU time 2.61 seconds
Started Aug 13 04:29:20 PM PDT 24
Finished Aug 13 04:29:23 PM PDT 24
Peak memory 214960 kb
Host smart-65ae80c4-b8bf-4e23-b7ec-38da75ad5cd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412006577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1412006577
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1068708685
Short name T1017
Test name
Test status
Simulation time 54015070 ps
CPU time 0.75 seconds
Started Aug 13 04:28:50 PM PDT 24
Finished Aug 13 04:28:51 PM PDT 24
Peak memory 203908 kb
Host smart-86cdc6a2-9284-4f4c-b49d-6ec099e9c62d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068708685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1068708685
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.766173831
Short name T1035
Test name
Test status
Simulation time 162571931 ps
CPU time 4.23 seconds
Started Aug 13 04:29:24 PM PDT 24
Finished Aug 13 04:29:28 PM PDT 24
Peak memory 213876 kb
Host smart-0cedb86e-d4cd-4e86-bda7-df0caea0e513
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766173831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.766173831
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2765666252
Short name T105
Test name
Test status
Simulation time 585485211 ps
CPU time 3.62 seconds
Started Aug 13 04:28:56 PM PDT 24
Finished Aug 13 04:29:00 PM PDT 24
Peak memory 215152 kb
Host smart-2584de99-8871-4201-8a92-3f38b7feb692
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765666252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2765666252
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3707590852
Short name T99
Test name
Test status
Simulation time 261658593 ps
CPU time 11.49 seconds
Started Aug 13 04:28:57 PM PDT 24
Finished Aug 13 04:29:09 PM PDT 24
Peak memory 215876 kb
Host smart-6243c2e8-c567-4533-9598-e06c28c3f3ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707590852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3707590852
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1870686959
Short name T68
Test name
Test status
Simulation time 69935884 ps
CPU time 2.76 seconds
Started Aug 13 04:29:11 PM PDT 24
Finished Aug 13 04:29:14 PM PDT 24
Peak memory 217724 kb
Host smart-7bc4ecb3-cefe-4ee5-a2c5-42995ae691ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870686959 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1870686959
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3335592004
Short name T1115
Test name
Test status
Simulation time 17240900 ps
CPU time 0.75 seconds
Started Aug 13 04:29:13 PM PDT 24
Finished Aug 13 04:29:14 PM PDT 24
Peak memory 203600 kb
Host smart-fe69051b-bd85-4f37-8334-ff112af6d677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335592004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3335592004
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3460976302
Short name T1126
Test name
Test status
Simulation time 302885875 ps
CPU time 1.91 seconds
Started Aug 13 04:29:09 PM PDT 24
Finished Aug 13 04:29:11 PM PDT 24
Peak memory 214984 kb
Host smart-de47f604-da5f-4fda-8920-ff416333be00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460976302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3460976302
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1395283195
Short name T251
Test name
Test status
Simulation time 33051715 ps
CPU time 1.82 seconds
Started Aug 13 04:29:50 PM PDT 24
Finished Aug 13 04:29:52 PM PDT 24
Peak memory 215124 kb
Host smart-0620e8e8-9c6a-4ba5-91b9-12f558dc2595
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395283195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1395283195
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1315425355
Short name T100
Test name
Test status
Simulation time 3248562157 ps
CPU time 20.61 seconds
Started Aug 13 04:29:13 PM PDT 24
Finished Aug 13 04:29:34 PM PDT 24
Peak memory 216568 kb
Host smart-42f93bcd-c8cd-4e3f-8429-9fc871594d0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315425355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1315425355
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1273434219
Short name T1112
Test name
Test status
Simulation time 393164982 ps
CPU time 2.56 seconds
Started Aug 13 04:29:14 PM PDT 24
Finished Aug 13 04:29:16 PM PDT 24
Peak memory 217740 kb
Host smart-e4f78481-6413-4a78-ae22-907e46d1901d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273434219 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1273434219
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2724604338
Short name T1116
Test name
Test status
Simulation time 87701914 ps
CPU time 2.36 seconds
Started Aug 13 04:29:40 PM PDT 24
Finished Aug 13 04:29:42 PM PDT 24
Peak memory 214940 kb
Host smart-d471b143-cad0-4df4-9d31-753b6ab14beb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724604338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2724604338
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2045627791
Short name T1127
Test name
Test status
Simulation time 65349605 ps
CPU time 0.7 seconds
Started Aug 13 04:29:01 PM PDT 24
Finished Aug 13 04:29:02 PM PDT 24
Peak memory 203620 kb
Host smart-757ec286-8438-44e9-a8d3-33754dfb20a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045627791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2045627791
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3170085685
Short name T1064
Test name
Test status
Simulation time 491789872 ps
CPU time 1.83 seconds
Started Aug 13 04:29:02 PM PDT 24
Finished Aug 13 04:29:04 PM PDT 24
Peak memory 214920 kb
Host smart-4a26e5d7-cefe-4afc-bc53-29cf37942f88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170085685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3170085685
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2612824481
Short name T106
Test name
Test status
Simulation time 201833604 ps
CPU time 4.53 seconds
Started Aug 13 04:28:57 PM PDT 24
Finished Aug 13 04:29:01 PM PDT 24
Peak memory 216316 kb
Host smart-35d67c13-8a11-4ab1-814f-89b37c778459
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612824481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2612824481
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3379845113
Short name T1117
Test name
Test status
Simulation time 489755539 ps
CPU time 2.86 seconds
Started Aug 13 04:29:05 PM PDT 24
Finished Aug 13 04:29:08 PM PDT 24
Peak memory 216424 kb
Host smart-a927a322-9c02-4720-ab8a-b8c28cfaf452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379845113 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3379845113
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1084945596
Short name T114
Test name
Test status
Simulation time 92237520 ps
CPU time 2.62 seconds
Started Aug 13 04:28:57 PM PDT 24
Finished Aug 13 04:29:00 PM PDT 24
Peak memory 214900 kb
Host smart-9cd89251-cff6-46e1-9bce-a2b8db8084a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084945596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1084945596
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4061943449
Short name T1074
Test name
Test status
Simulation time 19331092 ps
CPU time 0.69 seconds
Started Aug 13 04:29:05 PM PDT 24
Finished Aug 13 04:29:06 PM PDT 24
Peak memory 203712 kb
Host smart-de36e3e1-b4e2-4792-99c6-564e12c42fc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061943449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
4061943449
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.186090076
Short name T1047
Test name
Test status
Simulation time 108574281 ps
CPU time 2.8 seconds
Started Aug 13 04:29:04 PM PDT 24
Finished Aug 13 04:29:07 PM PDT 24
Peak memory 215068 kb
Host smart-6b65e5a5-a4b9-486d-81d7-1107aa3033e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186090076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.186090076
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2473929461
Short name T1102
Test name
Test status
Simulation time 209461396 ps
CPU time 2.78 seconds
Started Aug 13 04:29:11 PM PDT 24
Finished Aug 13 04:29:14 PM PDT 24
Peak memory 215132 kb
Host smart-49cf0dce-0c47-4c4d-8893-9ef52a1ef612
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473929461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2473929461
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1580310864
Short name T145
Test name
Test status
Simulation time 378777845 ps
CPU time 7.89 seconds
Started Aug 13 04:29:00 PM PDT 24
Finished Aug 13 04:29:08 PM PDT 24
Peak memory 214980 kb
Host smart-17ce1202-e149-47bb-a2b8-c9b264659348
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580310864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1580310864
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2603482225
Short name T1030
Test name
Test status
Simulation time 196397438 ps
CPU time 1.67 seconds
Started Aug 13 04:28:58 PM PDT 24
Finished Aug 13 04:28:59 PM PDT 24
Peak memory 215004 kb
Host smart-37487772-4625-4441-a8f1-3c80f36daf10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603482225 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2603482225
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1341736303
Short name T1111
Test name
Test status
Simulation time 53012242 ps
CPU time 1.65 seconds
Started Aug 13 04:29:08 PM PDT 24
Finished Aug 13 04:29:10 PM PDT 24
Peak memory 206824 kb
Host smart-ca1ab62b-9cda-40a3-a7f6-4c6ca0ab1304
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341736303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1341736303
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1633377093
Short name T1087
Test name
Test status
Simulation time 17843663 ps
CPU time 0.77 seconds
Started Aug 13 04:29:02 PM PDT 24
Finished Aug 13 04:29:03 PM PDT 24
Peak memory 203884 kb
Host smart-dbd64def-edce-4ba4-9ce0-84bbb702a356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633377093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1633377093
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.388870242
Short name T1129
Test name
Test status
Simulation time 207774959 ps
CPU time 4.35 seconds
Started Aug 13 04:29:15 PM PDT 24
Finished Aug 13 04:29:19 PM PDT 24
Peak memory 214904 kb
Host smart-c77742fb-8791-49f1-aedb-95a3d948f9d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388870242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.388870242
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.208360807
Short name T1110
Test name
Test status
Simulation time 7026184915 ps
CPU time 17.83 seconds
Started Aug 13 04:28:54 PM PDT 24
Finished Aug 13 04:29:12 PM PDT 24
Peak memory 215092 kb
Host smart-84906f75-792e-4841-aa9e-017960f1c93f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208360807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.208360807
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1228797965
Short name T1055
Test name
Test status
Simulation time 88232663 ps
CPU time 2.59 seconds
Started Aug 13 04:29:56 PM PDT 24
Finished Aug 13 04:29:59 PM PDT 24
Peak memory 216300 kb
Host smart-8d964671-f689-428e-a32c-bd3dba8a9610
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228797965 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1228797965
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2647358265
Short name T111
Test name
Test status
Simulation time 109238116 ps
CPU time 2.5 seconds
Started Aug 13 04:28:56 PM PDT 24
Finished Aug 13 04:28:58 PM PDT 24
Peak memory 206756 kb
Host smart-3811e5b2-ecd9-4418-b03a-5ee397b651f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647358265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2647358265
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1030331352
Short name T1075
Test name
Test status
Simulation time 40987227 ps
CPU time 0.69 seconds
Started Aug 13 04:29:08 PM PDT 24
Finished Aug 13 04:29:09 PM PDT 24
Peak memory 203724 kb
Host smart-a0076878-2553-4225-9a7f-60c533fc05bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030331352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1030331352
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3413198491
Short name T1067
Test name
Test status
Simulation time 383366905 ps
CPU time 4.25 seconds
Started Aug 13 04:29:54 PM PDT 24
Finished Aug 13 04:29:59 PM PDT 24
Peak memory 214888 kb
Host smart-bbcbe370-4954-4710-830c-bf7d83e865a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413198491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3413198491
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1295791449
Short name T1090
Test name
Test status
Simulation time 293326060 ps
CPU time 18.15 seconds
Started Aug 13 04:29:03 PM PDT 24
Finished Aug 13 04:29:22 PM PDT 24
Peak memory 215008 kb
Host smart-abd078cf-a1ee-452a-9146-65303442af42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295791449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1295791449
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1339471705
Short name T1063
Test name
Test status
Simulation time 61160969 ps
CPU time 1.67 seconds
Started Aug 13 04:29:10 PM PDT 24
Finished Aug 13 04:29:12 PM PDT 24
Peak memory 215140 kb
Host smart-42fd1eea-c466-4b23-ad91-17130d537547
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339471705 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1339471705
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4057468668
Short name T1101
Test name
Test status
Simulation time 84894336 ps
CPU time 1.93 seconds
Started Aug 13 04:29:51 PM PDT 24
Finished Aug 13 04:29:58 PM PDT 24
Peak memory 206672 kb
Host smart-5f96eb82-04ee-49fe-95ce-7cb674b9264a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057468668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4057468668
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.123295074
Short name T1008
Test name
Test status
Simulation time 170377384 ps
CPU time 0.72 seconds
Started Aug 13 04:29:23 PM PDT 24
Finished Aug 13 04:29:24 PM PDT 24
Peak memory 203568 kb
Host smart-d3ded702-8c7d-4937-b714-ac07ba0f5e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123295074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.123295074
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3238817421
Short name T1094
Test name
Test status
Simulation time 49876373 ps
CPU time 1.68 seconds
Started Aug 13 04:28:55 PM PDT 24
Finished Aug 13 04:28:57 PM PDT 24
Peak memory 215384 kb
Host smart-a2dfd41a-42da-4523-8996-ccfad5a46868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238817421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3238817421
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1327412883
Short name T1057
Test name
Test status
Simulation time 999501884 ps
CPU time 4.13 seconds
Started Aug 13 04:28:57 PM PDT 24
Finished Aug 13 04:29:01 PM PDT 24
Peak memory 215228 kb
Host smart-c55b2943-db3c-42de-95b6-9a6c84fa700d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327412883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1327412883
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2813790669
Short name T1027
Test name
Test status
Simulation time 222918813 ps
CPU time 6.88 seconds
Started Aug 13 04:29:57 PM PDT 24
Finished Aug 13 04:30:04 PM PDT 24
Peak memory 215056 kb
Host smart-8bcb0b69-0f59-4217-83c6-ea85d91c924c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813790669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2813790669
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2455625079
Short name T151
Test name
Test status
Simulation time 1775316797 ps
CPU time 3.52 seconds
Started Aug 13 04:28:51 PM PDT 24
Finished Aug 13 04:28:54 PM PDT 24
Peak memory 218252 kb
Host smart-887d3ce4-d8d3-48b4-83e9-bb94c2bb242a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455625079 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2455625079
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4255999068
Short name T112
Test name
Test status
Simulation time 196102991 ps
CPU time 2.83 seconds
Started Aug 13 04:28:57 PM PDT 24
Finished Aug 13 04:29:00 PM PDT 24
Peak memory 214948 kb
Host smart-964c5411-c642-4c76-be7f-09b304b9141a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255999068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
4255999068
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.55443270
Short name T1123
Test name
Test status
Simulation time 13135299 ps
CPU time 0.74 seconds
Started Aug 13 04:29:06 PM PDT 24
Finished Aug 13 04:29:07 PM PDT 24
Peak memory 203624 kb
Host smart-806d5814-4946-48f9-922f-cd5e1d7f68a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55443270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.55443270
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2632708305
Short name T1028
Test name
Test status
Simulation time 65613285 ps
CPU time 3.87 seconds
Started Aug 13 04:29:22 PM PDT 24
Finished Aug 13 04:29:26 PM PDT 24
Peak memory 214864 kb
Host smart-7c6ad86f-bcb5-4621-9553-ad25ce58f870
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632708305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2632708305
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2382388186
Short name T1082
Test name
Test status
Simulation time 43986383 ps
CPU time 1.47 seconds
Started Aug 13 04:29:04 PM PDT 24
Finished Aug 13 04:29:10 PM PDT 24
Peak memory 215088 kb
Host smart-9c8d48fc-3b50-4bd5-a01a-b94328afdca0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382388186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2382388186
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3178123846
Short name T255
Test name
Test status
Simulation time 1681519576 ps
CPU time 19.12 seconds
Started Aug 13 04:29:18 PM PDT 24
Finished Aug 13 04:29:42 PM PDT 24
Peak memory 215196 kb
Host smart-e0494b99-5cad-4a99-be8f-014c49545417
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178123846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3178123846
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3707744533
Short name T1058
Test name
Test status
Simulation time 430699420 ps
CPU time 3.05 seconds
Started Aug 13 04:29:11 PM PDT 24
Finished Aug 13 04:29:14 PM PDT 24
Peak memory 217292 kb
Host smart-67beea8b-2fd1-484a-b957-12ac4889182d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707744533 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3707744533
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.269181624
Short name T1069
Test name
Test status
Simulation time 106035967 ps
CPU time 2.58 seconds
Started Aug 13 04:29:01 PM PDT 24
Finished Aug 13 04:29:04 PM PDT 24
Peak memory 214916 kb
Host smart-c737be88-3210-44db-964b-c9687c609e6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269181624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.269181624
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.439813973
Short name T1072
Test name
Test status
Simulation time 15905286 ps
CPU time 0.74 seconds
Started Aug 13 04:29:14 PM PDT 24
Finished Aug 13 04:29:15 PM PDT 24
Peak memory 203920 kb
Host smart-09038813-296a-4b6e-984d-169287f383dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439813973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.439813973
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1837649165
Short name T1026
Test name
Test status
Simulation time 166732267 ps
CPU time 4.17 seconds
Started Aug 13 04:29:10 PM PDT 24
Finished Aug 13 04:29:14 PM PDT 24
Peak memory 215036 kb
Host smart-7aef5a1e-cc75-4078-ac3f-3d2beed039eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837649165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1837649165
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1262390440
Short name T70
Test name
Test status
Simulation time 381501233 ps
CPU time 4.11 seconds
Started Aug 13 04:29:08 PM PDT 24
Finished Aug 13 04:29:12 PM PDT 24
Peak memory 215140 kb
Host smart-5e7aee35-3244-4b12-9efe-ddf70ae1cff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262390440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1262390440
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3280035841
Short name T1131
Test name
Test status
Simulation time 704407090 ps
CPU time 8.37 seconds
Started Aug 13 04:29:11 PM PDT 24
Finished Aug 13 04:29:20 PM PDT 24
Peak memory 215684 kb
Host smart-6d1619f9-5ed3-4b99-9d6c-8f5340ec6c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280035841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3280035841
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.835911025
Short name T98
Test name
Test status
Simulation time 314397673 ps
CPU time 2.56 seconds
Started Aug 13 04:29:03 PM PDT 24
Finished Aug 13 04:29:06 PM PDT 24
Peak memory 216448 kb
Host smart-5b3b9e21-c8f0-468d-8163-dd3f6443d1ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835911025 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.835911025
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1931072604
Short name T1088
Test name
Test status
Simulation time 55173101 ps
CPU time 1.92 seconds
Started Aug 13 04:29:11 PM PDT 24
Finished Aug 13 04:29:13 PM PDT 24
Peak memory 215004 kb
Host smart-30d735a4-92fc-4d7e-bbbb-306efdddd1a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931072604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1931072604
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2666080955
Short name T1106
Test name
Test status
Simulation time 13508178 ps
CPU time 0.69 seconds
Started Aug 13 04:29:18 PM PDT 24
Finished Aug 13 04:29:19 PM PDT 24
Peak memory 203924 kb
Host smart-af9ff04b-a88f-4528-86be-32dcf3c585fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666080955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2666080955
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.168256419
Short name T136
Test name
Test status
Simulation time 918600838 ps
CPU time 3.9 seconds
Started Aug 13 04:29:17 PM PDT 24
Finished Aug 13 04:29:21 PM PDT 24
Peak memory 214940 kb
Host smart-d51883c3-faec-47ff-9b0b-4d8b96c6b50a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168256419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.168256419
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2889101516
Short name T1118
Test name
Test status
Simulation time 403925631 ps
CPU time 5.03 seconds
Started Aug 13 04:28:59 PM PDT 24
Finished Aug 13 04:29:04 PM PDT 24
Peak memory 215272 kb
Host smart-8414881e-e0d9-411d-9390-21422925b6be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889101516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2889101516
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2258552116
Short name T252
Test name
Test status
Simulation time 318093186 ps
CPU time 11.8 seconds
Started Aug 13 04:29:32 PM PDT 24
Finished Aug 13 04:29:44 PM PDT 24
Peak memory 215068 kb
Host smart-ca5a95b7-5e2f-42e9-ab4b-47727c41041f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258552116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2258552116
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1534834973
Short name T1065
Test name
Test status
Simulation time 1071625951 ps
CPU time 23.6 seconds
Started Aug 13 04:29:04 PM PDT 24
Finished Aug 13 04:29:27 PM PDT 24
Peak memory 206660 kb
Host smart-8c3c61e1-76a7-45bf-b80f-3901994096a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534834973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1534834973
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.441641810
Short name T122
Test name
Test status
Simulation time 4409307921 ps
CPU time 26.04 seconds
Started Aug 13 04:29:12 PM PDT 24
Finished Aug 13 04:29:38 PM PDT 24
Peak memory 206804 kb
Host smart-95ffdf77-6efe-4883-8b31-602f3f322eb1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441641810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.441641810
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.775315947
Short name T1056
Test name
Test status
Simulation time 30961660 ps
CPU time 0.93 seconds
Started Aug 13 04:29:05 PM PDT 24
Finished Aug 13 04:29:06 PM PDT 24
Peak memory 206636 kb
Host smart-ef2c3617-31fd-4256-a87b-e58d266703c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775315947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.775315947
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3973924137
Short name T1046
Test name
Test status
Simulation time 77666143 ps
CPU time 2.62 seconds
Started Aug 13 04:29:03 PM PDT 24
Finished Aug 13 04:29:06 PM PDT 24
Peak memory 217484 kb
Host smart-114f8b14-86a6-40d0-9b3a-44a1666d5055
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973924137 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3973924137
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4248620672
Short name T1036
Test name
Test status
Simulation time 30397002 ps
CPU time 1.72 seconds
Started Aug 13 04:28:43 PM PDT 24
Finished Aug 13 04:28:45 PM PDT 24
Peak memory 214916 kb
Host smart-b78e2160-df19-4a2a-ab69-24e4f47b8092
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248620672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
248620672
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2507560137
Short name T1040
Test name
Test status
Simulation time 48212892 ps
CPU time 0.69 seconds
Started Aug 13 04:28:50 PM PDT 24
Finished Aug 13 04:28:51 PM PDT 24
Peak memory 203620 kb
Host smart-d2a9cf50-5004-4462-b5b9-ff910e4d9574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507560137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
507560137
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1322967639
Short name T113
Test name
Test status
Simulation time 85294257 ps
CPU time 1.67 seconds
Started Aug 13 04:29:03 PM PDT 24
Finished Aug 13 04:29:05 PM PDT 24
Peak memory 214984 kb
Host smart-51df9626-9d73-41a8-adca-e73c1df38034
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322967639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1322967639
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4242438935
Short name T1128
Test name
Test status
Simulation time 34347521 ps
CPU time 0.7 seconds
Started Aug 13 04:29:10 PM PDT 24
Finished Aug 13 04:29:11 PM PDT 24
Peak memory 203420 kb
Host smart-42bdf5e2-c3e0-49cd-865a-1e017cef4fee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242438935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4242438935
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3725800646
Short name T1020
Test name
Test status
Simulation time 695631331 ps
CPU time 2.6 seconds
Started Aug 13 04:29:01 PM PDT 24
Finished Aug 13 04:29:04 PM PDT 24
Peak memory 206756 kb
Host smart-a73596b8-2dbe-4041-8e03-19c3ca28e887
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725800646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3725800646
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1219432084
Short name T1124
Test name
Test status
Simulation time 860596979 ps
CPU time 4.88 seconds
Started Aug 13 04:28:55 PM PDT 24
Finished Aug 13 04:29:00 PM PDT 24
Peak memory 215168 kb
Host smart-df4d3e15-1dfa-4cf1-a47f-fba6a67dc12f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219432084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
219432084
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2682395579
Short name T258
Test name
Test status
Simulation time 797405645 ps
CPU time 12.36 seconds
Started Aug 13 04:28:54 PM PDT 24
Finished Aug 13 04:29:06 PM PDT 24
Peak memory 215384 kb
Host smart-21d6ecff-e316-4461-8cde-60182f3b39d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682395579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2682395579
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3572046573
Short name T1077
Test name
Test status
Simulation time 48767136 ps
CPU time 0.71 seconds
Started Aug 13 04:29:12 PM PDT 24
Finished Aug 13 04:29:13 PM PDT 24
Peak memory 203656 kb
Host smart-a4bb7aa7-d4fd-4450-a56d-840814576324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572046573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3572046573
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2900798648
Short name T1083
Test name
Test status
Simulation time 19628335 ps
CPU time 0.69 seconds
Started Aug 13 04:29:03 PM PDT 24
Finished Aug 13 04:29:04 PM PDT 24
Peak memory 203940 kb
Host smart-847477f2-39e4-48f4-be41-2134bc50583f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900798648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2900798648
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3929244677
Short name T1054
Test name
Test status
Simulation time 25126682 ps
CPU time 0.7 seconds
Started Aug 13 04:29:18 PM PDT 24
Finished Aug 13 04:29:19 PM PDT 24
Peak memory 203888 kb
Host smart-a5833069-e065-4cb4-b152-d13e57f15d44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929244677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3929244677
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1522589591
Short name T1031
Test name
Test status
Simulation time 187130607 ps
CPU time 0.75 seconds
Started Aug 13 04:29:16 PM PDT 24
Finished Aug 13 04:29:16 PM PDT 24
Peak memory 203556 kb
Host smart-78af933c-ba76-43c0-8262-c083f1c2859c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522589591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1522589591
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.709202389
Short name T1061
Test name
Test status
Simulation time 53082022 ps
CPU time 0.75 seconds
Started Aug 13 04:29:26 PM PDT 24
Finished Aug 13 04:29:27 PM PDT 24
Peak memory 203608 kb
Host smart-015eecfa-12eb-41ea-81c0-71adb4cde432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709202389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.709202389
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.850594069
Short name T1050
Test name
Test status
Simulation time 42572588 ps
CPU time 0.76 seconds
Started Aug 13 04:29:06 PM PDT 24
Finished Aug 13 04:29:07 PM PDT 24
Peak memory 203604 kb
Host smart-5f5596d2-51fe-4a71-9274-16665f1894ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850594069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.850594069
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.754387813
Short name T1125
Test name
Test status
Simulation time 18972813 ps
CPU time 0.78 seconds
Started Aug 13 04:29:05 PM PDT 24
Finished Aug 13 04:29:06 PM PDT 24
Peak memory 203592 kb
Host smart-2a463637-9a23-406d-9657-49ccefc5da8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754387813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.754387813
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3670659440
Short name T1121
Test name
Test status
Simulation time 10895219 ps
CPU time 0.71 seconds
Started Aug 13 04:29:21 PM PDT 24
Finished Aug 13 04:29:22 PM PDT 24
Peak memory 203580 kb
Host smart-ba975704-d9a3-434c-84dd-d7a7ab948f43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670659440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3670659440
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1052889375
Short name T1019
Test name
Test status
Simulation time 12344440 ps
CPU time 0.74 seconds
Started Aug 13 04:29:17 PM PDT 24
Finished Aug 13 04:29:18 PM PDT 24
Peak memory 203632 kb
Host smart-eb7cc30d-2508-49c2-acfd-07c0e7b6b8c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052889375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1052889375
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1293820676
Short name T1081
Test name
Test status
Simulation time 14044591 ps
CPU time 0.67 seconds
Started Aug 13 04:29:17 PM PDT 24
Finished Aug 13 04:29:18 PM PDT 24
Peak memory 203920 kb
Host smart-56f79434-75c0-435a-b8d6-714bf6b5369d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293820676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1293820676
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2900939286
Short name T1060
Test name
Test status
Simulation time 218104337 ps
CPU time 13.94 seconds
Started Aug 13 04:28:52 PM PDT 24
Finished Aug 13 04:29:06 PM PDT 24
Peak memory 214908 kb
Host smart-874a3f82-07a2-453c-98ee-f6d3654097bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900939286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2900939286
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1184741513
Short name T1010
Test name
Test status
Simulation time 639182661 ps
CPU time 12.29 seconds
Started Aug 13 04:28:54 PM PDT 24
Finished Aug 13 04:29:07 PM PDT 24
Peak memory 206820 kb
Host smart-8a71d8dd-52a1-4494-a423-00b55696403a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184741513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1184741513
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.952505322
Short name T88
Test name
Test status
Simulation time 31460833 ps
CPU time 1.21 seconds
Started Aug 13 04:28:56 PM PDT 24
Finished Aug 13 04:28:57 PM PDT 24
Peak memory 206596 kb
Host smart-1224a0c9-5183-4e1e-b7e5-6eaa57a74c83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952505322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.952505322
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.217960371
Short name T1070
Test name
Test status
Simulation time 54962242 ps
CPU time 1.74 seconds
Started Aug 13 04:28:58 PM PDT 24
Finished Aug 13 04:29:00 PM PDT 24
Peak memory 215136 kb
Host smart-a791278a-90c3-4252-97eb-fe9fc4852abb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217960371 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.217960371
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4289524464
Short name T1076
Test name
Test status
Simulation time 103353635 ps
CPU time 2.31 seconds
Started Aug 13 04:28:56 PM PDT 24
Finished Aug 13 04:28:58 PM PDT 24
Peak memory 215008 kb
Host smart-448d19a6-8b3a-4ee2-a21b-3c977823f883
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289524464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
289524464
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.393357275
Short name T1120
Test name
Test status
Simulation time 18004914 ps
CPU time 0.71 seconds
Started Aug 13 04:28:50 PM PDT 24
Finished Aug 13 04:28:51 PM PDT 24
Peak memory 203584 kb
Host smart-851dba47-cc57-4c15-8153-2fb6f1516461
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393357275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.393357275
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.346359463
Short name T1104
Test name
Test status
Simulation time 107980469 ps
CPU time 1.6 seconds
Started Aug 13 04:28:52 PM PDT 24
Finished Aug 13 04:28:54 PM PDT 24
Peak memory 214972 kb
Host smart-410a3679-6a3f-4bcd-b9d9-813f6188eb33
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346359463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.346359463
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.330875272
Short name T1091
Test name
Test status
Simulation time 12163053 ps
CPU time 0.64 seconds
Started Aug 13 04:28:48 PM PDT 24
Finished Aug 13 04:28:48 PM PDT 24
Peak memory 203420 kb
Host smart-fac0c8eb-18ef-4fd1-b37d-73646c886541
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330875272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.330875272
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2296692366
Short name T1018
Test name
Test status
Simulation time 61557591 ps
CPU time 1.84 seconds
Started Aug 13 04:28:55 PM PDT 24
Finished Aug 13 04:28:56 PM PDT 24
Peak memory 214944 kb
Host smart-b2848ce1-a342-4a30-94c8-5abe5a8b62ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296692366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2296692366
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3374794141
Short name T96
Test name
Test status
Simulation time 67172097 ps
CPU time 2.42 seconds
Started Aug 13 04:28:55 PM PDT 24
Finished Aug 13 04:28:57 PM PDT 24
Peak memory 215216 kb
Host smart-a7e2ce92-b711-49e7-88a0-e9e2c3403a02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374794141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
374794141
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.90712311
Short name T146
Test name
Test status
Simulation time 2786258083 ps
CPU time 15.52 seconds
Started Aug 13 04:28:46 PM PDT 24
Finished Aug 13 04:29:02 PM PDT 24
Peak memory 215220 kb
Host smart-2a78e43d-b7b3-42d2-bf70-be6675d16dd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90712311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_t
l_intg_err.90712311
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3067439824
Short name T1109
Test name
Test status
Simulation time 24950924 ps
CPU time 0.69 seconds
Started Aug 13 04:29:03 PM PDT 24
Finished Aug 13 04:29:08 PM PDT 24
Peak memory 203632 kb
Host smart-8c44a919-2351-4d51-8656-0f9c013fcd63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067439824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3067439824
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1473918382
Short name T1114
Test name
Test status
Simulation time 17156334 ps
CPU time 0.69 seconds
Started Aug 13 04:29:25 PM PDT 24
Finished Aug 13 04:29:26 PM PDT 24
Peak memory 203532 kb
Host smart-b2e7e697-7d19-4d68-b37b-d85be35a4cdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473918382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1473918382
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1706248194
Short name T1085
Test name
Test status
Simulation time 33398938 ps
CPU time 0.69 seconds
Started Aug 13 04:29:14 PM PDT 24
Finished Aug 13 04:29:15 PM PDT 24
Peak memory 203728 kb
Host smart-182707b9-922b-48f3-83ce-306d542cdbbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706248194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1706248194
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.844258138
Short name T1103
Test name
Test status
Simulation time 49998862 ps
CPU time 0.7 seconds
Started Aug 13 04:28:59 PM PDT 24
Finished Aug 13 04:29:00 PM PDT 24
Peak memory 203640 kb
Host smart-cff0a07c-47ca-443b-b9e8-f34064ca3a6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844258138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.844258138
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2888700848
Short name T1034
Test name
Test status
Simulation time 48669049 ps
CPU time 0.68 seconds
Started Aug 13 04:29:13 PM PDT 24
Finished Aug 13 04:29:14 PM PDT 24
Peak memory 203608 kb
Host smart-8fb8a602-51a2-45c2-921f-6a37c52da7ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888700848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2888700848
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1310275333
Short name T1107
Test name
Test status
Simulation time 48242179 ps
CPU time 0.69 seconds
Started Aug 13 04:29:07 PM PDT 24
Finished Aug 13 04:29:07 PM PDT 24
Peak memory 203620 kb
Host smart-5e9e572d-de5a-4340-8672-10f72ee8a106
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310275333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1310275333
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2452916840
Short name T1038
Test name
Test status
Simulation time 45375168 ps
CPU time 0.73 seconds
Started Aug 13 04:29:08 PM PDT 24
Finished Aug 13 04:29:09 PM PDT 24
Peak memory 204024 kb
Host smart-d4fbd729-9fcb-417a-8e0a-be5b31f3cf12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452916840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2452916840
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2006057132
Short name T1100
Test name
Test status
Simulation time 14366390 ps
CPU time 0.73 seconds
Started Aug 13 04:29:24 PM PDT 24
Finished Aug 13 04:29:25 PM PDT 24
Peak memory 203716 kb
Host smart-e507ff2e-730b-4df3-9fea-852b42425254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006057132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2006057132
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3240742337
Short name T1049
Test name
Test status
Simulation time 24519838 ps
CPU time 0.7 seconds
Started Aug 13 04:29:08 PM PDT 24
Finished Aug 13 04:29:09 PM PDT 24
Peak memory 203628 kb
Host smart-32222601-cc36-45f9-a0aa-a21361dd83fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240742337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3240742337
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2190541292
Short name T1029
Test name
Test status
Simulation time 22393079 ps
CPU time 0.71 seconds
Started Aug 13 04:29:04 PM PDT 24
Finished Aug 13 04:29:05 PM PDT 24
Peak memory 203588 kb
Host smart-1258f221-2670-48bf-a314-2d870ee12a12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190541292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2190541292
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2611129706
Short name T119
Test name
Test status
Simulation time 790362077 ps
CPU time 8.11 seconds
Started Aug 13 04:28:54 PM PDT 24
Finished Aug 13 04:29:02 PM PDT 24
Peak memory 206752 kb
Host smart-a02d8c7f-ae9a-450b-9991-e5cede4c291e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611129706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2611129706
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2469332482
Short name T1084
Test name
Test status
Simulation time 186259854 ps
CPU time 11.27 seconds
Started Aug 13 04:28:56 PM PDT 24
Finished Aug 13 04:29:07 PM PDT 24
Peak memory 206676 kb
Host smart-7b6d3d3e-d205-459c-a5d6-ff2a65aca9d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469332482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2469332482
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1718502072
Short name T1080
Test name
Test status
Simulation time 262850797 ps
CPU time 1.39 seconds
Started Aug 13 04:28:41 PM PDT 24
Finished Aug 13 04:28:43 PM PDT 24
Peak memory 206732 kb
Host smart-29c0625d-e171-467e-89d7-0f49096d9bad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718502072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1718502072
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4124611493
Short name T108
Test name
Test status
Simulation time 232949759 ps
CPU time 3.59 seconds
Started Aug 13 04:28:53 PM PDT 24
Finished Aug 13 04:28:57 PM PDT 24
Peak memory 217660 kb
Host smart-5618156b-19a0-448d-8b45-159c1bd93559
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124611493 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4124611493
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1321549160
Short name T116
Test name
Test status
Simulation time 247331074 ps
CPU time 1.92 seconds
Started Aug 13 04:28:58 PM PDT 24
Finished Aug 13 04:29:00 PM PDT 24
Peak memory 214936 kb
Host smart-bdc67c11-de01-4633-ae3a-a0d177238c75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321549160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
321549160
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1020319221
Short name T1013
Test name
Test status
Simulation time 57331958 ps
CPU time 0.76 seconds
Started Aug 13 04:28:49 PM PDT 24
Finished Aug 13 04:28:50 PM PDT 24
Peak memory 203588 kb
Host smart-a9e66b49-b631-49d5-8d68-4f40b79e1bbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020319221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
020319221
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2051257133
Short name T117
Test name
Test status
Simulation time 74954912 ps
CPU time 2.24 seconds
Started Aug 13 04:29:19 PM PDT 24
Finished Aug 13 04:29:21 PM PDT 24
Peak memory 214988 kb
Host smart-8d8f3013-e94a-4b7c-94f8-07e081e93d56
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051257133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2051257133
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3767909677
Short name T1012
Test name
Test status
Simulation time 10186158 ps
CPU time 0.65 seconds
Started Aug 13 04:28:50 PM PDT 24
Finished Aug 13 04:28:50 PM PDT 24
Peak memory 203460 kb
Host smart-22d72292-bb26-4e6c-941a-5a760ac476a6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767909677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3767909677
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3455633748
Short name T1043
Test name
Test status
Simulation time 41076335 ps
CPU time 1.67 seconds
Started Aug 13 04:28:50 PM PDT 24
Finished Aug 13 04:28:52 PM PDT 24
Peak memory 215024 kb
Host smart-9e3299e0-0fee-4333-a823-40b11ebebbb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455633748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3455633748
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1341745171
Short name T1119
Test name
Test status
Simulation time 161980625 ps
CPU time 2.17 seconds
Started Aug 13 04:29:00 PM PDT 24
Finished Aug 13 04:29:02 PM PDT 24
Peak memory 215140 kb
Host smart-3c6f8f31-717a-42d4-9aea-1bb8fd40a500
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341745171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
341745171
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3174734991
Short name T1092
Test name
Test status
Simulation time 16662244 ps
CPU time 0.76 seconds
Started Aug 13 04:29:10 PM PDT 24
Finished Aug 13 04:29:10 PM PDT 24
Peak memory 203608 kb
Host smart-42d40d84-854a-42f1-b241-4bfa7d858d09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174734991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3174734991
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.909468731
Short name T1016
Test name
Test status
Simulation time 11799956 ps
CPU time 0.78 seconds
Started Aug 13 04:29:20 PM PDT 24
Finished Aug 13 04:29:20 PM PDT 24
Peak memory 202840 kb
Host smart-78edf82f-6dc8-4640-9278-9b7d300cb55c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909468731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.909468731
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4071107631
Short name T1048
Test name
Test status
Simulation time 95389006 ps
CPU time 0.74 seconds
Started Aug 13 04:29:13 PM PDT 24
Finished Aug 13 04:29:14 PM PDT 24
Peak memory 203844 kb
Host smart-86280edf-af13-4b5a-b021-78575731fcbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071107631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4071107631
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2891269255
Short name T1014
Test name
Test status
Simulation time 47046658 ps
CPU time 0.72 seconds
Started Aug 13 04:29:19 PM PDT 24
Finished Aug 13 04:29:20 PM PDT 24
Peak memory 203604 kb
Host smart-2f7483fd-dc7f-47f7-9b0a-ebfab90de0a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891269255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2891269255
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2135768368
Short name T1052
Test name
Test status
Simulation time 45770341 ps
CPU time 0.68 seconds
Started Aug 13 04:29:07 PM PDT 24
Finished Aug 13 04:29:08 PM PDT 24
Peak memory 203960 kb
Host smart-272bedc7-e614-4ebf-827a-7bddf77be9fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135768368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2135768368
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3708613687
Short name T1023
Test name
Test status
Simulation time 42431029 ps
CPU time 0.71 seconds
Started Aug 13 04:29:10 PM PDT 24
Finished Aug 13 04:29:11 PM PDT 24
Peak memory 203936 kb
Host smart-7978261f-3c2e-4bd4-b9c5-2534df3953ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708613687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3708613687
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4186490682
Short name T1011
Test name
Test status
Simulation time 16426921 ps
CPU time 0.79 seconds
Started Aug 13 04:29:15 PM PDT 24
Finished Aug 13 04:29:16 PM PDT 24
Peak memory 203616 kb
Host smart-969c62b7-9248-41e8-95bb-0ff8b559f988
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186490682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4186490682
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3061211847
Short name T1095
Test name
Test status
Simulation time 58451460 ps
CPU time 0.73 seconds
Started Aug 13 04:29:12 PM PDT 24
Finished Aug 13 04:29:13 PM PDT 24
Peak memory 203972 kb
Host smart-81e024ed-329f-46eb-b701-5f57a6d1bb25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061211847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3061211847
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2209482209
Short name T1089
Test name
Test status
Simulation time 26396376 ps
CPU time 0.73 seconds
Started Aug 13 04:29:12 PM PDT 24
Finished Aug 13 04:29:13 PM PDT 24
Peak memory 203872 kb
Host smart-ec1e7c3c-8352-4b5e-9421-496a0def8ea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209482209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2209482209
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.23233698
Short name T1044
Test name
Test status
Simulation time 24175554 ps
CPU time 0.8 seconds
Started Aug 13 04:29:04 PM PDT 24
Finished Aug 13 04:29:05 PM PDT 24
Peak memory 203716 kb
Host smart-b43853f4-3d41-4346-8016-8d20b25b0484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23233698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.23233698
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.58514239
Short name T1045
Test name
Test status
Simulation time 55896335 ps
CPU time 1.78 seconds
Started Aug 13 04:29:11 PM PDT 24
Finished Aug 13 04:29:13 PM PDT 24
Peak memory 216164 kb
Host smart-2b780fa0-50f9-4a27-86e1-7567532e3bc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58514239 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.58514239
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3572854976
Short name T1105
Test name
Test status
Simulation time 192476398 ps
CPU time 1.35 seconds
Started Aug 13 04:29:13 PM PDT 24
Finished Aug 13 04:29:15 PM PDT 24
Peak memory 205968 kb
Host smart-87714293-5c95-46e9-aea5-e0df162b273d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572854976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
572854976
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1438045617
Short name T1071
Test name
Test status
Simulation time 12261816 ps
CPU time 0.74 seconds
Started Aug 13 04:29:02 PM PDT 24
Finished Aug 13 04:29:03 PM PDT 24
Peak memory 203572 kb
Host smart-a5dcc9da-f6be-4a59-9b1c-48bd674b00a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438045617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
438045617
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2185948051
Short name T1051
Test name
Test status
Simulation time 233137607 ps
CPU time 1.71 seconds
Started Aug 13 04:28:49 PM PDT 24
Finished Aug 13 04:28:51 PM PDT 24
Peak memory 214832 kb
Host smart-9894d63f-e80d-4710-b65a-ef5d80d5fd55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185948051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2185948051
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2411354967
Short name T1099
Test name
Test status
Simulation time 67219411 ps
CPU time 1.95 seconds
Started Aug 13 04:28:52 PM PDT 24
Finished Aug 13 04:28:54 PM PDT 24
Peak memory 215476 kb
Host smart-8de3958d-735b-4b8b-a68b-71976d8b024f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411354967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
411354967
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.266580788
Short name T1093
Test name
Test status
Simulation time 928120643 ps
CPU time 13.54 seconds
Started Aug 13 04:28:44 PM PDT 24
Finished Aug 13 04:28:58 PM PDT 24
Peak memory 215060 kb
Host smart-5940fb20-9bdd-47da-beb8-7c1d047810a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266580788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.266580788
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4102038344
Short name T69
Test name
Test status
Simulation time 51437151 ps
CPU time 1.7 seconds
Started Aug 13 04:29:11 PM PDT 24
Finished Aug 13 04:29:13 PM PDT 24
Peak memory 215088 kb
Host smart-b9434875-9d79-4216-a6d6-bce5661be157
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102038344 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4102038344
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.734371151
Short name T149
Test name
Test status
Simulation time 759565642 ps
CPU time 1.24 seconds
Started Aug 13 04:29:07 PM PDT 24
Finished Aug 13 04:29:08 PM PDT 24
Peak memory 214984 kb
Host smart-1a7797ef-a7af-4d11-862e-344cd391b604
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734371151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.734371151
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1194055878
Short name T1062
Test name
Test status
Simulation time 11032752 ps
CPU time 0.7 seconds
Started Aug 13 04:28:54 PM PDT 24
Finished Aug 13 04:28:54 PM PDT 24
Peak memory 203900 kb
Host smart-bc7ace21-604a-4be7-9b66-2d01e30ddad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194055878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
194055878
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2020690895
Short name T137
Test name
Test status
Simulation time 30580317 ps
CPU time 1.67 seconds
Started Aug 13 04:29:15 PM PDT 24
Finished Aug 13 04:29:17 PM PDT 24
Peak memory 214940 kb
Host smart-24a31b4e-a403-4859-a077-6794010c40b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020690895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2020690895
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3386122769
Short name T104
Test name
Test status
Simulation time 863603193 ps
CPU time 5.26 seconds
Started Aug 13 04:28:49 PM PDT 24
Finished Aug 13 04:28:54 PM PDT 24
Peak memory 216224 kb
Host smart-20ed56e4-9987-4e94-8446-0cb4a90e57e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386122769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
386122769
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.865617585
Short name T1025
Test name
Test status
Simulation time 101463430 ps
CPU time 6.37 seconds
Started Aug 13 04:29:04 PM PDT 24
Finished Aug 13 04:29:10 PM PDT 24
Peak memory 215040 kb
Host smart-46fe5185-0c19-48f3-8803-562028015ebe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865617585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.865617585
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1209320994
Short name T1042
Test name
Test status
Simulation time 58205777 ps
CPU time 3.77 seconds
Started Aug 13 04:29:14 PM PDT 24
Finished Aug 13 04:29:18 PM PDT 24
Peak memory 218188 kb
Host smart-e4853f47-38f9-4f5e-b11a-01f8c2379491
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209320994 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1209320994
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2873625508
Short name T120
Test name
Test status
Simulation time 96443499 ps
CPU time 2.59 seconds
Started Aug 13 04:29:10 PM PDT 24
Finished Aug 13 04:29:12 PM PDT 24
Peak memory 214952 kb
Host smart-1e9da593-b0b4-4fa6-8826-465971f64997
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873625508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
873625508
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4202033103
Short name T1053
Test name
Test status
Simulation time 46143182 ps
CPU time 0.73 seconds
Started Aug 13 04:29:12 PM PDT 24
Finished Aug 13 04:29:13 PM PDT 24
Peak memory 203912 kb
Host smart-3374b098-7f69-4354-8f7d-6b10597a8258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202033103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4
202033103
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.408431238
Short name T1021
Test name
Test status
Simulation time 265895752 ps
CPU time 1.85 seconds
Started Aug 13 04:29:08 PM PDT 24
Finished Aug 13 04:29:10 PM PDT 24
Peak memory 214844 kb
Host smart-006aa2c4-6df2-4ac3-8970-25b305d4ad0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408431238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.408431238
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.461115422
Short name T1098
Test name
Test status
Simulation time 313413974 ps
CPU time 2.57 seconds
Started Aug 13 04:29:01 PM PDT 24
Finished Aug 13 04:29:03 PM PDT 24
Peak memory 216584 kb
Host smart-2697ffb6-73aa-4291-bd51-7d8386c0740a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461115422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.461115422
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2324739724
Short name T257
Test name
Test status
Simulation time 1034330181 ps
CPU time 21.77 seconds
Started Aug 13 04:29:30 PM PDT 24
Finished Aug 13 04:29:52 PM PDT 24
Peak memory 215024 kb
Host smart-ac924f39-48ac-4782-9c5d-24b10f7bef31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324739724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2324739724
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2814994856
Short name T148
Test name
Test status
Simulation time 107866860 ps
CPU time 2.61 seconds
Started Aug 13 04:28:58 PM PDT 24
Finished Aug 13 04:29:01 PM PDT 24
Peak memory 216060 kb
Host smart-c6aa0790-0e82-4658-8227-b5b342ddf227
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814994856 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2814994856
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1889601413
Short name T118
Test name
Test status
Simulation time 31162770 ps
CPU time 2.04 seconds
Started Aug 13 04:28:54 PM PDT 24
Finished Aug 13 04:28:56 PM PDT 24
Peak memory 214900 kb
Host smart-66b5f656-ca02-4388-ada2-634c2390e0b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889601413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
889601413
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3152195679
Short name T1122
Test name
Test status
Simulation time 13598348 ps
CPU time 0.74 seconds
Started Aug 13 04:28:57 PM PDT 24
Finished Aug 13 04:28:58 PM PDT 24
Peak memory 203948 kb
Host smart-7d1e78f7-e630-4306-9909-d155dbc51ccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152195679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
152195679
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4150081823
Short name T1015
Test name
Test status
Simulation time 156852603 ps
CPU time 3.75 seconds
Started Aug 13 04:29:11 PM PDT 24
Finished Aug 13 04:29:15 PM PDT 24
Peak memory 215776 kb
Host smart-b65c6af9-e00e-479c-88aa-1f1208e192e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150081823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.4150081823
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2129754500
Short name T107
Test name
Test status
Simulation time 3758562545 ps
CPU time 4.83 seconds
Started Aug 13 04:29:16 PM PDT 24
Finished Aug 13 04:29:21 PM PDT 24
Peak memory 216220 kb
Host smart-83a1a7fa-58b8-4be3-8960-767119890752
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129754500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
129754500
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1756630882
Short name T254
Test name
Test status
Simulation time 776924065 ps
CPU time 8.29 seconds
Started Aug 13 04:29:17 PM PDT 24
Finished Aug 13 04:29:25 PM PDT 24
Peak memory 215016 kb
Host smart-9a3e0bfb-1976-46f2-b139-e8551ce5a5e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756630882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1756630882
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.82851042
Short name T1108
Test name
Test status
Simulation time 103627196 ps
CPU time 2.97 seconds
Started Aug 13 04:29:15 PM PDT 24
Finished Aug 13 04:29:18 PM PDT 24
Peak memory 218060 kb
Host smart-122030da-d288-4ca3-b5ec-fb3fcb016626
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82851042 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.82851042
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1587172290
Short name T1059
Test name
Test status
Simulation time 77225060 ps
CPU time 1.94 seconds
Started Aug 13 04:28:59 PM PDT 24
Finished Aug 13 04:29:01 PM PDT 24
Peak memory 206760 kb
Host smart-91e6e42d-4f36-4309-9b35-11a9cdc36350
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587172290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
587172290
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2745094159
Short name T1033
Test name
Test status
Simulation time 15701497 ps
CPU time 0.73 seconds
Started Aug 13 04:29:14 PM PDT 24
Finished Aug 13 04:29:14 PM PDT 24
Peak memory 203848 kb
Host smart-06dd626c-3086-44cb-b91b-55bc30a2f2a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745094159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
745094159
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2631896147
Short name T150
Test name
Test status
Simulation time 141350238 ps
CPU time 3.02 seconds
Started Aug 13 04:29:07 PM PDT 24
Finished Aug 13 04:29:11 PM PDT 24
Peak memory 214876 kb
Host smart-8e60adec-1d91-4973-932d-1526249f49f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631896147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2631896147
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2208298022
Short name T103
Test name
Test status
Simulation time 245711607 ps
CPU time 2.27 seconds
Started Aug 13 04:28:55 PM PDT 24
Finished Aug 13 04:28:57 PM PDT 24
Peak memory 215232 kb
Host smart-2ad8a888-16d9-4ccc-b253-0ff73b238705
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208298022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
208298022
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.405829345
Short name T1041
Test name
Test status
Simulation time 418316821 ps
CPU time 17.2 seconds
Started Aug 13 04:29:00 PM PDT 24
Finished Aug 13 04:29:17 PM PDT 24
Peak memory 214988 kb
Host smart-27dce2ac-b597-41ca-99c1-06693e84f337
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405829345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.405829345
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2780656398
Short name T540
Test name
Test status
Simulation time 81426225 ps
CPU time 0.71 seconds
Started Aug 13 04:30:51 PM PDT 24
Finished Aug 13 04:30:52 PM PDT 24
Peak memory 206132 kb
Host smart-d5a80b16-cc30-4b2f-87f5-98c435f8a10e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780656398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
780656398
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3204060807
Short name T691
Test name
Test status
Simulation time 1928990916 ps
CPU time 9.1 seconds
Started Aug 13 04:30:48 PM PDT 24
Finished Aug 13 04:30:58 PM PDT 24
Peak memory 233480 kb
Host smart-646837b4-e246-4483-ae02-bacf91b7d75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204060807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3204060807
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3672774757
Short name T404
Test name
Test status
Simulation time 20600846 ps
CPU time 0.79 seconds
Started Aug 13 04:30:45 PM PDT 24
Finished Aug 13 04:30:46 PM PDT 24
Peak memory 207232 kb
Host smart-c3e93e5b-9e8a-4153-97e5-1dbdabc63bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672774757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3672774757
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3086713466
Short name T42
Test name
Test status
Simulation time 27003396864 ps
CPU time 49.97 seconds
Started Aug 13 04:30:49 PM PDT 24
Finished Aug 13 04:31:39 PM PDT 24
Peak memory 258028 kb
Host smart-a0fd709f-4fdf-4622-b9e6-2249a11b5c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086713466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3086713466
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.829880373
Short name T885
Test name
Test status
Simulation time 13357369404 ps
CPU time 82.5 seconds
Started Aug 13 04:30:49 PM PDT 24
Finished Aug 13 04:32:11 PM PDT 24
Peak memory 239124 kb
Host smart-67140145-ebd3-4d78-814a-b2944e944614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829880373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.829880373
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1206196501
Short name T440
Test name
Test status
Simulation time 2729648663 ps
CPU time 10.72 seconds
Started Aug 13 04:30:39 PM PDT 24
Finished Aug 13 04:30:50 PM PDT 24
Peak memory 233780 kb
Host smart-747102a8-dbee-4f04-8a76-22334e5da20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206196501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1206196501
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.4100230653
Short name T64
Test name
Test status
Simulation time 6133446159 ps
CPU time 40.07 seconds
Started Aug 13 04:30:46 PM PDT 24
Finished Aug 13 04:31:26 PM PDT 24
Peak memory 253412 kb
Host smart-7257a641-c85a-4515-b0a2-e9667e76462f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100230653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.4100230653
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2229294592
Short name T344
Test name
Test status
Simulation time 44309806 ps
CPU time 2.49 seconds
Started Aug 13 04:30:43 PM PDT 24
Finished Aug 13 04:30:45 PM PDT 24
Peak memory 233432 kb
Host smart-ba4821a9-d952-4474-967a-35278ad8e7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229294592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2229294592
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2924847824
Short name T333
Test name
Test status
Simulation time 13851801847 ps
CPU time 40.18 seconds
Started Aug 13 04:30:34 PM PDT 24
Finished Aug 13 04:31:14 PM PDT 24
Peak memory 241688 kb
Host smart-48a70263-e917-481c-a8a7-2bc6ac3ec987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924847824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2924847824
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1669550682
Short name T130
Test name
Test status
Simulation time 7623368214 ps
CPU time 6.84 seconds
Started Aug 13 04:30:50 PM PDT 24
Finished Aug 13 04:30:57 PM PDT 24
Peak memory 233560 kb
Host smart-603c6cd1-5a0b-409e-b094-7e8e92618cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669550682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1669550682
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3655811626
Short name T482
Test name
Test status
Simulation time 3018331398 ps
CPU time 10.88 seconds
Started Aug 13 04:30:45 PM PDT 24
Finished Aug 13 04:30:56 PM PDT 24
Peak memory 240980 kb
Host smart-22dc2778-5144-4b89-acab-6b5155125987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655811626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3655811626
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2817579173
Short name T836
Test name
Test status
Simulation time 891585628 ps
CPU time 4.62 seconds
Started Aug 13 04:30:44 PM PDT 24
Finished Aug 13 04:30:49 PM PDT 24
Peak memory 223880 kb
Host smart-a1e5e30b-ac82-45ad-b630-e480e4cf9a8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2817579173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2817579173
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2461133219
Short name T74
Test name
Test status
Simulation time 509179511 ps
CPU time 1.86 seconds
Started Aug 13 04:30:47 PM PDT 24
Finished Aug 13 04:30:49 PM PDT 24
Peak memory 237032 kb
Host smart-7108e2ef-22c6-4ca9-98cf-dbad40157c8b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461133219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2461133219
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1257839076
Short name T39
Test name
Test status
Simulation time 27182012197 ps
CPU time 37.63 seconds
Started Aug 13 04:30:53 PM PDT 24
Finished Aug 13 04:31:31 PM PDT 24
Peak memory 221632 kb
Host smart-7eefa2b9-d116-4e5b-bc86-1a68218ec73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257839076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1257839076
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3376708612
Short name T970
Test name
Test status
Simulation time 1084270563 ps
CPU time 3.57 seconds
Started Aug 13 04:30:46 PM PDT 24
Finished Aug 13 04:30:50 PM PDT 24
Peak memory 216972 kb
Host smart-28f96440-6dce-4089-b7de-aca212484fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376708612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3376708612
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2599291129
Short name T499
Test name
Test status
Simulation time 98653082 ps
CPU time 0.81 seconds
Started Aug 13 04:30:46 PM PDT 24
Finished Aug 13 04:30:47 PM PDT 24
Peak memory 206796 kb
Host smart-caf3a073-36f0-4ebf-9bcb-293121b3efa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599291129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2599291129
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1607753828
Short name T783
Test name
Test status
Simulation time 208739416 ps
CPU time 0.91 seconds
Started Aug 13 04:30:36 PM PDT 24
Finished Aug 13 04:30:37 PM PDT 24
Peak memory 206748 kb
Host smart-649bb641-efda-4153-9d86-46cd44b25482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607753828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1607753828
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1967537505
Short name T577
Test name
Test status
Simulation time 2424463032 ps
CPU time 6.48 seconds
Started Aug 13 04:30:42 PM PDT 24
Finished Aug 13 04:30:49 PM PDT 24
Peak memory 225284 kb
Host smart-850778a4-d3e8-46e3-a253-5365077eff52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967537505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1967537505
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2534582023
Short name T492
Test name
Test status
Simulation time 21637942073 ps
CPU time 38.87 seconds
Started Aug 13 04:30:52 PM PDT 24
Finished Aug 13 04:31:31 PM PDT 24
Peak memory 225360 kb
Host smart-31c39a80-38f8-4203-8e63-237bea8a4f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534582023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2534582023
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2011533415
Short name T383
Test name
Test status
Simulation time 15920601 ps
CPU time 0.73 seconds
Started Aug 13 04:30:51 PM PDT 24
Finished Aug 13 04:30:52 PM PDT 24
Peak memory 207292 kb
Host smart-d2983eed-e70d-4767-89c5-3b1372e04c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011533415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2011533415
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3275380703
Short name T967
Test name
Test status
Simulation time 4995070851 ps
CPU time 57.91 seconds
Started Aug 13 04:30:47 PM PDT 24
Finished Aug 13 04:31:45 PM PDT 24
Peak memory 255212 kb
Host smart-4298455b-cb8f-4c7a-b892-4dd651291b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275380703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3275380703
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.459337610
Short name T607
Test name
Test status
Simulation time 4232299561 ps
CPU time 73.54 seconds
Started Aug 13 04:30:50 PM PDT 24
Finished Aug 13 04:32:04 PM PDT 24
Peak memory 250128 kb
Host smart-f0145307-d778-4232-b304-40c44f4b9d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459337610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.459337610
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3578920782
Short name T804
Test name
Test status
Simulation time 5360269535 ps
CPU time 17.75 seconds
Started Aug 13 04:30:48 PM PDT 24
Finished Aug 13 04:31:06 PM PDT 24
Peak memory 218552 kb
Host smart-7eda7ec6-2511-4d04-b179-f58685f60ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578920782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3578920782
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3725930868
Short name T830
Test name
Test status
Simulation time 942599495 ps
CPU time 5.29 seconds
Started Aug 13 04:30:51 PM PDT 24
Finished Aug 13 04:30:56 PM PDT 24
Peak memory 225308 kb
Host smart-bdea88ee-9d84-43d3-9832-363c575f0398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725930868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3725930868
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.37026044
Short name T784
Test name
Test status
Simulation time 33528466458 ps
CPU time 81.74 seconds
Started Aug 13 04:30:48 PM PDT 24
Finished Aug 13 04:32:10 PM PDT 24
Peak memory 257184 kb
Host smart-5b235c45-f86d-43b7-b8df-2238f213931f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37026044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.37026044
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1292531875
Short name T373
Test name
Test status
Simulation time 71631544 ps
CPU time 2.23 seconds
Started Aug 13 04:30:51 PM PDT 24
Finished Aug 13 04:30:54 PM PDT 24
Peak memory 223844 kb
Host smart-6ea0ff79-179b-4392-bb56-7cc94b5cfcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292531875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1292531875
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3907816929
Short name T261
Test name
Test status
Simulation time 620650923 ps
CPU time 13.4 seconds
Started Aug 13 04:30:49 PM PDT 24
Finished Aug 13 04:31:03 PM PDT 24
Peak memory 236388 kb
Host smart-11bc34ff-19ec-4e10-8f1e-5db0cbb8dfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907816929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3907816929
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2755901002
Short name T78
Test name
Test status
Simulation time 1149175103 ps
CPU time 4.05 seconds
Started Aug 13 04:30:52 PM PDT 24
Finished Aug 13 04:30:56 PM PDT 24
Peak memory 233420 kb
Host smart-e562af94-49e2-4cf5-b3d6-4d2da49c0793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755901002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2755901002
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.333974852
Short name T775
Test name
Test status
Simulation time 6584742972 ps
CPU time 12.21 seconds
Started Aug 13 04:30:53 PM PDT 24
Finished Aug 13 04:31:05 PM PDT 24
Peak memory 234588 kb
Host smart-ca63fa11-3f1e-4587-9362-dc0f4ee920b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333974852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.333974852
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.850826827
Short name T75
Test name
Test status
Simulation time 86099777 ps
CPU time 1.13 seconds
Started Aug 13 04:30:51 PM PDT 24
Finished Aug 13 04:30:53 PM PDT 24
Peak memory 236436 kb
Host smart-e328b655-5397-4e5e-b9d5-fa807fa73355
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850826827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.850826827
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2016260131
Short name T675
Test name
Test status
Simulation time 18810267036 ps
CPU time 22.87 seconds
Started Aug 13 04:30:52 PM PDT 24
Finished Aug 13 04:31:15 PM PDT 24
Peak memory 217212 kb
Host smart-099d21e1-325e-4a7f-a669-7cd692d6f4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016260131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2016260131
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1238655459
Short name T843
Test name
Test status
Simulation time 10921836 ps
CPU time 0.65 seconds
Started Aug 13 04:30:43 PM PDT 24
Finished Aug 13 04:30:44 PM PDT 24
Peak memory 206320 kb
Host smart-1c60bbbb-e3ec-42b5-866f-6b98c6cf2224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238655459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1238655459
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1655871900
Short name T411
Test name
Test status
Simulation time 588719464 ps
CPU time 6.24 seconds
Started Aug 13 04:30:49 PM PDT 24
Finished Aug 13 04:30:55 PM PDT 24
Peak memory 216952 kb
Host smart-f1423826-a515-483d-a672-07f6f428926f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655871900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1655871900
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3612839612
Short name T160
Test name
Test status
Simulation time 16943105 ps
CPU time 0.76 seconds
Started Aug 13 04:30:51 PM PDT 24
Finished Aug 13 04:30:52 PM PDT 24
Peak memory 206708 kb
Host smart-7e54bb8b-0cd6-4bdb-9e42-3251a0d6d03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612839612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3612839612
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3179098247
Short name T957
Test name
Test status
Simulation time 355966309 ps
CPU time 2.39 seconds
Started Aug 13 04:30:48 PM PDT 24
Finished Aug 13 04:30:51 PM PDT 24
Peak memory 225220 kb
Host smart-50b56dd3-5044-4253-9921-9fb004f17fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179098247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3179098247
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1402422910
Short name T766
Test name
Test status
Simulation time 77420931 ps
CPU time 0.72 seconds
Started Aug 13 04:31:24 PM PDT 24
Finished Aug 13 04:31:25 PM PDT 24
Peak memory 205600 kb
Host smart-eb8ea04f-3bd0-404e-92d8-506f633a3ae7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402422910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1402422910
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.19786298
Short name T433
Test name
Test status
Simulation time 1412462093 ps
CPU time 9.67 seconds
Started Aug 13 04:31:26 PM PDT 24
Finished Aug 13 04:31:36 PM PDT 24
Peak memory 225180 kb
Host smart-528b6666-668d-494a-be7a-8afdf590b2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19786298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.19786298
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3187266976
Short name T880
Test name
Test status
Simulation time 50527448 ps
CPU time 0.76 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:31:09 PM PDT 24
Peak memory 207544 kb
Host smart-c9363c1c-183d-4b2c-82d5-707258069f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187266976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3187266976
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3004815745
Short name T165
Test name
Test status
Simulation time 75044594866 ps
CPU time 163.35 seconds
Started Aug 13 04:31:06 PM PDT 24
Finished Aug 13 04:33:49 PM PDT 24
Peak memory 267176 kb
Host smart-55c5edf6-fa96-477b-98d5-f06f6ad9757b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004815745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3004815745
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2769686186
Short name T595
Test name
Test status
Simulation time 15166784973 ps
CPU time 23.97 seconds
Started Aug 13 04:31:18 PM PDT 24
Finished Aug 13 04:31:42 PM PDT 24
Peak memory 218712 kb
Host smart-aa378009-bec6-40e5-88e7-cfa6d12c847d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769686186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2769686186
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.378421679
Short name T876
Test name
Test status
Simulation time 495593639 ps
CPU time 9.59 seconds
Started Aug 13 04:31:24 PM PDT 24
Finished Aug 13 04:31:34 PM PDT 24
Peak memory 225212 kb
Host smart-bd92df68-78a4-4a7d-91b3-850fd8bcb6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378421679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.378421679
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.746344702
Short name T910
Test name
Test status
Simulation time 26033238408 ps
CPU time 53.43 seconds
Started Aug 13 04:31:29 PM PDT 24
Finished Aug 13 04:32:22 PM PDT 24
Peak memory 238132 kb
Host smart-1557b5e6-38d3-4a34-b23b-2dbfd90d4fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746344702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.746344702
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3427344845
Short name T197
Test name
Test status
Simulation time 1581713490 ps
CPU time 10.29 seconds
Started Aug 13 04:31:12 PM PDT 24
Finished Aug 13 04:31:23 PM PDT 24
Peak memory 225188 kb
Host smart-f09854b6-f7e1-4fd8-b0cc-6f468efe8698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427344845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3427344845
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2778398803
Short name T996
Test name
Test status
Simulation time 2867271642 ps
CPU time 11.6 seconds
Started Aug 13 04:31:04 PM PDT 24
Finished Aug 13 04:31:16 PM PDT 24
Peak memory 250808 kb
Host smart-84815a38-801b-43b9-9a38-280e283c83cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778398803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2778398803
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.384688106
Short name T729
Test name
Test status
Simulation time 791818201 ps
CPU time 5.62 seconds
Started Aug 13 04:31:04 PM PDT 24
Finished Aug 13 04:31:09 PM PDT 24
Peak memory 241496 kb
Host smart-f3642007-56d3-46a8-8cea-4673226a7011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384688106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.384688106
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3380538193
Short name T682
Test name
Test status
Simulation time 1592438877 ps
CPU time 5.59 seconds
Started Aug 13 04:31:29 PM PDT 24
Finished Aug 13 04:31:34 PM PDT 24
Peak memory 233368 kb
Host smart-0eb24db4-3515-4a31-9e96-c57ab73be747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380538193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3380538193
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3719602802
Short name T629
Test name
Test status
Simulation time 844757902 ps
CPU time 5.97 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:12 PM PDT 24
Peak memory 223328 kb
Host smart-c3c68210-44d7-4a7a-91ef-9801999d7c21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3719602802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3719602802
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3239779643
Short name T918
Test name
Test status
Simulation time 15386629176 ps
CPU time 21.93 seconds
Started Aug 13 04:31:07 PM PDT 24
Finished Aug 13 04:31:29 PM PDT 24
Peak memory 217360 kb
Host smart-76a51ca1-ce78-4c85-aad8-86a91003873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239779643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3239779643
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1645360529
Short name T687
Test name
Test status
Simulation time 1569422847 ps
CPU time 4.58 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:10 PM PDT 24
Peak memory 217072 kb
Host smart-9d644f7e-3822-40b5-8b04-54fcc3481d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645360529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1645360529
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1640059767
Short name T637
Test name
Test status
Simulation time 25768775 ps
CPU time 0.94 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:06 PM PDT 24
Peak memory 207352 kb
Host smart-8e9faee5-050b-498f-a281-f2a9cb69d56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640059767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1640059767
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1312831392
Short name T670
Test name
Test status
Simulation time 14841090 ps
CPU time 0.68 seconds
Started Aug 13 04:31:13 PM PDT 24
Finished Aug 13 04:31:14 PM PDT 24
Peak memory 206324 kb
Host smart-ba5d7665-2a31-4d0a-afbc-edfd695d82bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312831392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1312831392
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3620118316
Short name T846
Test name
Test status
Simulation time 5343324851 ps
CPU time 17.19 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:23 PM PDT 24
Peak memory 235296 kb
Host smart-66c95933-66db-4653-8787-a43e369f30ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620118316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3620118316
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.4199750887
Short name T905
Test name
Test status
Simulation time 108693019 ps
CPU time 0.73 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:06 PM PDT 24
Peak memory 206128 kb
Host smart-cfa8b4d7-04c7-4167-a7f6-868722dc3001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199750887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4199750887
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1456965969
Short name T751
Test name
Test status
Simulation time 547610171 ps
CPU time 2.45 seconds
Started Aug 13 04:31:04 PM PDT 24
Finished Aug 13 04:31:07 PM PDT 24
Peak memory 225208 kb
Host smart-4e96457f-7421-44f2-a54a-cc71932a1da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456965969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1456965969
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3685455182
Short name T82
Test name
Test status
Simulation time 14415601 ps
CPU time 0.78 seconds
Started Aug 13 04:31:14 PM PDT 24
Finished Aug 13 04:31:15 PM PDT 24
Peak memory 207276 kb
Host smart-030d34d0-ef1c-42fc-a34d-c27c79ce95d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685455182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3685455182
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1846129327
Short name T793
Test name
Test status
Simulation time 88969305161 ps
CPU time 202.59 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:34:31 PM PDT 24
Peak memory 256920 kb
Host smart-7972beed-faaa-4f8f-93cd-8e64ec071580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846129327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1846129327
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2160845529
Short name T989
Test name
Test status
Simulation time 4266874407 ps
CPU time 78.18 seconds
Started Aug 13 04:31:24 PM PDT 24
Finished Aug 13 04:32:42 PM PDT 24
Peak memory 257640 kb
Host smart-0fe87532-8d3d-4a78-830f-555c8aca08da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160845529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2160845529
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.984712749
Short name T901
Test name
Test status
Simulation time 124709474195 ps
CPU time 254.69 seconds
Started Aug 13 04:31:22 PM PDT 24
Finished Aug 13 04:35:37 PM PDT 24
Peak memory 249140 kb
Host smart-acbf5dc1-785d-48c4-afbe-8403cbd3fa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984712749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.984712749
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3526975891
Short name T887
Test name
Test status
Simulation time 232496483 ps
CPU time 5.68 seconds
Started Aug 13 04:31:10 PM PDT 24
Finished Aug 13 04:31:16 PM PDT 24
Peak memory 233436 kb
Host smart-9995b98d-c9ff-4208-892a-be7b1515c276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526975891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3526975891
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.348531783
Short name T259
Test name
Test status
Simulation time 4448663405 ps
CPU time 62.38 seconds
Started Aug 13 04:31:27 PM PDT 24
Finished Aug 13 04:32:34 PM PDT 24
Peak memory 250136 kb
Host smart-b085585c-14c5-40b3-be26-5f4829b7fc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348531783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.348531783
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.4029347300
Short name T553
Test name
Test status
Simulation time 6956943301 ps
CPU time 11.89 seconds
Started Aug 13 04:31:17 PM PDT 24
Finished Aug 13 04:31:29 PM PDT 24
Peak memory 225368 kb
Host smart-7181bfb2-bd54-409e-9552-231796c42302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029347300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4029347300
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.434305089
Short name T568
Test name
Test status
Simulation time 5391962747 ps
CPU time 37.44 seconds
Started Aug 13 04:31:18 PM PDT 24
Finished Aug 13 04:31:56 PM PDT 24
Peak memory 234656 kb
Host smart-b7487704-ad14-4598-ae15-5e70183375eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434305089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.434305089
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1719546128
Short name T591
Test name
Test status
Simulation time 5090300539 ps
CPU time 16.71 seconds
Started Aug 13 04:31:27 PM PDT 24
Finished Aug 13 04:31:43 PM PDT 24
Peak memory 233564 kb
Host smart-e386f323-22c8-43cb-bdcc-3daac90dc329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719546128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1719546128
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3126377386
Short name T48
Test name
Test status
Simulation time 816439314 ps
CPU time 3.88 seconds
Started Aug 13 04:31:18 PM PDT 24
Finished Aug 13 04:31:22 PM PDT 24
Peak memory 225276 kb
Host smart-064430be-5a66-4b2b-94a0-f0eb348e1e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126377386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3126377386
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.432373085
Short name T415
Test name
Test status
Simulation time 2928626592 ps
CPU time 5.6 seconds
Started Aug 13 04:31:04 PM PDT 24
Finished Aug 13 04:31:09 PM PDT 24
Peak memory 221532 kb
Host smart-65aaad16-000c-4af1-858c-42b523963780
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=432373085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.432373085
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3288977975
Short name T605
Test name
Test status
Simulation time 52672359 ps
CPU time 1 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:06 PM PDT 24
Peak memory 208184 kb
Host smart-6c4fe23f-1af0-40fb-8475-d31137abadd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288977975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3288977975
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3162334112
Short name T332
Test name
Test status
Simulation time 321264576 ps
CPU time 2.18 seconds
Started Aug 13 04:31:18 PM PDT 24
Finished Aug 13 04:31:20 PM PDT 24
Peak memory 217076 kb
Host smart-1f2e58fc-3cdf-45f3-88a4-78c3ef2b6c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162334112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3162334112
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3151718058
Short name T380
Test name
Test status
Simulation time 250728037 ps
CPU time 2.08 seconds
Started Aug 13 04:31:06 PM PDT 24
Finished Aug 13 04:31:09 PM PDT 24
Peak memory 217028 kb
Host smart-e9edac01-5305-4627-9eb3-f8f2fc4338e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151718058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3151718058
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1935833079
Short name T953
Test name
Test status
Simulation time 111438844 ps
CPU time 0.89 seconds
Started Aug 13 04:31:21 PM PDT 24
Finished Aug 13 04:31:22 PM PDT 24
Peak memory 207776 kb
Host smart-51320c83-61c3-4007-9d3d-4c70936d774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935833079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1935833079
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.125633100
Short name T952
Test name
Test status
Simulation time 709131206 ps
CPU time 4.87 seconds
Started Aug 13 04:31:29 PM PDT 24
Finished Aug 13 04:31:34 PM PDT 24
Peak memory 225272 kb
Host smart-faf4bc54-7670-4d10-b20c-ce3f036f477d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125633100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.125633100
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1247798370
Short name T847
Test name
Test status
Simulation time 15572099 ps
CPU time 0.71 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:31:08 PM PDT 24
Peak memory 206420 kb
Host smart-b51ba805-133f-45bc-a647-66d30932a538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247798370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1247798370
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2259314276
Short name T506
Test name
Test status
Simulation time 493583652 ps
CPU time 3.59 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:31:12 PM PDT 24
Peak memory 225296 kb
Host smart-b6c67d5f-f345-4a74-8044-69b4ae0adf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259314276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2259314276
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.492008170
Short name T315
Test name
Test status
Simulation time 37570683 ps
CPU time 0.75 seconds
Started Aug 13 04:31:24 PM PDT 24
Finished Aug 13 04:31:25 PM PDT 24
Peak memory 207428 kb
Host smart-36129d4d-c763-4d51-be12-6cad50c5dd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492008170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.492008170
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1435274987
Short name T223
Test name
Test status
Simulation time 9489069799 ps
CPU time 59.77 seconds
Started Aug 13 04:31:06 PM PDT 24
Finished Aug 13 04:32:06 PM PDT 24
Peak memory 256448 kb
Host smart-74011a59-b7a2-43dd-a52d-22a1f1d0a19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435274987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1435274987
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3040872468
Short name T269
Test name
Test status
Simulation time 2890926538 ps
CPU time 67.05 seconds
Started Aug 13 04:31:24 PM PDT 24
Finished Aug 13 04:32:36 PM PDT 24
Peak memory 250324 kb
Host smart-f984b13a-8352-4a84-ab24-32cfe5904ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040872468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3040872468
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3777892061
Short name T873
Test name
Test status
Simulation time 378058735 ps
CPU time 7.08 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:13 PM PDT 24
Peak memory 225268 kb
Host smart-7b74d08a-089e-4562-a1c7-0cd47773f5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777892061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3777892061
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1305973033
Short name T589
Test name
Test status
Simulation time 5349043649 ps
CPU time 69.64 seconds
Started Aug 13 04:31:12 PM PDT 24
Finished Aug 13 04:32:21 PM PDT 24
Peak memory 255012 kb
Host smart-28ee6888-f6d3-4f27-be97-7367a4def853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305973033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1305973033
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2641004168
Short name T941
Test name
Test status
Simulation time 2744255711 ps
CPU time 6.16 seconds
Started Aug 13 04:31:06 PM PDT 24
Finished Aug 13 04:31:12 PM PDT 24
Peak memory 225244 kb
Host smart-ef3f6768-a66b-4e4f-a993-20721b6535dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641004168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2641004168
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2114623395
Short name T446
Test name
Test status
Simulation time 1020637312 ps
CPU time 10 seconds
Started Aug 13 04:31:25 PM PDT 24
Finished Aug 13 04:31:35 PM PDT 24
Peak memory 225160 kb
Host smart-f98553da-486d-484a-adf3-548357f905fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114623395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2114623395
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1812559778
Short name T657
Test name
Test status
Simulation time 3977383825 ps
CPU time 11.05 seconds
Started Aug 13 04:31:10 PM PDT 24
Finished Aug 13 04:31:21 PM PDT 24
Peak memory 225252 kb
Host smart-1f25c1d0-2bf7-4545-a97c-ce9f2134559c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812559778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1812559778
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.704034710
Short name T636
Test name
Test status
Simulation time 3095190522 ps
CPU time 11.36 seconds
Started Aug 13 04:31:12 PM PDT 24
Finished Aug 13 04:31:23 PM PDT 24
Peak memory 225348 kb
Host smart-e27ffb4c-bfb2-422a-93fd-1440c4666ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704034710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.704034710
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.906337470
Short name T549
Test name
Test status
Simulation time 2729298116 ps
CPU time 6.45 seconds
Started Aug 13 04:31:09 PM PDT 24
Finished Aug 13 04:31:15 PM PDT 24
Peak memory 223964 kb
Host smart-63a2964e-415b-453b-9243-19c023b6a83d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=906337470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.906337470
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.357994679
Short name T879
Test name
Test status
Simulation time 258083931 ps
CPU time 0.93 seconds
Started Aug 13 04:31:27 PM PDT 24
Finished Aug 13 04:31:28 PM PDT 24
Peak memory 208504 kb
Host smart-7d9c033e-b5db-4ec5-93ca-a414a4e7d336
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357994679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.357994679
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.867970037
Short name T792
Test name
Test status
Simulation time 625913054 ps
CPU time 9.72 seconds
Started Aug 13 04:31:27 PM PDT 24
Finished Aug 13 04:31:37 PM PDT 24
Peak memory 217152 kb
Host smart-3deaca42-3f80-4cf2-aba1-f2562d4909fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867970037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.867970037
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1942270930
Short name T76
Test name
Test status
Simulation time 7147260846 ps
CPU time 6.98 seconds
Started Aug 13 04:31:19 PM PDT 24
Finished Aug 13 04:31:26 PM PDT 24
Peak memory 217164 kb
Host smart-200c5ccc-4c2b-42f0-b62c-1b283de70d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942270930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1942270930
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3039055258
Short name T965
Test name
Test status
Simulation time 43398799 ps
CPU time 1.88 seconds
Started Aug 13 04:31:09 PM PDT 24
Finished Aug 13 04:31:11 PM PDT 24
Peak memory 217092 kb
Host smart-72506e84-a87e-49e0-8ea0-36f4ac6122d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039055258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3039055258
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2640594504
Short name T386
Test name
Test status
Simulation time 19213469 ps
CPU time 0.76 seconds
Started Aug 13 04:31:29 PM PDT 24
Finished Aug 13 04:31:30 PM PDT 24
Peak memory 206724 kb
Host smart-d7a78179-8a6f-44d2-a3ef-060e83884be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640594504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2640594504
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1965891076
Short name T757
Test name
Test status
Simulation time 1724399093 ps
CPU time 10.13 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:31:18 PM PDT 24
Peak memory 233460 kb
Host smart-2bf7385c-40c9-4027-87db-c00ef458f9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965891076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1965891076
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2328808399
Short name T357
Test name
Test status
Simulation time 58290537 ps
CPU time 0.72 seconds
Started Aug 13 04:31:43 PM PDT 24
Finished Aug 13 04:31:44 PM PDT 24
Peak memory 205612 kb
Host smart-96f5aa2b-04ee-4ed2-a453-6ae6baa243c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328808399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2328808399
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1789554794
Short name T472
Test name
Test status
Simulation time 720823157 ps
CPU time 4.82 seconds
Started Aug 13 04:31:28 PM PDT 24
Finished Aug 13 04:31:33 PM PDT 24
Peak memory 233460 kb
Host smart-213b55ff-ce56-438f-a086-c5066c673008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789554794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1789554794
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.632437525
Short name T437
Test name
Test status
Simulation time 80086058 ps
CPU time 0.78 seconds
Started Aug 13 04:31:06 PM PDT 24
Finished Aug 13 04:31:07 PM PDT 24
Peak memory 207348 kb
Host smart-8e5cc3d6-f477-4cda-aea5-ab6152eb53fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632437525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.632437525
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2236258776
Short name T216
Test name
Test status
Simulation time 46338842736 ps
CPU time 150.63 seconds
Started Aug 13 04:31:46 PM PDT 24
Finished Aug 13 04:34:17 PM PDT 24
Peak memory 273272 kb
Host smart-e2694bac-e673-4b90-a509-affc2a0bc19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236258776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2236258776
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2641570666
Short name T774
Test name
Test status
Simulation time 6131163162 ps
CPU time 66.31 seconds
Started Aug 13 04:31:27 PM PDT 24
Finished Aug 13 04:32:39 PM PDT 24
Peak memory 240272 kb
Host smart-0497da7e-1558-4ec7-a177-6ef9c71d1fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641570666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2641570666
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3105830418
Short name T528
Test name
Test status
Simulation time 8547327225 ps
CPU time 60.37 seconds
Started Aug 13 04:31:31 PM PDT 24
Finished Aug 13 04:32:32 PM PDT 24
Peak memory 249988 kb
Host smart-4fa2794b-22f0-47d1-b5f8-c493434880bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105830418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3105830418
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3527745709
Short name T268
Test name
Test status
Simulation time 2789126317 ps
CPU time 9.26 seconds
Started Aug 13 04:31:33 PM PDT 24
Finished Aug 13 04:31:43 PM PDT 24
Peak memory 233600 kb
Host smart-cbf2341c-7731-4892-96fd-d2cd7ac5bf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527745709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3527745709
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.52583309
Short name T706
Test name
Test status
Simulation time 498717031 ps
CPU time 10.97 seconds
Started Aug 13 04:31:35 PM PDT 24
Finished Aug 13 04:31:46 PM PDT 24
Peak memory 234728 kb
Host smart-38e0ca5f-e931-4b13-982a-575983c011bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52583309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.52583309
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2505684357
Short name T81
Test name
Test status
Simulation time 2778610870 ps
CPU time 11.1 seconds
Started Aug 13 04:31:15 PM PDT 24
Finished Aug 13 04:31:27 PM PDT 24
Peak memory 233684 kb
Host smart-e064fb79-c224-4923-98d7-d36d49a1eafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505684357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2505684357
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.278234498
Short name T180
Test name
Test status
Simulation time 1871944366 ps
CPU time 8.03 seconds
Started Aug 13 04:31:18 PM PDT 24
Finished Aug 13 04:31:26 PM PDT 24
Peak memory 233428 kb
Host smart-598d0183-d0b3-4093-8ca3-011f0ba279d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278234498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.278234498
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1412056195
Short name T983
Test name
Test status
Simulation time 231145790 ps
CPU time 4.52 seconds
Started Aug 13 04:31:32 PM PDT 24
Finished Aug 13 04:31:36 PM PDT 24
Peak memory 223880 kb
Host smart-ff05e26c-59f9-4757-9d2b-3fcc500638fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1412056195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1412056195
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1540758800
Short name T593
Test name
Test status
Simulation time 36319731449 ps
CPU time 167.47 seconds
Started Aug 13 04:31:43 PM PDT 24
Finished Aug 13 04:34:31 PM PDT 24
Peak memory 251608 kb
Host smart-d5ea126f-3950-4700-a1ec-8fc61b56523d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540758800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1540758800
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2977934966
Short name T623
Test name
Test status
Simulation time 15325311098 ps
CPU time 26.66 seconds
Started Aug 13 04:31:43 PM PDT 24
Finished Aug 13 04:32:10 PM PDT 24
Peak memory 217256 kb
Host smart-b3538dcc-87c3-4d79-ad32-ab7c333cb949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977934966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2977934966
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1689724700
Short name T27
Test name
Test status
Simulation time 14589221 ps
CPU time 0.67 seconds
Started Aug 13 04:31:32 PM PDT 24
Finished Aug 13 04:31:33 PM PDT 24
Peak memory 206416 kb
Host smart-8fc9dee1-025a-4409-9d7a-b0950ad1741d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689724700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1689724700
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3689184478
Short name T343
Test name
Test status
Simulation time 46408129 ps
CPU time 0.82 seconds
Started Aug 13 04:31:36 PM PDT 24
Finished Aug 13 04:31:37 PM PDT 24
Peak memory 206748 kb
Host smart-463da396-af25-42eb-b181-61c541739f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689184478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3689184478
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2441975056
Short name T993
Test name
Test status
Simulation time 234219200 ps
CPU time 0.89 seconds
Started Aug 13 04:31:39 PM PDT 24
Finished Aug 13 04:31:40 PM PDT 24
Peak memory 206720 kb
Host smart-58dbdc11-f316-46ef-b003-af1e985e169c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441975056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2441975056
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1356241058
Short name T460
Test name
Test status
Simulation time 3171475422 ps
CPU time 7.02 seconds
Started Aug 13 04:31:40 PM PDT 24
Finished Aug 13 04:31:47 PM PDT 24
Peak memory 233628 kb
Host smart-7e36d1d9-128c-48bf-9740-15669bc20cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356241058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1356241058
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.191560911
Short name T840
Test name
Test status
Simulation time 19393306 ps
CPU time 0.71 seconds
Started Aug 13 04:31:35 PM PDT 24
Finished Aug 13 04:31:36 PM PDT 24
Peak memory 205608 kb
Host smart-c16bc72d-01ad-435c-ad12-6384c20a95e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191560911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.191560911
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1837209546
Short name T644
Test name
Test status
Simulation time 150205793 ps
CPU time 5.01 seconds
Started Aug 13 04:31:29 PM PDT 24
Finished Aug 13 04:31:35 PM PDT 24
Peak memory 225220 kb
Host smart-91309a21-3e1a-4fa1-a3af-a8c2c1e50939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837209546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1837209546
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2391870997
Short name T689
Test name
Test status
Simulation time 20835985 ps
CPU time 0.8 seconds
Started Aug 13 04:31:35 PM PDT 24
Finished Aug 13 04:31:36 PM PDT 24
Peak memory 207008 kb
Host smart-129193e1-e0c3-4688-b1a1-68e8d85ee62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391870997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2391870997
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3782241755
Short name T600
Test name
Test status
Simulation time 963762617 ps
CPU time 19.59 seconds
Started Aug 13 04:31:31 PM PDT 24
Finished Aug 13 04:31:51 PM PDT 24
Peak memory 241680 kb
Host smart-37898a21-851a-4c53-a099-d31f661ae195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782241755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3782241755
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2834944565
Short name T187
Test name
Test status
Simulation time 10808351370 ps
CPU time 102.77 seconds
Started Aug 13 04:31:32 PM PDT 24
Finished Aug 13 04:33:15 PM PDT 24
Peak memory 267072 kb
Host smart-25c854b2-ca95-4b9b-b0bc-d582043570c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834944565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2834944565
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3312311854
Short name T173
Test name
Test status
Simulation time 20297749630 ps
CPU time 148.44 seconds
Started Aug 13 04:31:47 PM PDT 24
Finished Aug 13 04:34:16 PM PDT 24
Peak memory 255836 kb
Host smart-f42eba33-15c6-4340-89bf-1451f2109896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312311854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3312311854
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.4000386847
Short name T199
Test name
Test status
Simulation time 1407804122 ps
CPU time 9.05 seconds
Started Aug 13 04:31:45 PM PDT 24
Finished Aug 13 04:31:54 PM PDT 24
Peak memory 233492 kb
Host smart-aacb75ae-8be2-48e1-9b24-98e133cc3ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000386847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4000386847
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3394820530
Short name T452
Test name
Test status
Simulation time 643992977 ps
CPU time 5.28 seconds
Started Aug 13 04:31:24 PM PDT 24
Finished Aug 13 04:31:29 PM PDT 24
Peak memory 225220 kb
Host smart-e9066d24-2bf0-4d7e-9b41-846056687a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394820530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3394820530
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4246441645
Short name T182
Test name
Test status
Simulation time 400839730 ps
CPU time 6.74 seconds
Started Aug 13 04:31:29 PM PDT 24
Finished Aug 13 04:31:36 PM PDT 24
Peak memory 233516 kb
Host smart-ffe847bc-8c93-4b62-975d-6234c93b2478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246441645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4246441645
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3202887425
Short name T986
Test name
Test status
Simulation time 4784527285 ps
CPU time 15.22 seconds
Started Aug 13 04:31:26 PM PDT 24
Finished Aug 13 04:31:42 PM PDT 24
Peak memory 225344 kb
Host smart-4050e8d3-fd72-43a3-91f1-cb05e68e56ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202887425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3202887425
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.934759601
Short name T139
Test name
Test status
Simulation time 184875998 ps
CPU time 3.72 seconds
Started Aug 13 04:31:50 PM PDT 24
Finished Aug 13 04:31:54 PM PDT 24
Peak memory 223872 kb
Host smart-fb63b610-cd7b-4623-aec4-3901ec985112
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=934759601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.934759601
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1928370214
Short name T769
Test name
Test status
Simulation time 18953636732 ps
CPU time 276.21 seconds
Started Aug 13 04:31:34 PM PDT 24
Finished Aug 13 04:36:10 PM PDT 24
Peak memory 274704 kb
Host smart-b3f5bbf2-8dcd-465a-a31e-5297556f10e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928370214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1928370214
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1420041672
Short name T824
Test name
Test status
Simulation time 6672769694 ps
CPU time 29.75 seconds
Started Aug 13 04:31:23 PM PDT 24
Finished Aug 13 04:31:53 PM PDT 24
Peak memory 217336 kb
Host smart-608f97ad-4b5c-4f5f-b9b9-24c077c9e77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420041672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1420041672
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2573771050
Short name T432
Test name
Test status
Simulation time 2699772190 ps
CPU time 8.65 seconds
Started Aug 13 04:31:35 PM PDT 24
Finished Aug 13 04:31:44 PM PDT 24
Peak memory 217108 kb
Host smart-8993397c-ba33-44ff-b0ef-2eb4e0316896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573771050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2573771050
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2486648219
Short name T663
Test name
Test status
Simulation time 51126455 ps
CPU time 0.88 seconds
Started Aug 13 04:31:33 PM PDT 24
Finished Aug 13 04:31:34 PM PDT 24
Peak memory 207724 kb
Host smart-01fb445a-7a23-4d2e-bd76-bfc9dc1add4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486648219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2486648219
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3114800970
Short name T852
Test name
Test status
Simulation time 138691778 ps
CPU time 0.94 seconds
Started Aug 13 04:31:28 PM PDT 24
Finished Aug 13 04:31:29 PM PDT 24
Peak memory 206716 kb
Host smart-d72776fc-4be7-40bf-9343-12de3cfe82fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114800970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3114800970
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.576896847
Short name T992
Test name
Test status
Simulation time 2044302677 ps
CPU time 9.45 seconds
Started Aug 13 04:31:24 PM PDT 24
Finished Aug 13 04:31:34 PM PDT 24
Peak memory 235496 kb
Host smart-5e35afe8-f044-49b4-882a-4e101e43ce43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576896847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.576896847
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1596157040
Short name T997
Test name
Test status
Simulation time 199810712 ps
CPU time 0.71 seconds
Started Aug 13 04:31:35 PM PDT 24
Finished Aug 13 04:31:35 PM PDT 24
Peak memory 206452 kb
Host smart-2aaef058-ade9-4649-aaf4-3779ed563617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596157040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1596157040
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1285344306
Short name T477
Test name
Test status
Simulation time 75134070 ps
CPU time 2.27 seconds
Started Aug 13 04:31:35 PM PDT 24
Finished Aug 13 04:31:37 PM PDT 24
Peak memory 225236 kb
Host smart-9d0e7e18-c43e-46bf-8757-06d9e24440f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285344306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1285344306
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.4101831990
Short name T164
Test name
Test status
Simulation time 104087990 ps
CPU time 0.79 seconds
Started Aug 13 04:31:35 PM PDT 24
Finished Aug 13 04:31:36 PM PDT 24
Peak memory 207292 kb
Host smart-aec0bf7d-3486-4a7d-a540-a4cdf2ccb299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101831990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4101831990
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3368873234
Short name T896
Test name
Test status
Simulation time 93181383012 ps
CPU time 165.88 seconds
Started Aug 13 04:31:47 PM PDT 24
Finished Aug 13 04:34:33 PM PDT 24
Peak memory 251520 kb
Host smart-3ab2e8d3-4378-4953-b74b-026ca70c6101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368873234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3368873234
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.434577216
Short name T833
Test name
Test status
Simulation time 68665748849 ps
CPU time 234.89 seconds
Started Aug 13 04:31:36 PM PDT 24
Finished Aug 13 04:35:32 PM PDT 24
Peak memory 265852 kb
Host smart-ce9ec90c-3754-412f-8b0b-024631132fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434577216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.434577216
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.4229048172
Short name T972
Test name
Test status
Simulation time 82814163623 ps
CPU time 276.35 seconds
Started Aug 13 04:31:46 PM PDT 24
Finished Aug 13 04:36:22 PM PDT 24
Peak memory 269772 kb
Host smart-3c328e10-02a5-4ffa-91ff-58b49b589125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229048172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.4229048172
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.39674976
Short name T895
Test name
Test status
Simulation time 2162913628 ps
CPU time 32.52 seconds
Started Aug 13 04:31:49 PM PDT 24
Finished Aug 13 04:32:22 PM PDT 24
Peak memory 233580 kb
Host smart-51f1dcdb-5b34-4856-8da6-9cf0e8cb20c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39674976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.39674976
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2001325852
Short name T213
Test name
Test status
Simulation time 28937474388 ps
CPU time 160.67 seconds
Started Aug 13 04:31:24 PM PDT 24
Finished Aug 13 04:34:04 PM PDT 24
Peak memory 256968 kb
Host smart-e46fec5a-fc37-4bf8-99f7-185aa786f9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001325852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2001325852
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.4231609149
Short name T538
Test name
Test status
Simulation time 449056752 ps
CPU time 4.33 seconds
Started Aug 13 04:31:46 PM PDT 24
Finished Aug 13 04:31:51 PM PDT 24
Peak memory 225268 kb
Host smart-639555f5-cb45-420f-834f-8ce84a634ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231609149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.4231609149
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.943279802
Short name T618
Test name
Test status
Simulation time 163010385 ps
CPU time 2.16 seconds
Started Aug 13 04:31:35 PM PDT 24
Finished Aug 13 04:31:38 PM PDT 24
Peak memory 224956 kb
Host smart-d4dfec2a-ba6d-45e3-89d7-2f0564f12a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943279802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.943279802
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2754309653
Short name T230
Test name
Test status
Simulation time 13095518326 ps
CPU time 11.03 seconds
Started Aug 13 04:31:45 PM PDT 24
Finished Aug 13 04:31:57 PM PDT 24
Peak memory 225332 kb
Host smart-404e5591-61c8-427a-bd96-d485d10d2aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754309653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2754309653
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2907627758
Short name T462
Test name
Test status
Simulation time 368353070 ps
CPU time 6.02 seconds
Started Aug 13 04:31:38 PM PDT 24
Finished Aug 13 04:31:44 PM PDT 24
Peak memory 225220 kb
Host smart-d4839cb6-1c38-4046-a780-c21236a9691c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907627758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2907627758
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1336302912
Short name T805
Test name
Test status
Simulation time 6548827429 ps
CPU time 20.44 seconds
Started Aug 13 04:31:25 PM PDT 24
Finished Aug 13 04:31:45 PM PDT 24
Peak memory 224128 kb
Host smart-bc9b3f45-02d2-4c92-926c-2439d3b8ad16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1336302912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1336302912
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.297297360
Short name T764
Test name
Test status
Simulation time 14297289630 ps
CPU time 166.42 seconds
Started Aug 13 04:31:45 PM PDT 24
Finished Aug 13 04:34:31 PM PDT 24
Peak memory 271984 kb
Host smart-522617a2-d198-40a3-9147-ef68a50a69f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297297360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.297297360
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3884657373
Short name T872
Test name
Test status
Simulation time 1872810555 ps
CPU time 22.52 seconds
Started Aug 13 04:31:45 PM PDT 24
Finished Aug 13 04:32:07 PM PDT 24
Peak memory 217248 kb
Host smart-03048014-af5f-452c-928d-2b604e0ab75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884657373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3884657373
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2306697037
Short name T909
Test name
Test status
Simulation time 5076362377 ps
CPU time 7.8 seconds
Started Aug 13 04:31:46 PM PDT 24
Finished Aug 13 04:31:54 PM PDT 24
Peak memory 217200 kb
Host smart-e8fb7601-d199-4da8-9d88-a01b2ee0005c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306697037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2306697037
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2262777463
Short name T938
Test name
Test status
Simulation time 62204792 ps
CPU time 1.62 seconds
Started Aug 13 04:31:32 PM PDT 24
Finished Aug 13 04:31:34 PM PDT 24
Peak memory 217104 kb
Host smart-30398ba9-3c57-476d-acd7-624dad637bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262777463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2262777463
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1768012871
Short name T868
Test name
Test status
Simulation time 446094990 ps
CPU time 0.93 seconds
Started Aug 13 04:31:39 PM PDT 24
Finished Aug 13 04:31:41 PM PDT 24
Peak memory 207768 kb
Host smart-a00ead8a-6dc9-422b-869e-ba4a8aafe9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768012871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1768012871
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1204502058
Short name T416
Test name
Test status
Simulation time 79018113 ps
CPU time 2.04 seconds
Started Aug 13 04:31:31 PM PDT 24
Finished Aug 13 04:31:33 PM PDT 24
Peak memory 229256 kb
Host smart-aa1a3a25-7abc-489d-b5ac-24c377dba59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204502058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1204502058
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3062006875
Short name T461
Test name
Test status
Simulation time 17883281 ps
CPU time 0.72 seconds
Started Aug 13 04:31:40 PM PDT 24
Finished Aug 13 04:31:41 PM PDT 24
Peak memory 206140 kb
Host smart-8a83c965-26fa-4257-923d-61f8cc2bf0d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062006875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3062006875
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.633637699
Short name T275
Test name
Test status
Simulation time 472136358 ps
CPU time 3.02 seconds
Started Aug 13 04:31:36 PM PDT 24
Finished Aug 13 04:31:40 PM PDT 24
Peak memory 225260 kb
Host smart-5d63f3a6-0eb7-4f8a-9a4a-a157ceeeb2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633637699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.633637699
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.93704684
Short name T417
Test name
Test status
Simulation time 15720356 ps
CPU time 0.84 seconds
Started Aug 13 04:31:27 PM PDT 24
Finished Aug 13 04:31:28 PM PDT 24
Peak memory 207316 kb
Host smart-a1ac9cde-bee5-435b-bee2-bc8e560c36e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93704684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.93704684
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2676711240
Short name T857
Test name
Test status
Simulation time 32646288635 ps
CPU time 80.91 seconds
Started Aug 13 04:31:31 PM PDT 24
Finished Aug 13 04:32:52 PM PDT 24
Peak memory 240656 kb
Host smart-55f32271-2abe-4577-8925-912f03381b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676711240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2676711240
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.745555728
Short name T561
Test name
Test status
Simulation time 6511143334 ps
CPU time 19.79 seconds
Started Aug 13 04:31:46 PM PDT 24
Finished Aug 13 04:32:06 PM PDT 24
Peak memory 218628 kb
Host smart-e95b2e50-653e-4424-ae76-ae6076b22e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745555728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.745555728
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1462160187
Short name T289
Test name
Test status
Simulation time 822360400 ps
CPU time 4.59 seconds
Started Aug 13 04:31:45 PM PDT 24
Finished Aug 13 04:31:50 PM PDT 24
Peak memory 225336 kb
Host smart-c68f5d4d-291d-4d35-8c08-51ff831f6d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462160187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1462160187
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3494218258
Short name T243
Test name
Test status
Simulation time 152836615826 ps
CPU time 229.06 seconds
Started Aug 13 04:31:48 PM PDT 24
Finished Aug 13 04:35:37 PM PDT 24
Peak memory 249984 kb
Host smart-0aa94583-46b8-44cd-ab8a-e921b2a8dded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494218258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3494218258
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2636831057
Short name T206
Test name
Test status
Simulation time 430319062 ps
CPU time 7.2 seconds
Started Aug 13 04:32:13 PM PDT 24
Finished Aug 13 04:32:20 PM PDT 24
Peak memory 225272 kb
Host smart-61b47312-9ea0-428a-8669-8eb2c80b8fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636831057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2636831057
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.128008167
Short name T897
Test name
Test status
Simulation time 313603516 ps
CPU time 3.16 seconds
Started Aug 13 04:31:38 PM PDT 24
Finished Aug 13 04:31:41 PM PDT 24
Peak memory 225192 kb
Host smart-9228a503-37ce-4bd6-ad02-6a731b0e255e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128008167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.128008167
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.384349359
Short name T351
Test name
Test status
Simulation time 162066225 ps
CPU time 2.6 seconds
Started Aug 13 04:31:42 PM PDT 24
Finished Aug 13 04:31:45 PM PDT 24
Peak memory 233460 kb
Host smart-714bc1fc-0a1d-46d3-a45b-d11938de07d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384349359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.384349359
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2747513369
Short name T597
Test name
Test status
Simulation time 4905782865 ps
CPU time 5.26 seconds
Started Aug 13 04:31:44 PM PDT 24
Finished Aug 13 04:31:50 PM PDT 24
Peak memory 225316 kb
Host smart-60cff054-8edc-4080-9570-2fdc3cca7664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747513369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2747513369
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.343452998
Short name T527
Test name
Test status
Simulation time 6142834250 ps
CPU time 20.13 seconds
Started Aug 13 04:31:33 PM PDT 24
Finished Aug 13 04:31:53 PM PDT 24
Peak memory 219708 kb
Host smart-ec2fd9be-c339-4727-9a84-86bf06414d8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=343452998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.343452998
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2225323339
Short name T656
Test name
Test status
Simulation time 149977033 ps
CPU time 1.19 seconds
Started Aug 13 04:31:39 PM PDT 24
Finished Aug 13 04:31:40 PM PDT 24
Peak memory 207996 kb
Host smart-d3f5ee4f-d14f-40f4-a922-bb0cfc616cec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225323339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2225323339
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3971647214
Short name T412
Test name
Test status
Simulation time 27592283176 ps
CPU time 41.9 seconds
Started Aug 13 04:31:51 PM PDT 24
Finished Aug 13 04:32:33 PM PDT 24
Peak memory 217224 kb
Host smart-3c2b7203-0521-4a53-bd01-6edd38bef502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971647214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3971647214
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2744783311
Short name T341
Test name
Test status
Simulation time 118791758 ps
CPU time 1.75 seconds
Started Aug 13 04:31:34 PM PDT 24
Finished Aug 13 04:31:36 PM PDT 24
Peak memory 217012 kb
Host smart-013fa56a-f513-4578-97b2-39af0b362b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744783311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2744783311
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.263098052
Short name T158
Test name
Test status
Simulation time 43976123 ps
CPU time 0.7 seconds
Started Aug 13 04:32:02 PM PDT 24
Finished Aug 13 04:32:03 PM PDT 24
Peak memory 206304 kb
Host smart-fb496b5d-de06-44ec-913e-7707a075488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263098052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.263098052
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2768454783
Short name T975
Test name
Test status
Simulation time 1613811519 ps
CPU time 5.69 seconds
Started Aug 13 04:31:41 PM PDT 24
Finished Aug 13 04:31:47 PM PDT 24
Peak memory 225316 kb
Host smart-71634922-69eb-4f4e-9ca1-1f3e4075258d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768454783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2768454783
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.997535070
Short name T933
Test name
Test status
Simulation time 145115326 ps
CPU time 0.69 seconds
Started Aug 13 04:31:32 PM PDT 24
Finished Aug 13 04:31:33 PM PDT 24
Peak memory 206272 kb
Host smart-a4e87fd4-b2fa-42d8-a272-6ad53e22f538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997535070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.997535070
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1808013165
Short name T761
Test name
Test status
Simulation time 2532166855 ps
CPU time 10.94 seconds
Started Aug 13 04:32:03 PM PDT 24
Finished Aug 13 04:32:14 PM PDT 24
Peak memory 225436 kb
Host smart-b7be1b6a-3453-44a0-8ae8-3ffb02950ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808013165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1808013165
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3738753556
Short name T854
Test name
Test status
Simulation time 20352922 ps
CPU time 0.75 seconds
Started Aug 13 04:31:45 PM PDT 24
Finished Aug 13 04:31:46 PM PDT 24
Peak memory 207248 kb
Host smart-8354ef28-60ab-4ef3-8857-fa760f879596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738753556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3738753556
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2914692364
Short name T212
Test name
Test status
Simulation time 275379854620 ps
CPU time 463.55 seconds
Started Aug 13 04:31:39 PM PDT 24
Finished Aug 13 04:39:27 PM PDT 24
Peak memory 257504 kb
Host smart-108e82a4-11d0-4698-a237-d1f0fe9d769a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914692364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2914692364
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2998620084
Short name T762
Test name
Test status
Simulation time 26255980636 ps
CPU time 278.22 seconds
Started Aug 13 04:31:32 PM PDT 24
Finished Aug 13 04:36:10 PM PDT 24
Peak memory 252948 kb
Host smart-c315fa10-b94c-43fa-a2f3-7b76febde58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998620084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2998620084
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3899983902
Short name T294
Test name
Test status
Simulation time 8346048261 ps
CPU time 27.44 seconds
Started Aug 13 04:31:45 PM PDT 24
Finished Aug 13 04:32:12 PM PDT 24
Peak memory 225424 kb
Host smart-5de5bf26-f8bf-4936-8377-73cbe605b256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899983902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3899983902
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.378981130
Short name T799
Test name
Test status
Simulation time 1730027402 ps
CPU time 34.96 seconds
Started Aug 13 04:31:50 PM PDT 24
Finished Aug 13 04:32:26 PM PDT 24
Peak memory 252424 kb
Host smart-8b5a3d99-32b8-46dc-81cf-59cdd104f63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378981130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.378981130
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.741430416
Short name T995
Test name
Test status
Simulation time 504479258 ps
CPU time 4.47 seconds
Started Aug 13 04:31:49 PM PDT 24
Finished Aug 13 04:31:54 PM PDT 24
Peak memory 233472 kb
Host smart-68729d98-d682-48e0-bfe6-9c603187bf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741430416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.741430416
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.792409849
Short name T720
Test name
Test status
Simulation time 19181277774 ps
CPU time 41.1 seconds
Started Aug 13 04:31:47 PM PDT 24
Finished Aug 13 04:32:28 PM PDT 24
Peak memory 241704 kb
Host smart-2d5ddbf7-28ac-4f6f-be7c-1f75d99ddd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792409849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.792409849
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.4176572981
Short name T328
Test name
Test status
Simulation time 104758729 ps
CPU time 2.14 seconds
Started Aug 13 04:31:47 PM PDT 24
Finished Aug 13 04:31:49 PM PDT 24
Peak memory 223648 kb
Host smart-d062e902-dfd7-4694-9a52-8e4aeb8c5c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176572981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.4176572981
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.313789769
Short name T557
Test name
Test status
Simulation time 32215144 ps
CPU time 2.15 seconds
Started Aug 13 04:31:35 PM PDT 24
Finished Aug 13 04:31:37 PM PDT 24
Peak memory 223860 kb
Host smart-5dec2587-95bc-42c6-b1d4-f425dc91a168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313789769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.313789769
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1584238236
Short name T436
Test name
Test status
Simulation time 91255119 ps
CPU time 3.31 seconds
Started Aug 13 04:31:41 PM PDT 24
Finished Aug 13 04:31:44 PM PDT 24
Peak memory 221692 kb
Host smart-3d6f41e4-420c-4783-924b-135c3f03b51d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1584238236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1584238236
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.4070606323
Short name T244
Test name
Test status
Simulation time 126160250899 ps
CPU time 362.29 seconds
Started Aug 13 04:31:39 PM PDT 24
Finished Aug 13 04:37:42 PM PDT 24
Peak memory 271136 kb
Host smart-5454fa9b-1d73-425c-9c70-cd95d8680d0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070606323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.4070606323
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.937375936
Short name T853
Test name
Test status
Simulation time 907651720 ps
CPU time 7.3 seconds
Started Aug 13 04:31:47 PM PDT 24
Finished Aug 13 04:31:54 PM PDT 24
Peak memory 218408 kb
Host smart-65b4a338-b7b8-40c8-b0c1-303cf817a4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937375936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.937375936
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.303430299
Short name T485
Test name
Test status
Simulation time 1852243567 ps
CPU time 5.78 seconds
Started Aug 13 04:31:46 PM PDT 24
Finished Aug 13 04:31:52 PM PDT 24
Peak memory 217080 kb
Host smart-e3109f1e-48b3-4cda-9fe7-13bf67c9f337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303430299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.303430299
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.628913984
Short name T410
Test name
Test status
Simulation time 62559487 ps
CPU time 1.35 seconds
Started Aug 13 04:31:44 PM PDT 24
Finished Aug 13 04:31:46 PM PDT 24
Peak memory 217000 kb
Host smart-0da16937-8253-4302-80a0-72c05ab8e294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628913984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.628913984
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1421817179
Short name T1006
Test name
Test status
Simulation time 55045985 ps
CPU time 0.89 seconds
Started Aug 13 04:31:37 PM PDT 24
Finished Aug 13 04:31:48 PM PDT 24
Peak memory 206752 kb
Host smart-99eb4ec7-c026-454c-a980-45ed576af02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421817179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1421817179
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3119409125
Short name T842
Test name
Test status
Simulation time 114211824 ps
CPU time 2.01 seconds
Started Aug 13 04:31:54 PM PDT 24
Finished Aug 13 04:31:57 PM PDT 24
Peak memory 224752 kb
Host smart-9fcd3cbb-3d2e-4155-8f19-21c4bc955ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119409125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3119409125
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4001014879
Short name T542
Test name
Test status
Simulation time 23711706 ps
CPU time 0.77 seconds
Started Aug 13 04:32:04 PM PDT 24
Finished Aug 13 04:32:05 PM PDT 24
Peak memory 206124 kb
Host smart-1d59513b-e513-4562-85af-3518a1617c3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001014879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4001014879
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2608023872
Short name T481
Test name
Test status
Simulation time 1731423298 ps
CPU time 14.91 seconds
Started Aug 13 04:31:46 PM PDT 24
Finished Aug 13 04:32:01 PM PDT 24
Peak memory 225264 kb
Host smart-47617350-1add-4c91-a069-95d6dceb1f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608023872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2608023872
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3875319
Short name T329
Test name
Test status
Simulation time 16314565 ps
CPU time 0.71 seconds
Started Aug 13 04:31:39 PM PDT 24
Finished Aug 13 04:31:40 PM PDT 24
Peak memory 206616 kb
Host smart-a78e16c3-22fc-4f72-b346-6fc2004e30be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3875319
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4277419606
Short name T598
Test name
Test status
Simulation time 45314734203 ps
CPU time 121.8 seconds
Started Aug 13 04:31:46 PM PDT 24
Finished Aug 13 04:33:48 PM PDT 24
Peak memory 250184 kb
Host smart-fb9d9f27-d79a-4c61-a08d-f518d473a347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277419606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4277419606
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3042680402
Short name T489
Test name
Test status
Simulation time 415846918 ps
CPU time 11.04 seconds
Started Aug 13 04:31:45 PM PDT 24
Finished Aug 13 04:31:56 PM PDT 24
Peak memory 233496 kb
Host smart-75bc0e53-f96a-4f8e-ab30-1db9a41abd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042680402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3042680402
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.860804308
Short name T369
Test name
Test status
Simulation time 19292699480 ps
CPU time 128.23 seconds
Started Aug 13 04:31:49 PM PDT 24
Finished Aug 13 04:33:58 PM PDT 24
Peak memory 251080 kb
Host smart-7fcfa72d-72c6-4bc4-8d8d-b06159e4058b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860804308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.860804308
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.841464936
Short name T529
Test name
Test status
Simulation time 480224381 ps
CPU time 5.56 seconds
Started Aug 13 04:31:54 PM PDT 24
Finished Aug 13 04:31:59 PM PDT 24
Peak memory 229104 kb
Host smart-fbfe4e25-0b36-4660-8612-53b1bea6fc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841464936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.841464936
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3107785606
Short name T337
Test name
Test status
Simulation time 8854802548 ps
CPU time 31.58 seconds
Started Aug 13 04:32:03 PM PDT 24
Finished Aug 13 04:32:35 PM PDT 24
Peak memory 241616 kb
Host smart-fc9896bc-48e3-4c13-95c0-1099f1722c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107785606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3107785606
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2129278248
Short name T1001
Test name
Test status
Simulation time 5403809416 ps
CPU time 13.82 seconds
Started Aug 13 04:31:49 PM PDT 24
Finished Aug 13 04:32:03 PM PDT 24
Peak memory 233480 kb
Host smart-4677b30c-222d-4851-86c6-def4e769f7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129278248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2129278248
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1442541155
Short name T723
Test name
Test status
Simulation time 745660314 ps
CPU time 7.52 seconds
Started Aug 13 04:31:55 PM PDT 24
Finished Aug 13 04:32:02 PM PDT 24
Peak memory 223356 kb
Host smart-0366ae58-2583-4fe3-9b9c-fd7181d73696
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1442541155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1442541155
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3135028146
Short name T717
Test name
Test status
Simulation time 88408141170 ps
CPU time 209.65 seconds
Started Aug 13 04:31:51 PM PDT 24
Finished Aug 13 04:35:21 PM PDT 24
Peak memory 253952 kb
Host smart-9e56dcee-71ae-462d-9aa8-0968f0f9fa02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135028146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3135028146
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1301419088
Short name T900
Test name
Test status
Simulation time 8249302436 ps
CPU time 21.7 seconds
Started Aug 13 04:31:48 PM PDT 24
Finished Aug 13 04:32:10 PM PDT 24
Peak memory 217444 kb
Host smart-119d6da5-faad-48ef-a42d-253d3b945ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301419088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1301419088
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1954981631
Short name T469
Test name
Test status
Simulation time 46044531 ps
CPU time 1.12 seconds
Started Aug 13 04:31:40 PM PDT 24
Finished Aug 13 04:31:42 PM PDT 24
Peak memory 207900 kb
Host smart-120305c2-6937-4f4e-bb45-13c964443761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954981631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1954981631
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3488919897
Short name T331
Test name
Test status
Simulation time 170199950 ps
CPU time 3.9 seconds
Started Aug 13 04:31:49 PM PDT 24
Finished Aug 13 04:31:53 PM PDT 24
Peak memory 217128 kb
Host smart-8b18f1c4-e0b3-48df-98ff-e0e00db45d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488919897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3488919897
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.245936485
Short name T539
Test name
Test status
Simulation time 49688112 ps
CPU time 0.89 seconds
Started Aug 13 04:31:40 PM PDT 24
Finished Aug 13 04:31:41 PM PDT 24
Peak memory 207780 kb
Host smart-45cb3ed0-3d71-4dfa-9a59-18b32a3cc47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245936485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.245936485
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2335276360
Short name T831
Test name
Test status
Simulation time 89418091 ps
CPU time 2.21 seconds
Started Aug 13 04:31:51 PM PDT 24
Finished Aug 13 04:31:53 PM PDT 24
Peak memory 224760 kb
Host smart-ea7f4b73-d39d-445d-98ca-7cee4dba89e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335276360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2335276360
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3375722232
Short name T981
Test name
Test status
Simulation time 26449789 ps
CPU time 0.72 seconds
Started Aug 13 04:31:52 PM PDT 24
Finished Aug 13 04:31:53 PM PDT 24
Peak memory 206600 kb
Host smart-1cdeebd7-b167-490e-b97f-6f3a01706f36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375722232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3375722232
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1021938725
Short name T944
Test name
Test status
Simulation time 618531218 ps
CPU time 2.35 seconds
Started Aug 13 04:31:49 PM PDT 24
Finished Aug 13 04:31:52 PM PDT 24
Peak memory 233444 kb
Host smart-cebbe0d1-ddcf-4fd6-ab1e-22efbe2ee5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021938725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1021938725
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.474224750
Short name T810
Test name
Test status
Simulation time 48600774 ps
CPU time 0.77 seconds
Started Aug 13 04:31:46 PM PDT 24
Finished Aug 13 04:31:47 PM PDT 24
Peak memory 207408 kb
Host smart-8d3f8c28-255f-45f7-a264-df9c7b80dee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474224750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.474224750
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3067476410
Short name T225
Test name
Test status
Simulation time 116254622164 ps
CPU time 418.29 seconds
Started Aug 13 04:31:52 PM PDT 24
Finished Aug 13 04:38:51 PM PDT 24
Peak memory 266508 kb
Host smart-abc41e86-2521-4a15-8820-6825f2936e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067476410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3067476410
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.4094055083
Short name T226
Test name
Test status
Simulation time 22266891073 ps
CPU time 182.43 seconds
Started Aug 13 04:32:18 PM PDT 24
Finished Aug 13 04:35:21 PM PDT 24
Peak memory 250272 kb
Host smart-bee6caf4-9e03-4f12-93fd-0461322e82f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094055083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4094055083
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.237259113
Short name T919
Test name
Test status
Simulation time 44663574399 ps
CPU time 377.68 seconds
Started Aug 13 04:31:57 PM PDT 24
Finished Aug 13 04:38:20 PM PDT 24
Peak memory 266460 kb
Host smart-47b5ab7e-a0fc-47a1-ac64-2806d57994b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237259113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.237259113
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1901859890
Short name T292
Test name
Test status
Simulation time 284105132 ps
CPU time 6.35 seconds
Started Aug 13 04:31:47 PM PDT 24
Finished Aug 13 04:31:53 PM PDT 24
Peak memory 225284 kb
Host smart-9814522a-ed5d-4574-90d8-63cfb5ef0843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901859890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1901859890
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2787167966
Short name T245
Test name
Test status
Simulation time 83577155069 ps
CPU time 135.71 seconds
Started Aug 13 04:31:43 PM PDT 24
Finished Aug 13 04:33:59 PM PDT 24
Peak memory 250000 kb
Host smart-dfe47d6f-88bf-4cbf-a6d7-4d6271b0477b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787167966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2787167966
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3596747961
Short name T882
Test name
Test status
Simulation time 203437983 ps
CPU time 2.73 seconds
Started Aug 13 04:31:48 PM PDT 24
Finished Aug 13 04:31:51 PM PDT 24
Peak memory 233516 kb
Host smart-875d3280-0a61-4517-b01d-d2a9e5fa3d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596747961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3596747961
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1443158860
Short name T200
Test name
Test status
Simulation time 760654269 ps
CPU time 5.94 seconds
Started Aug 13 04:31:49 PM PDT 24
Finished Aug 13 04:31:55 PM PDT 24
Peak memory 225264 kb
Host smart-45759537-85e9-407f-a355-4ca520c77063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443158860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1443158860
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1217616928
Short name T724
Test name
Test status
Simulation time 6919120209 ps
CPU time 18.72 seconds
Started Aug 13 04:31:44 PM PDT 24
Finished Aug 13 04:32:03 PM PDT 24
Peak memory 225340 kb
Host smart-e4005404-1c92-4992-a142-c9ff02a04c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217616928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1217616928
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.860989276
Short name T353
Test name
Test status
Simulation time 478244905 ps
CPU time 3.43 seconds
Started Aug 13 04:31:46 PM PDT 24
Finished Aug 13 04:31:54 PM PDT 24
Peak memory 225236 kb
Host smart-c382a05b-ac81-4089-9c05-650dc75ff2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860989276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.860989276
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2261403777
Short name T703
Test name
Test status
Simulation time 953228909 ps
CPU time 4.88 seconds
Started Aug 13 04:31:54 PM PDT 24
Finished Aug 13 04:31:59 PM PDT 24
Peak memory 221576 kb
Host smart-766e57f7-fd9c-4193-bc7e-c1a61b876ee3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2261403777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2261403777
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2039311569
Short name T168
Test name
Test status
Simulation time 51982916028 ps
CPU time 289.14 seconds
Started Aug 13 04:32:11 PM PDT 24
Finished Aug 13 04:37:00 PM PDT 24
Peak memory 251384 kb
Host smart-79777539-1aec-4ed5-be38-60f93012f01c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039311569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2039311569
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1687015794
Short name T379
Test name
Test status
Simulation time 10646752791 ps
CPU time 51.43 seconds
Started Aug 13 04:31:45 PM PDT 24
Finished Aug 13 04:32:37 PM PDT 24
Peak memory 217232 kb
Host smart-66d74a56-f09d-4eb2-8655-1ffec6df76e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687015794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1687015794
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1591735045
Short name T336
Test name
Test status
Simulation time 956545029 ps
CPU time 3.85 seconds
Started Aug 13 04:32:15 PM PDT 24
Finished Aug 13 04:32:19 PM PDT 24
Peak memory 217060 kb
Host smart-d373c01a-6114-47ce-8607-42d187daa613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591735045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1591735045
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1139666922
Short name T1003
Test name
Test status
Simulation time 270465719 ps
CPU time 3.87 seconds
Started Aug 13 04:31:50 PM PDT 24
Finished Aug 13 04:31:55 PM PDT 24
Peak memory 217032 kb
Host smart-3b6a6066-bfd8-4030-a5ff-07d7b130f09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139666922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1139666922
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1451401822
Short name T330
Test name
Test status
Simulation time 51891777 ps
CPU time 0.82 seconds
Started Aug 13 04:31:52 PM PDT 24
Finished Aug 13 04:31:53 PM PDT 24
Peak memory 206748 kb
Host smart-82eef3bb-e466-49c9-97d1-57bfe9079ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451401822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1451401822
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.730050164
Short name T58
Test name
Test status
Simulation time 593625488 ps
CPU time 6.36 seconds
Started Aug 13 04:32:17 PM PDT 24
Finished Aug 13 04:32:23 PM PDT 24
Peak memory 233476 kb
Host smart-aa78927a-77c8-49a1-978f-285f946b2f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730050164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.730050164
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1639449988
Short name T649
Test name
Test status
Simulation time 13293469 ps
CPU time 0.73 seconds
Started Aug 13 04:30:52 PM PDT 24
Finished Aug 13 04:30:53 PM PDT 24
Peak memory 205552 kb
Host smart-ea4e7aa8-8aa8-41a4-9c8d-921b1d4c7919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639449988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
639449988
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.37658047
Short name T176
Test name
Test status
Simulation time 6572785931 ps
CPU time 14.06 seconds
Started Aug 13 04:30:52 PM PDT 24
Finished Aug 13 04:31:06 PM PDT 24
Peak memory 225408 kb
Host smart-44b2929c-ff4b-4515-9f75-889c467059f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37658047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.37658047
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.4233857624
Short name T788
Test name
Test status
Simulation time 22009512 ps
CPU time 0.8 seconds
Started Aug 13 04:30:50 PM PDT 24
Finished Aug 13 04:30:51 PM PDT 24
Peak memory 207288 kb
Host smart-ddcf152a-e9b7-4861-8a30-6168ab97ee3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233857624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.4233857624
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2384728647
Short name T665
Test name
Test status
Simulation time 10966429 ps
CPU time 0.74 seconds
Started Aug 13 04:30:47 PM PDT 24
Finished Aug 13 04:30:48 PM PDT 24
Peak memory 216452 kb
Host smart-3f85d4db-1c90-4a07-b7bb-0d1cd7b5465c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384728647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2384728647
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3695835377
Short name T661
Test name
Test status
Simulation time 8349457101 ps
CPU time 51.88 seconds
Started Aug 13 04:30:58 PM PDT 24
Finished Aug 13 04:31:50 PM PDT 24
Peak memory 252092 kb
Host smart-79df340d-8c34-4889-ac68-b0bf61766294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695835377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3695835377
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2937239249
Short name T823
Test name
Test status
Simulation time 52016505644 ps
CPU time 449.68 seconds
Started Aug 13 04:30:49 PM PDT 24
Finished Aug 13 04:38:19 PM PDT 24
Peak memory 274064 kb
Host smart-dbf82f9c-0d98-4a14-af3c-0c21c34898f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937239249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2937239249
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1685621206
Short name T551
Test name
Test status
Simulation time 1050658346 ps
CPU time 20.56 seconds
Started Aug 13 04:30:52 PM PDT 24
Finished Aug 13 04:31:13 PM PDT 24
Peak memory 233384 kb
Host smart-ff7e437c-13d8-41be-a2cd-6695c25f433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685621206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1685621206
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3538561799
Short name T994
Test name
Test status
Simulation time 7333610465 ps
CPU time 11.02 seconds
Started Aug 13 04:30:52 PM PDT 24
Finished Aug 13 04:31:04 PM PDT 24
Peak memory 233848 kb
Host smart-78ffda6f-2a9b-45f6-b687-64b7fa20ff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538561799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3538561799
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1067565021
Short name T966
Test name
Test status
Simulation time 139009084 ps
CPU time 2.58 seconds
Started Aug 13 04:30:44 PM PDT 24
Finished Aug 13 04:30:46 PM PDT 24
Peak memory 233488 kb
Host smart-2b64fb1e-b85c-4e55-aa2f-174e9e066fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067565021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1067565021
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1089267383
Short name T543
Test name
Test status
Simulation time 831156264 ps
CPU time 6.05 seconds
Started Aug 13 04:30:53 PM PDT 24
Finished Aug 13 04:30:59 PM PDT 24
Peak memory 233504 kb
Host smart-252cb56e-744f-4968-82f6-fc009e36afa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089267383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1089267383
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.545199741
Short name T899
Test name
Test status
Simulation time 5738624343 ps
CPU time 10.08 seconds
Started Aug 13 04:30:42 PM PDT 24
Finished Aug 13 04:30:52 PM PDT 24
Peak memory 233500 kb
Host smart-68c78662-5fee-4eae-aa96-0c1261926e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545199741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
545199741
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4184628162
Short name T262
Test name
Test status
Simulation time 1724807418 ps
CPU time 6.31 seconds
Started Aug 13 04:30:51 PM PDT 24
Finished Aug 13 04:30:57 PM PDT 24
Peak memory 233412 kb
Host smart-af9ed60c-9296-4261-a7d6-696012e740fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184628162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4184628162
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3226867145
Short name T487
Test name
Test status
Simulation time 840511657 ps
CPU time 9.91 seconds
Started Aug 13 04:30:54 PM PDT 24
Finished Aug 13 04:31:04 PM PDT 24
Peak memory 222888 kb
Host smart-174a5ac9-7cd6-4807-921b-eb6e65614f2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3226867145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3226867145
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3186572207
Short name T73
Test name
Test status
Simulation time 76047081 ps
CPU time 0.99 seconds
Started Aug 13 04:30:49 PM PDT 24
Finished Aug 13 04:30:50 PM PDT 24
Peak memory 237024 kb
Host smart-f092e97c-3166-4edb-af68-712f3c6bbc51
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186572207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3186572207
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.227333689
Short name T152
Test name
Test status
Simulation time 4707792313 ps
CPU time 80.24 seconds
Started Aug 13 04:30:51 PM PDT 24
Finished Aug 13 04:32:12 PM PDT 24
Peak memory 263676 kb
Host smart-5c9f284c-4cb8-4dc9-b686-7daeb686703a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227333689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.227333689
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.101511117
Short name T62
Test name
Test status
Simulation time 7802440250 ps
CPU time 25.51 seconds
Started Aug 13 04:30:46 PM PDT 24
Finished Aug 13 04:31:11 PM PDT 24
Peak memory 217172 kb
Host smart-aeb00526-caa1-4434-aa6b-f4893444839f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101511117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.101511117
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1833194936
Short name T782
Test name
Test status
Simulation time 7751141853 ps
CPU time 20.41 seconds
Started Aug 13 04:30:44 PM PDT 24
Finished Aug 13 04:31:05 PM PDT 24
Peak memory 217220 kb
Host smart-0dc09983-4037-4cb6-956f-a953b737b311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833194936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1833194936
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.676062856
Short name T743
Test name
Test status
Simulation time 286201464 ps
CPU time 1.66 seconds
Started Aug 13 04:30:53 PM PDT 24
Finished Aug 13 04:30:56 PM PDT 24
Peak memory 216980 kb
Host smart-97fd37fa-7187-4cac-8c47-231cf260c43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676062856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.676062856
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1850797965
Short name T554
Test name
Test status
Simulation time 90648517 ps
CPU time 0.8 seconds
Started Aug 13 04:30:45 PM PDT 24
Finished Aug 13 04:30:46 PM PDT 24
Peak memory 206732 kb
Host smart-c00f6363-c86d-4740-a5a0-b970e065c393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850797965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1850797965
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.4052454738
Short name T700
Test name
Test status
Simulation time 1048285295 ps
CPU time 5.88 seconds
Started Aug 13 04:30:49 PM PDT 24
Finished Aug 13 04:30:55 PM PDT 24
Peak memory 241512 kb
Host smart-ed20d8a8-a58b-40d9-8526-8a8c6b6b61a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052454738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.4052454738
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1387590552
Short name T875
Test name
Test status
Simulation time 16255471 ps
CPU time 0.72 seconds
Started Aug 13 04:32:01 PM PDT 24
Finished Aug 13 04:32:02 PM PDT 24
Peak memory 206116 kb
Host smart-7a194dd9-dc2d-44ae-a89b-033e3ac53370
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387590552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1387590552
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3205457521
Short name T338
Test name
Test status
Simulation time 197666228 ps
CPU time 2.49 seconds
Started Aug 13 04:31:55 PM PDT 24
Finished Aug 13 04:31:58 PM PDT 24
Peak memory 233524 kb
Host smart-4720b7fd-5638-4ccb-9852-0941b48caa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205457521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3205457521
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1661416459
Short name T750
Test name
Test status
Simulation time 61876515 ps
CPU time 0.76 seconds
Started Aug 13 04:31:49 PM PDT 24
Finished Aug 13 04:31:50 PM PDT 24
Peak memory 207284 kb
Host smart-6a00870a-75e9-4044-8d6d-58b431d3cbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661416459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1661416459
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.914551172
Short name T739
Test name
Test status
Simulation time 2185072671 ps
CPU time 8.34 seconds
Started Aug 13 04:32:01 PM PDT 24
Finished Aug 13 04:32:10 PM PDT 24
Peak memory 225280 kb
Host smart-a0d0a996-7c39-4f48-a44c-6731df84140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914551172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.914551172
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4178521689
Short name T263
Test name
Test status
Simulation time 3205086357 ps
CPU time 31.66 seconds
Started Aug 13 04:31:44 PM PDT 24
Finished Aug 13 04:32:16 PM PDT 24
Peak memory 225556 kb
Host smart-67119f60-4b00-42ee-a759-c17990cb6a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178521689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4178521689
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.557636832
Short name T394
Test name
Test status
Simulation time 2747532799 ps
CPU time 12.38 seconds
Started Aug 13 04:32:02 PM PDT 24
Finished Aug 13 04:32:14 PM PDT 24
Peak memory 241840 kb
Host smart-9baa1774-43f8-451c-92f2-2b4fcba62156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557636832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.557636832
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2750334133
Short name T758
Test name
Test status
Simulation time 60882503150 ps
CPU time 53.55 seconds
Started Aug 13 04:32:05 PM PDT 24
Finished Aug 13 04:32:58 PM PDT 24
Peak memory 241820 kb
Host smart-601d6ec2-f9a0-4ffc-9877-0a4bb39158cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750334133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2750334133
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1207168543
Short name T737
Test name
Test status
Simulation time 273412018 ps
CPU time 5.11 seconds
Started Aug 13 04:32:05 PM PDT 24
Finished Aug 13 04:32:11 PM PDT 24
Peak memory 233580 kb
Host smart-c9afec0c-0c7e-4788-ba4e-b2bcd44851f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207168543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1207168543
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3299533515
Short name T834
Test name
Test status
Simulation time 107345912 ps
CPU time 3.39 seconds
Started Aug 13 04:31:56 PM PDT 24
Finished Aug 13 04:32:00 PM PDT 24
Peak memory 233500 kb
Host smart-e019cdb1-7c62-4a67-a3f1-87ee15ac99e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299533515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3299533515
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1841905790
Short name T232
Test name
Test status
Simulation time 555309229 ps
CPU time 2.99 seconds
Started Aug 13 04:32:08 PM PDT 24
Finished Aug 13 04:32:12 PM PDT 24
Peak memory 225264 kb
Host smart-02f787a4-96dc-4ab7-b1b5-db8f9b15479c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841905790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1841905790
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.299454010
Short name T547
Test name
Test status
Simulation time 2731626796 ps
CPU time 9.67 seconds
Started Aug 13 04:31:55 PM PDT 24
Finished Aug 13 04:32:05 PM PDT 24
Peak memory 239788 kb
Host smart-9a8f1c22-5df9-485c-abe4-4f5562da563f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299454010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.299454010
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2550599836
Short name T144
Test name
Test status
Simulation time 147163320 ps
CPU time 3.84 seconds
Started Aug 13 04:32:10 PM PDT 24
Finished Aug 13 04:32:14 PM PDT 24
Peak memory 221152 kb
Host smart-74cc8826-8dfc-49ed-ae3d-c80130e9dbf9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2550599836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2550599836
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3629053604
Short name T722
Test name
Test status
Simulation time 32091288596 ps
CPU time 57.2 seconds
Started Aug 13 04:32:08 PM PDT 24
Finished Aug 13 04:33:05 PM PDT 24
Peak memory 250096 kb
Host smart-2df50abe-50b9-40c4-b4af-2570193f8f8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629053604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3629053604
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2835768379
Short name T827
Test name
Test status
Simulation time 1844859561 ps
CPU time 25.28 seconds
Started Aug 13 04:32:02 PM PDT 24
Finished Aug 13 04:32:28 PM PDT 24
Peak memory 217272 kb
Host smart-7016b889-8c28-4b55-815a-47c5c49bcde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835768379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2835768379
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4227344769
Short name T754
Test name
Test status
Simulation time 3639045336 ps
CPU time 13.42 seconds
Started Aug 13 04:32:14 PM PDT 24
Finished Aug 13 04:32:27 PM PDT 24
Peak memory 217200 kb
Host smart-89c48352-cb77-473d-b0b3-1fe2cc050fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227344769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4227344769
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2023592037
Short name T929
Test name
Test status
Simulation time 127606991 ps
CPU time 1.03 seconds
Started Aug 13 04:31:58 PM PDT 24
Finished Aug 13 04:32:00 PM PDT 24
Peak memory 208612 kb
Host smart-c90e9a86-3c44-4488-92c6-516a02d81d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023592037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2023592037
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1574972191
Short name T324
Test name
Test status
Simulation time 377646887 ps
CPU time 0.96 seconds
Started Aug 13 04:31:56 PM PDT 24
Finished Aug 13 04:31:57 PM PDT 24
Peak memory 206700 kb
Host smart-8adfebcb-7d12-4fe5-9599-57964fd56ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574972191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1574972191
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1517380010
Short name T541
Test name
Test status
Simulation time 440798108 ps
CPU time 4.57 seconds
Started Aug 13 04:32:03 PM PDT 24
Finished Aug 13 04:32:08 PM PDT 24
Peak memory 230556 kb
Host smart-182419f2-f6f2-4cf5-9b54-65dae32bd095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517380010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1517380010
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3176840123
Short name T677
Test name
Test status
Simulation time 13862795 ps
CPU time 0.69 seconds
Started Aug 13 04:31:48 PM PDT 24
Finished Aug 13 04:31:48 PM PDT 24
Peak memory 205588 kb
Host smart-7dd2d878-feb2-439d-95eb-deb472bb407f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176840123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3176840123
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1453002106
Short name T1002
Test name
Test status
Simulation time 556757542 ps
CPU time 3.65 seconds
Started Aug 13 04:31:57 PM PDT 24
Finished Aug 13 04:32:00 PM PDT 24
Peak memory 233448 kb
Host smart-bb5349d8-55f2-4283-95c0-be89d912b40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453002106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1453002106
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1288655746
Short name T401
Test name
Test status
Simulation time 14919045 ps
CPU time 0.76 seconds
Started Aug 13 04:32:03 PM PDT 24
Finished Aug 13 04:32:04 PM PDT 24
Peak memory 207268 kb
Host smart-0efaa9d9-9c19-40d2-97ab-7e2044140b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288655746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1288655746
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1450019750
Short name T162
Test name
Test status
Simulation time 4619571512 ps
CPU time 28.12 seconds
Started Aug 13 04:32:15 PM PDT 24
Finished Aug 13 04:32:43 PM PDT 24
Peak memory 255680 kb
Host smart-9ca971bc-b70f-4424-9ff7-d970353ef566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450019750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1450019750
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1288275064
Short name T128
Test name
Test status
Simulation time 2704431372 ps
CPU time 56.97 seconds
Started Aug 13 04:32:04 PM PDT 24
Finished Aug 13 04:33:01 PM PDT 24
Peak memory 241912 kb
Host smart-7e2732b1-13e0-44cb-8750-c9dd3148e2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288275064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1288275064
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3500321458
Short name T249
Test name
Test status
Simulation time 50653571925 ps
CPU time 472.29 seconds
Started Aug 13 04:32:07 PM PDT 24
Finished Aug 13 04:40:00 PM PDT 24
Peak memory 255848 kb
Host smart-72e8329e-0998-4ef9-9a33-af035d70bddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500321458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3500321458
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.369205925
Short name T2
Test name
Test status
Simulation time 1008443463 ps
CPU time 6.66 seconds
Started Aug 13 04:31:58 PM PDT 24
Finished Aug 13 04:32:05 PM PDT 24
Peak memory 239124 kb
Host smart-10b9bf32-c9c8-41b2-9bf9-267887ba44b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369205925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.369205925
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1056695383
Short name T626
Test name
Test status
Simulation time 39310828586 ps
CPU time 64.39 seconds
Started Aug 13 04:32:02 PM PDT 24
Finished Aug 13 04:33:07 PM PDT 24
Peak memory 241792 kb
Host smart-5a36082a-7633-481b-8567-9f2ff51741f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056695383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1056695383
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2796159637
Short name T501
Test name
Test status
Simulation time 467946851 ps
CPU time 2.75 seconds
Started Aug 13 04:32:07 PM PDT 24
Finished Aug 13 04:32:10 PM PDT 24
Peak memory 225292 kb
Host smart-83c3770a-9588-4c96-a123-c55248420be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796159637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2796159637
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1283327655
Short name T904
Test name
Test status
Simulation time 1373013754 ps
CPU time 9.4 seconds
Started Aug 13 04:31:53 PM PDT 24
Finished Aug 13 04:32:03 PM PDT 24
Peak memory 236496 kb
Host smart-9dd57a44-ee0e-440e-9482-f689fd6c6334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283327655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1283327655
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.468738102
Short name T371
Test name
Test status
Simulation time 1647606254 ps
CPU time 6.53 seconds
Started Aug 13 04:31:51 PM PDT 24
Finished Aug 13 04:31:58 PM PDT 24
Peak memory 225236 kb
Host smart-bbf2e63a-d53f-43f7-b6cf-20ea93e5c7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468738102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.468738102
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3398482269
Short name T812
Test name
Test status
Simulation time 116043975 ps
CPU time 2.39 seconds
Started Aug 13 04:32:17 PM PDT 24
Finished Aug 13 04:32:20 PM PDT 24
Peak memory 225148 kb
Host smart-e6665962-0ef2-49b2-ac3a-fd612172ce3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398482269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3398482269
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.199367890
Short name T961
Test name
Test status
Simulation time 349125282 ps
CPU time 3.6 seconds
Started Aug 13 04:32:04 PM PDT 24
Finished Aug 13 04:32:08 PM PDT 24
Peak memory 222888 kb
Host smart-a59ea459-f47e-42ba-a50a-90891138f759
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=199367890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.199367890
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.620088716
Short name T443
Test name
Test status
Simulation time 2161705597 ps
CPU time 40.1 seconds
Started Aug 13 04:32:13 PM PDT 24
Finished Aug 13 04:32:53 PM PDT 24
Peak memory 241916 kb
Host smart-b162eb39-ea9a-458c-83c0-b62da811b8f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620088716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.620088716
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3813373029
Short name T680
Test name
Test status
Simulation time 4339195625 ps
CPU time 18.64 seconds
Started Aug 13 04:32:11 PM PDT 24
Finished Aug 13 04:32:30 PM PDT 24
Peak memory 217332 kb
Host smart-19c40d27-c9bc-4157-bc3a-869faca7035d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813373029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3813373029
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3094195958
Short name T524
Test name
Test status
Simulation time 9596500355 ps
CPU time 8.94 seconds
Started Aug 13 04:32:20 PM PDT 24
Finished Aug 13 04:32:29 PM PDT 24
Peak memory 218484 kb
Host smart-14268df4-cf88-450d-a8ef-ecf63c3c480b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094195958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3094195958
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2317511656
Short name T301
Test name
Test status
Simulation time 204584539 ps
CPU time 1.14 seconds
Started Aug 13 04:32:03 PM PDT 24
Finished Aug 13 04:32:04 PM PDT 24
Peak memory 208660 kb
Host smart-a4c8ca33-3483-41df-a9ca-8fab19feef88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317511656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2317511656
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2514776876
Short name T696
Test name
Test status
Simulation time 156998750 ps
CPU time 0.84 seconds
Started Aug 13 04:31:59 PM PDT 24
Finished Aug 13 04:32:00 PM PDT 24
Peak memory 207744 kb
Host smart-a224b02a-3d4d-4a30-bb23-b72d13e9528f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514776876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2514776876
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2912363336
Short name T385
Test name
Test status
Simulation time 956503289 ps
CPU time 3.5 seconds
Started Aug 13 04:32:03 PM PDT 24
Finished Aug 13 04:32:07 PM PDT 24
Peak memory 225268 kb
Host smart-b59540fe-d488-43d2-8ed9-922dfeacc016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912363336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2912363336
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.352665992
Short name T442
Test name
Test status
Simulation time 15758372 ps
CPU time 0.72 seconds
Started Aug 13 04:32:01 PM PDT 24
Finished Aug 13 04:32:02 PM PDT 24
Peak memory 206188 kb
Host smart-118e21ad-dfb6-4ad5-b458-675c95b3f015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352665992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.352665992
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1832224998
Short name T747
Test name
Test status
Simulation time 1569657717 ps
CPU time 17.9 seconds
Started Aug 13 04:32:10 PM PDT 24
Finished Aug 13 04:32:28 PM PDT 24
Peak memory 225228 kb
Host smart-bfd7bdb7-431d-4ff5-a6d0-dfa57a81dad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832224998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1832224998
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2529270151
Short name T937
Test name
Test status
Simulation time 17407726 ps
CPU time 0.77 seconds
Started Aug 13 04:31:58 PM PDT 24
Finished Aug 13 04:31:59 PM PDT 24
Peak memory 207292 kb
Host smart-c72ee53b-d4f9-4e41-b7ac-88b23b7a0a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529270151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2529270151
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3188231371
Short name T214
Test name
Test status
Simulation time 16737151201 ps
CPU time 103.68 seconds
Started Aug 13 04:32:04 PM PDT 24
Finished Aug 13 04:33:48 PM PDT 24
Peak memory 263220 kb
Host smart-3a952406-1835-47f2-bdec-a9f2fff3e6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188231371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3188231371
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4212884139
Short name T867
Test name
Test status
Simulation time 59645044839 ps
CPU time 264.3 seconds
Started Aug 13 04:32:14 PM PDT 24
Finished Aug 13 04:36:38 PM PDT 24
Peak memory 250048 kb
Host smart-1fedd8ed-798e-4d75-945c-60c77b6a5099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212884139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4212884139
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.558207719
Short name T813
Test name
Test status
Simulation time 2183655462 ps
CPU time 4.95 seconds
Started Aug 13 04:32:23 PM PDT 24
Finished Aug 13 04:32:28 PM PDT 24
Peak memory 225284 kb
Host smart-c513a5ff-c197-43b8-8b6d-b066bcda69f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558207719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.558207719
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2551350759
Short name T907
Test name
Test status
Simulation time 268884301 ps
CPU time 6.02 seconds
Started Aug 13 04:32:12 PM PDT 24
Finished Aug 13 04:32:18 PM PDT 24
Peak memory 225204 kb
Host smart-69a38ff3-f0a2-4c0d-885b-fdc6ba84d607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551350759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2551350759
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2558447208
Short name T419
Test name
Test status
Simulation time 44409302580 ps
CPU time 111.31 seconds
Started Aug 13 04:32:22 PM PDT 24
Finished Aug 13 04:34:14 PM PDT 24
Peak memory 265708 kb
Host smart-d9ed608f-9ca9-40ae-b95b-04659e2591d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558447208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2558447208
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1395468102
Short name T650
Test name
Test status
Simulation time 419937529 ps
CPU time 2.41 seconds
Started Aug 13 04:31:49 PM PDT 24
Finished Aug 13 04:31:51 PM PDT 24
Peak memory 225204 kb
Host smart-4ec08777-9ff5-4a97-a7d5-f72c5ad563c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395468102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1395468102
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.303323811
Short name T286
Test name
Test status
Simulation time 147061095 ps
CPU time 4.43 seconds
Started Aug 13 04:32:03 PM PDT 24
Finished Aug 13 04:32:12 PM PDT 24
Peak memory 225316 kb
Host smart-1856ef5d-8347-41f3-9211-54b2f71fe729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303323811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.303323811
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2820827879
Short name T509
Test name
Test status
Simulation time 10747031273 ps
CPU time 31.03 seconds
Started Aug 13 04:32:04 PM PDT 24
Finished Aug 13 04:32:36 PM PDT 24
Peak memory 225428 kb
Host smart-ffd88afa-9b8c-4ee9-8d68-0c768061dbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820827879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2820827879
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2998955179
Short name T960
Test name
Test status
Simulation time 2409616682 ps
CPU time 8.4 seconds
Started Aug 13 04:32:14 PM PDT 24
Finished Aug 13 04:32:23 PM PDT 24
Peak memory 225312 kb
Host smart-0e245cd0-d041-4294-b695-71e2c181e1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998955179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2998955179
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2194431882
Short name T345
Test name
Test status
Simulation time 155195816 ps
CPU time 3.28 seconds
Started Aug 13 04:32:26 PM PDT 24
Finished Aug 13 04:32:30 PM PDT 24
Peak memory 219524 kb
Host smart-8ee1e9e5-2def-4f4e-bb62-2db4a0692b2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2194431882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2194431882
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3668094449
Short name T632
Test name
Test status
Simulation time 154361398 ps
CPU time 0.94 seconds
Started Aug 13 04:32:19 PM PDT 24
Finished Aug 13 04:32:20 PM PDT 24
Peak memory 207704 kb
Host smart-2e6e1bf3-52ca-4b11-94e7-91ccb872ccc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668094449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3668094449
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2688864395
Short name T445
Test name
Test status
Simulation time 1531750982 ps
CPU time 14.65 seconds
Started Aug 13 04:32:08 PM PDT 24
Finished Aug 13 04:32:23 PM PDT 24
Peak memory 217484 kb
Host smart-9fd7fa04-0f2c-4a37-869b-f725007a3db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688864395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2688864395
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1274786685
Short name T319
Test name
Test status
Simulation time 17045991 ps
CPU time 0.69 seconds
Started Aug 13 04:32:18 PM PDT 24
Finished Aug 13 04:32:19 PM PDT 24
Peak memory 206440 kb
Host smart-1c152229-73bb-45d1-8afd-c337dcfda331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274786685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1274786685
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2340485728
Short name T360
Test name
Test status
Simulation time 295325513 ps
CPU time 2.96 seconds
Started Aug 13 04:31:53 PM PDT 24
Finished Aug 13 04:32:06 PM PDT 24
Peak memory 217156 kb
Host smart-09cb2bda-34bc-49d1-9806-9df3ccd97591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340485728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2340485728
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.957499453
Short name T358
Test name
Test status
Simulation time 36784234 ps
CPU time 0.8 seconds
Started Aug 13 04:32:03 PM PDT 24
Finished Aug 13 04:32:04 PM PDT 24
Peak memory 206796 kb
Host smart-c963e320-fdb6-430f-9954-90a0bf174f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957499453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.957499453
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2340174995
Short name T496
Test name
Test status
Simulation time 6659702220 ps
CPU time 11.49 seconds
Started Aug 13 04:32:24 PM PDT 24
Finished Aug 13 04:32:35 PM PDT 24
Peak memory 233580 kb
Host smart-b9c01365-1fb9-48d0-86d8-9376a8f288e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340174995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2340174995
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.54494766
Short name T567
Test name
Test status
Simulation time 64165020 ps
CPU time 0.71 seconds
Started Aug 13 04:31:54 PM PDT 24
Finished Aug 13 04:31:55 PM PDT 24
Peak memory 204376 kb
Host smart-2711b7c2-b587-4bfc-bbc3-4eece3d83a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54494766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.54494766
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.98412377
Short name T768
Test name
Test status
Simulation time 5117095484 ps
CPU time 14.52 seconds
Started Aug 13 04:31:58 PM PDT 24
Finished Aug 13 04:32:12 PM PDT 24
Peak memory 233568 kb
Host smart-040e7c8b-671c-4302-a914-80e9d772948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98412377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.98412377
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1561064500
Short name T354
Test name
Test status
Simulation time 54164199 ps
CPU time 0.78 seconds
Started Aug 13 04:32:09 PM PDT 24
Finished Aug 13 04:32:09 PM PDT 24
Peak memory 206268 kb
Host smart-2a21d429-8a29-4ce5-8ae0-4d008dc0e035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561064500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1561064500
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2009787852
Short name T267
Test name
Test status
Simulation time 32523506144 ps
CPU time 76.87 seconds
Started Aug 13 04:32:05 PM PDT 24
Finished Aug 13 04:33:22 PM PDT 24
Peak memory 249960 kb
Host smart-7a2aa9d3-eebd-45e6-a09b-0bf780be5428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009787852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2009787852
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3882518514
Short name T906
Test name
Test status
Simulation time 140167111343 ps
CPU time 181.05 seconds
Started Aug 13 04:32:19 PM PDT 24
Finished Aug 13 04:35:21 PM PDT 24
Peak memory 257948 kb
Host smart-8644a945-100b-4be0-944c-d77190c5d59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882518514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3882518514
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1899264394
Short name T806
Test name
Test status
Simulation time 5413570583 ps
CPU time 14.17 seconds
Started Aug 13 04:32:06 PM PDT 24
Finished Aug 13 04:32:20 PM PDT 24
Peak memory 218592 kb
Host smart-678dd222-a997-40cc-9c19-4b1c260fbce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899264394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1899264394
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.4120680639
Short name T790
Test name
Test status
Simulation time 678181962 ps
CPU time 10.85 seconds
Started Aug 13 04:32:14 PM PDT 24
Finished Aug 13 04:32:25 PM PDT 24
Peak memory 249892 kb
Host smart-d607408d-c845-47fb-88a6-77bfb71f68c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120680639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.4120680639
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2829010185
Short name T976
Test name
Test status
Simulation time 61636970 ps
CPU time 0.77 seconds
Started Aug 13 04:32:09 PM PDT 24
Finished Aug 13 04:32:09 PM PDT 24
Peak memory 216496 kb
Host smart-2f417b24-7869-4fc5-8edf-aa735526f321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829010185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2829010185
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3512109952
Short name T513
Test name
Test status
Simulation time 61263836 ps
CPU time 2.2 seconds
Started Aug 13 04:31:54 PM PDT 24
Finished Aug 13 04:31:57 PM PDT 24
Peak memory 233244 kb
Host smart-846156c5-29bc-4bff-8dd2-7a1b7239f610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512109952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3512109952
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2915531043
Short name T763
Test name
Test status
Simulation time 10379566434 ps
CPU time 21.13 seconds
Started Aug 13 04:32:02 PM PDT 24
Finished Aug 13 04:32:23 PM PDT 24
Peak memory 241824 kb
Host smart-885be571-8f2f-422b-a454-adcb908caf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915531043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2915531043
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1753855103
Short name T711
Test name
Test status
Simulation time 31194872 ps
CPU time 2.54 seconds
Started Aug 13 04:32:03 PM PDT 24
Finished Aug 13 04:32:06 PM PDT 24
Peak memory 231912 kb
Host smart-4658f7da-2aca-43d6-a5c3-355f3454cc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753855103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1753855103
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1693237763
Short name T471
Test name
Test status
Simulation time 31973861 ps
CPU time 2.23 seconds
Started Aug 13 04:32:24 PM PDT 24
Finished Aug 13 04:32:27 PM PDT 24
Peak memory 233140 kb
Host smart-3f1cbd3b-538e-435a-b6b3-1132b0d28ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693237763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1693237763
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2035281140
Short name T389
Test name
Test status
Simulation time 257819177 ps
CPU time 3.94 seconds
Started Aug 13 04:32:19 PM PDT 24
Finished Aug 13 04:32:23 PM PDT 24
Peak memory 223960 kb
Host smart-49c88862-e98a-4c2c-b846-f93b58789cd6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2035281140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2035281140
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.140324829
Short name T135
Test name
Test status
Simulation time 5912112079 ps
CPU time 79.61 seconds
Started Aug 13 04:32:23 PM PDT 24
Finished Aug 13 04:33:43 PM PDT 24
Peak memory 257836 kb
Host smart-64caa8f6-9e60-49ca-848e-24efed2236c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140324829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.140324829
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3195280147
Short name T643
Test name
Test status
Simulation time 2690330484 ps
CPU time 15.84 seconds
Started Aug 13 04:32:08 PM PDT 24
Finished Aug 13 04:32:29 PM PDT 24
Peak memory 217180 kb
Host smart-25bd82f6-fa88-4ed5-a630-ada4758f5d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195280147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3195280147
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.882131338
Short name T666
Test name
Test status
Simulation time 46626476626 ps
CPU time 10.44 seconds
Started Aug 13 04:31:54 PM PDT 24
Finished Aug 13 04:32:04 PM PDT 24
Peak memory 215932 kb
Host smart-cf786d4c-4cbe-4ca1-b1cf-37c0b15bbcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882131338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.882131338
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3348578676
Short name T606
Test name
Test status
Simulation time 78881130 ps
CPU time 3.93 seconds
Started Aug 13 04:32:19 PM PDT 24
Finished Aug 13 04:32:23 PM PDT 24
Peak memory 217048 kb
Host smart-35183074-eac9-40fa-9f46-a92969cb9674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348578676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3348578676
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.983735349
Short name T575
Test name
Test status
Simulation time 20372679 ps
CPU time 0.68 seconds
Started Aug 13 04:32:16 PM PDT 24
Finished Aug 13 04:32:17 PM PDT 24
Peak memory 206284 kb
Host smart-48988f03-e6fb-41dd-9873-f9d6ff68a107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983735349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.983735349
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2051756457
Short name T207
Test name
Test status
Simulation time 556336027 ps
CPU time 5.9 seconds
Started Aug 13 04:31:51 PM PDT 24
Finished Aug 13 04:31:58 PM PDT 24
Peak memory 238828 kb
Host smart-25191d60-bde4-415d-bc66-8e1579a79e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051756457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2051756457
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1471427183
Short name T820
Test name
Test status
Simulation time 13837380 ps
CPU time 0.76 seconds
Started Aug 13 04:32:23 PM PDT 24
Finished Aug 13 04:32:24 PM PDT 24
Peak memory 206484 kb
Host smart-63535db7-8eb2-47f3-a651-e843e57645ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471427183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1471427183
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.839831488
Short name T708
Test name
Test status
Simulation time 100319024 ps
CPU time 2.47 seconds
Started Aug 13 04:32:11 PM PDT 24
Finished Aug 13 04:32:14 PM PDT 24
Peak memory 233568 kb
Host smart-39deb056-166b-4839-a1a6-19b1d0ce83d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839831488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.839831488
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.40127406
Short name T126
Test name
Test status
Simulation time 20052496 ps
CPU time 0.8 seconds
Started Aug 13 04:32:15 PM PDT 24
Finished Aug 13 04:32:17 PM PDT 24
Peak memory 206268 kb
Host smart-1ccc7247-dc79-4b5d-a921-dd6297419476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40127406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.40127406
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.148729669
Short name T342
Test name
Test status
Simulation time 3045801446 ps
CPU time 48.75 seconds
Started Aug 13 04:32:17 PM PDT 24
Finished Aug 13 04:33:06 PM PDT 24
Peak memory 250868 kb
Host smart-1159db35-2cd3-4565-9d22-513072d264e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148729669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.148729669
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3771684686
Short name T89
Test name
Test status
Simulation time 84414706612 ps
CPU time 161.14 seconds
Started Aug 13 04:32:13 PM PDT 24
Finished Aug 13 04:34:54 PM PDT 24
Peak memory 257992 kb
Host smart-cb016075-b661-478b-a86c-1c60be9b36b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771684686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3771684686
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2886242407
Short name T183
Test name
Test status
Simulation time 44526409543 ps
CPU time 338.35 seconds
Started Aug 13 04:32:11 PM PDT 24
Finished Aug 13 04:37:50 PM PDT 24
Peak memory 251172 kb
Host smart-a309e16a-086b-4d54-a84d-85cf6d1d6448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886242407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2886242407
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2817613184
Short name T574
Test name
Test status
Simulation time 169121495 ps
CPU time 5.26 seconds
Started Aug 13 04:32:22 PM PDT 24
Finished Aug 13 04:32:27 PM PDT 24
Peak memory 234544 kb
Host smart-824d52c1-5e7e-4ae5-b740-b979eb33ba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817613184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2817613184
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2715399659
Short name T778
Test name
Test status
Simulation time 27907198720 ps
CPU time 66.39 seconds
Started Aug 13 04:32:16 PM PDT 24
Finished Aug 13 04:33:22 PM PDT 24
Peak memory 251964 kb
Host smart-33416648-02f8-49f3-af89-aa59316f284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715399659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2715399659
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2831040222
Short name T688
Test name
Test status
Simulation time 1956080872 ps
CPU time 20.03 seconds
Started Aug 13 04:32:20 PM PDT 24
Finished Aug 13 04:32:40 PM PDT 24
Peak memory 233528 kb
Host smart-2527d856-8adf-4e5b-b7de-52fc25e75990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831040222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2831040222
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1484950971
Short name T651
Test name
Test status
Simulation time 849378301 ps
CPU time 12.36 seconds
Started Aug 13 04:32:28 PM PDT 24
Finished Aug 13 04:32:40 PM PDT 24
Peak memory 225244 kb
Host smart-3bed367c-542f-4e49-a9b2-2ed2c009f138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484950971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1484950971
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2111773380
Short name T635
Test name
Test status
Simulation time 2117524779 ps
CPU time 3.67 seconds
Started Aug 13 04:32:24 PM PDT 24
Finished Aug 13 04:32:28 PM PDT 24
Peak memory 233472 kb
Host smart-e663f6d8-5314-4e85-af46-fa874ca2e979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111773380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2111773380
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.556096821
Short name T381
Test name
Test status
Simulation time 562709225 ps
CPU time 6.9 seconds
Started Aug 13 04:32:32 PM PDT 24
Finished Aug 13 04:32:39 PM PDT 24
Peak memory 238088 kb
Host smart-9b812218-de44-4aa0-85ac-9c1385c655f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556096821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.556096821
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.604697465
Short name T491
Test name
Test status
Simulation time 1507201681 ps
CPU time 6.56 seconds
Started Aug 13 04:32:03 PM PDT 24
Finished Aug 13 04:32:10 PM PDT 24
Peak memory 219612 kb
Host smart-29b25f94-7c41-4643-97f5-b205ce6ac020
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=604697465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.604697465
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1691293367
Short name T474
Test name
Test status
Simulation time 49586663272 ps
CPU time 135.03 seconds
Started Aug 13 04:32:27 PM PDT 24
Finished Aug 13 04:34:42 PM PDT 24
Peak memory 257212 kb
Host smart-e06c2f92-c088-488c-9120-197be8595610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691293367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1691293367
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2978221496
Short name T61
Test name
Test status
Simulation time 44837652376 ps
CPU time 17.47 seconds
Started Aug 13 04:32:03 PM PDT 24
Finished Aug 13 04:32:21 PM PDT 24
Peak memory 220948 kb
Host smart-d09b2d35-ec6f-4531-9733-40d2e53b0ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978221496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2978221496
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4041322068
Short name T998
Test name
Test status
Simulation time 44575870 ps
CPU time 0.68 seconds
Started Aug 13 04:31:59 PM PDT 24
Finished Aug 13 04:32:00 PM PDT 24
Peak memory 206400 kb
Host smart-d7b51444-f6c4-4d8e-9a9f-9d50baa44380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041322068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4041322068
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3978004002
Short name T320
Test name
Test status
Simulation time 20531862 ps
CPU time 1.13 seconds
Started Aug 13 04:32:23 PM PDT 24
Finished Aug 13 04:32:24 PM PDT 24
Peak memory 208932 kb
Host smart-2dbe9842-aaea-4440-aec4-c9cc23f6330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978004002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3978004002
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.559059644
Short name T962
Test name
Test status
Simulation time 32797597 ps
CPU time 0.88 seconds
Started Aug 13 04:32:22 PM PDT 24
Finished Aug 13 04:32:23 PM PDT 24
Peak memory 206740 kb
Host smart-6612e54b-de62-4133-baaf-c5db23e21a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559059644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.559059644
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3909318346
Short name T570
Test name
Test status
Simulation time 2959536053 ps
CPU time 13.48 seconds
Started Aug 13 04:32:18 PM PDT 24
Finished Aug 13 04:32:31 PM PDT 24
Peak memory 234652 kb
Host smart-04b74dd9-885b-447a-9496-58fdec2d4207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909318346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3909318346
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3607891911
Short name T312
Test name
Test status
Simulation time 12296515 ps
CPU time 0.74 seconds
Started Aug 13 04:32:27 PM PDT 24
Finished Aug 13 04:32:28 PM PDT 24
Peak memory 206736 kb
Host smart-5393fe7a-f550-4ee7-a623-5b78e083036c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607891911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3607891911
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1281956097
Short name T838
Test name
Test status
Simulation time 1641822120 ps
CPU time 7.54 seconds
Started Aug 13 04:32:15 PM PDT 24
Finished Aug 13 04:32:22 PM PDT 24
Peak memory 225372 kb
Host smart-8d6ee9c6-0aba-46c9-afaa-41d6427ca4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281956097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1281956097
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1511123520
Short name T579
Test name
Test status
Simulation time 20462742 ps
CPU time 0.74 seconds
Started Aug 13 04:32:16 PM PDT 24
Finished Aug 13 04:32:16 PM PDT 24
Peak memory 206204 kb
Host smart-ad73fd1c-50cb-454b-8650-a60d9d60d8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511123520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1511123520
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.978005582
Short name T196
Test name
Test status
Simulation time 33791154674 ps
CPU time 177.38 seconds
Started Aug 13 04:32:34 PM PDT 24
Finished Aug 13 04:35:32 PM PDT 24
Peak memory 254668 kb
Host smart-0d33260f-503d-4e53-b20e-6fa0f8f13781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978005582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.978005582
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2363792186
Short name T377
Test name
Test status
Simulation time 6948475982 ps
CPU time 57.79 seconds
Started Aug 13 04:32:17 PM PDT 24
Finished Aug 13 04:33:15 PM PDT 24
Peak memory 241884 kb
Host smart-ed8e9368-17f9-4e90-919c-fcc81fb1ba8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363792186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2363792186
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2472025597
Short name T297
Test name
Test status
Simulation time 4845149542 ps
CPU time 12.29 seconds
Started Aug 13 04:32:34 PM PDT 24
Finished Aug 13 04:32:47 PM PDT 24
Peak memory 250848 kb
Host smart-4696a309-d261-490a-bf0b-37cf125133bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472025597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2472025597
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2601093866
Short name T217
Test name
Test status
Simulation time 44206815255 ps
CPU time 148.63 seconds
Started Aug 13 04:32:20 PM PDT 24
Finished Aug 13 04:34:49 PM PDT 24
Peak memory 254720 kb
Host smart-c73e783f-e1c8-42c3-901b-6fd683422980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601093866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2601093866
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3457904596
Short name T999
Test name
Test status
Simulation time 333792297 ps
CPU time 2.41 seconds
Started Aug 13 04:32:19 PM PDT 24
Finished Aug 13 04:32:21 PM PDT 24
Peak memory 233216 kb
Host smart-16adcc72-289f-4987-a1b7-f7b2ede77d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457904596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3457904596
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.343970401
Short name T193
Test name
Test status
Simulation time 7318278470 ps
CPU time 14.52 seconds
Started Aug 13 04:32:01 PM PDT 24
Finished Aug 13 04:32:15 PM PDT 24
Peak memory 240356 kb
Host smart-e55223d4-4c83-4e52-9420-496bbb417a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343970401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.343970401
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.474249631
Short name T190
Test name
Test status
Simulation time 4428046582 ps
CPU time 14.53 seconds
Started Aug 13 04:32:10 PM PDT 24
Finished Aug 13 04:32:24 PM PDT 24
Peak memory 233552 kb
Host smart-8c7c716f-81b2-4857-b977-d9d05354aaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474249631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.474249631
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.443956754
Short name T449
Test name
Test status
Simulation time 810140143 ps
CPU time 3.63 seconds
Started Aug 13 04:32:02 PM PDT 24
Finished Aug 13 04:32:06 PM PDT 24
Peak memory 233500 kb
Host smart-2d229441-a2bb-4d01-91df-d425f2d8299e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443956754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.443956754
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1183438632
Short name T608
Test name
Test status
Simulation time 507493241 ps
CPU time 5.55 seconds
Started Aug 13 04:32:10 PM PDT 24
Finished Aug 13 04:32:15 PM PDT 24
Peak memory 221128 kb
Host smart-909703aa-72b0-44fc-b1ba-6fa116d56831
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1183438632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1183438632
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3326126231
Short name T63
Test name
Test status
Simulation time 5938366142 ps
CPU time 39.57 seconds
Started Aug 13 04:32:18 PM PDT 24
Finished Aug 13 04:32:58 PM PDT 24
Peak memory 250108 kb
Host smart-b03210e9-a1d8-434c-b14c-409bc1eccce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326126231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3326126231
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.937880023
Short name T798
Test name
Test status
Simulation time 2656127046 ps
CPU time 13.34 seconds
Started Aug 13 04:32:20 PM PDT 24
Finished Aug 13 04:32:34 PM PDT 24
Peak memory 217160 kb
Host smart-1f07e4b4-3301-4ad5-8d60-badfe139f6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937880023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.937880023
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1361801035
Short name T12
Test name
Test status
Simulation time 3869120684 ps
CPU time 6.03 seconds
Started Aug 13 04:32:23 PM PDT 24
Finished Aug 13 04:32:29 PM PDT 24
Peak memory 217148 kb
Host smart-a802f62f-259b-4936-808b-bda236894c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361801035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1361801035
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1440315886
Short name T893
Test name
Test status
Simulation time 152671776 ps
CPU time 1.24 seconds
Started Aug 13 04:32:13 PM PDT 24
Finished Aug 13 04:32:14 PM PDT 24
Peak memory 217188 kb
Host smart-b581b423-bc98-4541-a9c1-d43eb11b1fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440315886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1440315886
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.430821379
Short name T898
Test name
Test status
Simulation time 69150736 ps
CPU time 0.7 seconds
Started Aug 13 04:32:29 PM PDT 24
Finished Aug 13 04:32:30 PM PDT 24
Peak memory 206764 kb
Host smart-ba335275-a494-4c86-b91e-707b07e1be01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430821379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.430821379
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3108063436
Short name T10
Test name
Test status
Simulation time 11430403652 ps
CPU time 20.55 seconds
Started Aug 13 04:32:13 PM PDT 24
Finished Aug 13 04:32:33 PM PDT 24
Peak memory 241304 kb
Host smart-9743df25-dc16-41e9-9653-7340fba86a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108063436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3108063436
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3514098719
Short name T408
Test name
Test status
Simulation time 50589157 ps
CPU time 0.73 seconds
Started Aug 13 04:32:09 PM PDT 24
Finished Aug 13 04:32:10 PM PDT 24
Peak memory 206184 kb
Host smart-77831998-1fd8-45ea-99af-2cd000b457b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514098719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3514098719
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.440260658
Short name T946
Test name
Test status
Simulation time 309161044 ps
CPU time 5.85 seconds
Started Aug 13 04:32:31 PM PDT 24
Finished Aug 13 04:32:37 PM PDT 24
Peak memory 233468 kb
Host smart-11ec70d7-f57b-4277-b8a1-c0ff0dc15ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440260658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.440260658
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2228061913
Short name T659
Test name
Test status
Simulation time 70409777 ps
CPU time 0.76 seconds
Started Aug 13 04:32:17 PM PDT 24
Finished Aug 13 04:32:18 PM PDT 24
Peak memory 206296 kb
Host smart-eec3f453-a604-4aa7-92c0-3ad478e59a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228061913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2228061913
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.520482491
Short name T740
Test name
Test status
Simulation time 5594052466 ps
CPU time 21.57 seconds
Started Aug 13 04:32:07 PM PDT 24
Finished Aug 13 04:32:29 PM PDT 24
Peak memory 239464 kb
Host smart-d1b6c37a-a952-4b93-adef-023babec2602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520482491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.520482491
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1278383059
Short name T770
Test name
Test status
Simulation time 2193307443 ps
CPU time 35.95 seconds
Started Aug 13 04:32:02 PM PDT 24
Finished Aug 13 04:32:38 PM PDT 24
Peak memory 233740 kb
Host smart-ff708db9-ff8c-4a17-8a0c-922dee0368d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278383059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1278383059
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1853428378
Short name T287
Test name
Test status
Simulation time 796520260 ps
CPU time 6.03 seconds
Started Aug 13 04:32:30 PM PDT 24
Finished Aug 13 04:32:36 PM PDT 24
Peak memory 225348 kb
Host smart-c8bfcb5a-4a22-4e1d-8504-0044ef576736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853428378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1853428378
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.53613129
Short name T671
Test name
Test status
Simulation time 81834323482 ps
CPU time 98.88 seconds
Started Aug 13 04:32:11 PM PDT 24
Finished Aug 13 04:33:50 PM PDT 24
Peak memory 250000 kb
Host smart-efd646b4-608e-483c-8ae8-daaed3cdc582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53613129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.53613129
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1423556818
Short name T308
Test name
Test status
Simulation time 451165811 ps
CPU time 4.76 seconds
Started Aug 13 04:32:04 PM PDT 24
Finished Aug 13 04:32:09 PM PDT 24
Peak memory 225204 kb
Host smart-4963adc6-1a10-42c1-956d-f88b6b12ebe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423556818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1423556818
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1626298152
Short name T392
Test name
Test status
Simulation time 11237426003 ps
CPU time 100.38 seconds
Started Aug 13 04:32:20 PM PDT 24
Finished Aug 13 04:34:00 PM PDT 24
Peak memory 241976 kb
Host smart-ffecf0a0-62a1-4175-8d26-9ee611835650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626298152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1626298152
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1745644529
Short name T502
Test name
Test status
Simulation time 127014719 ps
CPU time 2.36 seconds
Started Aug 13 04:32:20 PM PDT 24
Finished Aug 13 04:32:22 PM PDT 24
Peak memory 225192 kb
Host smart-b8b0d8dc-6c67-4d90-b937-01d630362752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745644529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1745644529
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2043662219
Short name T646
Test name
Test status
Simulation time 1768844272 ps
CPU time 6.84 seconds
Started Aug 13 04:32:21 PM PDT 24
Finished Aug 13 04:32:28 PM PDT 24
Peak memory 225172 kb
Host smart-e4c7a7a7-3edb-48e3-a03e-3695a9af26a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043662219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2043662219
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.754651375
Short name T422
Test name
Test status
Simulation time 2713501365 ps
CPU time 11.99 seconds
Started Aug 13 04:32:18 PM PDT 24
Finished Aug 13 04:32:30 PM PDT 24
Peak memory 220304 kb
Host smart-72c8bc23-53c6-4539-8d54-687229a50742
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=754651375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.754651375
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3357848543
Short name T731
Test name
Test status
Simulation time 124643677 ps
CPU time 0.83 seconds
Started Aug 13 04:32:17 PM PDT 24
Finished Aug 13 04:32:18 PM PDT 24
Peak memory 206608 kb
Host smart-10e85b24-4054-401c-a081-54a0ba251658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357848543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3357848543
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.874743604
Short name T704
Test name
Test status
Simulation time 2416927308 ps
CPU time 25.99 seconds
Started Aug 13 04:32:07 PM PDT 24
Finished Aug 13 04:32:34 PM PDT 24
Peak memory 221208 kb
Host smart-ddc4036a-04a3-4205-aed9-2a162b69cefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874743604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.874743604
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.5542939
Short name T599
Test name
Test status
Simulation time 287578054 ps
CPU time 1.8 seconds
Started Aug 13 04:32:16 PM PDT 24
Finished Aug 13 04:32:18 PM PDT 24
Peak memory 216740 kb
Host smart-64b33791-b4b2-444d-951a-5679c4563b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5542939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.5542939
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.123263913
Short name T163
Test name
Test status
Simulation time 623513770 ps
CPU time 2.48 seconds
Started Aug 13 04:32:04 PM PDT 24
Finished Aug 13 04:32:06 PM PDT 24
Peak memory 217092 kb
Host smart-20a60fbf-b716-482e-b0a6-19a55ba32074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123263913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.123263913
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.254348527
Short name T409
Test name
Test status
Simulation time 22038619 ps
CPU time 0.75 seconds
Started Aug 13 04:32:14 PM PDT 24
Finished Aug 13 04:32:15 PM PDT 24
Peak memory 206748 kb
Host smart-4a3f1ddd-d378-4aa0-8f42-fefbdf5c237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254348527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.254348527
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.10627051
Short name T801
Test name
Test status
Simulation time 172513014 ps
CPU time 2.32 seconds
Started Aug 13 04:32:17 PM PDT 24
Finished Aug 13 04:32:21 PM PDT 24
Peak memory 224904 kb
Host smart-3abb1709-9f5e-40ef-86b6-978565c1eaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10627051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.10627051
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2740099050
Short name T621
Test name
Test status
Simulation time 13158105 ps
CPU time 0.71 seconds
Started Aug 13 04:32:17 PM PDT 24
Finished Aug 13 04:32:18 PM PDT 24
Peak memory 205624 kb
Host smart-0c038795-ba61-4621-a415-d2b4f5a00168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740099050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2740099050
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1032953318
Short name T839
Test name
Test status
Simulation time 276129221 ps
CPU time 4.21 seconds
Started Aug 13 04:32:26 PM PDT 24
Finished Aug 13 04:32:30 PM PDT 24
Peak memory 233472 kb
Host smart-7e4d8e10-7c2d-401a-81fc-28841cabf640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032953318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1032953318
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2571605197
Short name T391
Test name
Test status
Simulation time 18113442 ps
CPU time 0.77 seconds
Started Aug 13 04:32:12 PM PDT 24
Finished Aug 13 04:32:18 PM PDT 24
Peak memory 207448 kb
Host smart-094bc219-7110-4541-b531-dad40613d4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571605197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2571605197
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2326558110
Short name T85
Test name
Test status
Simulation time 32661474471 ps
CPU time 237.67 seconds
Started Aug 13 04:32:29 PM PDT 24
Finished Aug 13 04:36:27 PM PDT 24
Peak memory 249952 kb
Host smart-70789d26-216e-4087-9e49-1f13e5a811df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326558110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2326558110
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.70036053
Short name T83
Test name
Test status
Simulation time 643170182 ps
CPU time 17.05 seconds
Started Aug 13 04:32:10 PM PDT 24
Finished Aug 13 04:32:27 PM PDT 24
Peak memory 239196 kb
Host smart-296b0838-8523-4966-9167-658d61eaacb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70036053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.70036053
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3873525459
Short name T295
Test name
Test status
Simulation time 4870026145 ps
CPU time 18.96 seconds
Started Aug 13 04:32:28 PM PDT 24
Finished Aug 13 04:32:47 PM PDT 24
Peak memory 237580 kb
Host smart-b03eca81-d30d-44df-9d71-103c09f37bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873525459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3873525459
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.919053303
Short name T36
Test name
Test status
Simulation time 29833614894 ps
CPU time 57.26 seconds
Started Aug 13 04:32:26 PM PDT 24
Finished Aug 13 04:33:23 PM PDT 24
Peak memory 250788 kb
Host smart-4f11afcc-8ad9-40c6-8cdc-fa4a705f7c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919053303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.919053303
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2115870875
Short name T590
Test name
Test status
Simulation time 573915893 ps
CPU time 3.39 seconds
Started Aug 13 04:32:19 PM PDT 24
Finished Aug 13 04:32:23 PM PDT 24
Peak memory 225316 kb
Host smart-12b5e888-571b-41ae-a63d-ab83e049e494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115870875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2115870875
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2275132127
Short name T772
Test name
Test status
Simulation time 548841109 ps
CPU time 14.63 seconds
Started Aug 13 04:32:10 PM PDT 24
Finished Aug 13 04:32:25 PM PDT 24
Peak memory 233472 kb
Host smart-a8956714-7e50-47ec-827a-82294e03799d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275132127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2275132127
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2231163065
Short name T785
Test name
Test status
Simulation time 16007230217 ps
CPU time 18.03 seconds
Started Aug 13 04:32:21 PM PDT 24
Finished Aug 13 04:32:40 PM PDT 24
Peak memory 233512 kb
Host smart-3a35404b-2d23-4572-9aff-3f659cd8f60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231163065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2231163065
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2848061540
Short name T828
Test name
Test status
Simulation time 31434866 ps
CPU time 1.94 seconds
Started Aug 13 04:32:25 PM PDT 24
Finished Aug 13 04:32:27 PM PDT 24
Peak memory 225216 kb
Host smart-ef225d05-469a-4943-bd49-3d1f51aca903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848061540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2848061540
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1534632336
Short name T382
Test name
Test status
Simulation time 4064201684 ps
CPU time 10.54 seconds
Started Aug 13 04:32:15 PM PDT 24
Finished Aug 13 04:32:26 PM PDT 24
Peak memory 223972 kb
Host smart-59a4356a-dd3d-4c5e-a514-f62d01796492
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1534632336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1534632336
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3581072369
Short name T473
Test name
Test status
Simulation time 13897232844 ps
CPU time 102 seconds
Started Aug 13 04:32:20 PM PDT 24
Finished Aug 13 04:34:03 PM PDT 24
Peak memory 254256 kb
Host smart-9e145e34-a574-4e35-bd25-34f7e69bc37e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581072369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3581072369
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2168070880
Short name T780
Test name
Test status
Simulation time 1514911317 ps
CPU time 23.73 seconds
Started Aug 13 04:32:41 PM PDT 24
Finished Aug 13 04:33:05 PM PDT 24
Peak memory 217212 kb
Host smart-660da6fc-aa2a-462b-a1f1-4bdd88dec3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168070880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2168070880
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.93739097
Short name T519
Test name
Test status
Simulation time 1105220221 ps
CPU time 3.82 seconds
Started Aug 13 04:32:11 PM PDT 24
Finished Aug 13 04:32:15 PM PDT 24
Peak memory 216804 kb
Host smart-5953e9ac-0723-465d-9e99-d09a6854ae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93739097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.93739097
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.346118400
Short name T807
Test name
Test status
Simulation time 533959669 ps
CPU time 1.9 seconds
Started Aug 13 04:32:20 PM PDT 24
Finished Aug 13 04:32:22 PM PDT 24
Peak memory 217092 kb
Host smart-8dfe4e73-9d1a-4f5a-86aa-8780d32adaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346118400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.346118400
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3051853451
Short name T694
Test name
Test status
Simulation time 60393481 ps
CPU time 0.92 seconds
Started Aug 13 04:32:11 PM PDT 24
Finished Aug 13 04:32:12 PM PDT 24
Peak memory 206744 kb
Host smart-e5b27930-a169-4423-a863-8e9455594e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051853451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3051853451
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2341158566
Short name T181
Test name
Test status
Simulation time 7234804251 ps
CPU time 20.5 seconds
Started Aug 13 04:32:15 PM PDT 24
Finished Aug 13 04:32:36 PM PDT 24
Peak memory 233452 kb
Host smart-09c45dd5-a57b-4db3-a0e8-00d461e692b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341158566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2341158566
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1515803799
Short name T844
Test name
Test status
Simulation time 21600974 ps
CPU time 0.71 seconds
Started Aug 13 04:32:25 PM PDT 24
Finished Aug 13 04:32:25 PM PDT 24
Peak memory 206480 kb
Host smart-2fe3e152-80e4-4c99-9864-10550d97b61a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515803799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1515803799
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1492425566
Short name T886
Test name
Test status
Simulation time 212479265 ps
CPU time 3.78 seconds
Started Aug 13 04:32:25 PM PDT 24
Finished Aug 13 04:32:28 PM PDT 24
Peak memory 233432 kb
Host smart-9af4dd30-08fd-4f4e-ab4e-e5882c4e0077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492425566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1492425566
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1244557714
Short name T733
Test name
Test status
Simulation time 15047558 ps
CPU time 0.75 seconds
Started Aug 13 04:32:23 PM PDT 24
Finished Aug 13 04:32:24 PM PDT 24
Peak memory 207636 kb
Host smart-d943dee3-fc23-4427-88fb-d06224969a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244557714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1244557714
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3703261959
Short name T204
Test name
Test status
Simulation time 54866141900 ps
CPU time 376.13 seconds
Started Aug 13 04:32:41 PM PDT 24
Finished Aug 13 04:38:57 PM PDT 24
Peak memory 254484 kb
Host smart-f3b82b27-025a-4e57-8244-03ad38e05bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703261959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3703261959
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1792848280
Short name T756
Test name
Test status
Simulation time 14639027375 ps
CPU time 130.38 seconds
Started Aug 13 04:32:22 PM PDT 24
Finished Aug 13 04:34:33 PM PDT 24
Peak memory 250128 kb
Host smart-fd8d19a2-d89c-43a4-8e81-4badbf1ef8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792848280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1792848280
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2740141405
Short name T627
Test name
Test status
Simulation time 134765995101 ps
CPU time 326.79 seconds
Started Aug 13 04:32:47 PM PDT 24
Finished Aug 13 04:38:14 PM PDT 24
Peak memory 270872 kb
Host smart-8fef724d-5c76-47c0-ba1d-5f19a3ab5ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740141405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2740141405
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3287497636
Short name T427
Test name
Test status
Simulation time 469312704 ps
CPU time 4.62 seconds
Started Aug 13 04:33:12 PM PDT 24
Finished Aug 13 04:33:18 PM PDT 24
Peak memory 239720 kb
Host smart-b541a945-3847-43a7-b4d2-559b4f2625d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287497636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3287497636
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1375235643
Short name T495
Test name
Test status
Simulation time 1780396124 ps
CPU time 43.35 seconds
Started Aug 13 04:32:43 PM PDT 24
Finished Aug 13 04:33:27 PM PDT 24
Peak memory 253304 kb
Host smart-4e6f33ee-a20b-444a-9b14-59684cb653e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375235643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1375235643
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1122950974
Short name T592
Test name
Test status
Simulation time 2166951269 ps
CPU time 7.03 seconds
Started Aug 13 04:32:16 PM PDT 24
Finished Aug 13 04:32:23 PM PDT 24
Peak memory 220492 kb
Host smart-8fd18325-b7df-48e9-a56a-dbab985616e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122950974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1122950974
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.358039057
Short name T932
Test name
Test status
Simulation time 35488196984 ps
CPU time 89.99 seconds
Started Aug 13 04:32:22 PM PDT 24
Finished Aug 13 04:33:52 PM PDT 24
Peak memory 225388 kb
Host smart-23dcbb3e-983d-4c65-8fe4-46ac426a6a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358039057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.358039057
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1834414026
Short name T346
Test name
Test status
Simulation time 818057537 ps
CPU time 6.81 seconds
Started Aug 13 04:32:07 PM PDT 24
Finished Aug 13 04:32:14 PM PDT 24
Peak memory 233480 kb
Host smart-46ee703d-444d-4de4-b9b1-490b721c558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834414026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1834414026
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.822005396
Short name T753
Test name
Test status
Simulation time 51289567 ps
CPU time 1.95 seconds
Started Aug 13 04:32:22 PM PDT 24
Finished Aug 13 04:32:25 PM PDT 24
Peak memory 224200 kb
Host smart-0b128b0f-f323-4449-82d6-d38000dbc586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822005396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.822005396
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1910672901
Short name T368
Test name
Test status
Simulation time 1807483267 ps
CPU time 5.72 seconds
Started Aug 13 04:32:24 PM PDT 24
Finished Aug 13 04:32:30 PM PDT 24
Peak memory 222456 kb
Host smart-d0ab8f92-f941-43d0-9b22-a5db98057c48
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1910672901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1910672901
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1278872516
Short name T475
Test name
Test status
Simulation time 14575572159 ps
CPU time 38.54 seconds
Started Aug 13 04:32:24 PM PDT 24
Finished Aug 13 04:33:03 PM PDT 24
Peak memory 217220 kb
Host smart-14db315b-81c4-4410-9fa9-6200e1f448dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278872516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1278872516
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2940822506
Short name T307
Test name
Test status
Simulation time 504731659 ps
CPU time 3.41 seconds
Started Aug 13 04:32:16 PM PDT 24
Finished Aug 13 04:32:19 PM PDT 24
Peak memory 217136 kb
Host smart-1c782c82-d7d7-4a67-bb6a-923e231f44b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940822506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2940822506
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1430686036
Short name T669
Test name
Test status
Simulation time 116064909 ps
CPU time 2.02 seconds
Started Aug 13 04:32:17 PM PDT 24
Finished Aug 13 04:32:19 PM PDT 24
Peak memory 217116 kb
Host smart-f1ce4f5f-10d6-4c99-a332-8dda1ee5e284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430686036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1430686036
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1281009206
Short name T28
Test name
Test status
Simulation time 58764700 ps
CPU time 0.74 seconds
Started Aug 13 04:32:19 PM PDT 24
Finished Aug 13 04:32:20 PM PDT 24
Peak memory 206724 kb
Host smart-9300ccaa-c83f-400b-ac93-d2416b00b2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281009206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1281009206
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3466656746
Short name T576
Test name
Test status
Simulation time 1122017968 ps
CPU time 10.79 seconds
Started Aug 13 04:32:23 PM PDT 24
Finished Aug 13 04:32:34 PM PDT 24
Peak memory 236704 kb
Host smart-0c9fa09e-67b8-4322-9b68-91c23dbb2e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466656746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3466656746
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.223543399
Short name T309
Test name
Test status
Simulation time 20325400 ps
CPU time 0.67 seconds
Started Aug 13 04:32:15 PM PDT 24
Finished Aug 13 04:32:16 PM PDT 24
Peak memory 206160 kb
Host smart-e4973ebe-9aa1-4159-a5ed-27b9f660d664
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223543399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.223543399
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2369911446
Short name T672
Test name
Test status
Simulation time 34462755 ps
CPU time 2.48 seconds
Started Aug 13 04:32:15 PM PDT 24
Finished Aug 13 04:32:18 PM PDT 24
Peak memory 233180 kb
Host smart-ce0e5d83-2e9c-4c27-b482-6d4edc96c60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369911446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2369911446
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3705912859
Short name T15
Test name
Test status
Simulation time 13602728 ps
CPU time 0.92 seconds
Started Aug 13 04:33:12 PM PDT 24
Finished Aug 13 04:33:14 PM PDT 24
Peak memory 205644 kb
Host smart-9912c928-91df-4732-a8a2-d3e4e0fc84d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705912859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3705912859
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2791786253
Short name T690
Test name
Test status
Simulation time 3652820939 ps
CPU time 17.78 seconds
Started Aug 13 04:32:22 PM PDT 24
Finished Aug 13 04:32:39 PM PDT 24
Peak memory 239444 kb
Host smart-d74719f8-458a-4bce-bf51-b99f6d6b7b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791786253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2791786253
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3339268601
Short name T892
Test name
Test status
Simulation time 86131472269 ps
CPU time 232.75 seconds
Started Aug 13 04:33:33 PM PDT 24
Finished Aug 13 04:37:26 PM PDT 24
Peak memory 268388 kb
Host smart-4061cfba-2ae6-45b0-8471-65d3b1d150b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339268601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3339268601
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.876839107
Short name T721
Test name
Test status
Simulation time 63412427935 ps
CPU time 313.25 seconds
Started Aug 13 04:32:30 PM PDT 24
Finished Aug 13 04:37:44 PM PDT 24
Peak memory 250308 kb
Host smart-b0857a4b-09ce-4597-90a1-2aa617455c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876839107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.876839107
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.533021141
Short name T759
Test name
Test status
Simulation time 566255234 ps
CPU time 8.85 seconds
Started Aug 13 04:32:22 PM PDT 24
Finished Aug 13 04:32:31 PM PDT 24
Peak memory 234568 kb
Host smart-4a763b6b-12a9-4a6f-be68-6e920642e116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533021141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.533021141
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.4100110964
Short name T434
Test name
Test status
Simulation time 56597141 ps
CPU time 0.95 seconds
Started Aug 13 04:32:28 PM PDT 24
Finished Aug 13 04:32:29 PM PDT 24
Peak memory 216788 kb
Host smart-605eab7a-c24b-4ade-8b90-c3ae15a0ba98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100110964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.4100110964
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1490256545
Short name T939
Test name
Test status
Simulation time 284480990 ps
CPU time 3.54 seconds
Started Aug 13 04:32:23 PM PDT 24
Finished Aug 13 04:32:27 PM PDT 24
Peak memory 233764 kb
Host smart-808eed4d-2310-428a-8693-9873d24518de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490256545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1490256545
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1747390533
Short name T278
Test name
Test status
Simulation time 2647178687 ps
CPU time 8.32 seconds
Started Aug 13 04:32:21 PM PDT 24
Finished Aug 13 04:32:30 PM PDT 24
Peak memory 233564 kb
Host smart-3ff8fa5c-a045-4577-8644-70047c5165b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747390533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1747390533
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.4216898238
Short name T282
Test name
Test status
Simulation time 112455001 ps
CPU time 2.81 seconds
Started Aug 13 04:32:28 PM PDT 24
Finished Aug 13 04:32:31 PM PDT 24
Peak memory 233468 kb
Host smart-91ffdd3b-b58a-4c5a-b4e7-052a64f398d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216898238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.4216898238
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.442786036
Short name T532
Test name
Test status
Simulation time 15834269036 ps
CPU time 11.73 seconds
Started Aug 13 04:32:32 PM PDT 24
Finished Aug 13 04:32:44 PM PDT 24
Peak memory 219548 kb
Host smart-0f565328-458f-4b70-9df3-b8861e3f8183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442786036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.442786036
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2896902009
Short name T559
Test name
Test status
Simulation time 1709254026 ps
CPU time 8.72 seconds
Started Aug 13 04:33:43 PM PDT 24
Finished Aug 13 04:33:52 PM PDT 24
Peak memory 219700 kb
Host smart-f9cfc50e-f612-4e9d-8525-80e74a70850f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2896902009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2896902009
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4094002841
Short name T730
Test name
Test status
Simulation time 51212030 ps
CPU time 0.96 seconds
Started Aug 13 04:32:39 PM PDT 24
Finished Aug 13 04:32:40 PM PDT 24
Peak memory 207616 kb
Host smart-679ae66f-1364-4d99-bc21-2316df19ced6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094002841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4094002841
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4091802690
Short name T956
Test name
Test status
Simulation time 59908641200 ps
CPU time 24.06 seconds
Started Aug 13 04:32:15 PM PDT 24
Finished Aug 13 04:32:39 PM PDT 24
Peak memory 217172 kb
Host smart-02318a68-0e12-4071-8f97-25b239d8498f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091802690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4091802690
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.997967749
Short name T641
Test name
Test status
Simulation time 41174254 ps
CPU time 0.81 seconds
Started Aug 13 04:33:12 PM PDT 24
Finished Aug 13 04:33:14 PM PDT 24
Peak memory 204544 kb
Host smart-4d981780-dac7-4607-9e30-bacc9e5b79e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997967749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.997967749
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3281252922
Short name T819
Test name
Test status
Simulation time 56222221 ps
CPU time 1.25 seconds
Started Aug 13 04:32:34 PM PDT 24
Finished Aug 13 04:32:35 PM PDT 24
Peak memory 216868 kb
Host smart-0147f944-f530-4c41-add6-20bba824788c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281252922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3281252922
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.502601064
Short name T611
Test name
Test status
Simulation time 62725687 ps
CPU time 0.92 seconds
Started Aug 13 04:32:29 PM PDT 24
Finished Aug 13 04:32:30 PM PDT 24
Peak memory 206728 kb
Host smart-e830858a-c9c2-4f30-95f0-1d7c6d2a694b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502601064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.502601064
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1480609078
Short name T50
Test name
Test status
Simulation time 1571535643 ps
CPU time 7.52 seconds
Started Aug 13 04:32:46 PM PDT 24
Finished Aug 13 04:32:54 PM PDT 24
Peak memory 233500 kb
Host smart-b8270f31-d127-4515-b6c9-ce55e9910e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480609078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1480609078
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3432273378
Short name T311
Test name
Test status
Simulation time 43136061 ps
CPU time 0.73 seconds
Started Aug 13 04:30:55 PM PDT 24
Finished Aug 13 04:30:56 PM PDT 24
Peak memory 206488 kb
Host smart-f62821bb-348a-4c03-b2d5-66fe70db60e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432273378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
432273378
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2666940229
Short name T457
Test name
Test status
Simulation time 26492607 ps
CPU time 0.78 seconds
Started Aug 13 04:30:56 PM PDT 24
Finished Aug 13 04:30:57 PM PDT 24
Peak memory 207308 kb
Host smart-7b43140f-437a-4e98-808a-dd7a3532d960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666940229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2666940229
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2682214890
Short name T1004
Test name
Test status
Simulation time 561661661 ps
CPU time 10.51 seconds
Started Aug 13 04:30:52 PM PDT 24
Finished Aug 13 04:31:03 PM PDT 24
Peak memory 237664 kb
Host smart-5243a983-4ab5-4f0c-b77e-1249652b44c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682214890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2682214890
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4100227957
Short name T488
Test name
Test status
Simulation time 67476280354 ps
CPU time 298.64 seconds
Started Aug 13 04:30:54 PM PDT 24
Finished Aug 13 04:35:53 PM PDT 24
Peak memory 250144 kb
Host smart-3634cd35-9327-47c3-84b0-87416423c7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100227957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4100227957
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1336786439
Short name T464
Test name
Test status
Simulation time 51572971090 ps
CPU time 238.17 seconds
Started Aug 13 04:30:54 PM PDT 24
Finished Aug 13 04:34:53 PM PDT 24
Peak memory 258208 kb
Host smart-5806ab20-d183-4a46-a93b-549c1dd3a398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336786439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1336786439
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1855988205
Short name T141
Test name
Test status
Simulation time 282558318 ps
CPU time 8.63 seconds
Started Aug 13 04:30:53 PM PDT 24
Finished Aug 13 04:31:02 PM PDT 24
Peak memory 241696 kb
Host smart-fe667b78-4675-4bcd-8bce-f664220fc646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855988205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1855988205
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2865529041
Short name T977
Test name
Test status
Simulation time 2561580083 ps
CPU time 58.2 seconds
Started Aug 13 04:30:50 PM PDT 24
Finished Aug 13 04:31:48 PM PDT 24
Peak memory 254108 kb
Host smart-defdd2ff-1ff5-4f5d-973c-0eb3544d91f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865529041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2865529041
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3893280575
Short name T582
Test name
Test status
Simulation time 140984870 ps
CPU time 4.39 seconds
Started Aug 13 04:30:54 PM PDT 24
Finished Aug 13 04:30:59 PM PDT 24
Peak memory 233440 kb
Host smart-7a319896-76e6-419f-ac75-3c2b0c06261c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893280575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3893280575
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2073138993
Short name T913
Test name
Test status
Simulation time 810073707 ps
CPU time 5.66 seconds
Started Aug 13 04:30:48 PM PDT 24
Finished Aug 13 04:30:54 PM PDT 24
Peak memory 237948 kb
Host smart-37434bcf-425c-4387-b5df-7be60b99066c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073138993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2073138993
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2597306955
Short name T520
Test name
Test status
Simulation time 40914264 ps
CPU time 2.26 seconds
Started Aug 13 04:30:57 PM PDT 24
Finished Aug 13 04:30:59 PM PDT 24
Peak memory 233568 kb
Host smart-06ba3af7-7e70-4326-a654-8732f20b0fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597306955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2597306955
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1978263918
Short name T580
Test name
Test status
Simulation time 41950672 ps
CPU time 2.33 seconds
Started Aug 13 04:30:54 PM PDT 24
Finished Aug 13 04:30:56 PM PDT 24
Peak memory 233388 kb
Host smart-db377745-1f18-4fa7-867c-5827ee57dbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978263918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1978263918
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3197348223
Short name T447
Test name
Test status
Simulation time 624043082 ps
CPU time 6.95 seconds
Started Aug 13 04:30:53 PM PDT 24
Finished Aug 13 04:31:00 PM PDT 24
Peak memory 220108 kb
Host smart-50860b61-6f05-40b2-8410-1915318c1198
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3197348223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3197348223
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2738392949
Short name T803
Test name
Test status
Simulation time 403155993 ps
CPU time 1.07 seconds
Started Aug 13 04:31:00 PM PDT 24
Finished Aug 13 04:31:01 PM PDT 24
Peak memory 207808 kb
Host smart-7f854bb6-29e5-4b94-8d48-0db969bca22c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738392949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2738392949
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3216054063
Short name T755
Test name
Test status
Simulation time 10718744458 ps
CPU time 18.9 seconds
Started Aug 13 04:30:53 PM PDT 24
Finished Aug 13 04:31:13 PM PDT 24
Peak memory 217352 kb
Host smart-1ed131e4-dda4-41b4-839a-f3d20cbc4df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216054063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3216054063
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4227912872
Short name T372
Test name
Test status
Simulation time 965094945 ps
CPU time 6.35 seconds
Started Aug 13 04:30:49 PM PDT 24
Finished Aug 13 04:30:55 PM PDT 24
Peak memory 217092 kb
Host smart-5c6aea5b-bed1-47d3-a941-702fe50325e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227912872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4227912872
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2222191986
Short name T912
Test name
Test status
Simulation time 222650717 ps
CPU time 6.81 seconds
Started Aug 13 04:30:51 PM PDT 24
Finished Aug 13 04:30:58 PM PDT 24
Peak memory 217004 kb
Host smart-cab07db2-58e2-4f57-ba37-d548ec43f317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222191986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2222191986
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.996737506
Short name T14
Test name
Test status
Simulation time 41115289 ps
CPU time 0.79 seconds
Started Aug 13 04:30:54 PM PDT 24
Finished Aug 13 04:30:55 PM PDT 24
Peak memory 206816 kb
Host smart-f6198404-6cb5-46a5-8405-2479380667d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996737506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.996737506
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.710734903
Short name T652
Test name
Test status
Simulation time 32812431387 ps
CPU time 34.76 seconds
Started Aug 13 04:30:49 PM PDT 24
Finished Aug 13 04:31:24 PM PDT 24
Peak memory 233496 kb
Host smart-2d51b54c-5a48-4a8e-88f1-5cc8d001d89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710734903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.710734903
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3901801922
Short name T478
Test name
Test status
Simulation time 13168706 ps
CPU time 0.77 seconds
Started Aug 13 04:32:10 PM PDT 24
Finished Aug 13 04:32:11 PM PDT 24
Peak memory 206616 kb
Host smart-25a08541-4c5f-4210-9eef-4fac3794e89e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901801922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3901801922
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1935382768
Short name T127
Test name
Test status
Simulation time 1235596859 ps
CPU time 8.43 seconds
Started Aug 13 04:32:33 PM PDT 24
Finished Aug 13 04:32:42 PM PDT 24
Peak memory 225260 kb
Host smart-e100fc5a-5200-4fb7-9a9f-bbcc5e9340a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935382768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1935382768
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3870877282
Short name T560
Test name
Test status
Simulation time 19801426 ps
CPU time 0.75 seconds
Started Aug 13 04:32:47 PM PDT 24
Finished Aug 13 04:32:47 PM PDT 24
Peak memory 207412 kb
Host smart-c90e1278-9836-4a96-892d-107663c5cf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870877282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3870877282
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.4024987734
Short name T241
Test name
Test status
Simulation time 151690445562 ps
CPU time 242.29 seconds
Started Aug 13 04:33:32 PM PDT 24
Finished Aug 13 04:37:35 PM PDT 24
Peak memory 273916 kb
Host smart-e74fbe96-c7a9-4413-8b1d-8f905fe3f8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024987734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4024987734
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2203394644
Short name T697
Test name
Test status
Simulation time 16443672810 ps
CPU time 50.88 seconds
Started Aug 13 04:32:48 PM PDT 24
Finished Aug 13 04:33:39 PM PDT 24
Peak memory 241916 kb
Host smart-0a52a47b-bf07-4596-b864-b71afa8eb90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203394644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2203394644
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3555126927
Short name T60
Test name
Test status
Simulation time 381909608 ps
CPU time 7.16 seconds
Started Aug 13 04:32:23 PM PDT 24
Finished Aug 13 04:32:30 PM PDT 24
Peak memory 249452 kb
Host smart-dcdda3b6-c62b-4b89-a885-836433b0cbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555126927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3555126927
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3308849592
Short name T954
Test name
Test status
Simulation time 18563150716 ps
CPU time 61.89 seconds
Started Aug 13 04:32:28 PM PDT 24
Finished Aug 13 04:33:30 PM PDT 24
Peak memory 249948 kb
Host smart-3bd64c42-de93-41e2-ad6a-e38bb112868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308849592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3308849592
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.380801820
Short name T271
Test name
Test status
Simulation time 7572629507 ps
CPU time 19.58 seconds
Started Aug 13 04:33:32 PM PDT 24
Finished Aug 13 04:33:52 PM PDT 24
Peak memory 233484 kb
Host smart-fa50a8be-f021-44fb-b502-8b1ca4bbb1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380801820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.380801820
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2689619719
Short name T917
Test name
Test status
Simulation time 6125998207 ps
CPU time 17.41 seconds
Started Aug 13 04:32:26 PM PDT 24
Finished Aug 13 04:32:44 PM PDT 24
Peak memory 225352 kb
Host smart-644fb884-82bf-42fe-b61b-8b0ab33a3dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689619719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2689619719
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1085306810
Short name T950
Test name
Test status
Simulation time 504999246 ps
CPU time 4.94 seconds
Started Aug 13 04:32:09 PM PDT 24
Finished Aug 13 04:32:14 PM PDT 24
Peak memory 233452 kb
Host smart-4b5dc1cb-b804-41ce-850d-ee30af1a5985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085306810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1085306810
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.422682852
Short name T195
Test name
Test status
Simulation time 27767591603 ps
CPU time 21.35 seconds
Started Aug 13 04:33:29 PM PDT 24
Finished Aug 13 04:33:50 PM PDT 24
Peak memory 241284 kb
Host smart-c261716c-ce8f-48ee-a132-05a6d987c07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422682852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.422682852
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2970679650
Short name T883
Test name
Test status
Simulation time 2207039639 ps
CPU time 12 seconds
Started Aug 13 04:32:34 PM PDT 24
Finished Aug 13 04:32:46 PM PDT 24
Peak memory 219676 kb
Host smart-35c61858-4c01-4b5c-b5c0-41ec4cde1953
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2970679650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2970679650
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1856388765
Short name T640
Test name
Test status
Simulation time 20221313898 ps
CPU time 26.88 seconds
Started Aug 13 04:32:22 PM PDT 24
Finished Aug 13 04:32:50 PM PDT 24
Peak memory 217192 kb
Host smart-96992453-88be-4e4d-a34a-2a49c56293c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856388765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1856388765
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.575060721
Short name T556
Test name
Test status
Simulation time 824686064 ps
CPU time 5.79 seconds
Started Aug 13 04:32:31 PM PDT 24
Finished Aug 13 04:32:37 PM PDT 24
Peak memory 217096 kb
Host smart-a97d96c6-d100-4580-b02d-f11f4e2ff7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575060721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.575060721
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1190872363
Short name T676
Test name
Test status
Simulation time 141038150 ps
CPU time 0.69 seconds
Started Aug 13 04:32:34 PM PDT 24
Finished Aug 13 04:32:40 PM PDT 24
Peak memory 206340 kb
Host smart-e82d609b-db0d-4778-aec9-53bd8e0e9423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190872363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1190872363
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2339130721
Short name T393
Test name
Test status
Simulation time 65964374 ps
CPU time 0.71 seconds
Started Aug 13 04:32:26 PM PDT 24
Finished Aug 13 04:32:27 PM PDT 24
Peak memory 206716 kb
Host smart-cc6b5610-7fbf-4f44-90b5-eb93b2f9cfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339130721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2339130721
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1917872153
Short name T194
Test name
Test status
Simulation time 101322719 ps
CPU time 2.66 seconds
Started Aug 13 04:32:36 PM PDT 24
Finished Aug 13 04:32:39 PM PDT 24
Peak memory 233432 kb
Host smart-28acab92-0ea8-4246-b1d2-48944439eba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917872153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1917872153
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1584005238
Short name T726
Test name
Test status
Simulation time 40333032 ps
CPU time 0.74 seconds
Started Aug 13 04:32:30 PM PDT 24
Finished Aug 13 04:32:31 PM PDT 24
Peak memory 206096 kb
Host smart-20c99de6-81d6-45c5-b2d9-9ab8f200234a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584005238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1584005238
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2213824679
Short name T310
Test name
Test status
Simulation time 348243890 ps
CPU time 2.35 seconds
Started Aug 13 04:32:47 PM PDT 24
Finished Aug 13 04:32:50 PM PDT 24
Peak memory 225284 kb
Host smart-046bddc8-1d61-42e7-9e0d-6b4c10c89b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213824679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2213824679
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.344278186
Short name T323
Test name
Test status
Simulation time 67284708 ps
CPU time 0.81 seconds
Started Aug 13 04:32:09 PM PDT 24
Finished Aug 13 04:32:10 PM PDT 24
Peak memory 207428 kb
Host smart-2b3b20a9-61d9-4c11-93c4-2436425a5b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344278186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.344278186
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.801808535
Short name T7
Test name
Test status
Simulation time 13237145 ps
CPU time 0.77 seconds
Started Aug 13 04:32:45 PM PDT 24
Finished Aug 13 04:32:46 PM PDT 24
Peak memory 216540 kb
Host smart-a4a2d634-91fc-4710-be12-917350e67221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801808535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.801808535
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.927227973
Short name T533
Test name
Test status
Simulation time 6456732585 ps
CPU time 15.59 seconds
Started Aug 13 04:32:30 PM PDT 24
Finished Aug 13 04:32:46 PM PDT 24
Peak memory 218788 kb
Host smart-4084f3e6-cfa9-416b-a9dd-6cc904927e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927227973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.927227973
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.978432862
Short name T384
Test name
Test status
Simulation time 3878506274 ps
CPU time 53.11 seconds
Started Aug 13 04:32:47 PM PDT 24
Finished Aug 13 04:33:40 PM PDT 24
Peak memory 254780 kb
Host smart-2e9357e4-e426-4ba3-85b2-08a7caefc868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978432862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.978432862
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.166943901
Short name T290
Test name
Test status
Simulation time 2041380470 ps
CPU time 11.84 seconds
Started Aug 13 04:33:02 PM PDT 24
Finished Aug 13 04:33:14 PM PDT 24
Peak memory 225280 kb
Host smart-fa7ae33e-05cf-4176-a5fb-6685b20d89c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166943901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.166943901
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2908438419
Short name T794
Test name
Test status
Simulation time 7483816770 ps
CPU time 34.53 seconds
Started Aug 13 04:32:31 PM PDT 24
Finished Aug 13 04:33:06 PM PDT 24
Peak memory 240240 kb
Host smart-c503003e-ff84-4367-8530-623b3570e478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908438419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2908438419
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.625541081
Short name T866
Test name
Test status
Simulation time 1567582027 ps
CPU time 4.12 seconds
Started Aug 13 04:32:39 PM PDT 24
Finished Aug 13 04:32:43 PM PDT 24
Peak memory 233412 kb
Host smart-7e23c5a4-27e1-435d-adeb-5e5f48c79f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625541081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.625541081
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.4107925589
Short name T845
Test name
Test status
Simulation time 409822181 ps
CPU time 5.57 seconds
Started Aug 13 04:32:44 PM PDT 24
Finished Aug 13 04:32:50 PM PDT 24
Peak memory 225244 kb
Host smart-789d01ae-6746-4bc0-9418-17b9e0440262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107925589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.4107925589
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.44144846
Short name T174
Test name
Test status
Simulation time 44822064654 ps
CPU time 25.84 seconds
Started Aug 13 04:32:34 PM PDT 24
Finished Aug 13 04:33:00 PM PDT 24
Peak memory 249964 kb
Host smart-6e25bacd-3398-417b-8ce8-a4ff14d6055b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44144846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.44144846
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.219161856
Short name T715
Test name
Test status
Simulation time 14704908588 ps
CPU time 17.8 seconds
Started Aug 13 04:32:30 PM PDT 24
Finished Aug 13 04:32:48 PM PDT 24
Peak memory 225328 kb
Host smart-f72a2fbc-cea9-47a0-8ee7-dcc5ec779f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219161856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.219161856
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2183585371
Short name T630
Test name
Test status
Simulation time 748479944 ps
CPU time 4.07 seconds
Started Aug 13 04:32:33 PM PDT 24
Finished Aug 13 04:32:37 PM PDT 24
Peak memory 223956 kb
Host smart-72a34ba3-443b-4cef-9ce9-ff0bfc5fdc70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2183585371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2183585371
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3999047824
Short name T710
Test name
Test status
Simulation time 80704693 ps
CPU time 1.15 seconds
Started Aug 13 04:32:29 PM PDT 24
Finished Aug 13 04:32:30 PM PDT 24
Peak memory 207732 kb
Host smart-d298d99f-3162-4c47-964b-6db42cdbdefc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999047824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3999047824
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4070841125
Short name T80
Test name
Test status
Simulation time 7687343091 ps
CPU time 40.44 seconds
Started Aug 13 04:32:04 PM PDT 24
Finished Aug 13 04:32:44 PM PDT 24
Peak memory 217252 kb
Host smart-a34b9bae-1579-4610-8d6b-887f37dcd4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070841125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4070841125
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.429531085
Short name T569
Test name
Test status
Simulation time 4509622291 ps
CPU time 5.5 seconds
Started Aug 13 04:32:28 PM PDT 24
Finished Aug 13 04:32:33 PM PDT 24
Peak memory 217248 kb
Host smart-8796fc25-b898-4d1c-9e96-84322b1034cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429531085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.429531085
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3502644839
Short name T26
Test name
Test status
Simulation time 157711974 ps
CPU time 1.21 seconds
Started Aug 13 04:32:17 PM PDT 24
Finished Aug 13 04:32:18 PM PDT 24
Peak memory 208884 kb
Host smart-c595a62f-13c9-4a35-91c2-e2c653ecff6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502644839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3502644839
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3520368733
Short name T431
Test name
Test status
Simulation time 198971631 ps
CPU time 0.92 seconds
Started Aug 13 04:32:17 PM PDT 24
Finished Aug 13 04:32:18 PM PDT 24
Peak memory 206716 kb
Host smart-19ebf337-e55d-48f1-9644-86016dcffb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520368733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3520368733
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2168124202
Short name T265
Test name
Test status
Simulation time 6154662405 ps
CPU time 8.46 seconds
Started Aug 13 04:33:37 PM PDT 24
Finished Aug 13 04:33:45 PM PDT 24
Peak memory 233448 kb
Host smart-c0b0f67d-b8b6-471d-a70e-51cc29a312fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168124202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2168124202
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.176473593
Short name T423
Test name
Test status
Simulation time 37262359 ps
CPU time 0.69 seconds
Started Aug 13 04:33:33 PM PDT 24
Finished Aug 13 04:33:33 PM PDT 24
Peak memory 206044 kb
Host smart-86e74da3-58a6-48b3-a9a8-7ffe59be1d66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176473593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.176473593
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.787610342
Short name T280
Test name
Test status
Simulation time 2973982291 ps
CPU time 17.28 seconds
Started Aug 13 04:33:29 PM PDT 24
Finished Aug 13 04:33:46 PM PDT 24
Peak memory 233452 kb
Host smart-04f13aee-fa4c-4530-8d36-13177e225d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787610342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.787610342
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1543017051
Short name T586
Test name
Test status
Simulation time 33409521 ps
CPU time 0.74 seconds
Started Aug 13 04:32:29 PM PDT 24
Finished Aug 13 04:32:30 PM PDT 24
Peak memory 206584 kb
Host smart-39c2cbcd-ca69-44b6-a62e-5b686f07895f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543017051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1543017051
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.861530740
Short name T222
Test name
Test status
Simulation time 8788666548 ps
CPU time 24.75 seconds
Started Aug 13 04:33:27 PM PDT 24
Finished Aug 13 04:33:53 PM PDT 24
Peak memory 240472 kb
Host smart-a7fdd6e8-b834-482e-a85a-8bd37a577ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861530740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.861530740
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.4098747182
Short name T969
Test name
Test status
Simulation time 17699669596 ps
CPU time 97.99 seconds
Started Aug 13 04:32:45 PM PDT 24
Finished Aug 13 04:34:23 PM PDT 24
Peak memory 263424 kb
Host smart-eef42ffb-0ec4-47d4-80a3-d155f58a5da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098747182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.4098747182
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.157082591
Short name T296
Test name
Test status
Simulation time 175258532 ps
CPU time 7.54 seconds
Started Aug 13 04:32:21 PM PDT 24
Finished Aug 13 04:32:28 PM PDT 24
Peak memory 249728 kb
Host smart-c7b9b2ae-f9aa-4cfd-888f-e9bc853075ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157082591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.157082591
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2320665761
Short name T814
Test name
Test status
Simulation time 954692274 ps
CPU time 6.72 seconds
Started Aug 13 04:32:25 PM PDT 24
Finished Aug 13 04:32:32 PM PDT 24
Peak memory 225268 kb
Host smart-bb7e0b1f-5759-4a85-bf48-e544d6539c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320665761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2320665761
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.198319333
Short name T356
Test name
Test status
Simulation time 803948319 ps
CPU time 8.66 seconds
Started Aug 13 04:32:21 PM PDT 24
Finished Aug 13 04:32:30 PM PDT 24
Peak memory 233588 kb
Host smart-3fc94883-ace1-48e5-9edc-8da908020aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198319333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.198319333
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.321548734
Short name T535
Test name
Test status
Simulation time 916037906 ps
CPU time 11.41 seconds
Started Aug 13 04:32:46 PM PDT 24
Finished Aug 13 04:32:57 PM PDT 24
Peak memory 225312 kb
Host smart-6c32a426-0fe7-4d1f-9399-28709b66eed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321548734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.321548734
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3189596612
Short name T387
Test name
Test status
Simulation time 2663964605 ps
CPU time 6.11 seconds
Started Aug 13 04:32:58 PM PDT 24
Finished Aug 13 04:33:04 PM PDT 24
Peak memory 225476 kb
Host smart-f67671d0-fcff-4047-a13c-0bb4344d29d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189596612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3189596612
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3208431538
Short name T602
Test name
Test status
Simulation time 58263688 ps
CPU time 2.08 seconds
Started Aug 13 04:32:20 PM PDT 24
Finished Aug 13 04:32:22 PM PDT 24
Peak memory 224516 kb
Host smart-790765eb-92d5-45b3-96e3-3f3351c83fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208431538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3208431538
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3744918074
Short name T138
Test name
Test status
Simulation time 4824491658 ps
CPU time 12.8 seconds
Started Aug 13 04:33:01 PM PDT 24
Finished Aug 13 04:33:14 PM PDT 24
Peak memory 224228 kb
Host smart-3de5f15c-e05c-4f4e-9fdb-7bf631361045
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3744918074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3744918074
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2698832132
Short name T34
Test name
Test status
Simulation time 4931525416 ps
CPU time 120.6 seconds
Started Aug 13 04:32:34 PM PDT 24
Finished Aug 13 04:34:35 PM PDT 24
Peak memory 274576 kb
Host smart-063cc33a-2b1b-4e48-8eb5-015f40b41a6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698832132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2698832132
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3108793253
Short name T931
Test name
Test status
Simulation time 7081987933 ps
CPU time 37.95 seconds
Started Aug 13 04:32:33 PM PDT 24
Finished Aug 13 04:33:11 PM PDT 24
Peak memory 217124 kb
Host smart-fe89e575-4700-4792-86cd-ed1670e9ffc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108793253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3108793253
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1793986167
Short name T25
Test name
Test status
Simulation time 8561564211 ps
CPU time 7.72 seconds
Started Aug 13 04:32:34 PM PDT 24
Finished Aug 13 04:32:42 PM PDT 24
Peak memory 217248 kb
Host smart-6805327f-993b-4c48-9aae-cc4e8ae7c722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793986167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1793986167
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1412214938
Short name T943
Test name
Test status
Simulation time 16449726 ps
CPU time 0.84 seconds
Started Aug 13 04:32:22 PM PDT 24
Finished Aug 13 04:32:23 PM PDT 24
Peak memory 207276 kb
Host smart-f814e661-e3db-4792-b245-2535d87980c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412214938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1412214938
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3644419220
Short name T613
Test name
Test status
Simulation time 122626689 ps
CPU time 0.91 seconds
Started Aug 13 04:32:44 PM PDT 24
Finished Aug 13 04:32:48 PM PDT 24
Peak memory 206796 kb
Host smart-a4ecea95-7ebc-435f-9fc2-d35ecb103cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644419220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3644419220
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2667565382
Short name T809
Test name
Test status
Simulation time 94792721 ps
CPU time 2.23 seconds
Started Aug 13 04:32:29 PM PDT 24
Finished Aug 13 04:32:31 PM PDT 24
Peak memory 225296 kb
Host smart-c2410501-be26-47e8-aef4-0d9ddc08ae3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667565382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2667565382
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.697391120
Short name T841
Test name
Test status
Simulation time 37237092 ps
CPU time 0.69 seconds
Started Aug 13 04:32:33 PM PDT 24
Finished Aug 13 04:32:39 PM PDT 24
Peak memory 205560 kb
Host smart-722429be-a948-4c66-88a9-ae6ca3ef698b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697391120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.697391120
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.190381883
Short name T642
Test name
Test status
Simulation time 95793067 ps
CPU time 2.73 seconds
Started Aug 13 04:32:39 PM PDT 24
Finished Aug 13 04:32:42 PM PDT 24
Peak memory 233372 kb
Host smart-613087b6-463c-4f63-8613-667a5fd1315f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190381883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.190381883
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2738314877
Short name T503
Test name
Test status
Simulation time 19429118 ps
CPU time 0.76 seconds
Started Aug 13 04:32:36 PM PDT 24
Finished Aug 13 04:32:37 PM PDT 24
Peak memory 206304 kb
Host smart-6711482a-6c26-41cc-a3d4-94fcf2c08253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738314877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2738314877
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.398780452
Short name T11
Test name
Test status
Simulation time 1973055599 ps
CPU time 40.6 seconds
Started Aug 13 04:32:41 PM PDT 24
Finished Aug 13 04:33:22 PM PDT 24
Peak memory 252328 kb
Host smart-b17c3de3-7500-45e5-ac32-1d605f31450e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398780452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.398780452
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3712287686
Short name T837
Test name
Test status
Simulation time 2580081754 ps
CPU time 62.25 seconds
Started Aug 13 04:32:45 PM PDT 24
Finished Aug 13 04:33:47 PM PDT 24
Peak memory 258272 kb
Host smart-b1d4db49-e6b8-487c-aca9-b4cefad59874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712287686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3712287686
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2279112840
Short name T57
Test name
Test status
Simulation time 6358404120 ps
CPU time 80.72 seconds
Started Aug 13 04:32:28 PM PDT 24
Finished Aug 13 04:33:49 PM PDT 24
Peak memory 253608 kb
Host smart-98082c7a-2042-475d-a803-fbeb87bc02b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279112840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2279112840
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.311847020
Short name T915
Test name
Test status
Simulation time 251418141 ps
CPU time 4.84 seconds
Started Aug 13 04:32:34 PM PDT 24
Finished Aug 13 04:32:39 PM PDT 24
Peak memory 225296 kb
Host smart-60cf707c-ccdf-4c36-aa9e-58ad665fd380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311847020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.311847020
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.105153700
Short name T777
Test name
Test status
Simulation time 31413741039 ps
CPU time 104.71 seconds
Started Aug 13 04:32:30 PM PDT 24
Finished Aug 13 04:34:15 PM PDT 24
Peak memory 265136 kb
Host smart-34de88e3-507a-4294-a492-441ef43e098e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105153700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.105153700
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2044401673
Short name T188
Test name
Test status
Simulation time 659191485 ps
CPU time 10.53 seconds
Started Aug 13 04:32:32 PM PDT 24
Finished Aug 13 04:32:43 PM PDT 24
Peak memory 225548 kb
Host smart-134746b1-4357-4409-8354-fdda52bf891c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044401673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2044401673
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1216327988
Short name T871
Test name
Test status
Simulation time 21615109458 ps
CPU time 43.06 seconds
Started Aug 13 04:32:21 PM PDT 24
Finished Aug 13 04:33:05 PM PDT 24
Peak memory 250064 kb
Host smart-e569adb8-6286-4494-bfff-bc5bea1bd76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216327988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1216327988
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.4173714883
Short name T283
Test name
Test status
Simulation time 31782108 ps
CPU time 2.15 seconds
Started Aug 13 04:32:27 PM PDT 24
Finished Aug 13 04:32:34 PM PDT 24
Peak memory 225184 kb
Host smart-17cf9055-e9e1-43dc-8953-62da48fad111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173714883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.4173714883
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3550218972
Short name T159
Test name
Test status
Simulation time 253122727 ps
CPU time 3.94 seconds
Started Aug 13 04:32:38 PM PDT 24
Finished Aug 13 04:32:42 PM PDT 24
Peak memory 225428 kb
Host smart-bbdbbf9c-7ef7-4645-9087-671381ce4f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550218972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3550218972
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.327660623
Short name T742
Test name
Test status
Simulation time 1712219215 ps
CPU time 14.92 seconds
Started Aug 13 04:32:42 PM PDT 24
Finished Aug 13 04:32:57 PM PDT 24
Peak memory 220688 kb
Host smart-49e4f594-07b5-48fc-80d6-6cd68f2dc4b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=327660623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.327660623
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3108931961
Short name T748
Test name
Test status
Simulation time 4837498509 ps
CPU time 6.53 seconds
Started Aug 13 04:32:33 PM PDT 24
Finished Aug 13 04:32:40 PM PDT 24
Peak memory 217124 kb
Host smart-be047ad1-f7b9-4537-b5b1-413526fdae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108931961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3108931961
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.843339917
Short name T614
Test name
Test status
Simulation time 798277048 ps
CPU time 5.5 seconds
Started Aug 13 04:32:33 PM PDT 24
Finished Aug 13 04:32:39 PM PDT 24
Peak memory 217040 kb
Host smart-06fc34fb-f886-46a1-99dd-d88de0f8d32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843339917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.843339917
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1556339176
Short name T727
Test name
Test status
Simulation time 251132311 ps
CPU time 6.17 seconds
Started Aug 13 04:32:34 PM PDT 24
Finished Aug 13 04:32:40 PM PDT 24
Peak memory 217036 kb
Host smart-99960cc0-21da-40bd-b330-e7ce08236b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556339176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1556339176
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3905217936
Short name T322
Test name
Test status
Simulation time 31721043 ps
CPU time 0.68 seconds
Started Aug 13 04:32:48 PM PDT 24
Finished Aug 13 04:32:49 PM PDT 24
Peak memory 206360 kb
Host smart-be776649-e706-47bc-9ea3-c85264e7ce81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905217936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3905217936
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2542263019
Short name T920
Test name
Test status
Simulation time 445055522 ps
CPU time 3.55 seconds
Started Aug 13 04:32:42 PM PDT 24
Finished Aug 13 04:32:51 PM PDT 24
Peak memory 233516 kb
Host smart-8483cefd-c684-447d-91e8-60494fa49a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542263019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2542263019
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.735079712
Short name T66
Test name
Test status
Simulation time 17239053 ps
CPU time 0.68 seconds
Started Aug 13 04:32:40 PM PDT 24
Finished Aug 13 04:32:46 PM PDT 24
Peak memory 205604 kb
Host smart-c4e5e6df-54bd-4d58-bb05-560a7b9b1fa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735079712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.735079712
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2361062315
Short name T633
Test name
Test status
Simulation time 3731769866 ps
CPU time 4.27 seconds
Started Aug 13 04:32:49 PM PDT 24
Finished Aug 13 04:32:53 PM PDT 24
Peak memory 233608 kb
Host smart-b5646952-fb70-47fa-83de-7b7c78a11aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361062315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2361062315
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.4253872603
Short name T610
Test name
Test status
Simulation time 22212386 ps
CPU time 0.85 seconds
Started Aug 13 04:32:38 PM PDT 24
Finished Aug 13 04:32:39 PM PDT 24
Peak memory 207532 kb
Host smart-fcc397f2-ddb9-417c-8c56-5336a76439e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253872603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4253872603
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2136875990
Short name T470
Test name
Test status
Simulation time 86617343996 ps
CPU time 95.99 seconds
Started Aug 13 04:32:28 PM PDT 24
Finished Aug 13 04:34:05 PM PDT 24
Peak memory 250928 kb
Host smart-305b5f21-3691-49cb-83c8-d9c74404028e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136875990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2136875990
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3498677643
Short name T242
Test name
Test status
Simulation time 12423060618 ps
CPU time 114.34 seconds
Started Aug 13 04:32:47 PM PDT 24
Finished Aug 13 04:34:42 PM PDT 24
Peak memory 250136 kb
Host smart-e7753497-e83f-497f-a35f-21100977be7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498677643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3498677643
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.4270025169
Short name T500
Test name
Test status
Simulation time 3278575347 ps
CPU time 33.04 seconds
Started Aug 13 04:32:37 PM PDT 24
Finished Aug 13 04:33:11 PM PDT 24
Peak memory 257904 kb
Host smart-bfd98c4b-bf29-4510-a861-0db6286d7dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270025169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.4270025169
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2987442512
Short name T616
Test name
Test status
Simulation time 9504037411 ps
CPU time 10.88 seconds
Started Aug 13 04:32:40 PM PDT 24
Finished Aug 13 04:32:51 PM PDT 24
Peak memory 233636 kb
Host smart-910f7b50-12eb-4d35-9de0-837f9da6f3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987442512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2987442512
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.788176453
Short name T862
Test name
Test status
Simulation time 2898169849 ps
CPU time 48.64 seconds
Started Aug 13 04:32:35 PM PDT 24
Finished Aug 13 04:33:23 PM PDT 24
Peak memory 253168 kb
Host smart-d0426cf2-814c-400c-ba35-7fb5897a8477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788176453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.788176453
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.621078074
Short name T951
Test name
Test status
Simulation time 96730120 ps
CPU time 2.74 seconds
Started Aug 13 04:32:48 PM PDT 24
Finished Aug 13 04:32:51 PM PDT 24
Peak memory 225184 kb
Host smart-520ae10d-e2af-4aad-bee4-5222ff7c197e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621078074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.621078074
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.156758793
Short name T634
Test name
Test status
Simulation time 14686979409 ps
CPU time 47.75 seconds
Started Aug 13 04:32:33 PM PDT 24
Finished Aug 13 04:33:21 PM PDT 24
Peak memory 225312 kb
Host smart-7513ad66-ce92-49b5-a4a8-dc9921fde02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156758793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.156758793
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3123894750
Short name T889
Test name
Test status
Simulation time 3193238743 ps
CPU time 11.83 seconds
Started Aug 13 04:32:50 PM PDT 24
Finished Aug 13 04:33:02 PM PDT 24
Peak memory 235340 kb
Host smart-a6f0bdbe-05eb-4b4d-b803-437f0efae28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123894750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3123894750
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.301816857
Short name T745
Test name
Test status
Simulation time 120388146 ps
CPU time 2.56 seconds
Started Aug 13 04:32:58 PM PDT 24
Finished Aug 13 04:33:01 PM PDT 24
Peak memory 233476 kb
Host smart-fe75ac09-38a1-4fef-9dc9-e646aa0edfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301816857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.301816857
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2124145437
Short name T988
Test name
Test status
Simulation time 3569393284 ps
CPU time 9.56 seconds
Started Aug 13 04:32:46 PM PDT 24
Finished Aug 13 04:32:56 PM PDT 24
Peak memory 221408 kb
Host smart-5a26831b-875e-423f-a0d1-c18809de91cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2124145437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2124145437
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1064638475
Short name T153
Test name
Test status
Simulation time 179749242143 ps
CPU time 380.38 seconds
Started Aug 13 04:32:38 PM PDT 24
Finished Aug 13 04:38:59 PM PDT 24
Peak memory 266476 kb
Host smart-0d0492f0-2df4-4c88-b05a-2c11d5eb771b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064638475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1064638475
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2824622905
Short name T982
Test name
Test status
Simulation time 125231895028 ps
CPU time 39.58 seconds
Started Aug 13 04:32:43 PM PDT 24
Finished Aug 13 04:33:23 PM PDT 24
Peak memory 217100 kb
Host smart-d355832b-6318-40bb-babd-b45964e7ae8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824622905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2824622905
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.4109084224
Short name T305
Test name
Test status
Simulation time 4733407633 ps
CPU time 16.41 seconds
Started Aug 13 04:32:36 PM PDT 24
Finished Aug 13 04:32:52 PM PDT 24
Peak memory 217160 kb
Host smart-d6e50437-de2a-4419-ada5-0a3e938cdcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109084224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4109084224
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1025659712
Short name T596
Test name
Test status
Simulation time 11132887 ps
CPU time 0.68 seconds
Started Aug 13 04:32:43 PM PDT 24
Finished Aug 13 04:32:44 PM PDT 24
Peak memory 206356 kb
Host smart-15649a83-7dbb-4231-a71c-c3563b320131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025659712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1025659712
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3000386604
Short name T493
Test name
Test status
Simulation time 83228034 ps
CPU time 0.72 seconds
Started Aug 13 04:32:44 PM PDT 24
Finished Aug 13 04:32:44 PM PDT 24
Peak memory 206840 kb
Host smart-e553b30c-f158-479e-855e-1685d5847852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000386604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3000386604
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3586928624
Short name T601
Test name
Test status
Simulation time 3412610037 ps
CPU time 4.64 seconds
Started Aug 13 04:32:27 PM PDT 24
Finished Aug 13 04:32:32 PM PDT 24
Peak memory 233544 kb
Host smart-dec0c141-ed34-448b-a63f-d9794a5c690e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586928624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3586928624
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1177462777
Short name T578
Test name
Test status
Simulation time 19628069 ps
CPU time 0.71 seconds
Started Aug 13 04:32:28 PM PDT 24
Finished Aug 13 04:32:28 PM PDT 24
Peak memory 206508 kb
Host smart-e1359f52-823d-4f74-82aa-e79e10bf3077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177462777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1177462777
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.229202320
Short name T326
Test name
Test status
Simulation time 762188521 ps
CPU time 3.47 seconds
Started Aug 13 04:32:34 PM PDT 24
Finished Aug 13 04:32:38 PM PDT 24
Peak memory 225260 kb
Host smart-f515c4b7-4902-4809-be9b-2bb309d80fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229202320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.229202320
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2766384134
Short name T796
Test name
Test status
Simulation time 64885796 ps
CPU time 0.82 seconds
Started Aug 13 04:32:47 PM PDT 24
Finished Aug 13 04:32:48 PM PDT 24
Peak memory 207296 kb
Host smart-81addde2-9bc6-4777-a2c8-03863b9d3fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766384134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2766384134
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1788128771
Short name T686
Test name
Test status
Simulation time 4360213791 ps
CPU time 33.47 seconds
Started Aug 13 04:33:47 PM PDT 24
Finished Aug 13 04:34:21 PM PDT 24
Peak memory 249396 kb
Host smart-bf749eef-d114-470e-891b-7de85c3bbc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788128771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1788128771
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2659988369
Short name T927
Test name
Test status
Simulation time 15633735321 ps
CPU time 107.9 seconds
Started Aug 13 04:32:33 PM PDT 24
Finished Aug 13 04:34:21 PM PDT 24
Peak memory 250072 kb
Host smart-112a1ced-87ac-4e9e-a77e-f3e50f748096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659988369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2659988369
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2933036801
Short name T177
Test name
Test status
Simulation time 20477895861 ps
CPU time 115.87 seconds
Started Aug 13 04:32:33 PM PDT 24
Finished Aug 13 04:34:29 PM PDT 24
Peak memory 266584 kb
Host smart-44d87121-eaf8-4977-8770-b9d0c593f61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933036801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2933036801
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.718455426
Short name T573
Test name
Test status
Simulation time 305332268 ps
CPU time 7.97 seconds
Started Aug 13 04:32:37 PM PDT 24
Finished Aug 13 04:32:45 PM PDT 24
Peak memory 249868 kb
Host smart-5a217bef-7a3e-45e5-aa78-51f935726625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718455426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.718455426
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.197784486
Short name T797
Test name
Test status
Simulation time 73812283854 ps
CPU time 61.94 seconds
Started Aug 13 04:32:37 PM PDT 24
Finished Aug 13 04:33:39 PM PDT 24
Peak memory 240092 kb
Host smart-d375738c-8ac3-4b9c-b8ca-4c2f98c09ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197784486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.197784486
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1082919997
Short name T407
Test name
Test status
Simulation time 4976959603 ps
CPU time 12.01 seconds
Started Aug 13 04:32:43 PM PDT 24
Finished Aug 13 04:32:55 PM PDT 24
Peak memory 233648 kb
Host smart-2c02f2dc-6098-461d-9aab-d2b10ab53997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082919997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1082919997
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.127540588
Short name T744
Test name
Test status
Simulation time 4952163279 ps
CPU time 39.67 seconds
Started Aug 13 04:32:33 PM PDT 24
Finished Aug 13 04:33:12 PM PDT 24
Peak memory 233620 kb
Host smart-d28d1e24-62d0-4fab-aa1a-9e03a3e71764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127540588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.127540588
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1646914160
Short name T647
Test name
Test status
Simulation time 4138148002 ps
CPU time 4.37 seconds
Started Aug 13 04:32:47 PM PDT 24
Finished Aug 13 04:32:52 PM PDT 24
Peak memory 225348 kb
Host smart-d180ac45-f0bd-43a0-a0d4-9f87a83a27ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646914160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1646914160
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.4067227053
Short name T877
Test name
Test status
Simulation time 355376565 ps
CPU time 6.9 seconds
Started Aug 13 04:32:58 PM PDT 24
Finished Aug 13 04:33:05 PM PDT 24
Peak memory 233484 kb
Host smart-e7772e46-83d9-404a-a344-9a2b66cd05ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067227053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.4067227053
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2447676582
Short name T861
Test name
Test status
Simulation time 120859489 ps
CPU time 3.92 seconds
Started Aug 13 04:32:38 PM PDT 24
Finished Aug 13 04:32:42 PM PDT 24
Peak memory 219744 kb
Host smart-5f6b223a-1b3f-4b80-8189-981935f7aef1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2447676582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2447676582
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3727671154
Short name T157
Test name
Test status
Simulation time 20856239977 ps
CPU time 260.1 seconds
Started Aug 13 04:32:28 PM PDT 24
Finished Aug 13 04:36:48 PM PDT 24
Peak memory 271424 kb
Host smart-2b0f2eff-d10d-44e3-9a7a-139e43e153be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727671154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3727671154
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3741912189
Short name T617
Test name
Test status
Simulation time 7783022817 ps
CPU time 17.66 seconds
Started Aug 13 04:32:47 PM PDT 24
Finished Aug 13 04:33:05 PM PDT 24
Peak memory 217368 kb
Host smart-c8701a6e-64f9-4856-b1f4-40f197777d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741912189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3741912189
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4252479771
Short name T429
Test name
Test status
Simulation time 18171926658 ps
CPU time 11.35 seconds
Started Aug 13 04:32:43 PM PDT 24
Finished Aug 13 04:32:54 PM PDT 24
Peak memory 217400 kb
Host smart-1acfa404-47e1-4a57-8da9-4dd96f087d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252479771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4252479771
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2457393401
Short name T585
Test name
Test status
Simulation time 167561731 ps
CPU time 2.98 seconds
Started Aug 13 04:32:38 PM PDT 24
Finished Aug 13 04:32:41 PM PDT 24
Peak memory 217128 kb
Host smart-21abf1fc-b898-43ce-a3d5-2d20e7725210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457393401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2457393401
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3950083343
Short name T375
Test name
Test status
Simulation time 62855789 ps
CPU time 0.77 seconds
Started Aug 13 04:32:43 PM PDT 24
Finished Aug 13 04:32:44 PM PDT 24
Peak memory 207088 kb
Host smart-5af80e8e-930b-4261-97b6-b67a3afb3a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950083343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3950083343
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2139938535
Short name T936
Test name
Test status
Simulation time 5383834618 ps
CPU time 12.58 seconds
Started Aug 13 04:32:32 PM PDT 24
Finished Aug 13 04:32:45 PM PDT 24
Peak memory 225320 kb
Host smart-15d0a9c9-52fb-4780-9388-7710b357744b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139938535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2139938535
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.893147103
Short name T955
Test name
Test status
Simulation time 22226817 ps
CPU time 0.73 seconds
Started Aug 13 04:32:42 PM PDT 24
Finished Aug 13 04:32:43 PM PDT 24
Peak memory 205636 kb
Host smart-52ca9215-ab05-4e10-ad5c-0761afca8717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893147103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.893147103
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.586003927
Short name T863
Test name
Test status
Simulation time 356119400 ps
CPU time 2.36 seconds
Started Aug 13 04:32:47 PM PDT 24
Finished Aug 13 04:32:49 PM PDT 24
Peak memory 225200 kb
Host smart-cadd7de2-b308-4f0f-a857-b38aabddb956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586003927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.586003927
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.476580406
Short name T934
Test name
Test status
Simulation time 28652933 ps
CPU time 0.76 seconds
Started Aug 13 04:32:43 PM PDT 24
Finished Aug 13 04:32:44 PM PDT 24
Peak memory 206484 kb
Host smart-22362f1e-81b5-4148-b2a5-10ed0a239cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476580406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.476580406
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3067112820
Short name T483
Test name
Test status
Simulation time 18400064489 ps
CPU time 82.07 seconds
Started Aug 13 04:32:35 PM PDT 24
Finished Aug 13 04:33:57 PM PDT 24
Peak memory 257144 kb
Host smart-be142f04-2ec5-4d15-be93-1ae8ac96ee67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067112820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3067112820
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2948088774
Short name T161
Test name
Test status
Simulation time 16723344764 ps
CPU time 38.49 seconds
Started Aug 13 04:32:37 PM PDT 24
Finished Aug 13 04:33:16 PM PDT 24
Peak memory 251500 kb
Host smart-7cc03ed7-2808-4266-a988-5fc965f8cd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948088774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2948088774
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4062372673
Short name T215
Test name
Test status
Simulation time 48567070800 ps
CPU time 342.69 seconds
Started Aug 13 04:32:36 PM PDT 24
Finished Aug 13 04:38:19 PM PDT 24
Peak memory 263980 kb
Host smart-196e84de-3940-4eb0-974d-12db076b8e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062372673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.4062372673
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2061083887
Short name T990
Test name
Test status
Simulation time 56243048 ps
CPU time 3.62 seconds
Started Aug 13 04:32:50 PM PDT 24
Finished Aug 13 04:32:54 PM PDT 24
Peak memory 233468 kb
Host smart-b2e16a3e-1674-44c0-8a8f-6f2b67beb590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061083887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2061083887
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1782759988
Short name T760
Test name
Test status
Simulation time 2562722756 ps
CPU time 38.14 seconds
Started Aug 13 04:32:43 PM PDT 24
Finished Aug 13 04:33:22 PM PDT 24
Peak memory 252648 kb
Host smart-c5d7f7f5-7df8-4eee-b148-5fb87f68d23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782759988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1782759988
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2741593543
Short name T779
Test name
Test status
Simulation time 1051684041 ps
CPU time 8.81 seconds
Started Aug 13 04:32:50 PM PDT 24
Finished Aug 13 04:32:59 PM PDT 24
Peak memory 233444 kb
Host smart-5ce7231d-6b44-4906-9ef3-5d4b774a41d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741593543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2741593543
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1432209763
Short name T978
Test name
Test status
Simulation time 262070254 ps
CPU time 4.52 seconds
Started Aug 13 04:32:49 PM PDT 24
Finished Aug 13 04:32:54 PM PDT 24
Peak memory 233424 kb
Host smart-6dd1f895-d335-43df-8eae-e1ef6742869f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432209763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1432209763
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.345318887
Short name T707
Test name
Test status
Simulation time 1343024297 ps
CPU time 8.62 seconds
Started Aug 13 04:32:40 PM PDT 24
Finished Aug 13 04:32:49 PM PDT 24
Peak memory 251752 kb
Host smart-2b9a9bf7-8a6b-4ee4-adfc-7f8109a7ee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345318887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.345318887
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.461645343
Short name T18
Test name
Test status
Simulation time 132263412 ps
CPU time 2.55 seconds
Started Aug 13 04:32:44 PM PDT 24
Finished Aug 13 04:32:46 PM PDT 24
Peak memory 233560 kb
Host smart-9accb982-92eb-46f3-ab3f-2dfed568d65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461645343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.461645343
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2358982860
Short name T581
Test name
Test status
Simulation time 1215872114 ps
CPU time 5.76 seconds
Started Aug 13 04:32:53 PM PDT 24
Finished Aug 13 04:32:59 PM PDT 24
Peak memory 221044 kb
Host smart-a25dcb45-936d-4f13-bea7-2f99fa660ae0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2358982860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2358982860
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.675615081
Short name T980
Test name
Test status
Simulation time 225378794868 ps
CPU time 209.82 seconds
Started Aug 13 04:32:34 PM PDT 24
Finished Aug 13 04:36:04 PM PDT 24
Peak memory 250200 kb
Host smart-869eed1c-9e29-4e18-8140-5accae1dfb90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675615081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.675615081
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3223082756
Short name T765
Test name
Test status
Simulation time 17165492056 ps
CPU time 44.47 seconds
Started Aug 13 04:32:38 PM PDT 24
Finished Aug 13 04:33:23 PM PDT 24
Peak memory 217304 kb
Host smart-45106af9-1af8-4f48-b61c-3d8a0f2ac0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223082756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3223082756
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1996690852
Short name T584
Test name
Test status
Simulation time 923299860 ps
CPU time 4.03 seconds
Started Aug 13 04:32:41 PM PDT 24
Finished Aug 13 04:32:45 PM PDT 24
Peak memory 217020 kb
Host smart-4105fdba-a3a9-4e17-82fa-9fdf2a4683e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996690852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1996690852
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3996587240
Short name T926
Test name
Test status
Simulation time 287045962 ps
CPU time 2.31 seconds
Started Aug 13 04:32:33 PM PDT 24
Finished Aug 13 04:32:35 PM PDT 24
Peak memory 217068 kb
Host smart-f410a500-c720-458f-aa45-74970009bee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996587240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3996587240
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2129084202
Short name T348
Test name
Test status
Simulation time 59067790 ps
CPU time 0.75 seconds
Started Aug 13 04:32:34 PM PDT 24
Finished Aug 13 04:32:35 PM PDT 24
Peak memory 206724 kb
Host smart-660846cc-24e6-4e3c-99a4-2e3fc55453c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129084202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2129084202
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2068411663
Short name T902
Test name
Test status
Simulation time 3327896310 ps
CPU time 5.27 seconds
Started Aug 13 04:32:41 PM PDT 24
Finished Aug 13 04:32:46 PM PDT 24
Peak memory 225336 kb
Host smart-bd26b79d-9984-47a6-b79a-b736ce52fdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068411663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2068411663
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.4047254263
Short name T67
Test name
Test status
Simulation time 120566456 ps
CPU time 0.77 seconds
Started Aug 13 04:32:58 PM PDT 24
Finished Aug 13 04:32:59 PM PDT 24
Peak memory 205564 kb
Host smart-6508bc48-2745-465b-b526-d97dbbe5b9e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047254263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
4047254263
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2859359412
Short name T170
Test name
Test status
Simulation time 261120927 ps
CPU time 3.35 seconds
Started Aug 13 04:32:48 PM PDT 24
Finished Aug 13 04:32:51 PM PDT 24
Peak memory 225288 kb
Host smart-b47e7f25-9ae6-45a3-8175-2ccdf78b735e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859359412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2859359412
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2064764294
Short name T476
Test name
Test status
Simulation time 75392058 ps
CPU time 0.76 seconds
Started Aug 13 04:32:37 PM PDT 24
Finished Aug 13 04:32:38 PM PDT 24
Peak memory 207728 kb
Host smart-892b1c83-63e7-49bd-bb8b-aed796c6f4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064764294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2064764294
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3827936531
Short name T860
Test name
Test status
Simulation time 1915112274 ps
CPU time 18.79 seconds
Started Aug 13 04:32:32 PM PDT 24
Finished Aug 13 04:32:51 PM PDT 24
Peak memory 258088 kb
Host smart-8f01aca3-cb02-45e8-ad7b-3c95320fda80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827936531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3827936531
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2681386055
Short name T874
Test name
Test status
Simulation time 345782267751 ps
CPU time 448.27 seconds
Started Aug 13 04:32:46 PM PDT 24
Finished Aug 13 04:40:15 PM PDT 24
Peak memory 252616 kb
Host smart-549a78e1-4e72-48e6-8e0b-1d5f272b9cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681386055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2681386055
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2573322406
Short name T480
Test name
Test status
Simulation time 83332103644 ps
CPU time 108.72 seconds
Started Aug 13 04:32:42 PM PDT 24
Finished Aug 13 04:34:31 PM PDT 24
Peak memory 250120 kb
Host smart-aedcd6d5-5143-465f-8bf4-858f98c32465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573322406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2573322406
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.751610658
Short name T525
Test name
Test status
Simulation time 545374031 ps
CPU time 5.97 seconds
Started Aug 13 04:32:46 PM PDT 24
Finished Aug 13 04:32:52 PM PDT 24
Peak memory 249856 kb
Host smart-8a63adbe-bc01-4c24-b406-847dad53926c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751610658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.751610658
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.4162335135
Short name T865
Test name
Test status
Simulation time 105743050786 ps
CPU time 150 seconds
Started Aug 13 04:32:57 PM PDT 24
Finished Aug 13 04:35:27 PM PDT 24
Peak memory 239760 kb
Host smart-972178c2-17ac-411b-9733-13fb0e707d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162335135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.4162335135
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.701178180
Short name T3
Test name
Test status
Simulation time 2243179707 ps
CPU time 7.5 seconds
Started Aug 13 04:32:54 PM PDT 24
Finished Aug 13 04:33:01 PM PDT 24
Peak memory 225424 kb
Host smart-6fc3198c-835d-4a8a-8987-39803d9e0370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701178180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.701178180
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1981181177
Short name T198
Test name
Test status
Simulation time 4253759388 ps
CPU time 7.85 seconds
Started Aug 13 04:32:56 PM PDT 24
Finished Aug 13 04:33:04 PM PDT 24
Peak memory 233584 kb
Host smart-afa0f0b9-ea61-4e87-8c26-f80fe886e208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981181177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1981181177
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3000004708
Short name T231
Test name
Test status
Simulation time 15456766782 ps
CPU time 8.76 seconds
Started Aug 13 04:32:33 PM PDT 24
Finished Aug 13 04:32:42 PM PDT 24
Peak memory 225408 kb
Host smart-00c3bf74-ca0b-409a-a328-8d439918b1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000004708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3000004708
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2322851004
Short name T279
Test name
Test status
Simulation time 1257531608 ps
CPU time 4.12 seconds
Started Aug 13 04:32:56 PM PDT 24
Finished Aug 13 04:33:00 PM PDT 24
Peak memory 225132 kb
Host smart-47b13d17-e298-481e-9986-fd68763fff96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322851004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2322851004
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1530378639
Short name T948
Test name
Test status
Simulation time 267856571 ps
CPU time 3.1 seconds
Started Aug 13 04:33:03 PM PDT 24
Finished Aug 13 04:33:06 PM PDT 24
Peak memory 219372 kb
Host smart-6defc675-a067-446e-89fc-f077e453f8ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1530378639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1530378639
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.756099791
Short name T156
Test name
Test status
Simulation time 40373675146 ps
CPU time 436.52 seconds
Started Aug 13 04:32:57 PM PDT 24
Finished Aug 13 04:40:13 PM PDT 24
Peak memory 273740 kb
Host smart-c78761af-8157-48dc-8905-65ab41c9b25e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756099791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.756099791
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.677907584
Short name T958
Test name
Test status
Simulation time 9831745295 ps
CPU time 22.61 seconds
Started Aug 13 04:32:56 PM PDT 24
Finished Aug 13 04:33:19 PM PDT 24
Peak memory 217388 kb
Host smart-ba7478ea-0d4c-4cb1-ba7d-9b0bbf73241e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677907584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.677907584
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3458153786
Short name T29
Test name
Test status
Simulation time 2199583874 ps
CPU time 5.49 seconds
Started Aug 13 04:33:27 PM PDT 24
Finished Aug 13 04:33:33 PM PDT 24
Peak memory 215832 kb
Host smart-510ca09e-2042-4791-bb43-2a44370ca314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458153786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3458153786
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1023093202
Short name T947
Test name
Test status
Simulation time 259428354 ps
CPU time 8.01 seconds
Started Aug 13 04:32:50 PM PDT 24
Finished Aug 13 04:32:58 PM PDT 24
Peak memory 217032 kb
Host smart-9386f5f4-3565-4c1f-aace-8fde26af2adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023093202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1023093202
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.796698599
Short name T552
Test name
Test status
Simulation time 111613084 ps
CPU time 0.78 seconds
Started Aug 13 04:32:41 PM PDT 24
Finished Aug 13 04:32:42 PM PDT 24
Peak memory 206724 kb
Host smart-32cfcef7-7fc4-42f5-ad0b-ceb34db0f6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796698599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.796698599
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.457778510
Short name T430
Test name
Test status
Simulation time 118425689 ps
CPU time 2.69 seconds
Started Aug 13 04:33:00 PM PDT 24
Finished Aug 13 04:33:03 PM PDT 24
Peak memory 224916 kb
Host smart-24b1c9f7-e2ce-42e8-aa5b-ff74dafca474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457778510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.457778510
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.97734083
Short name T564
Test name
Test status
Simulation time 15151697 ps
CPU time 0.75 seconds
Started Aug 13 04:33:03 PM PDT 24
Finished Aug 13 04:33:04 PM PDT 24
Peak memory 206116 kb
Host smart-d9bafad0-5f06-4b7f-b0b2-9d10b9468e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97734083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.97734083
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3692179486
Short name T490
Test name
Test status
Simulation time 874958668 ps
CPU time 10.3 seconds
Started Aug 13 04:32:54 PM PDT 24
Finished Aug 13 04:33:05 PM PDT 24
Peak memory 233404 kb
Host smart-eef9a78e-255e-4b09-9998-7ba89109addd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692179486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3692179486
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2670263087
Short name T808
Test name
Test status
Simulation time 19323527 ps
CPU time 0.78 seconds
Started Aug 13 04:32:49 PM PDT 24
Finished Aug 13 04:32:50 PM PDT 24
Peak memory 206580 kb
Host smart-d45917ee-e4e8-4b28-b250-440532dfadb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670263087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2670263087
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2296538390
Short name T851
Test name
Test status
Simulation time 3612906866 ps
CPU time 12.59 seconds
Started Aug 13 04:32:52 PM PDT 24
Finished Aug 13 04:33:05 PM PDT 24
Peak memory 218580 kb
Host smart-ef438841-dd69-40b5-b229-ac1ab195c804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296538390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2296538390
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.4118965918
Short name T438
Test name
Test status
Simulation time 16793915546 ps
CPU time 52.06 seconds
Started Aug 13 04:32:55 PM PDT 24
Finished Aug 13 04:33:47 PM PDT 24
Peak memory 239932 kb
Host smart-2756c76b-7c71-413d-a5d9-66be397531c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118965918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.4118965918
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2546802851
Short name T660
Test name
Test status
Simulation time 5150005818 ps
CPU time 31.33 seconds
Started Aug 13 04:32:43 PM PDT 24
Finished Aug 13 04:33:25 PM PDT 24
Peak memory 241760 kb
Host smart-513804a4-8429-458b-96b6-7b3672b1c909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546802851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2546802851
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1492349235
Short name T227
Test name
Test status
Simulation time 6407844226 ps
CPU time 83.61 seconds
Started Aug 13 04:32:46 PM PDT 24
Finished Aug 13 04:34:10 PM PDT 24
Peak memory 271136 kb
Host smart-5221afc4-052d-4d4e-a340-2071c046f501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492349235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1492349235
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.368179851
Short name T622
Test name
Test status
Simulation time 150287298 ps
CPU time 4.1 seconds
Started Aug 13 04:33:07 PM PDT 24
Finished Aug 13 04:33:11 PM PDT 24
Peak memory 225204 kb
Host smart-2f76ba1c-0edb-4e04-b88b-a18876f53354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368179851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.368179851
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4067530707
Short name T713
Test name
Test status
Simulation time 404598729 ps
CPU time 5.45 seconds
Started Aug 13 04:32:47 PM PDT 24
Finished Aug 13 04:32:52 PM PDT 24
Peak memory 225260 kb
Host smart-acdde87c-0083-418a-adce-2eb17036ebe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067530707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4067530707
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2401936950
Short name T658
Test name
Test status
Simulation time 23595163491 ps
CPU time 22.55 seconds
Started Aug 13 04:32:34 PM PDT 24
Finished Aug 13 04:32:57 PM PDT 24
Peak memory 233532 kb
Host smart-c1decc1a-1b8f-4237-8296-0944d9193667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401936950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2401936950
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2100591716
Short name T572
Test name
Test status
Simulation time 3631788534 ps
CPU time 13.65 seconds
Started Aug 13 04:32:45 PM PDT 24
Finished Aug 13 04:32:59 PM PDT 24
Peak memory 225432 kb
Host smart-64863b2d-27e9-45c0-84e8-250feff497b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100591716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2100591716
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3460109661
Short name T45
Test name
Test status
Simulation time 245741179 ps
CPU time 4.44 seconds
Started Aug 13 04:32:46 PM PDT 24
Finished Aug 13 04:32:50 PM PDT 24
Peak memory 223156 kb
Host smart-d933a3b9-47c7-40ed-8994-d153e896091f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3460109661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3460109661
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2917653886
Short name T791
Test name
Test status
Simulation time 50250819 ps
CPU time 1 seconds
Started Aug 13 04:32:46 PM PDT 24
Finished Aug 13 04:32:48 PM PDT 24
Peak memory 207668 kb
Host smart-b268e219-9a93-4eb9-9059-ce36cb0b346a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917653886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2917653886
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3447423996
Short name T298
Test name
Test status
Simulation time 25700111905 ps
CPU time 35.85 seconds
Started Aug 13 04:32:46 PM PDT 24
Finished Aug 13 04:33:22 PM PDT 24
Peak memory 217204 kb
Host smart-3abbb508-a43f-44be-8c6e-a0ebd322e2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447423996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3447423996
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.426570009
Short name T59
Test name
Test status
Simulation time 492812077 ps
CPU time 1.67 seconds
Started Aug 13 04:32:50 PM PDT 24
Finished Aug 13 04:32:52 PM PDT 24
Peak memory 208584 kb
Host smart-0b226d4b-a0aa-4deb-a421-4bac5ee55da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426570009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.426570009
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3109430208
Short name T350
Test name
Test status
Simulation time 30433509 ps
CPU time 0.88 seconds
Started Aug 13 04:32:56 PM PDT 24
Finished Aug 13 04:32:57 PM PDT 24
Peak memory 207452 kb
Host smart-28dcd2b3-5977-4c4e-a0e0-55a259759aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109430208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3109430208
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1846205644
Short name T516
Test name
Test status
Simulation time 112621206 ps
CPU time 1.01 seconds
Started Aug 13 04:32:59 PM PDT 24
Finished Aug 13 04:33:00 PM PDT 24
Peak memory 207780 kb
Host smart-891975ef-35c0-4d8c-a785-8fdb93ee4213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846205644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1846205644
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.82713202
Short name T1007
Test name
Test status
Simulation time 238050270 ps
CPU time 5.53 seconds
Started Aug 13 04:32:47 PM PDT 24
Finished Aug 13 04:32:52 PM PDT 24
Peak memory 240088 kb
Host smart-46dca337-a8d1-4e3d-904e-23e208726dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82713202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.82713202
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4240268344
Short name T316
Test name
Test status
Simulation time 21962619 ps
CPU time 0.73 seconds
Started Aug 13 04:32:56 PM PDT 24
Finished Aug 13 04:32:57 PM PDT 24
Peak memory 206068 kb
Host smart-6b4faff9-8b5b-4ff6-b122-64e8571fbb83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240268344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4240268344
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3095395953
Short name T425
Test name
Test status
Simulation time 153403693 ps
CPU time 2.82 seconds
Started Aug 13 04:32:56 PM PDT 24
Finished Aug 13 04:32:59 PM PDT 24
Peak memory 233456 kb
Host smart-24483fde-58b2-4d2c-a32f-651b48d2fdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095395953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3095395953
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1795455776
Short name T441
Test name
Test status
Simulation time 21003109 ps
CPU time 0.74 seconds
Started Aug 13 04:32:33 PM PDT 24
Finished Aug 13 04:32:34 PM PDT 24
Peak memory 207272 kb
Host smart-3bd90fad-5fc0-42fb-937f-bfa751a995e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795455776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1795455776
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.997006045
Short name T826
Test name
Test status
Simulation time 432801619810 ps
CPU time 487.07 seconds
Started Aug 13 04:32:49 PM PDT 24
Finished Aug 13 04:40:57 PM PDT 24
Peak memory 251588 kb
Host smart-3e5e0e4c-6724-4c9a-9952-791cc74d36df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997006045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.997006045
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4125815146
Short name T247
Test name
Test status
Simulation time 6312995123 ps
CPU time 38.14 seconds
Started Aug 13 04:32:56 PM PDT 24
Finished Aug 13 04:33:39 PM PDT 24
Peak memory 241916 kb
Host smart-9882da3d-8318-4e56-a97c-448253dd2f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125815146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4125815146
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.694404574
Short name T1005
Test name
Test status
Simulation time 133712957 ps
CPU time 4.25 seconds
Started Aug 13 04:32:42 PM PDT 24
Finished Aug 13 04:32:47 PM PDT 24
Peak memory 234536 kb
Host smart-33563edc-a313-4349-8e2f-008653a96042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694404574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.694404574
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2680982060
Short name T395
Test name
Test status
Simulation time 2918018895 ps
CPU time 52.9 seconds
Started Aug 13 04:33:01 PM PDT 24
Finished Aug 13 04:33:54 PM PDT 24
Peak memory 249988 kb
Host smart-646e41ce-1f34-4cac-97d6-a995923b28b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680982060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2680982060
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.654585380
Short name T274
Test name
Test status
Simulation time 1549449764 ps
CPU time 5.06 seconds
Started Aug 13 04:32:56 PM PDT 24
Finished Aug 13 04:33:01 PM PDT 24
Peak memory 233488 kb
Host smart-e364c7ed-afbc-44b8-8f1e-7b54e4c7d3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654585380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.654585380
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3319594746
Short name T903
Test name
Test status
Simulation time 6854111186 ps
CPU time 24.53 seconds
Started Aug 13 04:32:48 PM PDT 24
Finished Aug 13 04:33:13 PM PDT 24
Peak memory 235212 kb
Host smart-f4fb6afb-4bf5-49ae-aa75-cbcf58986be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319594746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3319594746
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.125825168
Short name T701
Test name
Test status
Simulation time 44921635320 ps
CPU time 28.5 seconds
Started Aug 13 04:32:49 PM PDT 24
Finished Aug 13 04:33:17 PM PDT 24
Peak memory 233592 kb
Host smart-aaf14b66-b959-4464-a5e7-b986dbe15c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125825168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.125825168
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1937656243
Short name T698
Test name
Test status
Simulation time 2921514125 ps
CPU time 12.03 seconds
Started Aug 13 04:32:43 PM PDT 24
Finished Aug 13 04:32:55 PM PDT 24
Peak memory 238440 kb
Host smart-ecfb6c39-18cc-4226-9c22-6d3688f0a69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937656243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1937656243
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.836227546
Short name T359
Test name
Test status
Simulation time 199138489 ps
CPU time 3.7 seconds
Started Aug 13 04:32:59 PM PDT 24
Finished Aug 13 04:33:03 PM PDT 24
Peak memory 220720 kb
Host smart-6b84dd1a-08b7-4442-af55-d3c8a40ce18d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=836227546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.836227546
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.449656317
Short name T655
Test name
Test status
Simulation time 476556772 ps
CPU time 3.68 seconds
Started Aug 13 04:32:57 PM PDT 24
Finished Aug 13 04:33:01 PM PDT 24
Peak memory 217392 kb
Host smart-99bf27af-6e89-4a1a-8be5-5412e3237705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449656317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.449656317
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3812412022
Short name T544
Test name
Test status
Simulation time 3404820850 ps
CPU time 10.4 seconds
Started Aug 13 04:32:38 PM PDT 24
Finished Aug 13 04:32:48 PM PDT 24
Peak memory 217120 kb
Host smart-f56277db-9a97-45ae-a6c3-70fe8ec74f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812412022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3812412022
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1483253119
Short name T515
Test name
Test status
Simulation time 951365811 ps
CPU time 2.59 seconds
Started Aug 13 04:32:34 PM PDT 24
Finished Aug 13 04:32:37 PM PDT 24
Peak memory 217004 kb
Host smart-1800f56c-f9a5-4ca3-b2a6-4fcbbee5a03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483253119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1483253119
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2350869553
Short name T963
Test name
Test status
Simulation time 21496980 ps
CPU time 0.79 seconds
Started Aug 13 04:32:45 PM PDT 24
Finished Aug 13 04:32:46 PM PDT 24
Peak memory 206696 kb
Host smart-b289182e-9ae8-4e81-b4b3-71c9da46ce43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350869553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2350869553
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2953681351
Short name T979
Test name
Test status
Simulation time 17373003960 ps
CPU time 8.53 seconds
Started Aug 13 04:32:45 PM PDT 24
Finished Aug 13 04:32:54 PM PDT 24
Peak memory 239752 kb
Host smart-9d391126-0935-4fcd-b6d9-ecb9f0f06eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953681351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2953681351
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.495847114
Short name T517
Test name
Test status
Simulation time 14873528 ps
CPU time 0.75 seconds
Started Aug 13 04:30:56 PM PDT 24
Finished Aug 13 04:30:57 PM PDT 24
Peak memory 205540 kb
Host smart-4b43ca39-6fca-4178-a03f-7fe4afa7962c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495847114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.495847114
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3497548976
Short name T884
Test name
Test status
Simulation time 101106657 ps
CPU time 2.9 seconds
Started Aug 13 04:31:22 PM PDT 24
Finished Aug 13 04:31:25 PM PDT 24
Peak memory 233720 kb
Host smart-60ae42c9-5d0a-442e-9092-4a620f7f511a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497548976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3497548976
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.495364394
Short name T334
Test name
Test status
Simulation time 16314706 ps
CPU time 0.8 seconds
Started Aug 13 04:30:51 PM PDT 24
Finished Aug 13 04:30:52 PM PDT 24
Peak memory 207264 kb
Host smart-4f9dedc5-b397-41a0-bb66-81099a69d1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495364394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.495364394
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3157136615
Short name T238
Test name
Test status
Simulation time 18515361956 ps
CPU time 90.06 seconds
Started Aug 13 04:30:55 PM PDT 24
Finished Aug 13 04:32:25 PM PDT 24
Peak memory 252568 kb
Host smart-a4613576-9720-4c7b-a4c2-13c45fe01fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157136615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3157136615
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3206135333
Short name T363
Test name
Test status
Simulation time 21239150259 ps
CPU time 194.93 seconds
Started Aug 13 04:30:56 PM PDT 24
Finished Aug 13 04:34:11 PM PDT 24
Peak memory 251108 kb
Host smart-11fa5277-73bf-402c-a1cb-554547c34476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206135333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3206135333
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.550635970
Short name T444
Test name
Test status
Simulation time 2672953099 ps
CPU time 29.41 seconds
Started Aug 13 04:31:03 PM PDT 24
Finished Aug 13 04:31:33 PM PDT 24
Peak memory 240920 kb
Host smart-c17f276e-8542-4ce2-929d-214cd1e1a167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550635970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
550635970
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3231704279
Short name T321
Test name
Test status
Simulation time 1392794457 ps
CPU time 7.14 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:31:15 PM PDT 24
Peak memory 225224 kb
Host smart-2ea311d5-a146-4644-96bc-2ba5a453eae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231704279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3231704279
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.4163421861
Short name T40
Test name
Test status
Simulation time 4800120411 ps
CPU time 35.55 seconds
Started Aug 13 04:31:02 PM PDT 24
Finished Aug 13 04:31:38 PM PDT 24
Peak memory 240184 kb
Host smart-2b08563d-53a1-41dd-8a9f-91d2c2576967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163421861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.4163421861
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2042674601
Short name T405
Test name
Test status
Simulation time 3258578971 ps
CPU time 5.87 seconds
Started Aug 13 04:30:52 PM PDT 24
Finished Aug 13 04:30:58 PM PDT 24
Peak memory 225376 kb
Host smart-a3e74280-0615-4119-89db-9ed846c09da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042674601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2042674601
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2083759025
Short name T203
Test name
Test status
Simulation time 5847967892 ps
CPU time 17.12 seconds
Started Aug 13 04:30:49 PM PDT 24
Finished Aug 13 04:31:06 PM PDT 24
Peak memory 233536 kb
Host smart-a1eda67e-bf57-474d-897d-d09169e01f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083759025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2083759025
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1477889287
Short name T55
Test name
Test status
Simulation time 12890559507 ps
CPU time 15.57 seconds
Started Aug 13 04:30:49 PM PDT 24
Finished Aug 13 04:31:05 PM PDT 24
Peak memory 239412 kb
Host smart-173239bf-f24f-43b3-9199-bf63750f55a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477889287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1477889287
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3094399627
Short name T566
Test name
Test status
Simulation time 195190942 ps
CPU time 2.95 seconds
Started Aug 13 04:30:51 PM PDT 24
Finished Aug 13 04:30:54 PM PDT 24
Peak memory 233412 kb
Host smart-3df27fca-3b9f-4b48-b1d4-f96a5601474f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094399627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3094399627
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1092994736
Short name T816
Test name
Test status
Simulation time 2545650488 ps
CPU time 4.26 seconds
Started Aug 13 04:31:15 PM PDT 24
Finished Aug 13 04:31:20 PM PDT 24
Peak memory 220956 kb
Host smart-09b3ef6d-2740-44fc-960b-6868676a7a44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1092994736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1092994736
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2031200210
Short name T72
Test name
Test status
Simulation time 61272431 ps
CPU time 1.08 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:31:09 PM PDT 24
Peak memory 236392 kb
Host smart-4ee99afc-9ae2-4785-91ff-2824e0da5957
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031200210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2031200210
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2743020026
Short name T949
Test name
Test status
Simulation time 12491661846 ps
CPU time 58.77 seconds
Started Aug 13 04:30:55 PM PDT 24
Finished Aug 13 04:31:54 PM PDT 24
Peak memory 217148 kb
Host smart-10a3e9fe-7cf2-4088-b7ab-289c49a0b6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743020026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2743020026
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1193646999
Short name T5
Test name
Test status
Simulation time 4818962119 ps
CPU time 3.85 seconds
Started Aug 13 04:30:54 PM PDT 24
Finished Aug 13 04:30:58 PM PDT 24
Peak memory 217208 kb
Host smart-e47e8d5b-1b2f-4e3d-8636-6de7db16cba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193646999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1193646999
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1829616959
Short name T302
Test name
Test status
Simulation time 215064392 ps
CPU time 2.9 seconds
Started Aug 13 04:30:53 PM PDT 24
Finished Aug 13 04:30:57 PM PDT 24
Peak memory 217200 kb
Host smart-6c72df70-5176-4f32-b99e-594d03deab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829616959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1829616959
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2236757456
Short name T420
Test name
Test status
Simulation time 122948075 ps
CPU time 0.83 seconds
Started Aug 13 04:30:54 PM PDT 24
Finished Aug 13 04:30:55 PM PDT 24
Peak memory 206852 kb
Host smart-56317ed8-5e3a-48d4-9437-f7723439f284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236757456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2236757456
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1781500404
Short name T201
Test name
Test status
Simulation time 153994641606 ps
CPU time 28.06 seconds
Started Aug 13 04:30:56 PM PDT 24
Finished Aug 13 04:31:25 PM PDT 24
Peak memory 249992 kb
Host smart-99b0549a-dfc6-4c67-92b0-09eeed71dd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781500404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1781500404
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4290975078
Short name T424
Test name
Test status
Simulation time 23255299 ps
CPU time 0.7 seconds
Started Aug 13 04:33:14 PM PDT 24
Finished Aug 13 04:33:15 PM PDT 24
Peak memory 206212 kb
Host smart-0d6bcb93-ace0-419a-b36e-7f9cbb73cdce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290975078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4290975078
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2627891624
Short name T94
Test name
Test status
Simulation time 167326006 ps
CPU time 4.16 seconds
Started Aug 13 04:32:50 PM PDT 24
Finished Aug 13 04:32:54 PM PDT 24
Peak memory 225248 kb
Host smart-33a41959-3771-4059-857e-f273ea7bd1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627891624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2627891624
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3020355669
Short name T856
Test name
Test status
Simulation time 37418991 ps
CPU time 0.77 seconds
Started Aug 13 04:33:01 PM PDT 24
Finished Aug 13 04:33:02 PM PDT 24
Peak memory 207632 kb
Host smart-62e9cb7d-dfef-43a0-b31a-d4aea6aebb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020355669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3020355669
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1879253394
Short name T313
Test name
Test status
Simulation time 32455896 ps
CPU time 0.75 seconds
Started Aug 13 04:32:53 PM PDT 24
Finished Aug 13 04:32:54 PM PDT 24
Peak memory 216536 kb
Host smart-9977c31b-9b6f-43f5-b8f2-73c9b21d0520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879253394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1879253394
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2770317326
Short name T534
Test name
Test status
Simulation time 20268239906 ps
CPU time 106.8 seconds
Started Aug 13 04:33:54 PM PDT 24
Finished Aug 13 04:35:41 PM PDT 24
Peak memory 263852 kb
Host smart-f5c36750-3b15-4ac4-b86e-5cb27a5741ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770317326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2770317326
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2435029244
Short name T400
Test name
Test status
Simulation time 2094644782 ps
CPU time 47.91 seconds
Started Aug 13 04:32:41 PM PDT 24
Finished Aug 13 04:33:29 PM PDT 24
Peak memory 257452 kb
Host smart-4b114486-cdd6-44dd-a4d3-4913b0e17801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435029244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2435029244
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3429668520
Short name T749
Test name
Test status
Simulation time 1047327434 ps
CPU time 15.44 seconds
Started Aug 13 04:32:51 PM PDT 24
Finished Aug 13 04:33:07 PM PDT 24
Peak memory 246072 kb
Host smart-4bbaf50d-0401-4338-ad38-69f4669a71bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429668520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3429668520
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3795023755
Short name T679
Test name
Test status
Simulation time 15320718891 ps
CPU time 114.23 seconds
Started Aug 13 04:32:56 PM PDT 24
Finished Aug 13 04:34:50 PM PDT 24
Peak memory 240424 kb
Host smart-c122f8f6-bb69-4bf1-8f88-223c3239484c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795023755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3795023755
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1023634583
Short name T964
Test name
Test status
Simulation time 2166330284 ps
CPU time 10.45 seconds
Started Aug 13 04:32:59 PM PDT 24
Finished Aug 13 04:33:10 PM PDT 24
Peak memory 225408 kb
Host smart-22eeb8c0-851f-49bb-bd5e-affaf8a35120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023634583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1023634583
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2196391930
Short name T498
Test name
Test status
Simulation time 44342327674 ps
CPU time 57.13 seconds
Started Aug 13 04:32:46 PM PDT 24
Finished Aug 13 04:33:43 PM PDT 24
Peak memory 241632 kb
Host smart-3c04cdd3-fe14-407a-ad4a-c2dd1240a755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196391930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2196391930
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.4226367856
Short name T339
Test name
Test status
Simulation time 18329838857 ps
CPU time 24.81 seconds
Started Aug 13 04:33:01 PM PDT 24
Finished Aug 13 04:33:26 PM PDT 24
Peak memory 233568 kb
Host smart-73684744-dec7-4415-89b7-2ebb05a5a5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226367856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.4226367856
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4121964420
Short name T185
Test name
Test status
Simulation time 883298708 ps
CPU time 4.26 seconds
Started Aug 13 04:33:48 PM PDT 24
Finished Aug 13 04:33:53 PM PDT 24
Peak memory 233352 kb
Host smart-54a60395-c089-46ac-a3c3-968bcb6d52d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121964420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4121964420
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3006913306
Short name T565
Test name
Test status
Simulation time 90281669 ps
CPU time 3.87 seconds
Started Aug 13 04:33:00 PM PDT 24
Finished Aug 13 04:33:04 PM PDT 24
Peak memory 224028 kb
Host smart-b70aa159-33a6-454f-9d32-802cd6c4f53f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3006913306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3006913306
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1319589151
Short name T32
Test name
Test status
Simulation time 3967864825 ps
CPU time 86.27 seconds
Started Aug 13 04:32:37 PM PDT 24
Finished Aug 13 04:34:03 PM PDT 24
Peak memory 274084 kb
Host smart-027e895b-a859-4e77-a43a-023c22068ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319589151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1319589151
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4214387089
Short name T90
Test name
Test status
Simulation time 15292174744 ps
CPU time 17.42 seconds
Started Aug 13 04:33:02 PM PDT 24
Finished Aug 13 04:33:20 PM PDT 24
Peak memory 217284 kb
Host smart-05c06e0b-5ec0-4e44-8cb3-b708b5815c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214387089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4214387089
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.548715387
Short name T869
Test name
Test status
Simulation time 1983539954 ps
CPU time 3.11 seconds
Started Aug 13 04:32:41 PM PDT 24
Finished Aug 13 04:32:44 PM PDT 24
Peak memory 217008 kb
Host smart-28caa028-cc35-4773-afed-88acde60e7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548715387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.548715387
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2198869827
Short name T923
Test name
Test status
Simulation time 172149145 ps
CPU time 2.39 seconds
Started Aug 13 04:33:17 PM PDT 24
Finished Aug 13 04:33:20 PM PDT 24
Peak memory 217052 kb
Host smart-4ed34872-7295-4ba2-abf1-1e0c7436a3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198869827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2198869827
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3035442114
Short name T349
Test name
Test status
Simulation time 64101463 ps
CPU time 0.74 seconds
Started Aug 13 04:33:07 PM PDT 24
Finished Aug 13 04:33:08 PM PDT 24
Peak memory 206840 kb
Host smart-78d9ea9f-3152-4736-9e96-a33583a0d9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035442114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3035442114
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.4229649925
Short name T352
Test name
Test status
Simulation time 11665451745 ps
CPU time 11.91 seconds
Started Aug 13 04:32:43 PM PDT 24
Finished Aug 13 04:32:55 PM PDT 24
Peak memory 240124 kb
Host smart-287f85a7-a570-4229-9e5e-45c17a08b353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229649925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.4229649925
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2667796881
Short name T890
Test name
Test status
Simulation time 36943887 ps
CPU time 0.69 seconds
Started Aug 13 04:34:01 PM PDT 24
Finished Aug 13 04:34:02 PM PDT 24
Peak memory 206092 kb
Host smart-31af1aed-88db-4fdd-ab20-2f82a233659d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667796881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2667796881
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.595930815
Short name T366
Test name
Test status
Simulation time 128229218 ps
CPU time 2.49 seconds
Started Aug 13 04:32:48 PM PDT 24
Finished Aug 13 04:32:51 PM PDT 24
Peak memory 233396 kb
Host smart-46a5d797-f07c-411e-a16f-ff49612ff720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595930815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.595930815
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.65682939
Short name T465
Test name
Test status
Simulation time 39062692 ps
CPU time 0.78 seconds
Started Aug 13 04:32:56 PM PDT 24
Finished Aug 13 04:32:57 PM PDT 24
Peak memory 207316 kb
Host smart-7fa3947f-46d1-49fa-93dc-a40bd3264637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65682939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.65682939
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2488361025
Short name T664
Test name
Test status
Simulation time 167967908047 ps
CPU time 145.35 seconds
Started Aug 13 04:32:47 PM PDT 24
Finished Aug 13 04:35:12 PM PDT 24
Peak memory 255236 kb
Host smart-cc721a46-8248-43d9-b95b-f4edab6006c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488361025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2488361025
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.214395500
Short name T718
Test name
Test status
Simulation time 4720435589 ps
CPU time 79.69 seconds
Started Aug 13 04:32:59 PM PDT 24
Finished Aug 13 04:34:19 PM PDT 24
Peak memory 250692 kb
Host smart-b2e95c17-e832-4141-a848-a04268f1e146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214395500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.214395500
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2748639904
Short name T741
Test name
Test status
Simulation time 13435100383 ps
CPU time 86.32 seconds
Started Aug 13 04:32:41 PM PDT 24
Finished Aug 13 04:34:07 PM PDT 24
Peak memory 266176 kb
Host smart-b67bafdd-eb8a-4c59-bb5e-1300025d9dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748639904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2748639904
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2380429640
Short name T288
Test name
Test status
Simulation time 3997911874 ps
CPU time 30.53 seconds
Started Aug 13 04:33:01 PM PDT 24
Finished Aug 13 04:33:32 PM PDT 24
Peak memory 241128 kb
Host smart-e047de22-ed97-441f-a167-7e5d74c24ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380429640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2380429640
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1149141320
Short name T523
Test name
Test status
Simulation time 247330334714 ps
CPU time 232.18 seconds
Started Aug 13 04:32:51 PM PDT 24
Finished Aug 13 04:36:43 PM PDT 24
Peak memory 258208 kb
Host smart-8cedb272-c037-4160-8b5a-d3346d3f5b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149141320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1149141320
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4136398171
Short name T654
Test name
Test status
Simulation time 2804231193 ps
CPU time 13.95 seconds
Started Aug 13 04:34:08 PM PDT 24
Finished Aug 13 04:34:22 PM PDT 24
Peak memory 233484 kb
Host smart-d28b0a83-cb81-47cd-82e5-da6649782dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136398171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4136398171
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1842111522
Short name T426
Test name
Test status
Simulation time 152439026 ps
CPU time 4.79 seconds
Started Aug 13 04:32:52 PM PDT 24
Finished Aug 13 04:32:57 PM PDT 24
Peak memory 233940 kb
Host smart-e4f8e683-8246-4ccc-8501-3b211f63be4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842111522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1842111522
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2217173712
Short name T738
Test name
Test status
Simulation time 2274961897 ps
CPU time 4.48 seconds
Started Aug 13 04:32:54 PM PDT 24
Finished Aug 13 04:32:58 PM PDT 24
Peak memory 225360 kb
Host smart-ce1dc5e6-9b2b-4f88-8c5a-1c23e23bf49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217173712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2217173712
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1037823709
Short name T563
Test name
Test status
Simulation time 25093947544 ps
CPU time 30.95 seconds
Started Aug 13 04:33:03 PM PDT 24
Finished Aug 13 04:33:34 PM PDT 24
Peak memory 233620 kb
Host smart-e2088501-df57-4e7a-888e-cc367b5d144c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037823709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1037823709
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3132756015
Short name T44
Test name
Test status
Simulation time 180098957 ps
CPU time 3.8 seconds
Started Aug 13 04:32:55 PM PDT 24
Finished Aug 13 04:32:59 PM PDT 24
Peak memory 221056 kb
Host smart-8ee1480e-bc73-4d3e-9eef-c7defb56c3e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3132756015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3132756015
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3218515433
Short name T922
Test name
Test status
Simulation time 8900523477 ps
CPU time 127.24 seconds
Started Aug 13 04:32:51 PM PDT 24
Finished Aug 13 04:34:58 PM PDT 24
Peak memory 266408 kb
Host smart-8a06698f-56bd-477f-ae1e-b04a5df7d610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218515433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3218515433
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3179981968
Short name T928
Test name
Test status
Simulation time 1251087742 ps
CPU time 6.17 seconds
Started Aug 13 04:32:48 PM PDT 24
Finished Aug 13 04:32:54 PM PDT 24
Peak memory 217024 kb
Host smart-e8776ac1-1dce-4800-9701-9f0dcf08bc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179981968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3179981968
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.591530562
Short name T705
Test name
Test status
Simulation time 12143664 ps
CPU time 0.74 seconds
Started Aug 13 04:33:06 PM PDT 24
Finished Aug 13 04:33:07 PM PDT 24
Peak memory 206392 kb
Host smart-a7b38e18-fa18-4372-902c-5b4a49a5ce69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591530562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.591530562
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.4123504549
Short name T603
Test name
Test status
Simulation time 176330797 ps
CPU time 3.18 seconds
Started Aug 13 04:32:50 PM PDT 24
Finished Aug 13 04:32:53 PM PDT 24
Peak memory 217052 kb
Host smart-ae982b53-9527-431c-a2d2-3e0e6f079dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123504549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.4123504549
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3921977781
Short name T825
Test name
Test status
Simulation time 125993316 ps
CPU time 0.8 seconds
Started Aug 13 04:32:55 PM PDT 24
Finished Aug 13 04:32:56 PM PDT 24
Peak memory 206708 kb
Host smart-cc0b4abe-1e5a-483e-8a8d-bfaafe41f92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921977781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3921977781
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3263469871
Short name T8
Test name
Test status
Simulation time 87175695 ps
CPU time 2.61 seconds
Started Aug 13 04:32:54 PM PDT 24
Finished Aug 13 04:32:57 PM PDT 24
Peak memory 233088 kb
Host smart-bc57b688-8e55-4c34-9ecb-2298f4b7d6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263469871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3263469871
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1923385257
Short name T719
Test name
Test status
Simulation time 43017453 ps
CPU time 0.68 seconds
Started Aug 13 04:33:48 PM PDT 24
Finished Aug 13 04:33:48 PM PDT 24
Peak memory 206036 kb
Host smart-3410fcd6-7ee2-444f-bc24-c8153d6e5baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923385257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1923385257
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1170740641
Short name T974
Test name
Test status
Simulation time 263656889 ps
CPU time 3.88 seconds
Started Aug 13 04:33:56 PM PDT 24
Finished Aug 13 04:34:00 PM PDT 24
Peak memory 225192 kb
Host smart-4226e139-20a1-4121-a709-9116ad11e2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170740641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1170740641
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2796441318
Short name T583
Test name
Test status
Simulation time 57539384 ps
CPU time 0.78 seconds
Started Aug 13 04:32:45 PM PDT 24
Finished Aug 13 04:32:47 PM PDT 24
Peak memory 207544 kb
Host smart-308d06ac-a396-4330-a8c4-bf8eb7cd99be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796441318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2796441318
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.646553222
Short name T186
Test name
Test status
Simulation time 243806492940 ps
CPU time 406.33 seconds
Started Aug 13 04:32:47 PM PDT 24
Finished Aug 13 04:39:38 PM PDT 24
Peak memory 252628 kb
Host smart-4c937942-45bd-415b-9ee7-87109952900b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646553222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.646553222
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3635731663
Short name T921
Test name
Test status
Simulation time 50462109584 ps
CPU time 445.62 seconds
Started Aug 13 04:33:06 PM PDT 24
Finished Aug 13 04:40:32 PM PDT 24
Peak memory 266276 kb
Host smart-6124ba31-386a-4223-b0b8-767c5838d0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635731663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3635731663
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3650312673
Short name T221
Test name
Test status
Simulation time 51987397829 ps
CPU time 137.86 seconds
Started Aug 13 04:33:01 PM PDT 24
Finished Aug 13 04:35:19 PM PDT 24
Peak memory 257136 kb
Host smart-560afe10-f697-4488-8518-5bf242d36e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650312673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3650312673
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3472290687
Short name T304
Test name
Test status
Simulation time 1561808368 ps
CPU time 23.19 seconds
Started Aug 13 04:33:52 PM PDT 24
Finished Aug 13 04:34:16 PM PDT 24
Peak memory 241556 kb
Host smart-bc39df37-c569-4eea-9000-10a40242d5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472290687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3472290687
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1661511617
Short name T179
Test name
Test status
Simulation time 2776210810 ps
CPU time 57.02 seconds
Started Aug 13 04:33:04 PM PDT 24
Finished Aug 13 04:34:02 PM PDT 24
Peak memory 249564 kb
Host smart-a593be41-a167-43ff-a085-bd8e24aedb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661511617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1661511617
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.232637623
Short name T178
Test name
Test status
Simulation time 4412337356 ps
CPU time 10.87 seconds
Started Aug 13 04:32:50 PM PDT 24
Finished Aug 13 04:33:01 PM PDT 24
Peak memory 233616 kb
Host smart-2e2d33e2-9315-473d-8509-d96bdbcfda6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232637623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.232637623
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3365713062
Short name T683
Test name
Test status
Simulation time 25185031591 ps
CPU time 8.25 seconds
Started Aug 13 04:32:52 PM PDT 24
Finished Aug 13 04:33:01 PM PDT 24
Peak memory 225356 kb
Host smart-42abcd9f-9e02-4fd9-8393-e6bd0d9f1993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365713062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3365713062
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.328765490
Short name T397
Test name
Test status
Simulation time 1273671618 ps
CPU time 11.99 seconds
Started Aug 13 04:32:55 PM PDT 24
Finished Aug 13 04:33:07 PM PDT 24
Peak memory 241184 kb
Host smart-a62ea1c2-3e17-4bc5-b9db-7fdf415c6986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328765490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.328765490
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.194341899
Short name T143
Test name
Test status
Simulation time 516840583 ps
CPU time 7.38 seconds
Started Aug 13 04:32:48 PM PDT 24
Finished Aug 13 04:32:55 PM PDT 24
Peak memory 220264 kb
Host smart-14932545-188b-442e-8281-b1a796b5f9d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=194341899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.194341899
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2573559842
Short name T855
Test name
Test status
Simulation time 435445392 ps
CPU time 4.45 seconds
Started Aug 13 04:32:53 PM PDT 24
Finished Aug 13 04:32:58 PM PDT 24
Peak memory 217140 kb
Host smart-ff55cfbb-7860-4273-860f-0b7e959b967a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573559842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2573559842
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3456150851
Short name T625
Test name
Test status
Simulation time 1129404934 ps
CPU time 1.64 seconds
Started Aug 13 04:32:49 PM PDT 24
Finished Aug 13 04:32:51 PM PDT 24
Peak memory 208660 kb
Host smart-1905aa52-3433-4078-92e9-b50b211264af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456150851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3456150851
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.427447409
Short name T376
Test name
Test status
Simulation time 13224434 ps
CPU time 0.7 seconds
Started Aug 13 04:33:04 PM PDT 24
Finished Aug 13 04:33:04 PM PDT 24
Peak memory 206308 kb
Host smart-28963c5a-cdd4-44d5-8044-04d36cc4391a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427447409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.427447409
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3038395828
Short name T736
Test name
Test status
Simulation time 83919661 ps
CPU time 0.95 seconds
Started Aug 13 04:33:07 PM PDT 24
Finished Aug 13 04:33:08 PM PDT 24
Peak memory 206752 kb
Host smart-c3304417-ea01-4c43-86cd-b26736d740a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038395828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3038395828
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3940525738
Short name T531
Test name
Test status
Simulation time 157078693 ps
CPU time 2.58 seconds
Started Aug 13 04:33:52 PM PDT 24
Finished Aug 13 04:33:54 PM PDT 24
Peak memory 233340 kb
Host smart-25c4df83-6b91-470c-825a-746e1f2c86c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940525738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3940525738
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1960246281
Short name T463
Test name
Test status
Simulation time 49804172 ps
CPU time 0.69 seconds
Started Aug 13 04:32:49 PM PDT 24
Finished Aug 13 04:32:50 PM PDT 24
Peak memory 206220 kb
Host smart-f4aa66f6-1913-434e-9771-02c3a5f96a5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960246281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1960246281
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1283892850
Short name T396
Test name
Test status
Simulation time 8468827251 ps
CPU time 24.46 seconds
Started Aug 13 04:32:54 PM PDT 24
Finished Aug 13 04:33:19 PM PDT 24
Peak memory 233612 kb
Host smart-1ff71410-8e5f-4b47-bb6b-c0c10b0a1840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283892850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1283892850
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1145970790
Short name T1
Test name
Test status
Simulation time 177846834 ps
CPU time 0.71 seconds
Started Aug 13 04:33:54 PM PDT 24
Finished Aug 13 04:33:55 PM PDT 24
Peak memory 207156 kb
Host smart-db7d56e8-e696-4203-b71d-646a6d6be054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145970790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1145970790
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.675502048
Short name T991
Test name
Test status
Simulation time 12310154600 ps
CPU time 40.96 seconds
Started Aug 13 04:33:07 PM PDT 24
Finished Aug 13 04:33:48 PM PDT 24
Peak memory 252296 kb
Host smart-cc6c4ee7-8a64-495a-83c8-d048ec1b2e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675502048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.675502048
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3811628779
Short name T399
Test name
Test status
Simulation time 25504443569 ps
CPU time 23.19 seconds
Started Aug 13 04:32:46 PM PDT 24
Finished Aug 13 04:33:09 PM PDT 24
Peak memory 218640 kb
Host smart-a354f391-1dfb-4937-987c-acae5593ab39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811628779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3811628779
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.970234715
Short name T133
Test name
Test status
Simulation time 60387038058 ps
CPU time 294.45 seconds
Started Aug 13 04:33:52 PM PDT 24
Finished Aug 13 04:38:47 PM PDT 24
Peak memory 264056 kb
Host smart-fcf92a76-e7b4-41d9-b5a6-53307e454b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970234715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.970234715
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2277895692
Short name T728
Test name
Test status
Simulation time 202072833 ps
CPU time 3.47 seconds
Started Aug 13 04:32:56 PM PDT 24
Finished Aug 13 04:32:59 PM PDT 24
Peak memory 225204 kb
Host smart-19ebe496-4c3e-4280-9c6e-4d5c693b6915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277895692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2277895692
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.377169451
Short name T390
Test name
Test status
Simulation time 95900862072 ps
CPU time 164.95 seconds
Started Aug 13 04:32:53 PM PDT 24
Finished Aug 13 04:35:38 PM PDT 24
Peak memory 249992 kb
Host smart-83a0582d-27d4-4201-9f38-4171c4a1b3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377169451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.377169451
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1277937133
Short name T773
Test name
Test status
Simulation time 112852791 ps
CPU time 2.39 seconds
Started Aug 13 04:33:05 PM PDT 24
Finished Aug 13 04:33:08 PM PDT 24
Peak memory 227652 kb
Host smart-9c3c212c-7a7d-408a-badd-ab973f24b5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277937133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1277937133
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2136424130
Short name T355
Test name
Test status
Simulation time 2462116220 ps
CPU time 13.25 seconds
Started Aug 13 04:32:52 PM PDT 24
Finished Aug 13 04:33:05 PM PDT 24
Peak memory 233540 kb
Host smart-5ce5db8d-2ff6-4934-a2c2-3d775994eaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136424130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2136424130
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.820224974
Short name T667
Test name
Test status
Simulation time 4076963366 ps
CPU time 9.11 seconds
Started Aug 13 04:32:51 PM PDT 24
Finished Aug 13 04:33:00 PM PDT 24
Peak memory 236724 kb
Host smart-96520f54-e013-42f4-9ee0-70679c67be05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820224974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.820224974
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1003549906
Short name T403
Test name
Test status
Simulation time 2189856305 ps
CPU time 11.39 seconds
Started Aug 13 04:33:04 PM PDT 24
Finished Aug 13 04:33:15 PM PDT 24
Peak memory 241316 kb
Host smart-da7dc6e7-0727-4e6b-9f05-bc0514d5e843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003549906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1003549906
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3815629505
Short name T940
Test name
Test status
Simulation time 188595363 ps
CPU time 3.83 seconds
Started Aug 13 04:32:55 PM PDT 24
Finished Aug 13 04:32:59 PM PDT 24
Peak memory 220976 kb
Host smart-458aca93-19ae-47ea-a0ab-0e0ad72dc459
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3815629505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3815629505
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2909825025
Short name T22
Test name
Test status
Simulation time 48847758747 ps
CPU time 255.62 seconds
Started Aug 13 04:32:39 PM PDT 24
Finished Aug 13 04:36:55 PM PDT 24
Peak memory 273784 kb
Host smart-ab30be14-c776-4fe5-b437-d34bd3177cfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909825025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2909825025
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2847177071
Short name T507
Test name
Test status
Simulation time 13402329015 ps
CPU time 20.73 seconds
Started Aug 13 04:34:06 PM PDT 24
Finished Aug 13 04:34:27 PM PDT 24
Peak memory 217072 kb
Host smart-1b3c0f1b-3608-4e67-aa42-0c8ec68c2927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847177071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2847177071
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.330082305
Short name T648
Test name
Test status
Simulation time 2002981514 ps
CPU time 2.12 seconds
Started Aug 13 04:33:12 PM PDT 24
Finished Aug 13 04:33:14 PM PDT 24
Peak memory 208660 kb
Host smart-5a775aa8-b50e-46b8-b2d6-77cca94e4897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330082305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.330082305
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2375210498
Short name T335
Test name
Test status
Simulation time 64613171 ps
CPU time 1.24 seconds
Started Aug 13 04:34:06 PM PDT 24
Finished Aug 13 04:34:08 PM PDT 24
Peak memory 216692 kb
Host smart-fab384d3-74c0-4466-a9e2-ebe501fb20b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375210498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2375210498
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.612599370
Short name T734
Test name
Test status
Simulation time 40968743 ps
CPU time 0.74 seconds
Started Aug 13 04:32:59 PM PDT 24
Finished Aug 13 04:33:00 PM PDT 24
Peak memory 206708 kb
Host smart-ee7760c3-0bc8-42fe-a873-025002750c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612599370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.612599370
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.858003456
Short name T878
Test name
Test status
Simulation time 390362652 ps
CPU time 3.35 seconds
Started Aug 13 04:32:52 PM PDT 24
Finished Aug 13 04:32:55 PM PDT 24
Peak memory 225212 kb
Host smart-816ffcb7-75eb-4f2b-bc49-b5b0dda62f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858003456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.858003456
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1871613794
Short name T795
Test name
Test status
Simulation time 16992720 ps
CPU time 0.72 seconds
Started Aug 13 04:32:59 PM PDT 24
Finished Aug 13 04:33:00 PM PDT 24
Peak memory 206164 kb
Host smart-f1567510-0004-434c-8e47-93ed2c0ab6a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871613794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1871613794
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1744627088
Short name T79
Test name
Test status
Simulation time 80016274 ps
CPU time 2.29 seconds
Started Aug 13 04:33:29 PM PDT 24
Finished Aug 13 04:33:32 PM PDT 24
Peak memory 225336 kb
Host smart-f86bd78f-29f5-449f-b4f6-234e4870b1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744627088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1744627088
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.160996284
Short name T361
Test name
Test status
Simulation time 91215418 ps
CPU time 0.79 seconds
Started Aug 13 04:32:52 PM PDT 24
Finished Aug 13 04:32:53 PM PDT 24
Peak memory 207648 kb
Host smart-c65f359f-8bee-4753-abc7-71608c92edf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160996284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.160996284
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.271272329
Short name T428
Test name
Test status
Simulation time 42278625070 ps
CPU time 104.86 seconds
Started Aug 13 04:32:58 PM PDT 24
Finished Aug 13 04:34:43 PM PDT 24
Peak memory 258112 kb
Host smart-694625fb-a785-4269-86fd-87d9f0a21be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271272329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.271272329
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.741598634
Short name T374
Test name
Test status
Simulation time 23738065382 ps
CPU time 185.9 seconds
Started Aug 13 04:33:10 PM PDT 24
Finished Aug 13 04:36:16 PM PDT 24
Peak memory 250096 kb
Host smart-bec4217c-93b2-4852-bf34-986d2a607f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741598634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.741598634
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1725372881
Short name T537
Test name
Test status
Simulation time 27698322191 ps
CPU time 72.07 seconds
Started Aug 13 04:32:53 PM PDT 24
Finished Aug 13 04:34:05 PM PDT 24
Peak memory 233652 kb
Host smart-0ae53eca-a1e6-4280-a181-8e6799ea1a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725372881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1725372881
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.553094397
Short name T987
Test name
Test status
Simulation time 441007037 ps
CPU time 6.54 seconds
Started Aug 13 04:33:01 PM PDT 24
Finished Aug 13 04:33:08 PM PDT 24
Peak memory 236268 kb
Host smart-8cb9cea7-aa61-4238-8e7d-dbe10f3d4497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553094397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.553094397
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.4127416552
Short name T467
Test name
Test status
Simulation time 19409196579 ps
CPU time 68.5 seconds
Started Aug 13 04:32:59 PM PDT 24
Finished Aug 13 04:34:07 PM PDT 24
Peak memory 241056 kb
Host smart-2280177f-c421-4dfa-ac74-b3df20f14da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127416552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.4127416552
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.759448475
Short name T273
Test name
Test status
Simulation time 231770151 ps
CPU time 4.51 seconds
Started Aug 13 04:32:56 PM PDT 24
Finished Aug 13 04:33:00 PM PDT 24
Peak memory 225368 kb
Host smart-c529f830-6798-42b9-b15a-0c72a93ec4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759448475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.759448475
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3364932057
Short name T973
Test name
Test status
Simulation time 2884876479 ps
CPU time 5.57 seconds
Started Aug 13 04:33:09 PM PDT 24
Finished Aug 13 04:33:15 PM PDT 24
Peak memory 225316 kb
Host smart-d2062e45-33f0-42b4-a18d-0f5e3746efe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364932057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3364932057
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2755024014
Short name T811
Test name
Test status
Simulation time 964883250 ps
CPU time 8.61 seconds
Started Aug 13 04:33:37 PM PDT 24
Finished Aug 13 04:33:46 PM PDT 24
Peak memory 238620 kb
Host smart-34457b2b-e571-46f0-8469-9388b5902da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755024014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2755024014
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2134490976
Short name T466
Test name
Test status
Simulation time 3229606651 ps
CPU time 4.61 seconds
Started Aug 13 04:34:11 PM PDT 24
Finished Aug 13 04:34:15 PM PDT 24
Peak memory 233412 kb
Host smart-021c173d-8be0-4d2a-9599-6456b1e05e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134490976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2134490976
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2661510545
Short name T347
Test name
Test status
Simulation time 1191795723 ps
CPU time 8.2 seconds
Started Aug 13 04:33:00 PM PDT 24
Finished Aug 13 04:33:08 PM PDT 24
Peak memory 219780 kb
Host smart-86a48239-a329-43e0-95e3-6d0b919ceeba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2661510545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2661510545
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2206990802
Short name T693
Test name
Test status
Simulation time 137797262751 ps
CPU time 289.49 seconds
Started Aug 13 04:33:02 PM PDT 24
Finished Aug 13 04:37:52 PM PDT 24
Peak memory 266580 kb
Host smart-7e86189d-1482-4a50-bbd4-d12323c82a6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206990802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2206990802
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1286553702
Short name T984
Test name
Test status
Simulation time 242555988 ps
CPU time 2.19 seconds
Started Aug 13 04:32:47 PM PDT 24
Finished Aug 13 04:32:49 PM PDT 24
Peak memory 217096 kb
Host smart-85d38026-8ae0-466d-ba17-5023c11b0fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286553702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1286553702
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1065049235
Short name T881
Test name
Test status
Simulation time 6140126841 ps
CPU time 6.13 seconds
Started Aug 13 04:32:44 PM PDT 24
Finished Aug 13 04:32:50 PM PDT 24
Peak memory 217168 kb
Host smart-5b49c6a5-4691-4d60-9338-eedd915e899d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065049235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1065049235
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1887251606
Short name T453
Test name
Test status
Simulation time 585021957 ps
CPU time 1.59 seconds
Started Aug 13 04:33:37 PM PDT 24
Finished Aug 13 04:33:39 PM PDT 24
Peak memory 215568 kb
Host smart-39c827ff-155a-49c8-a261-11ea3cf620b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887251606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1887251606
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1600125909
Short name T849
Test name
Test status
Simulation time 143642871 ps
CPU time 0.79 seconds
Started Aug 13 04:32:59 PM PDT 24
Finished Aug 13 04:32:59 PM PDT 24
Peak memory 206784 kb
Host smart-45e6f986-c886-4bdc-82ae-c7480373155e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600125909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1600125909
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.866969394
Short name T276
Test name
Test status
Simulation time 12311227017 ps
CPU time 14.68 seconds
Started Aug 13 04:32:57 PM PDT 24
Finished Aug 13 04:33:12 PM PDT 24
Peak memory 238980 kb
Host smart-37605404-a976-437e-a9ab-66411ceeb203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866969394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.866969394
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3156747952
Short name T327
Test name
Test status
Simulation time 120758767 ps
CPU time 0.73 seconds
Started Aug 13 04:32:59 PM PDT 24
Finished Aug 13 04:33:00 PM PDT 24
Peak memory 206152 kb
Host smart-994584a7-a4c7-46ac-88cc-4d9dece25c75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156747952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3156747952
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.718937033
Short name T864
Test name
Test status
Simulation time 181840287 ps
CPU time 2.65 seconds
Started Aug 13 04:33:11 PM PDT 24
Finished Aug 13 04:33:13 PM PDT 24
Peak memory 233496 kb
Host smart-f544999b-f84f-428d-a1fc-c3ee31d3d5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718937033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.718937033
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1958489821
Short name T318
Test name
Test status
Simulation time 27012562 ps
CPU time 0.75 seconds
Started Aug 13 04:33:11 PM PDT 24
Finished Aug 13 04:33:12 PM PDT 24
Peak memory 207636 kb
Host smart-7dd0db72-eb78-4e33-aa5e-dbdb74608826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958489821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1958489821
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1780849800
Short name T510
Test name
Test status
Simulation time 26844606325 ps
CPU time 24.78 seconds
Started Aug 13 04:32:59 PM PDT 24
Finished Aug 13 04:33:24 PM PDT 24
Peak memory 234836 kb
Host smart-6eceb16a-29a0-4661-98cb-2b440f982c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780849800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1780849800
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3356309820
Short name T84
Test name
Test status
Simulation time 33359493792 ps
CPU time 312.09 seconds
Started Aug 13 04:33:15 PM PDT 24
Finished Aug 13 04:38:27 PM PDT 24
Peak memory 257240 kb
Host smart-5ae2d3e2-e115-48ba-b0d2-641636f84b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356309820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3356309820
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2308299087
Short name T228
Test name
Test status
Simulation time 8475582531 ps
CPU time 64.67 seconds
Started Aug 13 04:33:14 PM PDT 24
Finished Aug 13 04:34:19 PM PDT 24
Peak memory 241876 kb
Host smart-e93e752f-4fe7-4033-b711-aa8851725738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308299087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2308299087
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.38597897
Short name T959
Test name
Test status
Simulation time 10574518236 ps
CPU time 41.81 seconds
Started Aug 13 04:33:06 PM PDT 24
Finished Aug 13 04:33:47 PM PDT 24
Peak memory 241784 kb
Host smart-62669c10-1961-4788-b947-49dba52750d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38597897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.38597897
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2185761238
Short name T674
Test name
Test status
Simulation time 129836655095 ps
CPU time 199.8 seconds
Started Aug 13 04:33:02 PM PDT 24
Finished Aug 13 04:36:21 PM PDT 24
Peak memory 252352 kb
Host smart-30faf7e3-3305-444a-b887-8e8247450627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185761238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2185761238
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1673954245
Short name T735
Test name
Test status
Simulation time 2071940237 ps
CPU time 7.62 seconds
Started Aug 13 04:32:52 PM PDT 24
Finished Aug 13 04:33:00 PM PDT 24
Peak memory 225280 kb
Host smart-7129d615-d451-4082-b550-0380bac2318e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673954245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1673954245
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1227376025
Short name T530
Test name
Test status
Simulation time 6250444820 ps
CPU time 25.52 seconds
Started Aug 13 04:33:05 PM PDT 24
Finished Aug 13 04:33:31 PM PDT 24
Peak memory 234644 kb
Host smart-23eec0e8-2258-43d7-af86-7015c302cf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227376025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1227376025
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2005809323
Short name T454
Test name
Test status
Simulation time 1815372389 ps
CPU time 8.23 seconds
Started Aug 13 04:33:13 PM PDT 24
Finished Aug 13 04:33:21 PM PDT 24
Peak memory 233508 kb
Host smart-34784b30-a6d9-4726-a1be-103bada1606c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005809323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2005809323
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3142182976
Short name T662
Test name
Test status
Simulation time 2362607180 ps
CPU time 6.59 seconds
Started Aug 13 04:33:08 PM PDT 24
Finished Aug 13 04:33:15 PM PDT 24
Peak memory 233628 kb
Host smart-76e4e9af-fda6-454b-9167-fbd88e7e1be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142182976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3142182976
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.223295447
Short name T456
Test name
Test status
Simulation time 5821642376 ps
CPU time 17.21 seconds
Started Aug 13 04:33:04 PM PDT 24
Finished Aug 13 04:33:21 PM PDT 24
Peak memory 219968 kb
Host smart-6b4c57fe-9dce-472c-b19c-db343f7f2146
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=223295447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.223295447
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1838664474
Short name T169
Test name
Test status
Simulation time 126055847297 ps
CPU time 318.18 seconds
Started Aug 13 04:32:58 PM PDT 24
Finished Aug 13 04:38:16 PM PDT 24
Peak memory 267764 kb
Host smart-1fe304fa-ea92-4f1e-8eab-635d59a577ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838664474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1838664474
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3358608942
Short name T299
Test name
Test status
Simulation time 9654137493 ps
CPU time 19.92 seconds
Started Aug 13 04:33:07 PM PDT 24
Finished Aug 13 04:33:27 PM PDT 24
Peak memory 217312 kb
Host smart-3c930c6c-609c-4db3-aacc-ba9ba5f446eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358608942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3358608942
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1015189697
Short name T511
Test name
Test status
Simulation time 4851563491 ps
CPU time 3.92 seconds
Started Aug 13 04:33:04 PM PDT 24
Finished Aug 13 04:33:08 PM PDT 24
Peak memory 216840 kb
Host smart-3ff54007-1f94-4bfd-afcf-581519547147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015189697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1015189697
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.471554392
Short name T587
Test name
Test status
Simulation time 101492064 ps
CPU time 2.65 seconds
Started Aug 13 04:33:04 PM PDT 24
Finished Aug 13 04:33:07 PM PDT 24
Peak memory 217164 kb
Host smart-050afa96-2462-431a-8d9a-25ab40d5cfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471554392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.471554392
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2192026898
Short name T894
Test name
Test status
Simulation time 36120850 ps
CPU time 0.68 seconds
Started Aug 13 04:33:04 PM PDT 24
Finished Aug 13 04:33:05 PM PDT 24
Peak memory 206340 kb
Host smart-1dcc51f6-0663-4561-8097-cbe0e34ae4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192026898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2192026898
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.4152090668
Short name T829
Test name
Test status
Simulation time 1334503692 ps
CPU time 10.62 seconds
Started Aug 13 04:32:49 PM PDT 24
Finished Aug 13 04:32:59 PM PDT 24
Peak memory 225224 kb
Host smart-9b612a9c-6341-44ca-a286-6ac8f6d36b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152090668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.4152090668
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3192114051
Short name T504
Test name
Test status
Simulation time 14735384 ps
CPU time 0.73 seconds
Started Aug 13 04:33:01 PM PDT 24
Finished Aug 13 04:33:02 PM PDT 24
Peak memory 205616 kb
Host smart-54715608-1dce-483d-bfba-d5e9d011fd92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192114051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3192114051
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.453813494
Short name T362
Test name
Test status
Simulation time 490073052 ps
CPU time 3.37 seconds
Started Aug 13 04:33:02 PM PDT 24
Finished Aug 13 04:33:06 PM PDT 24
Peak memory 225388 kb
Host smart-b1c02a7f-afa4-4ce0-952f-4babf5d6b793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453813494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.453813494
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.613531179
Short name T789
Test name
Test status
Simulation time 72922669 ps
CPU time 0.76 seconds
Started Aug 13 04:32:57 PM PDT 24
Finished Aug 13 04:32:58 PM PDT 24
Peak memory 206560 kb
Host smart-635abd81-d9a0-42e8-84eb-d3db9c42de62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613531179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.613531179
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.155267129
Short name T367
Test name
Test status
Simulation time 4401010817 ps
CPU time 60.63 seconds
Started Aug 13 04:33:08 PM PDT 24
Finished Aug 13 04:34:09 PM PDT 24
Peak memory 255684 kb
Host smart-cf8c9dd9-0fa3-411a-91e6-496c0a82d0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155267129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.155267129
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3881916465
Short name T270
Test name
Test status
Simulation time 23456936015 ps
CPU time 237.96 seconds
Started Aug 13 04:32:49 PM PDT 24
Finished Aug 13 04:36:47 PM PDT 24
Peak memory 248940 kb
Host smart-46ec87e0-8599-49f4-a035-61643ed623c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881916465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3881916465
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1906732676
Short name T486
Test name
Test status
Simulation time 11881647871 ps
CPU time 33.8 seconds
Started Aug 13 04:33:09 PM PDT 24
Finished Aug 13 04:33:43 PM PDT 24
Peak memory 250080 kb
Host smart-fd94aa4f-6787-40ea-adfa-5813558f9175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906732676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1906732676
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.293531721
Short name T131
Test name
Test status
Simulation time 64439603903 ps
CPU time 160.25 seconds
Started Aug 13 04:32:53 PM PDT 24
Finished Aug 13 04:35:33 PM PDT 24
Peak memory 266364 kb
Host smart-f85ddda8-14d1-4fbc-ba82-7ab01b380276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293531721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.293531721
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1925048304
Short name T545
Test name
Test status
Simulation time 1321625900 ps
CPU time 6.62 seconds
Started Aug 13 04:33:12 PM PDT 24
Finished Aug 13 04:33:18 PM PDT 24
Peak memory 233760 kb
Host smart-0cd23593-8460-4e89-bb62-67bb546b06ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925048304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1925048304
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2892237569
Short name T364
Test name
Test status
Simulation time 2244132837 ps
CPU time 22.28 seconds
Started Aug 13 04:32:57 PM PDT 24
Finished Aug 13 04:33:19 PM PDT 24
Peak memory 233560 kb
Host smart-a9709be8-f004-4121-91f2-94d7e1aa0d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892237569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2892237569
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1670187373
Short name T786
Test name
Test status
Simulation time 2531194001 ps
CPU time 8.06 seconds
Started Aug 13 04:33:08 PM PDT 24
Finished Aug 13 04:33:16 PM PDT 24
Peak memory 225356 kb
Host smart-2a017d5d-0bec-4712-95f8-614ad2681761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670187373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1670187373
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1494806437
Short name T484
Test name
Test status
Simulation time 656862327 ps
CPU time 7.71 seconds
Started Aug 13 04:32:49 PM PDT 24
Finished Aug 13 04:32:57 PM PDT 24
Peak memory 241304 kb
Host smart-9b370d2e-ea90-4371-a1f0-ebbc6a08970a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494806437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1494806437
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1128144139
Short name T911
Test name
Test status
Simulation time 2263667795 ps
CPU time 14.79 seconds
Started Aug 13 04:33:00 PM PDT 24
Finished Aug 13 04:33:15 PM PDT 24
Peak memory 221244 kb
Host smart-fb360a66-573f-485d-a807-0ba0a7cdaf20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1128144139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1128144139
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.348640349
Short name T31
Test name
Test status
Simulation time 12834066976 ps
CPU time 155.75 seconds
Started Aug 13 04:32:51 PM PDT 24
Finished Aug 13 04:35:27 PM PDT 24
Peak memory 268472 kb
Host smart-2b52407a-d8d6-46f5-a74f-a5a9f6a14162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348640349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.348640349
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1534197294
Short name T945
Test name
Test status
Simulation time 26048585039 ps
CPU time 39.29 seconds
Started Aug 13 04:33:01 PM PDT 24
Finished Aug 13 04:33:40 PM PDT 24
Peak memory 217180 kb
Host smart-7ae3006c-590d-490d-bd4a-0aea8a0f8931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534197294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1534197294
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2283682319
Short name T514
Test name
Test status
Simulation time 579008972 ps
CPU time 1.79 seconds
Started Aug 13 04:33:10 PM PDT 24
Finished Aug 13 04:33:12 PM PDT 24
Peak memory 208640 kb
Host smart-d756fe2e-160a-4d8b-9c99-c6d8c970f7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283682319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2283682319
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.196940234
Short name T848
Test name
Test status
Simulation time 138955955 ps
CPU time 1.52 seconds
Started Aug 13 04:33:29 PM PDT 24
Finished Aug 13 04:33:31 PM PDT 24
Peak memory 208684 kb
Host smart-1e014602-8ea0-4f8f-9bb7-c8d7e6cd354b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196940234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.196940234
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1913925678
Short name T781
Test name
Test status
Simulation time 111777849 ps
CPU time 1.06 seconds
Started Aug 13 04:33:14 PM PDT 24
Finished Aug 13 04:33:26 PM PDT 24
Peak memory 207768 kb
Host smart-b966df17-11f7-48c5-bddc-dc137c7e58ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913925678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1913925678
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1884899688
Short name T414
Test name
Test status
Simulation time 333045119 ps
CPU time 6.33 seconds
Started Aug 13 04:33:09 PM PDT 24
Finished Aug 13 04:33:16 PM PDT 24
Peak memory 225376 kb
Host smart-204cd0ef-7b62-42bc-a60e-26f3dbd9f20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884899688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1884899688
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.4234072942
Short name T631
Test name
Test status
Simulation time 12806707 ps
CPU time 0.72 seconds
Started Aug 13 04:33:19 PM PDT 24
Finished Aug 13 04:33:20 PM PDT 24
Peak memory 206144 kb
Host smart-dd105ee9-4c45-4191-ae15-e0dc0baf1844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234072942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
4234072942
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.211752155
Short name T208
Test name
Test status
Simulation time 868156850 ps
CPU time 12.46 seconds
Started Aug 13 04:33:05 PM PDT 24
Finished Aug 13 04:33:17 PM PDT 24
Peak memory 225224 kb
Host smart-e9c36a86-1f8a-4905-b5ba-ccc6fe094d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211752155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.211752155
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.254566714
Short name T908
Test name
Test status
Simulation time 40147512 ps
CPU time 0.79 seconds
Started Aug 13 04:33:14 PM PDT 24
Finished Aug 13 04:33:15 PM PDT 24
Peak memory 206616 kb
Host smart-3cdf8cc0-c3b4-461a-8c61-cee007aad664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254566714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.254566714
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2385557180
Short name T619
Test name
Test status
Simulation time 4610718897 ps
CPU time 60.03 seconds
Started Aug 13 04:33:06 PM PDT 24
Finished Aug 13 04:34:06 PM PDT 24
Peak memory 250144 kb
Host smart-d7a65134-d7c7-4d40-abe9-e55ea8df5be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385557180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2385557180
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2139036311
Short name T132
Test name
Test status
Simulation time 9393155276 ps
CPU time 71.86 seconds
Started Aug 13 04:33:14 PM PDT 24
Finished Aug 13 04:34:25 PM PDT 24
Peak memory 250076 kb
Host smart-f250f1d7-6d30-4947-811c-a336af58509f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139036311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2139036311
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3486710553
Short name T234
Test name
Test status
Simulation time 25350449431 ps
CPU time 166.53 seconds
Started Aug 13 04:33:16 PM PDT 24
Finished Aug 13 04:36:02 PM PDT 24
Peak memory 256548 kb
Host smart-bf407ca3-5564-41b0-87bf-a0a58364e5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486710553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3486710553
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.938967246
Short name T93
Test name
Test status
Simulation time 49362251154 ps
CPU time 186.41 seconds
Started Aug 13 04:33:13 PM PDT 24
Finished Aug 13 04:36:20 PM PDT 24
Peak memory 253780 kb
Host smart-d57075da-246b-4698-a891-7f4a81d43361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938967246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.938967246
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1576081283
Short name T51
Test name
Test status
Simulation time 92501050 ps
CPU time 4.03 seconds
Started Aug 13 04:33:03 PM PDT 24
Finished Aug 13 04:33:07 PM PDT 24
Peak memory 233476 kb
Host smart-f35655f5-3b1d-4f57-a4bc-cb8a4b4e0877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576081283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1576081283
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3170744853
Short name T815
Test name
Test status
Simulation time 11911978721 ps
CPU time 27.76 seconds
Started Aug 13 04:33:01 PM PDT 24
Finished Aug 13 04:33:29 PM PDT 24
Peak memory 241360 kb
Host smart-ceb864e4-46d2-40ef-985d-6c27d6e8154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170744853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3170744853
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1165138710
Short name T421
Test name
Test status
Simulation time 3465230423 ps
CPU time 13.29 seconds
Started Aug 13 04:33:16 PM PDT 24
Finished Aug 13 04:33:30 PM PDT 24
Peak memory 233408 kb
Host smart-b746ff34-8c6b-4f86-844f-7a0f30d3be02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165138710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1165138710
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3872722692
Short name T205
Test name
Test status
Simulation time 71596462907 ps
CPU time 24.29 seconds
Started Aug 13 04:33:02 PM PDT 24
Finished Aug 13 04:33:26 PM PDT 24
Peak memory 233680 kb
Host smart-422c3475-3774-4f7a-8842-a325375baf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872722692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3872722692
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2398544869
Short name T685
Test name
Test status
Simulation time 1204223192 ps
CPU time 4.97 seconds
Started Aug 13 04:33:24 PM PDT 24
Finished Aug 13 04:33:29 PM PDT 24
Peak memory 220728 kb
Host smart-c88e8211-96ea-4089-9171-12a8a165a121
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2398544869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2398544869
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1561739633
Short name T546
Test name
Test status
Simulation time 121163374923 ps
CPU time 626.48 seconds
Started Aug 13 04:32:59 PM PDT 24
Finished Aug 13 04:43:26 PM PDT 24
Peak memory 273964 kb
Host smart-cbd86056-c33b-4430-91f0-7a0230898668
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561739633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1561739633
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1005145532
Short name T968
Test name
Test status
Simulation time 19797269389 ps
CPU time 49.83 seconds
Started Aug 13 04:33:06 PM PDT 24
Finished Aug 13 04:33:56 PM PDT 24
Peak memory 217324 kb
Host smart-06be905e-c965-4e53-ba16-0ddf10a0e35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005145532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1005145532
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2961265775
Short name T924
Test name
Test status
Simulation time 1575559464 ps
CPU time 2.17 seconds
Started Aug 13 04:32:58 PM PDT 24
Finished Aug 13 04:33:00 PM PDT 24
Peak memory 217036 kb
Host smart-ccaaafd9-4a7d-4171-8953-2e277ef493eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961265775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2961265775
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1831783507
Short name T413
Test name
Test status
Simulation time 391914846 ps
CPU time 1.79 seconds
Started Aug 13 04:32:54 PM PDT 24
Finished Aug 13 04:32:56 PM PDT 24
Peak memory 217028 kb
Host smart-6ac323f0-ee5d-40ca-85c9-13d99e1fe139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831783507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1831783507
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2569828985
Short name T714
Test name
Test status
Simulation time 146534230 ps
CPU time 0.85 seconds
Started Aug 13 04:33:03 PM PDT 24
Finished Aug 13 04:33:03 PM PDT 24
Peak memory 207872 kb
Host smart-b8cf973c-f4d9-462d-8d64-d32b6b7cc551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569828985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2569828985
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3248337081
Short name T388
Test name
Test status
Simulation time 173646148 ps
CPU time 2.98 seconds
Started Aug 13 04:33:11 PM PDT 24
Finished Aug 13 04:33:14 PM PDT 24
Peak memory 233428 kb
Host smart-961ceca2-f027-44ed-b41c-855b74efc09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248337081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3248337081
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2042687040
Short name T418
Test name
Test status
Simulation time 41395182 ps
CPU time 0.7 seconds
Started Aug 13 04:33:39 PM PDT 24
Finished Aug 13 04:33:40 PM PDT 24
Peak memory 206524 kb
Host smart-2233dff1-6c30-47a7-a5cf-ea1023eb325a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042687040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2042687040
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3606014048
Short name T673
Test name
Test status
Simulation time 166040753 ps
CPU time 2.46 seconds
Started Aug 13 04:33:12 PM PDT 24
Finished Aug 13 04:33:14 PM PDT 24
Peak memory 233144 kb
Host smart-86a7a583-0fd3-45f1-9d54-6b8b051dca63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606014048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3606014048
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3352982016
Short name T317
Test name
Test status
Simulation time 17759350 ps
CPU time 0.8 seconds
Started Aug 13 04:33:07 PM PDT 24
Finished Aug 13 04:33:08 PM PDT 24
Peak memory 207320 kb
Host smart-a11a02f9-49e7-430e-a78c-1b95623e5247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352982016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3352982016
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2017737437
Short name T220
Test name
Test status
Simulation time 9413343534 ps
CPU time 81.6 seconds
Started Aug 13 04:33:09 PM PDT 24
Finished Aug 13 04:34:31 PM PDT 24
Peak memory 238308 kb
Host smart-fae59b86-9913-4411-8d97-674c094b14d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017737437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2017737437
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.719424435
Short name T236
Test name
Test status
Simulation time 135398864660 ps
CPU time 152.81 seconds
Started Aug 13 04:33:03 PM PDT 24
Finished Aug 13 04:35:36 PM PDT 24
Peak memory 263840 kb
Host smart-5b37efdc-c474-4ca0-9d8f-159bc1955a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719424435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.719424435
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.285061075
Short name T16
Test name
Test status
Simulation time 873462209 ps
CPU time 19.14 seconds
Started Aug 13 04:33:25 PM PDT 24
Finished Aug 13 04:33:44 PM PDT 24
Peak memory 252232 kb
Host smart-a53671af-939c-47f3-973a-7aacac8ae9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285061075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.285061075
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2409663527
Short name T455
Test name
Test status
Simulation time 3140200470 ps
CPU time 23.05 seconds
Started Aug 13 04:33:13 PM PDT 24
Finished Aug 13 04:33:36 PM PDT 24
Peak memory 233616 kb
Host smart-0da139b2-4d6a-42f8-b48e-a8afa10376cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409663527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2409663527
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3223368013
Short name T266
Test name
Test status
Simulation time 7537684925 ps
CPU time 8.97 seconds
Started Aug 13 04:32:59 PM PDT 24
Finished Aug 13 04:33:08 PM PDT 24
Peak memory 233556 kb
Host smart-aaa377fd-5a0b-4039-aea0-7ae1f0ac1dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223368013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3223368013
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2885810423
Short name T858
Test name
Test status
Simulation time 4572705526 ps
CPU time 16.78 seconds
Started Aug 13 04:33:13 PM PDT 24
Finished Aug 13 04:33:30 PM PDT 24
Peak memory 241660 kb
Host smart-1282be0d-eae5-4ead-bc1b-a755e3c9677a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885810423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2885810423
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1499470029
Short name T771
Test name
Test status
Simulation time 3145472061 ps
CPU time 4.55 seconds
Started Aug 13 04:32:56 PM PDT 24
Finished Aug 13 04:33:01 PM PDT 24
Peak memory 225420 kb
Host smart-d2df418e-07ac-4f53-978c-9e7ac0926067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499470029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1499470029
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1218037860
Short name T406
Test name
Test status
Simulation time 44560201428 ps
CPU time 31.81 seconds
Started Aug 13 04:33:20 PM PDT 24
Finished Aug 13 04:33:52 PM PDT 24
Peak memory 233632 kb
Host smart-726364e2-8717-4270-ba55-0fa700cb803b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218037860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1218037860
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3296629414
Short name T802
Test name
Test status
Simulation time 2820837299 ps
CPU time 9.57 seconds
Started Aug 13 04:33:05 PM PDT 24
Finished Aug 13 04:33:15 PM PDT 24
Peak memory 223200 kb
Host smart-96bff022-6225-4f71-b4d3-f641c8290471
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3296629414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3296629414
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1039138999
Short name T154
Test name
Test status
Simulation time 44769319533 ps
CPU time 300.5 seconds
Started Aug 13 04:33:09 PM PDT 24
Finished Aug 13 04:38:10 PM PDT 24
Peak memory 257456 kb
Host smart-007d1b39-6cd8-4ccb-8f53-c632dc008b07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039138999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1039138999
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3880289434
Short name T402
Test name
Test status
Simulation time 5559727707 ps
CPU time 22.31 seconds
Started Aug 13 04:33:16 PM PDT 24
Finished Aug 13 04:33:38 PM PDT 24
Peak memory 217320 kb
Host smart-53eb61ed-e8fb-4598-8d60-968bcea934df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880289434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3880289434
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.203874158
Short name T942
Test name
Test status
Simulation time 666922664 ps
CPU time 3.22 seconds
Started Aug 13 04:33:10 PM PDT 24
Finished Aug 13 04:33:14 PM PDT 24
Peak memory 217068 kb
Host smart-569ffca9-673f-4deb-a18c-8a43783296db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203874158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.203874158
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3257753385
Short name T712
Test name
Test status
Simulation time 16825973 ps
CPU time 0.77 seconds
Started Aug 13 04:33:15 PM PDT 24
Finished Aug 13 04:33:21 PM PDT 24
Peak memory 206764 kb
Host smart-62031f1d-cc61-4f8f-a9c0-1573be1876e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257753385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3257753385
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2665694607
Short name T497
Test name
Test status
Simulation time 85880696 ps
CPU time 0.93 seconds
Started Aug 13 04:33:17 PM PDT 24
Finished Aug 13 04:33:18 PM PDT 24
Peak memory 206724 kb
Host smart-ec5c1584-b063-4b03-8659-328d9eae7c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665694607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2665694607
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.631365233
Short name T47
Test name
Test status
Simulation time 1874961992 ps
CPU time 9.12 seconds
Started Aug 13 04:33:01 PM PDT 24
Finished Aug 13 04:33:11 PM PDT 24
Peak memory 225336 kb
Host smart-ffaec486-6b63-42e5-97fd-4beb9a0c28d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631365233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.631365233
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.663418657
Short name T306
Test name
Test status
Simulation time 87285651 ps
CPU time 0.73 seconds
Started Aug 13 04:33:15 PM PDT 24
Finished Aug 13 04:33:16 PM PDT 24
Peak memory 206168 kb
Host smart-e3b5bcf5-0541-4ec6-a487-caae56e21bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663418657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.663418657
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.800340309
Short name T800
Test name
Test status
Simulation time 139202155 ps
CPU time 3.25 seconds
Started Aug 13 04:33:05 PM PDT 24
Finished Aug 13 04:33:09 PM PDT 24
Peak memory 233552 kb
Host smart-d4a7222c-7286-4c98-9d79-4621500a962e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800340309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.800340309
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2356515819
Short name T604
Test name
Test status
Simulation time 21240110 ps
CPU time 0.72 seconds
Started Aug 13 04:33:18 PM PDT 24
Finished Aug 13 04:33:19 PM PDT 24
Peak memory 207568 kb
Host smart-3e503bf9-42c6-41bf-9b84-386457f38c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356515819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2356515819
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1148305804
Short name T191
Test name
Test status
Simulation time 52790606952 ps
CPU time 173.5 seconds
Started Aug 13 04:33:05 PM PDT 24
Finished Aug 13 04:35:59 PM PDT 24
Peak memory 266880 kb
Host smart-203f9e30-94ad-4f60-a4d3-6ba6a8ad7e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148305804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1148305804
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2866290710
Short name T224
Test name
Test status
Simulation time 101727119949 ps
CPU time 147.53 seconds
Started Aug 13 04:33:26 PM PDT 24
Finished Aug 13 04:35:54 PM PDT 24
Peak memory 264384 kb
Host smart-0a114dbb-3e52-45fd-a279-8404c57f3fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866290710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2866290710
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2622864691
Short name T925
Test name
Test status
Simulation time 66976684935 ps
CPU time 385.03 seconds
Started Aug 13 04:33:12 PM PDT 24
Finished Aug 13 04:39:38 PM PDT 24
Peak memory 283356 kb
Host smart-ec25c93a-18ca-428b-8886-2370feddf749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622864691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2622864691
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.52958413
Short name T930
Test name
Test status
Simulation time 5685355281 ps
CPU time 28.19 seconds
Started Aug 13 04:33:12 PM PDT 24
Finished Aug 13 04:33:41 PM PDT 24
Peak memory 255880 kb
Host smart-311587f5-04ae-487b-966f-fcceb8634a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52958413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.52958413
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2361851994
Short name T916
Test name
Test status
Simulation time 36985424920 ps
CPU time 196.75 seconds
Started Aug 13 04:33:04 PM PDT 24
Finished Aug 13 04:36:21 PM PDT 24
Peak memory 266384 kb
Host smart-d52ed8c7-06ff-414e-9e89-0485c0f376b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361851994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2361851994
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3985253780
Short name T365
Test name
Test status
Simulation time 1788267363 ps
CPU time 8.81 seconds
Started Aug 13 04:33:16 PM PDT 24
Finished Aug 13 04:33:25 PM PDT 24
Peak memory 233400 kb
Host smart-762ba278-6f5c-4dd4-bf3c-f813253e5e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985253780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3985253780
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2396984600
Short name T272
Test name
Test status
Simulation time 165283839 ps
CPU time 5.43 seconds
Started Aug 13 04:33:27 PM PDT 24
Finished Aug 13 04:33:33 PM PDT 24
Peak memory 225300 kb
Host smart-32a416d2-d30f-4b40-9cc1-bb8a55c0714b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396984600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2396984600
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2256113655
Short name T281
Test name
Test status
Simulation time 868362918 ps
CPU time 3.16 seconds
Started Aug 13 04:33:14 PM PDT 24
Finished Aug 13 04:33:17 PM PDT 24
Peak memory 233456 kb
Host smart-4689e805-7125-4527-8f3a-a10f71419ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256113655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2256113655
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1708984821
Short name T468
Test name
Test status
Simulation time 220536185 ps
CPU time 5.04 seconds
Started Aug 13 04:33:05 PM PDT 24
Finished Aug 13 04:33:10 PM PDT 24
Peak memory 233460 kb
Host smart-131a2595-a093-4ba0-86a3-5f897d50badc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708984821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1708984821
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1964603317
Short name T142
Test name
Test status
Simulation time 71514545 ps
CPU time 3.62 seconds
Started Aug 13 04:33:16 PM PDT 24
Finished Aug 13 04:33:20 PM PDT 24
Peak memory 223808 kb
Host smart-6e345805-8c59-4987-ad61-3a47d7e62d53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1964603317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1964603317
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1557119109
Short name T818
Test name
Test status
Simulation time 14899267837 ps
CPU time 83.28 seconds
Started Aug 13 04:33:08 PM PDT 24
Finished Aug 13 04:34:31 PM PDT 24
Peak memory 250084 kb
Host smart-20b2e9f7-cb48-4225-aaf4-edac71d5fb0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557119109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1557119109
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3860287128
Short name T550
Test name
Test status
Simulation time 521472201 ps
CPU time 5.98 seconds
Started Aug 13 04:32:51 PM PDT 24
Finished Aug 13 04:32:57 PM PDT 24
Peak memory 220092 kb
Host smart-83b6e98b-5177-4460-85bf-0c913ddd02fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860287128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3860287128
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2911884939
Short name T518
Test name
Test status
Simulation time 1837026782 ps
CPU time 5.97 seconds
Started Aug 13 04:33:04 PM PDT 24
Finished Aug 13 04:33:10 PM PDT 24
Peak memory 217112 kb
Host smart-5edd291a-1af0-41fd-8b5b-d31fdf87a6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911884939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2911884939
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3214942237
Short name T378
Test name
Test status
Simulation time 327404901 ps
CPU time 1.18 seconds
Started Aug 13 04:33:04 PM PDT 24
Finished Aug 13 04:33:05 PM PDT 24
Peak memory 217188 kb
Host smart-fe34adbe-dd1b-4227-ac2e-36db467e7f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214942237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3214942237
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1433811998
Short name T548
Test name
Test status
Simulation time 51991171 ps
CPU time 0.72 seconds
Started Aug 13 04:33:17 PM PDT 24
Finished Aug 13 04:33:18 PM PDT 24
Peak memory 206744 kb
Host smart-d8bfe950-6123-4682-80e5-587037349bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433811998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1433811998
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3087742979
Short name T555
Test name
Test status
Simulation time 6945395307 ps
CPU time 14.14 seconds
Started Aug 13 04:33:05 PM PDT 24
Finished Aug 13 04:33:19 PM PDT 24
Peak memory 249936 kb
Host smart-a54f5878-b453-4117-a3bb-5277940f5ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087742979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3087742979
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.691216248
Short name T888
Test name
Test status
Simulation time 18096406 ps
CPU time 0.69 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:31:09 PM PDT 24
Peak memory 205572 kb
Host smart-b665fb27-89f4-49b8-a2a2-03a2c5ee9927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691216248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.691216248
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3708205430
Short name T571
Test name
Test status
Simulation time 4730732387 ps
CPU time 21.82 seconds
Started Aug 13 04:30:59 PM PDT 24
Finished Aug 13 04:31:21 PM PDT 24
Peak memory 233532 kb
Host smart-97727eab-c504-4af6-802f-02a7f23dc667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708205430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3708205430
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.558831745
Short name T370
Test name
Test status
Simulation time 70864055 ps
CPU time 0.72 seconds
Started Aug 13 04:31:03 PM PDT 24
Finished Aug 13 04:31:04 PM PDT 24
Peak memory 206252 kb
Host smart-de7b1e42-6626-40c7-8de4-df45bd1fbdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558831745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.558831745
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1973612359
Short name T668
Test name
Test status
Simulation time 22889118758 ps
CPU time 57.75 seconds
Started Aug 13 04:30:59 PM PDT 24
Finished Aug 13 04:31:57 PM PDT 24
Peak memory 250116 kb
Host smart-08b4ec24-c809-4c3b-9897-0b94596f9e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973612359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1973612359
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4170376298
Short name T817
Test name
Test status
Simulation time 3552894831 ps
CPU time 63.16 seconds
Started Aug 13 04:30:58 PM PDT 24
Finished Aug 13 04:32:01 PM PDT 24
Peak memory 250100 kb
Host smart-5983bf03-759f-469a-8027-af055cb93ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170376298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4170376298
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1077943993
Short name T325
Test name
Test status
Simulation time 1676538297 ps
CPU time 7.22 seconds
Started Aug 13 04:31:01 PM PDT 24
Finished Aug 13 04:31:09 PM PDT 24
Peak memory 234652 kb
Host smart-224567b3-dbcf-4b1d-9f56-d192a7c67a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077943993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1077943993
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2741343029
Short name T752
Test name
Test status
Simulation time 2418259604 ps
CPU time 20.52 seconds
Started Aug 13 04:30:59 PM PDT 24
Finished Aug 13 04:31:20 PM PDT 24
Peak memory 235028 kb
Host smart-fd6a3700-eccf-4c00-8a89-f7b8f0639a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741343029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2741343029
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3550081416
Short name T821
Test name
Test status
Simulation time 4913490610 ps
CPU time 12.74 seconds
Started Aug 13 04:30:58 PM PDT 24
Finished Aug 13 04:31:11 PM PDT 24
Peak memory 233684 kb
Host smart-02b244bc-0d3c-4683-8a6a-3fa873e330a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550081416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3550081416
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3346984683
Short name T210
Test name
Test status
Simulation time 80203731399 ps
CPU time 81.67 seconds
Started Aug 13 04:31:01 PM PDT 24
Finished Aug 13 04:32:23 PM PDT 24
Peak memory 240604 kb
Host smart-95865372-b09c-49b9-88c6-a1078b2c1d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346984683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3346984683
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2094721424
Short name T184
Test name
Test status
Simulation time 538742026 ps
CPU time 6.03 seconds
Started Aug 13 04:31:01 PM PDT 24
Finished Aug 13 04:31:07 PM PDT 24
Peak memory 240004 kb
Host smart-4bcd1314-998d-40ec-8b58-9c6a4c6157b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094721424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2094721424
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2430266302
Short name T832
Test name
Test status
Simulation time 84942820 ps
CPU time 2.32 seconds
Started Aug 13 04:30:52 PM PDT 24
Finished Aug 13 04:30:55 PM PDT 24
Peak memory 233116 kb
Host smart-da3f4d84-60ca-4bc0-ad5c-5dab50aa4104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430266302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2430266302
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2810428633
Short name T914
Test name
Test status
Simulation time 202379465 ps
CPU time 4.83 seconds
Started Aug 13 04:30:59 PM PDT 24
Finished Aug 13 04:31:04 PM PDT 24
Peak memory 223872 kb
Host smart-49269fc7-4b75-4a7b-849b-581f0411876b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2810428633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2810428633
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2109444464
Short name T494
Test name
Test status
Simulation time 3564683836 ps
CPU time 26.71 seconds
Started Aug 13 04:31:03 PM PDT 24
Finished Aug 13 04:31:30 PM PDT 24
Peak memory 225392 kb
Host smart-70533a09-7d76-4c6a-851e-11fdbf37e458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109444464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2109444464
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.470067187
Short name T521
Test name
Test status
Simulation time 13329713297 ps
CPU time 24.71 seconds
Started Aug 13 04:30:54 PM PDT 24
Finished Aug 13 04:31:19 PM PDT 24
Peak memory 217644 kb
Host smart-c2461988-197a-424f-bce7-30a065a4cbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470067187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.470067187
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2557204109
Short name T458
Test name
Test status
Simulation time 32565775289 ps
CPU time 20.26 seconds
Started Aug 13 04:31:21 PM PDT 24
Finished Aug 13 04:31:41 PM PDT 24
Peak memory 217192 kb
Host smart-280a9004-1c7f-451e-a939-7e5a74de671d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557204109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2557204109
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2729465827
Short name T732
Test name
Test status
Simulation time 243392181 ps
CPU time 2.3 seconds
Started Aug 13 04:30:54 PM PDT 24
Finished Aug 13 04:30:57 PM PDT 24
Peak memory 217036 kb
Host smart-937d9c9d-5181-42c1-8b19-189420866960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729465827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2729465827
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2344846068
Short name T314
Test name
Test status
Simulation time 104513921 ps
CPU time 1 seconds
Started Aug 13 04:30:58 PM PDT 24
Finished Aug 13 04:30:59 PM PDT 24
Peak memory 207880 kb
Host smart-48886be4-6978-45b9-9236-9d20da78d670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344846068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2344846068
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1674433715
Short name T678
Test name
Test status
Simulation time 700444186 ps
CPU time 4.27 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:10 PM PDT 24
Peak memory 225176 kb
Host smart-fa66f4f5-1ea4-46f2-ba37-ccc71fc921b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674433715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1674433715
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1160666716
Short name T459
Test name
Test status
Simulation time 23085348 ps
CPU time 0.73 seconds
Started Aug 13 04:30:54 PM PDT 24
Finished Aug 13 04:30:55 PM PDT 24
Peak memory 205584 kb
Host smart-c2546cfe-fc48-4367-8244-9109763766e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160666716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
160666716
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3087778244
Short name T787
Test name
Test status
Simulation time 13612834819 ps
CPU time 34.47 seconds
Started Aug 13 04:30:59 PM PDT 24
Finished Aug 13 04:31:34 PM PDT 24
Peak memory 225372 kb
Host smart-4127b7c6-bf63-4524-bb9c-399788a52284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087778244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3087778244
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3910589079
Short name T340
Test name
Test status
Simulation time 84861928 ps
CPU time 0.85 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:06 PM PDT 24
Peak memory 207620 kb
Host smart-233624db-65bf-43d7-a80c-5050e0468763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910589079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3910589079
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3003859509
Short name T285
Test name
Test status
Simulation time 3591944801 ps
CPU time 19.56 seconds
Started Aug 13 04:31:00 PM PDT 24
Finished Aug 13 04:31:20 PM PDT 24
Peak memory 233552 kb
Host smart-09ab8ed4-d72e-46c4-82fa-cd7b0c538f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003859509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3003859509
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1754341094
Short name T512
Test name
Test status
Simulation time 14404807435 ps
CPU time 32.24 seconds
Started Aug 13 04:31:01 PM PDT 24
Finished Aug 13 04:31:33 PM PDT 24
Peak memory 233800 kb
Host smart-ef94a109-577f-42ce-b646-aaa19972805a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754341094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1754341094
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.4180927798
Short name T935
Test name
Test status
Simulation time 3213144869 ps
CPU time 11.95 seconds
Started Aug 13 04:30:56 PM PDT 24
Finished Aug 13 04:31:08 PM PDT 24
Peak memory 225304 kb
Host smart-a0f48edd-7989-4497-8769-93d358a2dd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180927798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.4180927798
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2416220038
Short name T95
Test name
Test status
Simulation time 15129142193 ps
CPU time 53.98 seconds
Started Aug 13 04:31:02 PM PDT 24
Finished Aug 13 04:31:56 PM PDT 24
Peak memory 254260 kb
Host smart-4f1d2589-a060-4c9c-837c-089cbfd72ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416220038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2416220038
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3232046061
Short name T870
Test name
Test status
Simulation time 138661389 ps
CPU time 3.14 seconds
Started Aug 13 04:31:02 PM PDT 24
Finished Aug 13 04:31:06 PM PDT 24
Peak memory 225196 kb
Host smart-fc2b04e9-c36f-4fe5-8430-6d152d42c525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232046061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3232046061
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1034007436
Short name T638
Test name
Test status
Simulation time 167256008 ps
CPU time 3.2 seconds
Started Aug 13 04:31:11 PM PDT 24
Finished Aug 13 04:31:15 PM PDT 24
Peak memory 225328 kb
Host smart-364fef22-e674-47dc-9fab-09385cacd69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034007436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1034007436
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4047825891
Short name T681
Test name
Test status
Simulation time 110036550 ps
CPU time 2.4 seconds
Started Aug 13 04:31:24 PM PDT 24
Finished Aug 13 04:31:27 PM PDT 24
Peak memory 224252 kb
Host smart-eae856ce-6269-4315-ad6e-032faa57d075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047825891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4047825891
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.615684196
Short name T702
Test name
Test status
Simulation time 347176016 ps
CPU time 4.07 seconds
Started Aug 13 04:31:00 PM PDT 24
Finished Aug 13 04:31:10 PM PDT 24
Peak memory 233412 kb
Host smart-45dfa4ab-4629-4b80-8f84-e7c2bde61eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615684196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.615684196
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2361381179
Short name T46
Test name
Test status
Simulation time 853376796 ps
CPU time 6.12 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:31:14 PM PDT 24
Peak memory 220160 kb
Host smart-fe1d86e3-d180-47ce-99bf-ac51345c7d4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2361381179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2361381179
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3018105138
Short name T985
Test name
Test status
Simulation time 16717762659 ps
CPU time 192.28 seconds
Started Aug 13 04:30:56 PM PDT 24
Finished Aug 13 04:34:08 PM PDT 24
Peak memory 250076 kb
Host smart-836470b7-eb2f-4daa-a49b-6c0571a391b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018105138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3018105138
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3673711569
Short name T303
Test name
Test status
Simulation time 34371101209 ps
CPU time 21.97 seconds
Started Aug 13 04:31:02 PM PDT 24
Finished Aug 13 04:31:24 PM PDT 24
Peak memory 217172 kb
Host smart-cff8c049-0b2b-4bba-82a3-a5ebdf506413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673711569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3673711569
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1741301282
Short name T479
Test name
Test status
Simulation time 1351539637 ps
CPU time 6.08 seconds
Started Aug 13 04:30:59 PM PDT 24
Finished Aug 13 04:31:05 PM PDT 24
Peak memory 217040 kb
Host smart-1219adbf-5968-403c-9f16-866e3de1077f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741301282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1741301282
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3826964005
Short name T776
Test name
Test status
Simulation time 57536486 ps
CPU time 1.18 seconds
Started Aug 13 04:31:03 PM PDT 24
Finished Aug 13 04:31:04 PM PDT 24
Peak memory 208744 kb
Host smart-fd284945-b9e8-4f92-be2a-6c7977212632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826964005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3826964005
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.579344059
Short name T451
Test name
Test status
Simulation time 132766224 ps
CPU time 0.8 seconds
Started Aug 13 04:31:11 PM PDT 24
Finished Aug 13 04:31:17 PM PDT 24
Peak memory 206736 kb
Host smart-cf995741-91f6-4204-8c5f-dd42df025690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579344059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.579344059
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2268343643
Short name T65
Test name
Test status
Simulation time 2559153682 ps
CPU time 5.15 seconds
Started Aug 13 04:30:58 PM PDT 24
Finished Aug 13 04:31:04 PM PDT 24
Peak memory 225312 kb
Host smart-3dd6f95c-bf9d-484b-80d6-d51f91e48ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268343643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2268343643
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3716230381
Short name T4
Test name
Test status
Simulation time 21026194 ps
CPU time 0.68 seconds
Started Aug 13 04:31:30 PM PDT 24
Finished Aug 13 04:31:31 PM PDT 24
Peak memory 206180 kb
Host smart-03070e44-b204-488d-b226-eebcce24a2ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716230381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
716230381
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2316589593
Short name T211
Test name
Test status
Simulation time 2049459696 ps
CPU time 6.43 seconds
Started Aug 13 04:31:10 PM PDT 24
Finished Aug 13 04:31:16 PM PDT 24
Peak memory 233544 kb
Host smart-15a8c317-7766-4635-9e09-3a9423615adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316589593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2316589593
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.291965659
Short name T767
Test name
Test status
Simulation time 47858068 ps
CPU time 0.73 seconds
Started Aug 13 04:31:14 PM PDT 24
Finished Aug 13 04:31:15 PM PDT 24
Peak memory 206180 kb
Host smart-c7d1f370-fd5f-44d0-8fd4-16a371e64ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291965659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.291965659
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.480496923
Short name T43
Test name
Test status
Simulation time 25132496477 ps
CPU time 84.3 seconds
Started Aug 13 04:31:02 PM PDT 24
Finished Aug 13 04:32:27 PM PDT 24
Peak memory 249912 kb
Host smart-3cdd3f24-b586-4eaf-89e2-dc2d33287044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480496923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.480496923
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2445414589
Short name T125
Test name
Test status
Simulation time 5786912790 ps
CPU time 40.68 seconds
Started Aug 13 04:31:18 PM PDT 24
Finished Aug 13 04:31:59 PM PDT 24
Peak memory 242136 kb
Host smart-6c02ce2a-9963-42f6-a389-c739b3787ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445414589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2445414589
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3199793637
Short name T716
Test name
Test status
Simulation time 103625838 ps
CPU time 3.73 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:31:12 PM PDT 24
Peak memory 225284 kb
Host smart-e9685e73-4b30-4614-a9f2-15c3bf33af11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199793637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3199793637
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2620557158
Short name T709
Test name
Test status
Simulation time 170066076026 ps
CPU time 259.31 seconds
Started Aug 13 04:31:01 PM PDT 24
Finished Aug 13 04:35:20 PM PDT 24
Peak memory 257364 kb
Host smart-5764fe62-7530-43b1-ab76-ab2f271153f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620557158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2620557158
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.773337172
Short name T859
Test name
Test status
Simulation time 63596947 ps
CPU time 2.2 seconds
Started Aug 13 04:30:54 PM PDT 24
Finished Aug 13 04:30:57 PM PDT 24
Peak memory 233116 kb
Host smart-eae6cc00-f3fb-4b3e-93fc-88411ff97600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773337172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.773337172
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2295177404
Short name T398
Test name
Test status
Simulation time 27150130495 ps
CPU time 59.9 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:32:08 PM PDT 24
Peak memory 235044 kb
Host smart-b794c5aa-8ffc-4801-818e-b5be19f3c5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295177404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2295177404
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1991399142
Short name T202
Test name
Test status
Simulation time 55365776517 ps
CPU time 18.47 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:24 PM PDT 24
Peak memory 225420 kb
Host smart-2cb344cd-5f39-4375-8503-99875b89efd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991399142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1991399142
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2479029147
Short name T620
Test name
Test status
Simulation time 4082136405 ps
CPU time 5.7 seconds
Started Aug 13 04:31:16 PM PDT 24
Finished Aug 13 04:31:22 PM PDT 24
Peak memory 233572 kb
Host smart-74f95448-cdbf-4836-915a-3683186d8778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479029147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2479029147
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2389971878
Short name T835
Test name
Test status
Simulation time 334295163 ps
CPU time 4.84 seconds
Started Aug 13 04:31:21 PM PDT 24
Finished Aug 13 04:31:31 PM PDT 24
Peak memory 219632 kb
Host smart-4ad38402-e73f-47ee-ae4a-7c313f712e73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2389971878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2389971878
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3604867831
Short name T167
Test name
Test status
Simulation time 128330691469 ps
CPU time 610.15 seconds
Started Aug 13 04:31:03 PM PDT 24
Finished Aug 13 04:41:14 PM PDT 24
Peak memory 267916 kb
Host smart-9f093b0f-94ec-403d-ba51-36c859fcb64c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604867831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3604867831
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2381356876
Short name T435
Test name
Test status
Simulation time 13283531752 ps
CPU time 18.69 seconds
Started Aug 13 04:30:58 PM PDT 24
Finished Aug 13 04:31:17 PM PDT 24
Peak memory 217168 kb
Host smart-3e59d24d-8ae6-419d-a0ed-cc5ccb3a65a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381356876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2381356876
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.12741740
Short name T450
Test name
Test status
Simulation time 9225065640 ps
CPU time 4.32 seconds
Started Aug 13 04:31:04 PM PDT 24
Finished Aug 13 04:31:08 PM PDT 24
Peak memory 217224 kb
Host smart-2a006b2b-e31c-418c-a527-5460b3a966a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12741740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.12741740
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3325894398
Short name T624
Test name
Test status
Simulation time 31367244 ps
CPU time 0.7 seconds
Started Aug 13 04:31:06 PM PDT 24
Finished Aug 13 04:31:07 PM PDT 24
Peak memory 206336 kb
Host smart-6055430a-1f03-4941-ac6b-addd872c0b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325894398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3325894398
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2184009082
Short name T615
Test name
Test status
Simulation time 126352572 ps
CPU time 0.85 seconds
Started Aug 13 04:31:23 PM PDT 24
Finished Aug 13 04:31:24 PM PDT 24
Peak memory 206976 kb
Host smart-c0c19e15-dca6-4bba-9409-ff97411fdffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184009082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2184009082
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2302907286
Short name T695
Test name
Test status
Simulation time 16450868914 ps
CPU time 11.91 seconds
Started Aug 13 04:30:59 PM PDT 24
Finished Aug 13 04:31:12 PM PDT 24
Peak memory 225336 kb
Host smart-144d2c7f-d237-4852-bcaf-1c6b8224d5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302907286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2302907286
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.534986838
Short name T725
Test name
Test status
Simulation time 16410938 ps
CPU time 0.74 seconds
Started Aug 13 04:31:07 PM PDT 24
Finished Aug 13 04:31:08 PM PDT 24
Peak memory 206112 kb
Host smart-cd3ee124-94c7-42ae-abae-97658d68a750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534986838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.534986838
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.68458984
Short name T189
Test name
Test status
Simulation time 516347125 ps
CPU time 3.44 seconds
Started Aug 13 04:31:29 PM PDT 24
Finished Aug 13 04:31:32 PM PDT 24
Peak memory 225236 kb
Host smart-e2b24c15-e267-4605-95aa-a3a9478640a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68458984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.68458984
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1452631531
Short name T612
Test name
Test status
Simulation time 43597702 ps
CPU time 0.77 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:06 PM PDT 24
Peak memory 207656 kb
Host smart-623347f4-f689-4919-a64b-d3a2ea6df506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452631531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1452631531
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2546903189
Short name T522
Test name
Test status
Simulation time 43689177307 ps
CPU time 74.57 seconds
Started Aug 13 04:31:23 PM PDT 24
Finished Aug 13 04:32:38 PM PDT 24
Peak memory 253376 kb
Host smart-43c97751-067e-4dc9-8877-79f919b0287a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546903189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2546903189
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.499290499
Short name T891
Test name
Test status
Simulation time 2979952412 ps
CPU time 45.89 seconds
Started Aug 13 04:31:11 PM PDT 24
Finished Aug 13 04:31:57 PM PDT 24
Peak memory 253764 kb
Host smart-7888d909-d223-405c-9064-c273a426f716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499290499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
499290499
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3051377972
Short name T746
Test name
Test status
Simulation time 477066437 ps
CPU time 4.37 seconds
Started Aug 13 04:31:19 PM PDT 24
Finished Aug 13 04:31:23 PM PDT 24
Peak memory 233444 kb
Host smart-29dcd6a4-eab0-494d-a635-fd9e90fc8a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051377972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3051377972
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2310288724
Short name T124
Test name
Test status
Simulation time 2064752329 ps
CPU time 50.95 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:56 PM PDT 24
Peak memory 252388 kb
Host smart-f5bf764a-aac3-4f1b-8634-b44f91501f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310288724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2310288724
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.72692313
Short name T439
Test name
Test status
Simulation time 2882629865 ps
CPU time 15.47 seconds
Started Aug 13 04:31:03 PM PDT 24
Finished Aug 13 04:31:19 PM PDT 24
Peak memory 233532 kb
Host smart-4b407cef-52d6-4c8a-a825-5983b601eff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72692313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.72692313
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.4108724736
Short name T609
Test name
Test status
Simulation time 1526164338 ps
CPU time 11.16 seconds
Started Aug 13 04:31:20 PM PDT 24
Finished Aug 13 04:31:36 PM PDT 24
Peak memory 233436 kb
Host smart-ecfcc7e3-2396-46a2-b117-58ee97832b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108724736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.4108724736
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2919749015
Short name T54
Test name
Test status
Simulation time 4294615658 ps
CPU time 5.5 seconds
Started Aug 13 04:31:15 PM PDT 24
Finished Aug 13 04:31:20 PM PDT 24
Peak memory 225348 kb
Host smart-89c2004d-8fd1-489b-848c-3d65b187f708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919749015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2919749015
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2375053304
Short name T850
Test name
Test status
Simulation time 4557026156 ps
CPU time 5.59 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:11 PM PDT 24
Peak memory 233524 kb
Host smart-e768ae4d-e7d7-4eb8-b7c2-965d3231fc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375053304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2375053304
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2517333613
Short name T699
Test name
Test status
Simulation time 2743285209 ps
CPU time 9.79 seconds
Started Aug 13 04:31:07 PM PDT 24
Finished Aug 13 04:31:17 PM PDT 24
Peak memory 224160 kb
Host smart-5bcd299d-b558-499d-86aa-2a74fee682b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2517333613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2517333613
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2163720784
Short name T134
Test name
Test status
Simulation time 52122617310 ps
CPU time 270.11 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:35:38 PM PDT 24
Peak memory 264676 kb
Host smart-437b55a3-131e-432b-9a04-3dc354b38b5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163720784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2163720784
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.471456166
Short name T38
Test name
Test status
Simulation time 6583626654 ps
CPU time 18.09 seconds
Started Aug 13 04:31:06 PM PDT 24
Finished Aug 13 04:31:24 PM PDT 24
Peak memory 217140 kb
Host smart-1b04c0c0-087c-4ed7-9288-68e2000a611b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471456166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.471456166
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1608394881
Short name T30
Test name
Test status
Simulation time 3901905567 ps
CPU time 13.23 seconds
Started Aug 13 04:31:01 PM PDT 24
Finished Aug 13 04:31:15 PM PDT 24
Peak memory 217208 kb
Host smart-fbaead05-2c23-4a59-bb90-47d447318e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608394881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1608394881
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1256581270
Short name T588
Test name
Test status
Simulation time 16613831 ps
CPU time 0.82 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:06 PM PDT 24
Peak memory 207368 kb
Host smart-0799f026-736b-4ba6-9a9e-7364b34915ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256581270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1256581270
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1732619168
Short name T971
Test name
Test status
Simulation time 134836807 ps
CPU time 0.85 seconds
Started Aug 13 04:31:10 PM PDT 24
Finished Aug 13 04:31:11 PM PDT 24
Peak memory 207740 kb
Host smart-0d854e33-b792-4aca-86df-205214d1bf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732619168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1732619168
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2109620261
Short name T277
Test name
Test status
Simulation time 1903606713 ps
CPU time 5.69 seconds
Started Aug 13 04:31:07 PM PDT 24
Finished Aug 13 04:31:13 PM PDT 24
Peak memory 225212 kb
Host smart-7dd6b67f-681a-45ac-b17b-d3f0ea6be01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109620261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2109620261
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3701739840
Short name T448
Test name
Test status
Simulation time 53958864 ps
CPU time 0.75 seconds
Started Aug 13 04:31:17 PM PDT 24
Finished Aug 13 04:31:18 PM PDT 24
Peak memory 205564 kb
Host smart-4dc1ef91-af68-4507-a7d4-3e12c9fd7fcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701739840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
701739840
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1600891907
Short name T505
Test name
Test status
Simulation time 52802227 ps
CPU time 2.42 seconds
Started Aug 13 04:31:07 PM PDT 24
Finished Aug 13 04:31:10 PM PDT 24
Peak memory 233252 kb
Host smart-4c771033-ab94-45b4-8aa4-b3f11917d29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600891907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1600891907
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.759446990
Short name T639
Test name
Test status
Simulation time 48098344 ps
CPU time 0.81 seconds
Started Aug 13 04:31:06 PM PDT 24
Finished Aug 13 04:31:07 PM PDT 24
Peak memory 207224 kb
Host smart-67229406-d155-407b-8287-f44cf7b9b4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759446990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.759446990
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.492822874
Short name T645
Test name
Test status
Simulation time 2117668514 ps
CPU time 8.08 seconds
Started Aug 13 04:31:14 PM PDT 24
Finished Aug 13 04:31:22 PM PDT 24
Peak memory 249848 kb
Host smart-52bd3fed-b6e4-4283-a95d-b05b6db06b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492822874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.492822874
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2022408430
Short name T628
Test name
Test status
Simulation time 7268757464 ps
CPU time 46.8 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:31:55 PM PDT 24
Peak memory 225420 kb
Host smart-0a965255-ff64-465c-aff8-16243323178c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022408430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2022408430
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4052421954
Short name T248
Test name
Test status
Simulation time 23904538867 ps
CPU time 174.31 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:33:59 PM PDT 24
Peak memory 256832 kb
Host smart-44250138-a49f-4ccb-8424-bacbf6fce9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052421954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4052421954
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2707334603
Short name T508
Test name
Test status
Simulation time 53571816 ps
CPU time 2.69 seconds
Started Aug 13 04:31:22 PM PDT 24
Finished Aug 13 04:31:25 PM PDT 24
Peak memory 233480 kb
Host smart-26254c38-f7b2-4dc8-b22d-1af607fb1aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707334603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2707334603
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1695339335
Short name T594
Test name
Test status
Simulation time 817941490 ps
CPU time 6 seconds
Started Aug 13 04:31:21 PM PDT 24
Finished Aug 13 04:31:27 PM PDT 24
Peak memory 233476 kb
Host smart-b93d47a4-94b6-455d-b9fe-b9428e4c2334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695339335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1695339335
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3829833346
Short name T653
Test name
Test status
Simulation time 7373179044 ps
CPU time 27.18 seconds
Started Aug 13 04:31:22 PM PDT 24
Finished Aug 13 04:31:49 PM PDT 24
Peak memory 233616 kb
Host smart-9915152f-47de-4b31-8f77-82f2e4a5a0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829833346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3829833346
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2688692990
Short name T284
Test name
Test status
Simulation time 678848430 ps
CPU time 6.02 seconds
Started Aug 13 04:31:09 PM PDT 24
Finished Aug 13 04:31:15 PM PDT 24
Peak memory 225152 kb
Host smart-7b87aa64-3d64-4cab-b55c-edbbc4a469ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688692990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2688692990
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3006026893
Short name T684
Test name
Test status
Simulation time 246302367 ps
CPU time 4.06 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:31:12 PM PDT 24
Peak memory 225152 kb
Host smart-b417c072-37f3-4c8f-aa38-ee4c78dc4377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006026893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3006026893
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.797758551
Short name T536
Test name
Test status
Simulation time 198533492 ps
CPU time 3.66 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:09 PM PDT 24
Peak memory 221204 kb
Host smart-b8516803-f0e7-41b1-94c2-45d19b17ab56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=797758551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.797758551
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3259539467
Short name T155
Test name
Test status
Simulation time 19852919174 ps
CPU time 47.95 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:31:57 PM PDT 24
Peak memory 238792 kb
Host smart-8973da7c-940b-4b7b-8a96-fc817423e6fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259539467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3259539467
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1886960459
Short name T822
Test name
Test status
Simulation time 2518175301 ps
CPU time 13.97 seconds
Started Aug 13 04:31:22 PM PDT 24
Finished Aug 13 04:31:36 PM PDT 24
Peak memory 217148 kb
Host smart-9bf11b0f-acbe-4247-9002-2cd540e09757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886960459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1886960459
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1342850328
Short name T558
Test name
Test status
Simulation time 37195852464 ps
CPU time 6.64 seconds
Started Aug 13 04:31:08 PM PDT 24
Finished Aug 13 04:31:15 PM PDT 24
Peak memory 217168 kb
Host smart-419fdded-e20b-43b6-8957-8a86957cebaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342850328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1342850328
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3133284619
Short name T692
Test name
Test status
Simulation time 446220312 ps
CPU time 1.88 seconds
Started Aug 13 04:31:07 PM PDT 24
Finished Aug 13 04:31:09 PM PDT 24
Peak memory 216956 kb
Host smart-5d855816-5fcc-4454-a51b-cdf7d4156d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133284619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3133284619
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2775929513
Short name T562
Test name
Test status
Simulation time 252837491 ps
CPU time 1.02 seconds
Started Aug 13 04:31:03 PM PDT 24
Finished Aug 13 04:31:05 PM PDT 24
Peak memory 207708 kb
Host smart-6ae236b9-a777-4b1b-8e26-4e740ae19bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775929513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2775929513
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3693531769
Short name T526
Test name
Test status
Simulation time 163526293 ps
CPU time 2.53 seconds
Started Aug 13 04:31:05 PM PDT 24
Finished Aug 13 04:31:07 PM PDT 24
Peak memory 225264 kb
Host smart-ce299308-278d-4c0b-8c53-a08121351599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693531769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3693531769
Directory /workspace/9.spi_device_upload/latest
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