Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2492674	1			T1	535		T2	10		T3	761
all_values[1]	2492674	1			T1	535		T2	10		T3	761
all_values[2]	2492674	1			T1	535		T2	10		T3	761
all_values[3]	2492674	1			T1	535		T2	10		T3	761
all_values[4]	2492674	1			T1	535		T2	10		T3	761
all_values[5]	2492674	1			T1	535		T2	10		T3	761
all_values[6]	2492674	1			T1	535		T2	10		T3	761
all_values[7]	2492674	1			T1	535		T2	10		T3	761

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18681909

1

T1

4280

T2

80

T3

6088

auto[1]

1259483

1

T15

9471

T17

42

T18

118

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19917024

1

T1

4280

T2

80

T3

6088

auto[1]

24368

1

T14

486

T31

117

T56

58

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2420096	1			T1	535		T2	10		T3	761
all_values[0]	auto[0]	auto[1]	11334	1			T14	271		T31	60		T56	29
all_values[0]	auto[1]	auto[0]	60773	1			T15	3029		T17	2		T18	8
all_values[0]	auto[1]	auto[1]	471	1			T15	125		T17	6		T18	4
all_values[1]	auto[0]	auto[0]	2325456	1			T1	535		T2	10		T3	761
all_values[1]	auto[0]	auto[1]	7491	1			T14	148		T31	50		T56	29
all_values[1]	auto[1]	auto[0]	159303	1			T15	3072		T17	3		T18	7
all_values[1]	auto[1]	auto[1]	424	1			T15	81		T17	1		T18	14
all_values[2]	auto[0]	auto[0]	2263075	1			T1	535		T2	10		T3	761
all_values[2]	auto[0]	auto[1]	2626	1			T14	67		T31	7		T57	29
all_values[2]	auto[1]	auto[0]	226736	1			T15	2		T17	4		T18	10
all_values[2]	auto[1]	auto[1]	237	1			T17	4		T18	10		T20	1
all_values[3]	auto[0]	auto[0]	2439893	1			T1	535		T2	10		T3	761
all_values[3]	auto[0]	auto[1]	190	1			T15	7		T17	3		T18	9
all_values[3]	auto[1]	auto[0]	52412	1			T17	2		T18	5		T22	2
all_values[3]	auto[1]	auto[1]	179	1			T15	1		T17	2		T18	4
all_values[4]	auto[0]	auto[0]	2200785	1			T1	535		T2	10		T3	761
all_values[4]	auto[0]	auto[1]	174	1			T15	1		T17	3		T18	9
all_values[4]	auto[1]	auto[0]	291532	1			T15	3149		T17	5		T18	6
all_values[4]	auto[1]	auto[1]	183	1			T15	5		T17	1		T18	2
all_values[5]	auto[0]	auto[0]	2379890	1			T1	535		T2	10		T3	761
all_values[5]	auto[0]	auto[1]	172	1			T15	2		T17	2		T18	7
all_values[5]	auto[1]	auto[0]	112465	1			T15	1		T18	12		T20	2
all_values[5]	auto[1]	auto[1]	147	1			T15	1		T17	2		T18	4
all_values[6]	auto[0]	auto[0]	2260507	1			T1	535		T2	10		T3	761
all_values[6]	auto[0]	auto[1]	186	1			T17	3		T18	5		T20	1
all_values[6]	auto[1]	auto[0]	231800	1			T15	2		T17	1		T18	11
all_values[6]	auto[1]	auto[1]	181	1			T15	1		T17	4		T18	4
all_values[7]	auto[0]	auto[0]	2369838	1			T1	535		T2	10		T3	761
all_values[7]	auto[0]	auto[1]	196	1			T15	2		T17	1		T18	6
all_values[7]	auto[1]	auto[0]	122463	1			T15	2		T17	3		T18	6
all_values[7]	auto[1]	auto[1]	177	1			T17	2		T18	11		T21	1