Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34682	1			T1	74		T3	6		T4	4
auto[SpiFlashAddrCfg]	7903	1			T1	4		T3	8		T9	32
auto[SpiFlashAddr3b]	9242	1			T1	10		T4	14		T5	6
auto[SpiFlashAddr4b]	7745	1			T3	6		T4	4		T9	32

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33730

1

T1

88

T3

20

T5

8

auto[1]

25842

1

T4

22

T9

79

T14

133

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31544

1

T1

2

T3

12

T4

18

auto[1]

28028

1

T1

86

T3

8

T4

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39366	1			T1	78		T3	6		T4	14
values[1]	1097	1			T5	4		T9	4		T14	4
values[2]	1493	1			T9	1		T14	17		T44	9
values[3]	1465	1			T1	2		T3	2		T9	3
values[4]	1461	1			T3	2		T9	3		T14	4
values[5]	1542	1			T1	2		T9	6		T14	8
values[6]	1493	1			T3	2		T9	11		T14	16
values[7]	1511	1			T1	4		T9	7		T14	19
values[8]	10144	1			T1	2		T3	8		T4	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33316

1

T1

88

T3

20

T4

22

auto[1]

26256

1

T9

160

T10

3

T50

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56145

1

T1

84

T3

20

T4

12

write

3427

1

T1

4

T4

10

T9

14

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19605

1

T1

6

T3

14

T4

8

valids[0x1]

39967

1

T1

82

T3

6

T4

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1618	1			T3	4		T9	8		T14	8
internal_process_ops[0x5a]	1596	1			T9	8		T14	10		T44	6
internal_process_ops[0x05]	20343	1			T1	70		T9	2		T14	51
internal_process_ops[0x35]	1589	1			T9	5		T11	2		T14	11
internal_process_ops[0x15]	1592	1			T4	4		T5	2		T9	4
internal_process_ops[0x03]	1089	1			T9	2		T14	5		T44	4
internal_process_ops[0x0b]	1049	1			T1	2		T5	2		T9	3
internal_process_ops[0x3b]	1109	1			T3	2		T9	1		T14	9
internal_process_ops[0x6b]	1054	1			T13	2		T14	13		T44	6
internal_process_ops[0xbb]	1065	1			T3	4		T9	2		T10	1
internal_process_ops[0xeb]	1109	1			T3	2		T4	2		T14	8

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57918

1

T1

88

T3

20

T4

12

auto[1]

1654

1

T4

10

T9

2

T14

10

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57153

1

T1

82

T3

20

T4

22

auto[1]

2419

1

T1

6

T9

9

T14

19

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11712

1

T1

74

T3

6

T5

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6735

1

T4

4

T14

46

T53

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2158

1

T3

8

T14

29

T52

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1992

1

T14

16

T44

15

T55

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2661

1

T1

10

T5

6

T13

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2204

1

T4

6

T14

43

T44

30

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2186

1

T3

6

T14

37

T44

9

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1906

1

T4

2

T14

22

T44

9

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

127

1

T14

2

T43

2

T58

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

106

1

T14

4

T55

1

T31

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

119

1

T14

1

T44

1

T31

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

128

1

T14

1

T55

2

T56

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

135

1

T1

4

T44

1

T31

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

87

1

T14

1

T44

1

T57

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

85

1

T44

2

T31

1

T56

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

103

1

T44

1

T57

1

T43

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

127

1

T14

2

T44

1

T31

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

103

1

T44

1

T31

1

T56

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

101

1

T44

1

T54

1

T58

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

115

1

T4

8

T44

1

T31

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

141

1

T44

3

T31

2

T56

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

115

1

T14

1

T57

2

T43

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

89

1

T14

1

T56

4

T43

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

81

1

T4

2

T14

3

T56

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8560

1

T9

34

T51

21

T48

60

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6774

1

T9

19

T51

11

T48

175

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1481

1

T9

9

T50

4

T51

7

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1423

1

T9

21

T51

6

T48

27

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1790

1

T9

20

T51

1

T48

25

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1726

1

T9

12

T51

3

T48

28

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1394

1

T9

11

T10

3

T50

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1443

1

T9

20

T51

3

T48

19

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

112

1

T9

4

T51

1

T48

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

118

1

T51

1

T48

1

T181

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

102

1

T48

1

T49

1

T181

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

89

1

T48

1

T49

2

T15

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

121

1

T49

1

T181

1

T59

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

89

1

T9

1

T48

1

T95

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

116

1

T9

1

T48

2

T181

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

113

1

T48

2

T49

4

T181

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

113

1

T95

1

T181

2

T15

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

96

1

T9

1

T51

1

T95

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

105

1

T9

6

T48

1

T181

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

101

1

T95

3

T59

2

T15

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

98

1

T9

1

T15

4

T24

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

100

1

T181

2

T59

1

T15

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

82

1

T48

3

T49

3

T59

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

110

1

T51

1

T15

1

T25

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4200	1			T1	2		T3	2		T14	68
auto[0]	values[0]	valids[0x1]	17269	1			T1	76		T3	4		T4	14
auto[0]	values[1]	valids[0x1]	591	1			T5	4		T14	4		T44	6
auto[0]	values[2]	valids[0x0]	549	1			T14	13		T44	6		T55	3
auto[0]	values[2]	valids[0x1]	348	1			T14	4		T44	3		T55	3
auto[0]	values[3]	valids[0x0]	581	1			T3	2		T14	3		T44	11
auto[0]	values[3]	valids[0x1]	332	1			T1	2		T14	6		T44	4
auto[0]	values[4]	valids[0x0]	536	1			T3	2		T14	2		T44	7
auto[0]	values[4]	valids[0x1]	323	1			T14	2		T55	1		T31	2
auto[0]	values[5]	valids[0x0]	556	1			T14	3		T52	2		T44	2
auto[0]	values[5]	valids[0x1]	350	1			T1	2		T14	5		T182	2
auto[0]	values[6]	valids[0x0]	560	1			T3	2		T14	14		T44	1
auto[0]	values[6]	valids[0x1]	327	1			T14	2		T44	3		T55	2
auto[0]	values[7]	valids[0x0]	572	1			T1	4		T14	17		T44	1
auto[0]	values[7]	valids[0x1]	320	1			T14	2		T44	1		T55	1
auto[0]	values[8]	valids[0x0]	3727	1			T3	6		T4	8		T13	2
auto[0]	values[8]	valids[0x1]	2175	1			T1	2		T3	2		T5	2
auto[1]	values[0]	valids[0x0]	3738	1			T9	33		T51	8		T48	49
auto[1]	values[0]	valids[0x1]	14159	1			T9	44		T10	2		T51	26
auto[1]	values[1]	valids[0x1]	506	1			T9	4		T51	5		T48	5
auto[1]	values[2]	valids[0x0]	354	1			T51	4		T48	6		T49	5
auto[1]	values[2]	valids[0x1]	242	1			T9	1		T48	1		T95	1
auto[1]	values[3]	valids[0x0]	302	1			T9	2		T50	2		T48	3
auto[1]	values[3]	valids[0x1]	250	1			T9	1		T48	6		T95	1
auto[1]	values[4]	valids[0x0]	378	1			T9	3		T51	2		T48	8
auto[1]	values[4]	valids[0x1]	224	1			T51	1		T48	4		T49	5
auto[1]	values[5]	valids[0x0]	375	1			T9	5		T51	1		T48	9
auto[1]	values[5]	valids[0x1]	261	1			T9	1		T51	1		T48	6
auto[1]	values[6]	valids[0x0]	362	1			T9	2		T48	8		T49	7
auto[1]	values[6]	valids[0x1]	244	1			T9	9		T48	2		T49	3
auto[1]	values[7]	valids[0x0]	389	1			T9	2		T48	7		T49	5
auto[1]	values[7]	valids[0x1]	230	1			T9	5		T48	1		T95	5
auto[1]	values[8]	valids[0x0]	2426	1			T9	29		T10	1		T50	1
auto[1]	values[8]	valids[0x1]	1816	1			T9	19		T50	2		T51	1