Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3378673

1

T1

13

T2

1

T3

1

auto[1]

28526

1

T1

70

T9

173

T14

40

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

915144

1

T1

13

T2

1

T3

1

auto[1]

2492055

1

T1

70

T5

6

T9

2190

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	578741	1			T1	83		T2	1		T3	1
auto[524288:1048575]	393262	1			T7	1269		T9	850		T10	324
auto[1048576:1572863]	411934	1			T7	4758		T9	24		T11	892
auto[1572864:2097151]	366383	1			T9	600		T10	1		T11	2151
auto[2097152:2621439]	429011	1			T7	2760		T9	32		T11	3296
auto[2621440:3145727]	459564	1			T7	3		T9	27		T10	536
auto[3145728:3670015]	363944	1			T9	38		T11	1		T14	7463
auto[3670016:4194303]	404360	1			T7	260		T9	957		T10	2

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2527847

1

T1

77

T2

1

T3

1

auto[1]

879352

1

T1

6

T7

9039

T9

5

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2954208

1

T1

83

T2

1

T3

1

auto[1]

452991

1

T9

224

T14

5941

T44

520

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	159087	1			T1	7		T2	1		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	334891	1			T1	6		T5	6		T11	211
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	95508	1			T7	1269		T9	44		T10	324
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	253476	1			T9	649		T11	2831		T14	2882
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	129936	1			T7	4758		T9	24		T11	892
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	221757	1			T14	2		T52	514		T44	1278
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	101851	1			T9	70		T10	1		T11	2150
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	211350	1			T9	512		T11	1		T14	1024
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	108720	1			T7	2760		T11	265		T14	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	270274	1			T11	3031		T14	953		T52	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	125233	1			T7	3		T9	19		T10	536
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	263834	1			T9	5		T14	824		T52	258
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	103563	1			T9	33		T11	1		T14	22
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	203176	1			T14	6916		T52	258		T44	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	77691	1			T7	260		T9	32		T10	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	270333	1			T9	768		T14	388		T52	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	1617	1			T9	13		T14	6		T55	12
auto[0]	auto[1]	auto[0:524287]	auto[1]	78930	1			T14	768		T31	119		T56	512
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	707	1			T9	6		T31	2		T43	8
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	39374	1			T31	4250		T43	181		T49	513
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1427	1			T57	5		T43	7		T48	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	55551	1			T14	984		T57	257		T43	1431
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1156	1			T9	7		T14	1		T55	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	48909	1			T14	1		T57	128		T43	647
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	894	1			T9	29		T14	2		T57	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	45397	1			T14	3395		T49	512		T95	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2402	1			T9	3		T44	1		T55	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	65612	1			T44	519		T31	256		T57	518
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	744	1			T14	2		T55	11		T57	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	52606	1			T14	513		T55	256		T56	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	603	1			T9	26		T14	3		T55	24
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	52064	1			T9	128		T14	257		T56	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	523	1			T1	6		T44	3		T31	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3096	1			T1	64		T44	39		T31	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	413	1			T9	23		T44	1		T31	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3434	1			T9	128		T44	14		T57	31
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	337	1			T14	2		T57	3		T43	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2099	1			T57	12		T43	8		T95	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	346	1			T9	5		T44	1		T56	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1975	1			T44	17		T56	12		T48	31
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	448	1			T14	1		T44	1		T56	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2400	1			T44	44		T56	35		T43	57
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	378	1			T14	4		T44	2		T31	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1638	1			T14	6		T44	14		T31	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	360	1			T9	5		T14	5		T44	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2830	1			T14	4		T44	6		T56	13
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	374	1			T14	4		T44	1		T31	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2877	1			T14	5		T44	1		T31	3
auto[1]	auto[1]	auto[0:524287]	auto[0]	100	1			T55	7		T31	1		T43	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	497	1			T48	9		T181	136		T23	11
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	83	1			T43	4		T49	1		T15	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	267	1			T43	25		T49	3		T15	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	136	1			T57	1		T43	1		T95	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	691	1			T57	6		T43	36		T95	5
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	79	1			T9	6		T14	1		T43	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	717	1			T14	3		T43	16		T48	51
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	135	1			T9	3		T95	4		T59	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	743	1			T95	6		T59	3		T23	78
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	124	1			T57	1		T43	3		T59	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	343	1			T59	4		T15	5		T201	20
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	74	1			T14	1		T24	1		T240	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	591	1			T24	1		T204	26		T241	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	95	1			T9	3		T14	1		T55	9
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	323	1			T14	3		T56	9		T59	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2056525	1			T1	12		T2	1		T3	1
auto[0]	auto[0]	auto[1]	874155	1			T1	1		T7	9039		T10	6394
auto[0]	auto[1]	auto[0]	443531	1			T9	212		T14	5932		T44	520
auto[0]	auto[1]	auto[1]	4462	1			T56	1		T43	2		T48	1
auto[1]	auto[0]	auto[0]	22932	1			T1	65		T9	158		T14	31
auto[1]	auto[0]	auto[1]	596	1			T1	5		T9	3		T44	1
auto[1]	auto[1]	auto[0]	4859	1			T9	10		T14	9		T55	14
auto[1]	auto[1]	auto[1]	139	1			T9	2		T55	2		T56	2