Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2492674	1			T1	535		T2	10		T3	761
all_pins[1]	2492674	1			T1	535		T2	10		T3	761
all_pins[2]	2492674	1			T1	535		T2	10		T3	761
all_pins[3]	2492674	1			T1	535		T2	10		T3	761
all_pins[4]	2492674	1			T1	535		T2	10		T3	761
all_pins[5]	2492674	1			T1	535		T2	10		T3	761
all_pins[6]	2492674	1			T1	535		T2	10		T3	761
all_pins[7]	2492674	1			T1	535		T2	10		T3	761

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19711707	1			T1	4280		T2	80		T3	6088
values[0x1]	229685	1			T15	238		T17	22		T18	53
transitions[0x0=>0x1]	228207	1			T15	149		T17	21		T18	40
transitions[0x1=>0x0]	228225	1			T15	149		T17	21		T18	40

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2492158	1			T1	535		T2	10		T3	761
all_pins[0]	values[0x1]	516	1			T15	139		T17	6		T18	4
all_pins[0]	transitions[0x0=>0x1]	316	1			T15	51		T17	5		T18	2
all_pins[0]	transitions[0x1=>0x0]	269	1			T15	3		T18	12		T21	3
all_pins[1]	values[0x0]	2492205	1			T1	535		T2	10		T3	761
all_pins[1]	values[0x1]	469	1			T15	91		T17	1		T18	14
all_pins[1]	transitions[0x0=>0x1]	385	1			T15	91		T17	1		T18	8
all_pins[1]	transitions[0x1=>0x0]	161	1			T17	4		T18	4		T20	1
all_pins[2]	values[0x0]	2492429	1			T1	535		T2	10		T3	761
all_pins[2]	values[0x1]	245	1			T17	4		T18	10		T20	1
all_pins[2]	transitions[0x0=>0x1]	195	1			T17	4		T18	7		T21	1
all_pins[2]	transitions[0x1=>0x0]	129	1			T15	1		T17	2		T18	1
all_pins[3]	values[0x0]	2492495	1			T1	535		T2	10		T3	761
all_pins[3]	values[0x1]	179	1			T15	1		T17	2		T18	4
all_pins[3]	transitions[0x0=>0x1]	141	1			T17	2		T18	4		T20	1
all_pins[3]	transitions[0x1=>0x0]	145	1			T15	4		T17	1		T18	2
all_pins[4]	values[0x0]	2492491	1			T1	535		T2	10		T3	761
all_pins[4]	values[0x1]	183	1			T15	5		T17	1		T18	2
all_pins[4]	transitions[0x0=>0x1]	146	1			T15	5		T17	1		T18	2
all_pins[4]	transitions[0x1=>0x0]	1485	1			T15	1		T17	2		T18	4
all_pins[5]	values[0x0]	2491152	1			T1	535		T2	10		T3	761
all_pins[5]	values[0x1]	1522	1			T15	1		T17	2		T18	4
all_pins[5]	transitions[0x0=>0x1]	550	1			T15	1		T17	2		T18	4
all_pins[5]	transitions[0x1=>0x0]	225422	1			T15	1		T17	4		T18	4
all_pins[6]	values[0x0]	2266280	1			T1	535		T2	10		T3	761
all_pins[6]	values[0x1]	226394	1			T15	1		T17	4		T18	4
all_pins[6]	transitions[0x0=>0x1]	226355	1			T15	1		T17	4		T18	3
all_pins[6]	transitions[0x1=>0x0]	138	1			T17	2		T18	10		T21	1
all_pins[7]	values[0x0]	2492497	1			T1	535		T2	10		T3	761
all_pins[7]	values[0x1]	177	1			T17	2		T18	11		T21	1
all_pins[7]	transitions[0x0=>0x1]	119	1			T17	2		T18	10		T21	1
all_pins[7]	transitions[0x1=>0x0]	476	1			T15	139		T17	6		T18	3