Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19658

1

T1

88

T3

20

T5

8

auto[1]

13658

1

T4

22

T14

133

T53

10

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4052	1			T11	4		T14	48		T44	20
values[1]	3666	1			T14	72		T182	18		T56	38
values[2]	4449	1			T14	30		T44	38		T55	20
values[3]	4424	1			T1	88		T14	40		T44	35
values[4]	4149	1			T5	8		T14	28		T52	12
values[5]	3659	1			T14	41		T44	34		T55	20
values[6]	4426	1			T4	22		T13	2		T14	20
values[7]	4491	1			T3	20		T14	41		T44	25

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4083	1			T14	28		T44	40		T56	48
values[1]	4280	1			T13	2		T14	61		T44	59
values[2]	4276	1			T31	20		T56	32		T218	22
values[3]	4703	1			T4	22		T14	50		T44	96
values[4]	4337	1			T11	4		T14	48		T52	12
values[5]	4139	1			T3	20		T5	8		T14	68
values[6]	3874	1			T14	20		T53	10		T55	40
values[7]	3624	1			T1	88		T14	45		T44	38

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	249	1			T44	6		T58	41		T37	12
auto[0]	values[0]	values[1]	293	1			T222	10		T16	10		T242	2
auto[0]	values[0]	values[2]	352	1			T100	140		T149	15		T227	14
auto[0]	values[0]	values[3]	346	1			T45	19		T236	12		T237	6
auto[0]	values[0]	values[4]	168	1			T11	4		T14	9		T215	13
auto[0]	values[0]	values[5]	209	1			T177	11		T197	32		T99	15
auto[0]	values[0]	values[6]	467	1			T56	12		T43	8		T54	16
auto[0]	values[0]	values[7]	200	1			T14	13		T31	9		T37	15
auto[0]	values[1]	values[0]	146	1			T45	11		T207	11		T19	16
auto[0]	values[1]	values[1]	319	1			T14	12		T43	11		T54	10
auto[0]	values[1]	values[2]	369	1			T226	8		T88	40		T58	15
auto[0]	values[1]	values[3]	288	1			T56	28		T198	18		T243	8
auto[0]	values[1]	values[4]	250	1			T182	18		T207	11		T17	12
auto[0]	values[1]	values[5]	384	1			T14	25		T16	14		T236	14
auto[0]	values[1]	values[6]	166	1			T223	6		T149	25		T244	12
auto[0]	values[1]	values[7]	191	1			T14	10		T45	14		T16	13
auto[0]	values[2]	values[0]	455	1			T43	11		T58	142		T212	16
auto[0]	values[2]	values[1]	258	1			T55	15		T213	6		T140	8
auto[0]	values[2]	values[2]	224	1			T205	14		T197	48		T211	17
auto[0]	values[2]	values[3]	392	1			T14	14		T204	22		T144	11
auto[0]	values[2]	values[4]	475	1			T31	16		T43	9		T97	24
auto[0]	values[2]	values[5]	222	1			T45	11		T173	20		T19	16
auto[0]	values[2]	values[6]	309	1			T23	18		T176	12		T22	14
auto[0]	values[2]	values[7]	273	1			T44	28		T26	26		T207	13
auto[0]	values[3]	values[0]	197	1			T57	7		T58	22		T16	12
auto[0]	values[3]	values[1]	225	1			T14	11		T43	34		T45	14
auto[0]	values[3]	values[2]	733	1			T31	7		T43	12		T17	16
auto[0]	values[3]	values[3]	351	1			T57	13		T245	6		T23	8
auto[0]	values[3]	values[4]	306	1			T57	16		T43	18		T197	10
auto[0]	values[3]	values[5]	314	1			T44	12		T57	14		T23	12
auto[0]	values[3]	values[6]	270	1			T14	13		T56	34		T232	16
auto[0]	values[3]	values[7]	332	1			T1	88		T16	18		T204	8
auto[0]	values[4]	values[0]	339	1			T14	21		T23	72		T205	11
auto[0]	values[4]	values[1]	208	1			T58	41		T205	7		T83	2
auto[0]	values[4]	values[2]	219	1			T56	23		T58	9		T246	2
auto[0]	values[4]	values[3]	456	1			T23	7		T37	8		T19	12
auto[0]	values[4]	values[4]	445	1			T52	12		T56	11		T247	10
auto[0]	values[4]	values[5]	423	1			T5	8		T58	66		T16	11
auto[0]	values[4]	values[6]	191	1			T31	15		T17	8		T177	13
auto[0]	values[4]	values[7]	326	1			T23	13		T236	16		T179	12
auto[0]	values[5]	values[0]	499	1			T221	14		T204	15		T177	15
auto[0]	values[5]	values[1]	457	1			T14	8		T44	10		T54	128
auto[0]	values[5]	values[2]	188	1			T248	2		T236	7		T19	17
auto[0]	values[5]	values[3]	359	1			T55	8		T249	58		T17	24
auto[0]	values[5]	values[4]	225	1			T23	16		T140	15		T144	9
auto[0]	values[5]	values[5]	215	1			T14	12		T43	32		T204	38
auto[0]	values[5]	values[6]	158	1			T206	8		T228	10		T201	20
auto[0]	values[5]	values[7]	236	1			T197	11		T227	13		T202	9
auto[0]	values[6]	values[0]	444	1			T44	5		T56	36		T27	18
auto[0]	values[6]	values[1]	352	1			T13	2		T31	5		T228	13
auto[0]	values[6]	values[2]	188	1			T43	35		T16	10		T149	28
auto[0]	values[6]	values[3]	285	1			T44	14		T23	13		T204	14
auto[0]	values[6]	values[4]	239	1			T14	13		T44	8		T16	15
auto[0]	values[6]	values[5]	385	1			T56	15		T54	10		T250	10
auto[0]	values[6]	values[6]	302	1			T55	21		T31	21		T43	10
auto[0]	values[6]	values[7]	153	1			T43	7		T45	19		T149	14
auto[0]	values[7]	values[0]	354	1			T57	11		T251	6		T149	12
auto[0]	values[7]	values[1]	569	1			T44	12		T57	55		T23	211
auto[0]	values[7]	values[2]	351	1			T207	8		T252	4		T204	33
auto[0]	values[7]	values[3]	208	1			T14	15		T45	8		T207	10
auto[0]	values[7]	values[4]	356	1			T45	12		T37	7		T204	28
auto[0]	values[7]	values[5]	220	1			T3	20		T14	11		T45	14
auto[0]	values[7]	values[6]	274	1			T234	14		T45	12		T215	38
auto[0]	values[7]	values[7]	301	1			T43	32		T149	17		T253	13
auto[1]	values[0]	values[0]	193	1			T44	14		T58	11		T37	8
auto[1]	values[0]	values[1]	163	1			T16	10		T215	2		T254	20
auto[1]	values[0]	values[2]	148	1			T255	20		T149	5		T227	9
auto[1]	values[0]	values[3]	161	1			T45	21		T236	8		T140	4
auto[1]	values[0]	values[4]	252	1			T14	19		T215	7		T19	39
auto[1]	values[0]	values[5]	243	1			T177	9		T197	96		T256	20
auto[1]	values[0]	values[6]	335	1			T56	15		T43	73		T54	4
auto[1]	values[0]	values[7]	273	1			T14	7		T31	12		T37	25
auto[1]	values[1]	values[0]	92	1			T45	9		T207	9		T19	21
auto[1]	values[1]	values[1]	198	1			T14	9		T43	18		T54	10
auto[1]	values[1]	values[2]	350	1			T58	5		T225	4		T204	29
auto[1]	values[1]	values[3]	193	1			T56	10		T37	13		T196	8
auto[1]	values[1]	values[4]	134	1			T207	9		T17	17		T247	7
auto[1]	values[1]	values[5]	191	1			T14	1		T16	6		T236	13
auto[1]	values[1]	values[6]	140	1			T149	23		T244	9		T203	12
auto[1]	values[1]	values[7]	255	1			T14	15		T45	6		T16	8
auto[1]	values[2]	values[0]	211	1			T43	9		T58	11		T215	7
auto[1]	values[2]	values[1]	186	1			T55	5		T140	12		T149	9
auto[1]	values[2]	values[2]	107	1			T205	6		T257	8		T197	2
auto[1]	values[2]	values[3]	401	1			T14	16		T204	25		T144	9
auto[1]	values[2]	values[4]	414	1			T31	8		T43	20		T204	4
auto[1]	values[2]	values[5]	81	1			T45	9		T19	5		T168	7
auto[1]	values[2]	values[6]	208	1			T23	47		T22	6		T149	11
auto[1]	values[2]	values[7]	233	1			T44	10		T207	7		T201	7
auto[1]	values[3]	values[0]	83	1			T57	25		T58	7		T16	8
auto[1]	values[3]	values[1]	160	1			T14	9		T43	5		T45	6
auto[1]	values[3]	values[2]	257	1			T31	13		T43	10		T17	8
auto[1]	values[3]	values[3]	231	1			T57	10		T23	12		T37	4
auto[1]	values[3]	values[4]	314	1			T57	5		T43	57		T197	100
auto[1]	values[3]	values[5]	237	1			T44	23		T57	6		T23	18
auto[1]	values[3]	values[6]	220	1			T14	7		T56	8		T45	9
auto[1]	values[3]	values[7]	194	1			T16	6		T204	12		T201	17
auto[1]	values[4]	values[0]	152	1			T14	7		T23	7		T205	9
auto[1]	values[4]	values[1]	227	1			T58	12		T205	13		T149	12
auto[1]	values[4]	values[2]	134	1			T56	9		T58	11		T247	8
auto[1]	values[4]	values[3]	169	1			T23	13		T37	12		T19	8
auto[1]	values[4]	values[4]	211	1			T56	9		T247	20		T215	11
auto[1]	values[4]	values[5]	344	1			T58	14		T16	9		T23	9
auto[1]	values[4]	values[6]	141	1			T31	5		T17	18		T177	7
auto[1]	values[4]	values[7]	164	1			T23	7		T236	4		T197	20
auto[1]	values[5]	values[0]	207	1			T204	5		T177	5		T205	26
auto[1]	values[5]	values[1]	169	1			T14	12		T44	24		T54	1
auto[1]	values[5]	values[2]	316	1			T258	10		T236	16		T19	3
auto[1]	values[5]	values[3]	220	1			T55	12		T17	6		T19	41
auto[1]	values[5]	values[4]	113	1			T23	7		T140	17		T144	11
auto[1]	values[5]	values[5]	108	1			T14	9		T43	19		T204	7
auto[1]	values[5]	values[6]	73	1			T228	10		T201	15		T259	7
auto[1]	values[5]	values[7]	116	1			T197	9		T227	7		T202	11
auto[1]	values[6]	values[0]	261	1			T44	15		T56	12		T177	10
auto[1]	values[6]	values[1]	283	1			T31	15		T101	10		T228	7
auto[1]	values[6]	values[2]	130	1			T43	11		T16	11		T149	18
auto[1]	values[6]	values[3]	424	1			T4	22		T44	82		T23	7
auto[1]	values[6]	values[4]	200	1			T14	7		T44	29		T16	11
auto[1]	values[6]	values[5]	422	1			T56	5		T54	131		T140	16
auto[1]	values[6]	values[6]	210	1			T53	10		T55	19		T31	6
auto[1]	values[6]	values[7]	148	1			T43	15		T45	21		T149	6
auto[1]	values[7]	values[0]	201	1			T57	19		T149	28		T253	6
auto[1]	values[7]	values[1]	213	1			T44	13		T57	17		T23	9
auto[1]	values[7]	values[2]	210	1			T218	22		T207	12		T204	11
auto[1]	values[7]	values[3]	219	1			T14	5		T45	12		T207	10
auto[1]	values[7]	values[4]	235	1			T45	8		T37	13		T260	12
auto[1]	values[7]	values[5]	141	1			T14	10		T45	6		T140	6
auto[1]	values[7]	values[6]	410	1			T45	8		T215	4		T19	41
auto[1]	values[7]	values[7]	229	1			T43	5		T149	3		T253	7