Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	452	1			T14	5		T31	2		T56	2
auto[ReadAddrCrossIntoMailbox]	322	1			T14	3		T31	1		T56	2
auto[ReadAddrCrossOutOfMailbox]	321	1			T14	2		T44	2		T31	3
auto[ReadAddrCrossAllMailbox]	251	1			T14	3		T44	1		T31	3
auto[ReadAddrOutsideMailbox]	3665	1			T1	2		T3	8		T4	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2475

1

T1

1

T3

4

T4

1

auto[1]

2536

1

T1

1

T3

4

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	835	1			T14	5		T44	4		T55	5
read_ops[0x0b]	813	1			T1	2		T5	2		T14	8
read_ops[0x3b]	881	1			T3	2		T14	9		T44	4
read_ops[0x6b]	803	1			T13	2		T14	13		T44	6
read_ops[0xbb]	830	1			T3	4		T14	7		T52	2
read_ops[0xeb]	849	1			T3	2		T4	2		T14	8

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T54	1		T58	1		T232	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T56	1		T232	1		T17	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T56	1		T57	1		T23	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	39	1			T31	1		T56	1		T43	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T45	2		T17	1		T205	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T43	1		T45	2		T140	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T58	1		T23	2		T17	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T31	1		T45	2		T215	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	301	1			T14	1		T44	1		T55	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	314	1			T14	4		T44	3		T55	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T14	1		T31	1		T43	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T14	1		T57	1		T23	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T54	1		T236	1		T204	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T14	1		T57	1		T43	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T31	1		T56	1		T45	3
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T37	2		T17	1		T215	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T215	1		T19	1		T201	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T56	1		T45	1		T23	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	306	1			T1	1		T5	1		T14	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	300	1			T1	1		T5	1		T14	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T232	3		T23	2		T219	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T56	1		T43	1		T232	3
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T57	1		T204	1		T19	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T45	1		T19	1		T140	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T58	2		T45	1		T228	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T43	3		T58	1		T247	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T56	1		T37	1		T204	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T31	1		T57	1		T43	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	324	1			T3	1		T44	2		T55	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	307	1			T3	1		T14	9		T44	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T14	1		T58	1		T16	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T14	1		T31	1		T43	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T16	1		T236	1		T201	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T14	1		T43	1		T45	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T31	1		T56	1		T16	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T14	1		T57	1		T54	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T14	1		T58	1		T19	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T57	1		T236	2		T204	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	291	1			T13	1		T14	6		T44	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	294	1			T13	1		T14	2		T44	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T43	1		T54	1		T232	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T14	1		T232	4		T45	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T57	1		T58	1		T201	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T14	1		T43	1		T58	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T56	1		T204	1		T215	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T43	1		T58	1		T23	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T45	1		T17	2		T149	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T14	1		T45	1		T177	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	260	1			T3	2		T52	1		T44	4
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	324	1			T3	2		T14	4		T52	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T236	1		T201	2		T144	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T43	2		T23	2		T204	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T57	1		T45	1		T23	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T43	4		T204	2		T140	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T56	1		T144	1		T149	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T14	1		T44	2		T31	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T14	1		T31	1		T149	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T44	1		T23	2		T204	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	318	1			T3	1		T4	1		T14	5
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	326	1			T3	1		T4	1		T14	1