Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	776	1			T15	8		T17	10		T18	24
all_values[1]	776	1			T15	8		T17	10		T18	24
all_values[2]	776	1			T15	8		T17	10		T18	24
all_values[3]	776	1			T15	8		T17	10		T18	24
all_values[4]	776	1			T15	8		T17	10		T18	24
all_values[5]	776	1			T15	8		T17	10		T18	24
all_values[6]	776	1			T15	8		T17	10		T18	24
all_values[7]	776	1			T15	8		T17	10		T18	24

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3216

1

T15

45

T17

46

T18

86

auto[1]

2992

1

T15

19

T17

34

T18

106

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2506

1

T15

28

T17

31

T18

71

auto[1]

3702

1

T15

36

T17

49

T18

121

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3591

1

T15

39

T17

48

T18

104

auto[1]

2617

1

T15

25

T17

32

T18

88

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	130	1			T15	2		T17	2		T18	4
all_values[0]	auto[0]	auto[0]	auto[1]	83	1			T17	2		T18	3		T22	1
all_values[0]	auto[0]	auto[1]	auto[0]	133	1			T15	2		T18	3		T21	4
all_values[0]	auto[0]	auto[1]	auto[1]	83	1			T15	1		T17	1		T18	3
all_values[0]	auto[1]	auto[0]	auto[1]	181	1			T15	2		T17	1		T18	6
all_values[0]	auto[1]	auto[1]	auto[1]	166	1			T15	1		T17	4		T18	5
all_values[1]	auto[0]	auto[0]	auto[0]	161	1			T15	1		T17	2		T18	4
all_values[1]	auto[0]	auto[0]	auto[1]	73	1			T17	1		T21	2		T22	1
all_values[1]	auto[0]	auto[1]	auto[0]	153	1			T15	1		T17	4		T18	3
all_values[1]	auto[0]	auto[1]	auto[1]	75	1			T15	1		T18	5		T20	1
all_values[1]	auto[1]	auto[0]	auto[1]	175	1			T15	3		T17	3		T18	2
all_values[1]	auto[1]	auto[1]	auto[1]	139	1			T15	2		T18	10		T20	2
all_values[2]	auto[0]	auto[0]	auto[0]	156	1			T15	4		T18	4		T21	2
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T15	1		T17	1		T18	1
all_values[2]	auto[0]	auto[1]	auto[0]	112	1			T17	2		T18	4		T21	1
all_values[2]	auto[0]	auto[1]	auto[1]	82	1			T17	2		T18	3		T36	2
all_values[2]	auto[1]	auto[0]	auto[1]	189	1			T15	2		T17	1		T18	5
all_values[2]	auto[1]	auto[1]	auto[1]	159	1			T15	1		T17	4		T18	7
all_values[3]	auto[0]	auto[0]	auto[0]	156	1			T17	3		T18	7		T22	2
all_values[3]	auto[0]	auto[0]	auto[1]	79	1			T15	4		T17	3		T18	2
all_values[3]	auto[0]	auto[1]	auto[0]	146	1			T17	1		T18	3		T36	2
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T17	1		T18	1		T21	2
all_values[3]	auto[1]	auto[0]	auto[1]	175	1			T15	3		T17	1		T18	6
all_values[3]	auto[1]	auto[1]	auto[1]	148	1			T15	1		T17	1		T18	5
all_values[4]	auto[0]	auto[0]	auto[0]	160	1			T15	1		T17	2		T18	5
all_values[4]	auto[0]	auto[0]	auto[1]	67	1			T17	1		T18	3		T20	1
all_values[4]	auto[0]	auto[1]	auto[0]	149	1			T17	2		T18	6		T21	3
all_values[4]	auto[0]	auto[1]	auto[1]	75	1			T15	3		T17	1		T18	1
all_values[4]	auto[1]	auto[0]	auto[1]	160	1			T15	2		T17	3		T18	4
all_values[4]	auto[1]	auto[1]	auto[1]	165	1			T15	2		T17	1		T18	5
all_values[5]	auto[0]	auto[0]	auto[0]	226	1			T15	4		T17	5		T18	5
all_values[5]	auto[0]	auto[1]	auto[0]	231	1			T15	1		T17	1		T18	8
all_values[5]	auto[1]	auto[0]	auto[1]	166	1			T15	3		T17	4		T18	5
all_values[5]	auto[1]	auto[1]	auto[1]	153	1			T18	6		T20	2		T21	2
all_values[6]	auto[0]	auto[0]	auto[0]	160	1			T15	6		T17	2		T18	7
all_values[6]	auto[0]	auto[0]	auto[1]	82	1			T17	1		T18	3		T22	1
all_values[6]	auto[0]	auto[1]	auto[0]	149	1			T15	1		T18	5		T21	3
all_values[6]	auto[0]	auto[1]	auto[1]	73	1			T17	1		T18	1		T20	1
all_values[6]	auto[1]	auto[0]	auto[1]	160	1			T17	3		T18	3		T20	2
all_values[6]	auto[1]	auto[1]	auto[1]	152	1			T15	1		T17	3		T18	5
all_values[7]	auto[0]	auto[0]	auto[0]	144	1			T15	4		T17	3		T18	1
all_values[7]	auto[0]	auto[0]	auto[1]	92	1			T15	1		T17	2		T18	2
all_values[7]	auto[0]	auto[1]	auto[0]	140	1			T15	1		T17	2		T18	2
all_values[7]	auto[0]	auto[1]	auto[1]	71	1			T18	5		T21	1		T36	3
all_values[7]	auto[1]	auto[0]	auto[1]	163	1			T15	2		T18	4		T22	4
all_values[7]	auto[1]	auto[1]	auto[1]	166	1			T17	3		T18	10		T21	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal