Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1771

1

T12

1

T14

8

T28

6

auto[1]

1783

1

T14

10

T28

2

T30

9

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1959

1

T12

1

T14

17

T30

14

auto[1]

1595

1

T14

1

T28

8

T30

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2785

1

T12

1

T14

9

T28

8

auto[1]

769

1

T14

9

T30

7

T31

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	699	1			T14	2		T28	4		T30	2
valid[1]	726	1			T14	5		T30	3		T31	2
valid[2]	729	1			T12	1		T14	2		T30	4
valid[3]	724	1			T14	3		T28	1		T30	4
valid[4]	676	1			T14	6		T28	3		T30	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	103	1			T34	2		T93	1		T54	2
auto[0]	auto[0]	valid[0]	auto[1]	149	1			T28	3		T93	1		T94	1
auto[0]	auto[0]	valid[1]	auto[0]	122	1			T14	2		T30	1		T93	1
auto[0]	auto[0]	valid[1]	auto[1]	152	1			T32	1		T34	1		T94	2
auto[0]	auto[0]	valid[2]	auto[0]	119	1			T12	1		T14	1		T30	1
auto[0]	auto[0]	valid[2]	auto[1]	165	1			T32	2		T94	1		T96	2
auto[0]	auto[0]	valid[3]	auto[0]	126	1			T34	1		T95	1		T59	1
auto[0]	auto[0]	valid[3]	auto[1]	171	1			T28	1		T30	1		T32	1
auto[0]	auto[0]	valid[4]	auto[0]	111	1			T14	2		T56	1		T43	1
auto[0]	auto[0]	valid[4]	auto[1]	164	1			T28	2		T30	1		T93	1
auto[0]	auto[1]	valid[0]	auto[0]	128	1			T48	1		T95	2		T59	2
auto[0]	auto[1]	valid[0]	auto[1]	174	1			T28	1		T311	4		T312	1
auto[0]	auto[1]	valid[1]	auto[0]	132	1			T14	1		T30	1		T31	1
auto[0]	auto[1]	valid[1]	auto[1]	157	1			T30	1		T93	1		T94	1
auto[0]	auto[1]	valid[2]	auto[0]	123	1			T30	2		T34	2		T57	1
auto[0]	auto[1]	valid[2]	auto[1]	169	1			T94	1		T96	2		T313	1
auto[0]	auto[1]	valid[3]	auto[0]	113	1			T14	2		T30	1		T43	1
auto[0]	auto[1]	valid[3]	auto[1]	156	1			T94	1		T313	1		T311	1
auto[0]	auto[1]	valid[4]	auto[0]	113	1			T30	1		T95	3		T59	2
auto[0]	auto[1]	valid[4]	auto[1]	138	1			T14	1		T28	1		T311	2
auto[1]	auto[0]	valid[0]	auto[0]	74	1			T14	2		T30	2		T31	1
auto[1]	auto[0]	valid[1]	auto[0]	85	1			T31	1		T34	2		T54	1
auto[1]	auto[0]	valid[2]	auto[0]	80	1			T34	1		T95	1		T15	1
auto[1]	auto[0]	valid[3]	auto[0]	80	1			T30	2		T34	1		T303	1
auto[1]	auto[0]	valid[4]	auto[0]	70	1			T14	1		T56	1		T93	1
auto[1]	auto[1]	valid[0]	auto[0]	71	1			T54	1		T95	2		T17	1
auto[1]	auto[1]	valid[1]	auto[0]	78	1			T14	2		T93	3		T95	1
auto[1]	auto[1]	valid[2]	auto[0]	73	1			T14	1		T30	1		T57	1
auto[1]	auto[1]	valid[3]	auto[0]	78	1			T14	1		T31	1		T57	1
auto[1]	auto[1]	valid[4]	auto[0]	80	1			T14	2		T30	2		T95	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal