Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50505

1

T6

9

T12

14

T14

363

auto[1]

16576

1

T14

52

T28

93

T30

49

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48527

1

T6

4

T12

9

T14

270

auto[1]

18554

1

T6

5

T12

5

T14

145

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34402	1			T6	4		T12	6		T14	208
others[1]	5648	1			T6	1		T12	1		T14	40
others[2]	5704	1			T6	1		T14	51		T28	9
others[3]	6447	1			T6	1		T12	3		T14	41
interest[1]	3653	1			T12	1		T14	17		T28	5
interest[4]	22567	1			T6	3		T12	1		T14	148
interest[64]	11227	1			T6	2		T12	3		T14	58

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16322	1			T6	2		T12	5		T14	101
auto[0]	auto[0]	others[1]	2707	1			T12	1		T14	23		T29	1
auto[0]	auto[0]	others[2]	2708	1			T6	1		T14	27		T30	13
auto[0]	auto[0]	others[3]	3087	1			T12	2		T14	25		T30	24
auto[0]	auto[0]	interest[1]	1769	1			T12	1		T14	6		T30	9
auto[0]	auto[0]	interest[4]	10584	1			T6	1		T12	1		T14	69
auto[0]	auto[0]	interest[64]	5358	1			T6	1		T14	36		T30	19
auto[0]	auto[1]	others[0]	8684	1			T14	31		T28	57		T30	26
auto[0]	auto[1]	others[1]	1348	1			T14	5		T28	4		T30	7
auto[0]	auto[1]	others[2]	1394	1			T14	5		T28	9		T30	5
auto[0]	auto[1]	others[3]	1546	1			T14	3		T28	4		T30	2
auto[0]	auto[1]	interest[1]	898	1			T14	1		T28	5		T30	2
auto[0]	auto[1]	interest[4]	5848	1			T14	25		T28	39		T30	15
auto[0]	auto[1]	interest[64]	2706	1			T14	7		T28	14		T30	7
auto[1]	auto[0]	others[0]	9396	1			T6	2		T12	1		T14	76
auto[1]	auto[0]	others[1]	1593	1			T6	1		T14	12		T30	10
auto[1]	auto[0]	others[2]	1602	1			T14	19		T30	8		T31	8
auto[1]	auto[0]	others[3]	1814	1			T6	1		T12	1		T14	13
auto[1]	auto[0]	interest[1]	986	1			T14	10		T30	3		T31	3
auto[1]	auto[0]	interest[4]	6135	1			T6	2		T14	54		T30	34
auto[1]	auto[0]	interest[64]	3163	1			T6	1		T12	3		T14	15

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal