Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 94.01 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T164 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1728790021 Aug 15 05:11:43 PM PDT 24 Aug 15 05:11:48 PM PDT 24 208091721 ps
T165 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1685104632 Aug 15 05:11:40 PM PDT 24 Aug 15 05:11:42 PM PDT 24 72074185 ps
T1029 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2536321957 Aug 15 05:11:52 PM PDT 24 Aug 15 05:11:52 PM PDT 24 13465996 ps
T1030 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3119905409 Aug 15 05:11:24 PM PDT 24 Aug 15 05:11:25 PM PDT 24 22710801 ps
T1031 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1987508669 Aug 15 05:12:03 PM PDT 24 Aug 15 05:12:03 PM PDT 24 16827487 ps
T1032 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2791823716 Aug 15 05:11:41 PM PDT 24 Aug 15 05:11:42 PM PDT 24 34227921 ps
T111 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3878271985 Aug 15 05:11:43 PM PDT 24 Aug 15 05:11:47 PM PDT 24 740776155 ps
T1033 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1666190223 Aug 15 05:11:53 PM PDT 24 Aug 15 05:11:56 PM PDT 24 448189222 ps
T132 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3348943312 Aug 15 05:11:51 PM PDT 24 Aug 15 05:11:53 PM PDT 24 151853229 ps
T1034 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.184511169 Aug 15 05:12:03 PM PDT 24 Aug 15 05:12:04 PM PDT 24 167526364 ps
T116 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.806927801 Aug 15 05:11:32 PM PDT 24 Aug 15 05:11:34 PM PDT 24 32340775 ps
T1035 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1076880321 Aug 15 05:11:45 PM PDT 24 Aug 15 05:11:47 PM PDT 24 73398207 ps
T1036 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2344668954 Aug 15 05:11:52 PM PDT 24 Aug 15 05:11:53 PM PDT 24 47245924 ps
T1037 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2883190737 Aug 15 05:11:34 PM PDT 24 Aug 15 05:11:35 PM PDT 24 17601208 ps
T91 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.610257255 Aug 15 05:11:31 PM PDT 24 Aug 15 05:11:32 PM PDT 24 22137949 ps
T1038 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1824957769 Aug 15 05:11:43 PM PDT 24 Aug 15 05:11:44 PM PDT 24 51463671 ps
T1039 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1440092966 Aug 15 05:11:24 PM PDT 24 Aug 15 05:11:28 PM PDT 24 2852179795 ps
T1040 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1374879916 Aug 15 05:12:03 PM PDT 24 Aug 15 05:12:03 PM PDT 24 47067372 ps
T115 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3334951995 Aug 15 05:11:24 PM PDT 24 Aug 15 05:11:27 PM PDT 24 265399197 ps
T185 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3779691906 Aug 15 05:11:54 PM PDT 24 Aug 15 05:12:17 PM PDT 24 15848695340 ps
T113 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1818925603 Aug 15 05:11:41 PM PDT 24 Aug 15 05:11:54 PM PDT 24 201989584 ps
T1041 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3110503503 Aug 15 05:11:24 PM PDT 24 Aug 15 05:11:25 PM PDT 24 35357057 ps
T1042 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1040882281 Aug 15 05:11:54 PM PDT 24 Aug 15 05:11:55 PM PDT 24 12896850 ps
T1043 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2538799280 Aug 15 05:12:03 PM PDT 24 Aug 15 05:12:04 PM PDT 24 31791456 ps
T1044 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1787317959 Aug 15 05:11:35 PM PDT 24 Aug 15 05:11:36 PM PDT 24 17374974 ps
T192 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3032753781 Aug 15 05:11:53 PM PDT 24 Aug 15 05:12:00 PM PDT 24 397315338 ps
T1045 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1574782517 Aug 15 05:11:53 PM PDT 24 Aug 15 05:11:54 PM PDT 24 40800540 ps
T1046 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1636645621 Aug 15 05:11:32 PM PDT 24 Aug 15 05:11:33 PM PDT 24 39002810 ps
T1047 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4004726126 Aug 15 05:11:53 PM PDT 24 Aug 15 05:11:57 PM PDT 24 160341658 ps
T1048 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3757040157 Aug 15 05:11:53 PM PDT 24 Aug 15 05:11:54 PM PDT 24 40688518 ps
T1049 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4022877662 Aug 15 05:11:30 PM PDT 24 Aug 15 05:11:31 PM PDT 24 21162079 ps
T187 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2928345700 Aug 15 05:11:54 PM PDT 24 Aug 15 05:12:10 PM PDT 24 567203102 ps
T1050 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2033245593 Aug 15 05:12:04 PM PDT 24 Aug 15 05:12:05 PM PDT 24 166187374 ps
T1051 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4246198364 Aug 15 05:11:54 PM PDT 24 Aug 15 05:11:55 PM PDT 24 31905068 ps
T133 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2020689537 Aug 15 05:11:45 PM PDT 24 Aug 15 05:11:46 PM PDT 24 61233831 ps
T1052 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2106168535 Aug 15 05:11:55 PM PDT 24 Aug 15 05:11:58 PM PDT 24 176715007 ps
T1053 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3976189932 Aug 15 05:12:03 PM PDT 24 Aug 15 05:12:04 PM PDT 24 36221460 ps
T107 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4143836607 Aug 15 05:11:15 PM PDT 24 Aug 15 05:11:21 PM PDT 24 2140298235 ps
T1054 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1642300289 Aug 15 05:12:04 PM PDT 24 Aug 15 05:12:05 PM PDT 24 31567876 ps
T1055 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1540789274 Aug 15 05:11:17 PM PDT 24 Aug 15 05:11:51 PM PDT 24 1862218506 ps
T108 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1763669626 Aug 15 05:11:54 PM PDT 24 Aug 15 05:11:59 PM PDT 24 808200266 ps
T1056 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2823135583 Aug 15 05:11:32 PM PDT 24 Aug 15 05:11:33 PM PDT 24 50362078 ps
T186 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2879683319 Aug 15 05:11:41 PM PDT 24 Aug 15 05:11:56 PM PDT 24 563892470 ps
T188 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1258536555 Aug 15 05:11:45 PM PDT 24 Aug 15 05:11:59 PM PDT 24 197579372 ps
T1057 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3702580789 Aug 15 05:11:32 PM PDT 24 Aug 15 05:11:34 PM PDT 24 395384929 ps
T1058 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3964236902 Aug 15 05:11:24 PM PDT 24 Aug 15 05:11:26 PM PDT 24 20793347 ps
T134 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.710346786 Aug 15 05:11:31 PM PDT 24 Aug 15 05:11:34 PM PDT 24 1666466849 ps
T1059 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2071917737 Aug 15 05:11:27 PM PDT 24 Aug 15 05:11:29 PM PDT 24 54895890 ps
T119 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1003757799 Aug 15 05:11:41 PM PDT 24 Aug 15 05:11:46 PM PDT 24 431616366 ps
T1060 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3107857388 Aug 15 05:11:23 PM PDT 24 Aug 15 05:11:24 PM PDT 24 12176931 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1424995002 Aug 15 05:11:25 PM PDT 24 Aug 15 05:11:35 PM PDT 24 720088707 ps
T1062 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4028016382 Aug 15 05:11:45 PM PDT 24 Aug 15 05:11:47 PM PDT 24 89054604 ps
T189 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1643107524 Aug 15 05:11:44 PM PDT 24 Aug 15 05:11:53 PM PDT 24 299231511 ps
T1063 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2492067629 Aug 15 05:11:51 PM PDT 24 Aug 15 05:11:52 PM PDT 24 50101749 ps
T183 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3079769101 Aug 15 05:11:41 PM PDT 24 Aug 15 05:11:45 PM PDT 24 63910697 ps
T1064 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2080745251 Aug 15 05:11:54 PM PDT 24 Aug 15 05:11:58 PM PDT 24 60430567 ps
T1065 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2181603296 Aug 15 05:11:52 PM PDT 24 Aug 15 05:11:53 PM PDT 24 26486134 ps
T1066 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3343014000 Aug 15 05:12:03 PM PDT 24 Aug 15 05:12:04 PM PDT 24 16582335 ps
T135 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1756273824 Aug 15 05:11:25 PM PDT 24 Aug 15 05:11:27 PM PDT 24 108199690 ps
T1067 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2009601161 Aug 15 05:11:46 PM PDT 24 Aug 15 05:11:47 PM PDT 24 44972629 ps
T1068 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.954031482 Aug 15 05:11:45 PM PDT 24 Aug 15 05:11:47 PM PDT 24 60027979 ps
T1069 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3950290437 Aug 15 05:11:32 PM PDT 24 Aug 15 05:11:46 PM PDT 24 634512583 ps
T1070 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1178914461 Aug 15 05:11:51 PM PDT 24 Aug 15 05:12:16 PM PDT 24 1068933006 ps
T1071 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2231765390 Aug 15 05:11:34 PM PDT 24 Aug 15 05:11:39 PM PDT 24 893486467 ps
T1072 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2448731526 Aug 15 05:12:04 PM PDT 24 Aug 15 05:12:05 PM PDT 24 58110279 ps
T1073 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.579409569 Aug 15 05:11:42 PM PDT 24 Aug 15 05:11:43 PM PDT 24 15776777 ps
T1074 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.601578156 Aug 15 05:11:51 PM PDT 24 Aug 15 05:11:53 PM PDT 24 100871285 ps
T1075 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2566353724 Aug 15 05:11:54 PM PDT 24 Aug 15 05:11:55 PM PDT 24 54813663 ps
T190 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4076066299 Aug 15 05:11:31 PM PDT 24 Aug 15 05:11:45 PM PDT 24 2392283628 ps
T1076 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2376015132 Aug 15 05:11:46 PM PDT 24 Aug 15 05:11:50 PM PDT 24 71987486 ps
T1077 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3360868498 Aug 15 05:11:41 PM PDT 24 Aug 15 05:11:48 PM PDT 24 263354126 ps
T136 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1608095797 Aug 15 05:11:32 PM PDT 24 Aug 15 05:11:54 PM PDT 24 627499779 ps
T1078 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2422428581 Aug 15 05:11:54 PM PDT 24 Aug 15 05:11:54 PM PDT 24 54618345 ps
T137 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.981725929 Aug 15 05:11:24 PM PDT 24 Aug 15 05:11:39 PM PDT 24 2850395768 ps
T138 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1706900721 Aug 15 05:11:32 PM PDT 24 Aug 15 05:11:45 PM PDT 24 357584322 ps
T1079 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.279329201 Aug 15 05:11:32 PM PDT 24 Aug 15 05:11:35 PM PDT 24 262149031 ps
T1080 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2080071747 Aug 15 05:11:46 PM PDT 24 Aug 15 05:11:48 PM PDT 24 266829724 ps
T1081 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2528232894 Aug 15 05:11:36 PM PDT 24 Aug 15 05:11:38 PM PDT 24 56829835 ps
T92 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.204988021 Aug 15 05:11:17 PM PDT 24 Aug 15 05:11:18 PM PDT 24 59959254 ps
T1082 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3550616674 Aug 15 05:11:34 PM PDT 24 Aug 15 05:11:36 PM PDT 24 26212894 ps
T1083 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.235932682 Aug 15 05:11:44 PM PDT 24 Aug 15 05:11:46 PM PDT 24 180933596 ps
T1084 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3951819806 Aug 15 05:11:42 PM PDT 24 Aug 15 05:11:45 PM PDT 24 44733371 ps
T1085 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.994069586 Aug 15 05:11:44 PM PDT 24 Aug 15 05:11:47 PM PDT 24 427538156 ps
T191 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2940404001 Aug 15 05:11:19 PM PDT 24 Aug 15 05:11:26 PM PDT 24 218326371 ps
T1086 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2507604047 Aug 15 05:11:55 PM PDT 24 Aug 15 05:11:56 PM PDT 24 21752037 ps
T1087 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1883944135 Aug 15 05:11:44 PM PDT 24 Aug 15 05:11:49 PM PDT 24 60922992 ps
T1088 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.703580316 Aug 15 05:11:35 PM PDT 24 Aug 15 05:11:39 PM PDT 24 78539465 ps
T1089 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1849295457 Aug 15 05:11:52 PM PDT 24 Aug 15 05:11:56 PM PDT 24 1412360547 ps
T1090 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.259062047 Aug 15 05:11:23 PM PDT 24 Aug 15 05:11:28 PM PDT 24 1458439674 ps
T1091 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.115613352 Aug 15 05:11:34 PM PDT 24 Aug 15 05:11:46 PM PDT 24 198987582 ps
T1092 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1339281335 Aug 15 05:11:53 PM PDT 24 Aug 15 05:11:55 PM PDT 24 72565489 ps
T184 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3424905023 Aug 15 05:11:44 PM PDT 24 Aug 15 05:11:49 PM PDT 24 180976310 ps
T1093 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.668646584 Aug 15 05:12:04 PM PDT 24 Aug 15 05:12:05 PM PDT 24 20831772 ps
T1094 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3009941228 Aug 15 05:11:51 PM PDT 24 Aug 15 05:11:52 PM PDT 24 15017285 ps
T1095 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1309377793 Aug 15 05:11:25 PM PDT 24 Aug 15 05:11:26 PM PDT 24 151901061 ps
T1096 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3447681474 Aug 15 05:11:51 PM PDT 24 Aug 15 05:12:10 PM PDT 24 294401595 ps
T1097 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1857190229 Aug 15 05:12:03 PM PDT 24 Aug 15 05:12:04 PM PDT 24 17230486 ps
T1098 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3763531566 Aug 15 05:11:54 PM PDT 24 Aug 15 05:11:54 PM PDT 24 38670541 ps
T1099 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3195518594 Aug 15 05:11:53 PM PDT 24 Aug 15 05:11:54 PM PDT 24 24566153 ps
T1100 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3945540760 Aug 15 05:11:19 PM PDT 24 Aug 15 05:11:20 PM PDT 24 63714052 ps
T1101 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3095807339 Aug 15 05:11:19 PM PDT 24 Aug 15 05:11:21 PM PDT 24 36716668 ps
T1102 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3593386165 Aug 15 05:12:09 PM PDT 24 Aug 15 05:12:10 PM PDT 24 41863580 ps
T1103 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2169487885 Aug 15 05:11:51 PM PDT 24 Aug 15 05:11:54 PM PDT 24 86122171 ps
T1104 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2705660611 Aug 15 05:11:54 PM PDT 24 Aug 15 05:11:58 PM PDT 24 503177427 ps
T1105 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.928168444 Aug 15 05:11:32 PM PDT 24 Aug 15 05:11:33 PM PDT 24 73171188 ps
T1106 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2663214479 Aug 15 05:11:41 PM PDT 24 Aug 15 05:11:44 PM PDT 24 209657784 ps
T1107 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1836176937 Aug 15 05:12:02 PM PDT 24 Aug 15 05:12:03 PM PDT 24 25317731 ps
T1108 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4186443270 Aug 15 05:11:52 PM PDT 24 Aug 15 05:11:54 PM PDT 24 158347154 ps
T1109 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3634217960 Aug 15 05:11:43 PM PDT 24 Aug 15 05:11:46 PM PDT 24 190663339 ps
T1110 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1527148725 Aug 15 05:11:19 PM PDT 24 Aug 15 05:11:21 PM PDT 24 56964847 ps
T1111 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3598682924 Aug 15 05:11:54 PM PDT 24 Aug 15 05:11:56 PM PDT 24 156371265 ps
T1112 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3515401322 Aug 15 05:12:05 PM PDT 24 Aug 15 05:12:06 PM PDT 24 22630797 ps
T1113 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3438996832 Aug 15 05:11:43 PM PDT 24 Aug 15 05:11:47 PM PDT 24 138525003 ps
T1114 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.195003321 Aug 15 05:11:43 PM PDT 24 Aug 15 05:11:44 PM PDT 24 19909137 ps
T1115 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1638158075 Aug 15 05:11:51 PM PDT 24 Aug 15 05:11:52 PM PDT 24 37909056 ps
T1116 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.580792524 Aug 15 05:11:51 PM PDT 24 Aug 15 05:11:53 PM PDT 24 26176164 ps
T1117 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.417406125 Aug 15 05:11:23 PM PDT 24 Aug 15 05:11:26 PM PDT 24 133026601 ps
T1118 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3234030346 Aug 15 05:11:18 PM PDT 24 Aug 15 05:11:18 PM PDT 24 32746397 ps
T1119 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.491047437 Aug 15 05:11:43 PM PDT 24 Aug 15 05:11:52 PM PDT 24 355615915 ps
T1120 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.646470266 Aug 15 05:11:51 PM PDT 24 Aug 15 05:11:53 PM PDT 24 144651537 ps
T1121 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.788127002 Aug 15 05:11:33 PM PDT 24 Aug 15 05:11:40 PM PDT 24 224218068 ps
T1122 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.103292069 Aug 15 05:11:43 PM PDT 24 Aug 15 05:11:46 PM PDT 24 61463811 ps
T1123 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.810563164 Aug 15 05:11:54 PM PDT 24 Aug 15 05:11:55 PM PDT 24 22888232 ps
T1124 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2519529812 Aug 15 05:12:04 PM PDT 24 Aug 15 05:12:05 PM PDT 24 59752058 ps
T1125 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3640812203 Aug 15 05:11:25 PM PDT 24 Aug 15 05:11:34 PM PDT 24 1195023802 ps
T1126 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2141396245 Aug 15 05:11:52 PM PDT 24 Aug 15 05:11:54 PM PDT 24 95864644 ps
T1127 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1196415272 Aug 15 05:11:53 PM PDT 24 Aug 15 05:11:57 PM PDT 24 495735136 ps
T1128 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2259289831 Aug 15 05:11:33 PM PDT 24 Aug 15 05:11:36 PM PDT 24 551438025 ps
T1129 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2046677878 Aug 15 05:11:53 PM PDT 24 Aug 15 05:11:58 PM PDT 24 149901122 ps
T1130 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4226345690 Aug 15 05:11:49 PM PDT 24 Aug 15 05:12:13 PM PDT 24 17115978972 ps
T1131 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.887008031 Aug 15 05:11:32 PM PDT 24 Aug 15 05:11:33 PM PDT 24 24558692 ps

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3149938677
Short name T9
Test name
Test status
Simulation time 8896528245 ps
CPU time 43.08 seconds
Started Aug 15 05:16:29 PM PDT 24
Finished Aug 15 05:17:13 PM PDT 24
Peak memory 252884 kb
Host smart-ab0291bf-e522-4f11-afc0-d9eb9a06aecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149938677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3149938677
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.198510428
Short name T14
Test name
Test status
Simulation time 41419552484 ps
CPU time 435.3 seconds
Started Aug 15 05:16:29 PM PDT 24
Finished Aug 15 05:23:45 PM PDT 24
Peak memory 266356 kb
Host smart-28ee13f3-9d15-4a94-a7db-d3181d8bae19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198510428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.198510428
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1411288873
Short name T57
Test name
Test status
Simulation time 2171178287 ps
CPU time 58.67 seconds
Started Aug 15 05:13:02 PM PDT 24
Finished Aug 15 05:14:00 PM PDT 24
Peak memory 265924 kb
Host smart-7d4e39ad-0e97-4878-8d40-3e49cbd50a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411288873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1411288873
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.225790214
Short name T17
Test name
Test status
Simulation time 91965260009 ps
CPU time 456.5 seconds
Started Aug 15 05:14:15 PM PDT 24
Finished Aug 15 05:21:52 PM PDT 24
Peak memory 269848 kb
Host smart-0ee91d54-0310-49bd-ad5f-c7913015f805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225790214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.225790214
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3707949901
Short name T71
Test name
Test status
Simulation time 4254143555 ps
CPU time 23.64 seconds
Started Aug 15 05:11:24 PM PDT 24
Finished Aug 15 05:11:47 PM PDT 24
Peak memory 215208 kb
Host smart-3156f3df-821e-48da-b5ea-68f1eaef5bb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707949901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3707949901
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.491978762
Short name T149
Test name
Test status
Simulation time 273028256705 ps
CPU time 1277.8 seconds
Started Aug 15 05:15:14 PM PDT 24
Finished Aug 15 05:36:32 PM PDT 24
Peak memory 298944 kb
Host smart-bc08ed56-35e3-440f-afc4-91496a2ed7c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491978762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.491978762
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.61950850
Short name T73
Test name
Test status
Simulation time 33237409 ps
CPU time 0.76 seconds
Started Aug 15 05:13:09 PM PDT 24
Finished Aug 15 05:13:09 PM PDT 24
Peak memory 216784 kb
Host smart-c4c58ebe-6573-44cd-9f44-03b76136c1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61950850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.61950850
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.445225111
Short name T21
Test name
Test status
Simulation time 11284981942 ps
CPU time 225.37 seconds
Started Aug 15 05:16:09 PM PDT 24
Finished Aug 15 05:19:55 PM PDT 24
Peak memory 291120 kb
Host smart-6c92801e-212d-469f-b9d8-b1a957be0025
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445225111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.445225111
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1345318624
Short name T43
Test name
Test status
Simulation time 44692152595 ps
CPU time 213.4 seconds
Started Aug 15 05:14:40 PM PDT 24
Finished Aug 15 05:18:14 PM PDT 24
Peak memory 271268 kb
Host smart-aadde0db-a39c-4a50-8e7f-5d8c76699843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345318624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1345318624
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.679065005
Short name T105
Test name
Test status
Simulation time 207618992 ps
CPU time 5.94 seconds
Started Aug 15 05:11:50 PM PDT 24
Finished Aug 15 05:11:56 PM PDT 24
Peak memory 215328 kb
Host smart-ee6fe72a-a217-4f64-bd8c-a18d5d3bb92f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679065005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.679065005
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1637536106
Short name T197
Test name
Test status
Simulation time 19437243036 ps
CPU time 132.79 seconds
Started Aug 15 05:16:19 PM PDT 24
Finished Aug 15 05:18:32 PM PDT 24
Peak memory 270756 kb
Host smart-05eb9ced-cd63-4f6e-a84b-c446f68dde02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637536106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1637536106
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3004842645
Short name T45
Test name
Test status
Simulation time 25462908783 ps
CPU time 114.12 seconds
Started Aug 15 05:13:38 PM PDT 24
Finished Aug 15 05:15:32 PM PDT 24
Peak memory 265104 kb
Host smart-a3d41b1a-4a67-46c2-bb8a-4bbb618e06e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004842645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3004842645
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4167861836
Short name T201
Test name
Test status
Simulation time 27353989712 ps
CPU time 140.48 seconds
Started Aug 15 05:13:53 PM PDT 24
Finished Aug 15 05:16:14 PM PDT 24
Peak memory 266476 kb
Host smart-9408f54a-1484-4f1b-9597-428e62f296cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167861836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4167861836
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.15481813
Short name T359
Test name
Test status
Simulation time 14764267 ps
CPU time 0.73 seconds
Started Aug 15 05:13:10 PM PDT 24
Finished Aug 15 05:13:10 PM PDT 24
Peak memory 205664 kb
Host smart-c9a54d5d-7c72-4cdd-ac4f-a92cb4d0f479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15481813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.15481813
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.4252954590
Short name T10
Test name
Test status
Simulation time 1892211091 ps
CPU time 29.07 seconds
Started Aug 15 05:16:38 PM PDT 24
Finished Aug 15 05:17:08 PM PDT 24
Peak memory 241736 kb
Host smart-5464e0b0-5224-40e7-9e03-980b7128cf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252954590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4252954590
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3110842528
Short name T236
Test name
Test status
Simulation time 19799024117 ps
CPU time 253.65 seconds
Started Aug 15 05:14:14 PM PDT 24
Finished Aug 15 05:18:28 PM PDT 24
Peak memory 267544 kb
Host smart-c6ef29a1-c5f3-4421-afa1-8552cb7d1343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110842528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3110842528
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.810420143
Short name T128
Test name
Test status
Simulation time 11212422989 ps
CPU time 46.53 seconds
Started Aug 15 05:11:23 PM PDT 24
Finished Aug 15 05:12:10 PM PDT 24
Peak memory 215076 kb
Host smart-701afa18-0748-4884-8a75-3a7cf9a1b8a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810420143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.810420143
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1071793134
Short name T224
Test name
Test status
Simulation time 48093479477 ps
CPU time 164.37 seconds
Started Aug 15 05:14:02 PM PDT 24
Finished Aug 15 05:16:47 PM PDT 24
Peak memory 255280 kb
Host smart-b7ac0ed8-c643-426b-8469-dd6f07193d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071793134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1071793134
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1563989799
Short name T24
Test name
Test status
Simulation time 2752743137 ps
CPU time 48.51 seconds
Started Aug 15 05:13:19 PM PDT 24
Finished Aug 15 05:14:08 PM PDT 24
Peak memory 250100 kb
Host smart-482f7f1f-d851-4715-9206-586f31155dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563989799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1563989799
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.739425771
Short name T44
Test name
Test status
Simulation time 4038646590 ps
CPU time 71.34 seconds
Started Aug 15 05:15:36 PM PDT 24
Finished Aug 15 05:16:48 PM PDT 24
Peak memory 254036 kb
Host smart-45cb56ce-7fb8-402a-9bf4-01c7c3586fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739425771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.739425771
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1915389454
Short name T75
Test name
Test status
Simulation time 214287745 ps
CPU time 1.1 seconds
Started Aug 15 05:13:12 PM PDT 24
Finished Aug 15 05:13:13 PM PDT 24
Peak memory 237204 kb
Host smart-2c045b27-91d4-494f-be8d-60ea3cf3804b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915389454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1915389454
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2933482541
Short name T140
Test name
Test status
Simulation time 4677391734 ps
CPU time 103.18 seconds
Started Aug 15 05:16:03 PM PDT 24
Finished Aug 15 05:17:47 PM PDT 24
Peak memory 265828 kb
Host smart-96ef0494-f4ed-406f-b401-a73516235565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933482541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2933482541
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.768301233
Short name T37
Test name
Test status
Simulation time 18622184486 ps
CPU time 160.72 seconds
Started Aug 15 05:14:29 PM PDT 24
Finished Aug 15 05:17:10 PM PDT 24
Peak memory 252000 kb
Host smart-38b7185d-e167-4ff8-ab70-82298d3b5855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768301233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.768301233
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3558932158
Short name T238
Test name
Test status
Simulation time 45155438809 ps
CPU time 329.31 seconds
Started Aug 15 05:16:20 PM PDT 24
Finished Aug 15 05:21:49 PM PDT 24
Peak memory 301688 kb
Host smart-b65e5721-c5fe-4fae-9de9-da98101eb07d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558932158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3558932158
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3779691906
Short name T185
Test name
Test status
Simulation time 15848695340 ps
CPU time 22.84 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:12:17 PM PDT 24
Peak memory 215704 kb
Host smart-ac467aa5-e83d-4a56-b325-2bb937241c1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779691906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3779691906
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.535799809
Short name T34
Test name
Test status
Simulation time 9148074388 ps
CPU time 14.57 seconds
Started Aug 15 05:14:11 PM PDT 24
Finished Aug 15 05:14:26 PM PDT 24
Peak memory 217532 kb
Host smart-3c184244-0b22-40d5-9a58-a9679b4e9be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535799809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.535799809
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1973455284
Short name T285
Test name
Test status
Simulation time 16615368156 ps
CPU time 93.39 seconds
Started Aug 15 05:16:04 PM PDT 24
Finished Aug 15 05:17:38 PM PDT 24
Peak memory 264632 kb
Host smart-93478cdc-61fa-4499-8ad0-81840583fec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973455284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1973455284
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2058245326
Short name T208
Test name
Test status
Simulation time 169024729545 ps
CPU time 411.97 seconds
Started Aug 15 05:16:52 PM PDT 24
Finished Aug 15 05:23:44 PM PDT 24
Peak memory 264628 kb
Host smart-3027ef8c-16a1-4810-9f51-e38e6cffcbc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058245326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2058245326
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4143836607
Short name T107
Test name
Test status
Simulation time 2140298235 ps
CPU time 5.56 seconds
Started Aug 15 05:11:15 PM PDT 24
Finished Aug 15 05:11:21 PM PDT 24
Peak memory 215248 kb
Host smart-c845465f-c099-46ef-895a-6e2b41ceeb07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143836607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4
143836607
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4082701047
Short name T41
Test name
Test status
Simulation time 22655719248 ps
CPU time 259.19 seconds
Started Aug 15 05:16:39 PM PDT 24
Finished Aug 15 05:20:58 PM PDT 24
Peak memory 258068 kb
Host smart-30911bce-024f-40c3-aaa3-f178453b91d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082701047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4082701047
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1025071337
Short name T277
Test name
Test status
Simulation time 143923255439 ps
CPU time 260.31 seconds
Started Aug 15 05:13:13 PM PDT 24
Finished Aug 15 05:17:33 PM PDT 24
Peak memory 249040 kb
Host smart-986d3325-e4d3-4907-8fb5-d4d212380945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025071337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1025071337
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.866175415
Short name T18
Test name
Test status
Simulation time 454186596039 ps
CPU time 351.16 seconds
Started Aug 15 05:14:14 PM PDT 24
Finished Aug 15 05:20:05 PM PDT 24
Peak memory 266540 kb
Host smart-23aebe51-3851-4ef9-b0fc-05b23d99f71f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866175415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.866175415
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2801287827
Short name T296
Test name
Test status
Simulation time 180469903 ps
CPU time 9.14 seconds
Started Aug 15 05:14:16 PM PDT 24
Finished Aug 15 05:14:25 PM PDT 24
Peak memory 241088 kb
Host smart-09eb086b-dacd-417d-a3fd-a7f587dc1aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801287827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2801287827
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.4060381107
Short name T299
Test name
Test status
Simulation time 1016756236 ps
CPU time 10.28 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:14:56 PM PDT 24
Peak memory 233544 kb
Host smart-c7028af5-8995-4fda-a4b3-022108da56ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060381107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.4060381107
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2146936842
Short name T274
Test name
Test status
Simulation time 224783569083 ps
CPU time 520.01 seconds
Started Aug 15 05:14:54 PM PDT 24
Finished Aug 15 05:23:34 PM PDT 24
Peak memory 257364 kb
Host smart-0a8c9ca4-a8d2-46ec-aa3a-c5185c1c2418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146936842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2146936842
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1931533586
Short name T288
Test name
Test status
Simulation time 48554877303 ps
CPU time 118.18 seconds
Started Aug 15 05:16:29 PM PDT 24
Finished Aug 15 05:18:28 PM PDT 24
Peak memory 251056 kb
Host smart-12e28081-0701-4024-a611-0773011aceff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931533586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1931533586
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2940404001
Short name T191
Test name
Test status
Simulation time 218326371 ps
CPU time 6.75 seconds
Started Aug 15 05:11:19 PM PDT 24
Finished Aug 15 05:11:26 PM PDT 24
Peak memory 215196 kb
Host smart-eff03779-5399-4287-aae4-e7ab6d04aad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940404001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2940404001
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2926185029
Short name T268
Test name
Test status
Simulation time 23730044553 ps
CPU time 82.95 seconds
Started Aug 15 05:13:10 PM PDT 24
Finished Aug 15 05:14:33 PM PDT 24
Peak memory 256220 kb
Host smart-572149dd-399f-45d2-8536-e260db8598af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926185029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2926185029
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.686175842
Short name T169
Test name
Test status
Simulation time 6561309965 ps
CPU time 54.62 seconds
Started Aug 15 05:14:05 PM PDT 24
Finished Aug 15 05:15:00 PM PDT 24
Peak memory 251168 kb
Host smart-ace6dd0f-9374-436f-b115-c9c52410209f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686175842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.686175842
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1533637291
Short name T93
Test name
Test status
Simulation time 1492166087 ps
CPU time 15.14 seconds
Started Aug 15 05:14:03 PM PDT 24
Finished Aug 15 05:14:18 PM PDT 24
Peak memory 217124 kb
Host smart-3cadeed2-790f-4e4f-bbe5-4536b8dbcd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533637291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1533637291
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2453626705
Short name T42
Test name
Test status
Simulation time 9559041967 ps
CPU time 150.34 seconds
Started Aug 15 05:14:34 PM PDT 24
Finished Aug 15 05:17:05 PM PDT 24
Peak memory 267580 kb
Host smart-bda6d590-1adc-49dd-8882-3de4e0c66ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453626705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2453626705
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3164437169
Short name T864
Test name
Test status
Simulation time 4937289230 ps
CPU time 10.47 seconds
Started Aug 15 05:14:29 PM PDT 24
Finished Aug 15 05:14:39 PM PDT 24
Peak memory 233640 kb
Host smart-61e4e017-ffd2-4312-91cd-2c1eb787e80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164437169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3164437169
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2512322589
Short name T314
Test name
Test status
Simulation time 3741038476 ps
CPU time 15.3 seconds
Started Aug 15 05:14:30 PM PDT 24
Finished Aug 15 05:14:46 PM PDT 24
Peak memory 217492 kb
Host smart-83b80200-8c11-4d03-a900-d89efb3f4e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512322589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2512322589
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2279689090
Short name T227
Test name
Test status
Simulation time 34133294860 ps
CPU time 224.1 seconds
Started Aug 15 05:14:50 PM PDT 24
Finished Aug 15 05:18:35 PM PDT 24
Peak memory 253080 kb
Host smart-c4fb2b15-397f-4ce1-9195-aaca02c617d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279689090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2279689090
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3553475583
Short name T161
Test name
Test status
Simulation time 4627706967 ps
CPU time 18.74 seconds
Started Aug 15 05:15:34 PM PDT 24
Finished Aug 15 05:15:53 PM PDT 24
Peak memory 233660 kb
Host smart-1b52e852-ce7f-4101-8bed-282475d93e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553475583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3553475583
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2662467965
Short name T846
Test name
Test status
Simulation time 65529616705 ps
CPU time 141.8 seconds
Started Aug 15 05:14:12 PM PDT 24
Finished Aug 15 05:16:33 PM PDT 24
Peak memory 257880 kb
Host smart-66699d9b-1ca2-43f6-8543-ce5e4fe36bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662467965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2662467965
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3628321658
Short name T225
Test name
Test status
Simulation time 247663446 ps
CPU time 2.65 seconds
Started Aug 15 05:13:09 PM PDT 24
Finished Aug 15 05:13:11 PM PDT 24
Peak memory 225276 kb
Host smart-15c74267-b4cc-4ad1-9102-39f7dd97f915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628321658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3628321658
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1751820076
Short name T89
Test name
Test status
Simulation time 227841814 ps
CPU time 1.61 seconds
Started Aug 15 05:11:24 PM PDT 24
Finished Aug 15 05:11:25 PM PDT 24
Peak memory 206824 kb
Host smart-638194dc-8305-4c0c-8c40-2d6102e9ee05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751820076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1751820076
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3334951995
Short name T115
Test name
Test status
Simulation time 265399197 ps
CPU time 2.16 seconds
Started Aug 15 05:11:24 PM PDT 24
Finished Aug 15 05:11:27 PM PDT 24
Peak memory 215256 kb
Host smart-b719c52f-196d-4443-9db9-d5677f718c89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334951995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
334951995
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1818925603
Short name T113
Test name
Test status
Simulation time 201989584 ps
CPU time 12.91 seconds
Started Aug 15 05:11:41 PM PDT 24
Finished Aug 15 05:11:54 PM PDT 24
Peak memory 215148 kb
Host smart-02ec17dc-6922-4911-8f81-330596be48d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818925603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1818925603
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2253440094
Short name T1024
Test name
Test status
Simulation time 1200023487 ps
CPU time 8.68 seconds
Started Aug 15 05:11:18 PM PDT 24
Finished Aug 15 05:11:27 PM PDT 24
Peak memory 215072 kb
Host smart-62e30ddc-379e-4759-bfe4-96eeb13373f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253440094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2253440094
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1540789274
Short name T1055
Test name
Test status
Simulation time 1862218506 ps
CPU time 34.39 seconds
Started Aug 15 05:11:17 PM PDT 24
Finished Aug 15 05:11:51 PM PDT 24
Peak memory 215068 kb
Host smart-83874fcc-efc8-4c5f-8e7c-b434603c7391
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540789274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1540789274
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.204988021
Short name T92
Test name
Test status
Simulation time 59959254 ps
CPU time 1.2 seconds
Started Aug 15 05:11:17 PM PDT 24
Finished Aug 15 05:11:18 PM PDT 24
Peak memory 216088 kb
Host smart-6f4efe73-c574-46e1-96ab-be1b8f7a8102
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204988021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.204988021
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1779588731
Short name T117
Test name
Test status
Simulation time 126574339 ps
CPU time 3.62 seconds
Started Aug 15 05:11:25 PM PDT 24
Finished Aug 15 05:11:29 PM PDT 24
Peak memory 217368 kb
Host smart-b739e025-652c-4096-88f0-273fa124c17f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779588731 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1779588731
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3095807339
Short name T1101
Test name
Test status
Simulation time 36716668 ps
CPU time 1.74 seconds
Started Aug 15 05:11:19 PM PDT 24
Finished Aug 15 05:11:21 PM PDT 24
Peak memory 215076 kb
Host smart-85862070-2c4f-41c4-a20b-1bedf6393bd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095807339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
095807339
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3945540760
Short name T1100
Test name
Test status
Simulation time 63714052 ps
CPU time 0.75 seconds
Started Aug 15 05:11:19 PM PDT 24
Finished Aug 15 05:11:20 PM PDT 24
Peak memory 203752 kb
Host smart-9659cd15-a02f-45b1-96eb-9208c56f135f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945540760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
945540760
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1527148725
Short name T1110
Test name
Test status
Simulation time 56964847 ps
CPU time 1.34 seconds
Started Aug 15 05:11:19 PM PDT 24
Finished Aug 15 05:11:21 PM PDT 24
Peak memory 215088 kb
Host smart-48ce0b1b-ce7e-4cf1-bcab-8602bff72a7d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527148725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1527148725
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3234030346
Short name T1118
Test name
Test status
Simulation time 32746397 ps
CPU time 0.68 seconds
Started Aug 15 05:11:18 PM PDT 24
Finished Aug 15 05:11:18 PM PDT 24
Peak memory 203576 kb
Host smart-8d66d7c7-bb19-4337-a2db-f3e0f048f22e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234030346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3234030346
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2071917737
Short name T1059
Test name
Test status
Simulation time 54895890 ps
CPU time 1.79 seconds
Started Aug 15 05:11:27 PM PDT 24
Finished Aug 15 05:11:29 PM PDT 24
Peak memory 214964 kb
Host smart-2e61f105-1986-4c7a-b44f-ab4001050424
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071917737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2071917737
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1424995002
Short name T1061
Test name
Test status
Simulation time 720088707 ps
CPU time 9.16 seconds
Started Aug 15 05:11:25 PM PDT 24
Finished Aug 15 05:11:35 PM PDT 24
Peak memory 215072 kb
Host smart-7dc931fb-6472-4a10-94a4-a21f0c78fc0d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424995002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1424995002
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.417406125
Short name T1117
Test name
Test status
Simulation time 133026601 ps
CPU time 2.83 seconds
Started Aug 15 05:11:23 PM PDT 24
Finished Aug 15 05:11:26 PM PDT 24
Peak memory 217620 kb
Host smart-8d81a3c3-6d11-48ce-ad94-84ef0e8d08b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417406125 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.417406125
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1756273824
Short name T135
Test name
Test status
Simulation time 108199690 ps
CPU time 2.2 seconds
Started Aug 15 05:11:25 PM PDT 24
Finished Aug 15 05:11:27 PM PDT 24
Peak memory 215016 kb
Host smart-279f375b-df01-4e5d-9f53-c0cfd92fccf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756273824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
756273824
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1309377793
Short name T1095
Test name
Test status
Simulation time 151901061 ps
CPU time 0.72 seconds
Started Aug 15 05:11:25 PM PDT 24
Finished Aug 15 05:11:26 PM PDT 24
Peak memory 203660 kb
Host smart-cd5e01be-434b-49fa-b169-bfeee2f0f7dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309377793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
309377793
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3964236902
Short name T1058
Test name
Test status
Simulation time 20793347 ps
CPU time 1.26 seconds
Started Aug 15 05:11:24 PM PDT 24
Finished Aug 15 05:11:26 PM PDT 24
Peak memory 215028 kb
Host smart-f3c78f00-0da1-458e-ad28-bf04951d1e30
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964236902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3964236902
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3107857388
Short name T1060
Test name
Test status
Simulation time 12176931 ps
CPU time 0.69 seconds
Started Aug 15 05:11:23 PM PDT 24
Finished Aug 15 05:11:24 PM PDT 24
Peak memory 203532 kb
Host smart-269bff08-895c-4d91-8832-d86fc2755568
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107857388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3107857388
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3347262309
Short name T1018
Test name
Test status
Simulation time 158014805 ps
CPU time 3.73 seconds
Started Aug 15 05:11:25 PM PDT 24
Finished Aug 15 05:11:29 PM PDT 24
Peak memory 215028 kb
Host smart-cbf6a656-3f76-4f2c-8e15-1889dc9b74a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347262309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3347262309
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3640812203
Short name T1125
Test name
Test status
Simulation time 1195023802 ps
CPU time 8.37 seconds
Started Aug 15 05:11:25 PM PDT 24
Finished Aug 15 05:11:34 PM PDT 24
Peak memory 215356 kb
Host smart-4d196db4-e0ed-417c-83cc-2480a4438bc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640812203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3640812203
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4028016382
Short name T1062
Test name
Test status
Simulation time 89054604 ps
CPU time 1.7 seconds
Started Aug 15 05:11:45 PM PDT 24
Finished Aug 15 05:11:47 PM PDT 24
Peak memory 215232 kb
Host smart-a4450067-4b8a-4312-b20f-43a568ff795d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028016382 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.4028016382
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.103292069
Short name T1122
Test name
Test status
Simulation time 61463811 ps
CPU time 2.08 seconds
Started Aug 15 05:11:43 PM PDT 24
Finished Aug 15 05:11:46 PM PDT 24
Peak memory 206744 kb
Host smart-ea5ed85e-9236-4f1b-af75-31865ecd7c69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103292069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.103292069
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1824957769
Short name T1038
Test name
Test status
Simulation time 51463671 ps
CPU time 0.71 seconds
Started Aug 15 05:11:43 PM PDT 24
Finished Aug 15 05:11:44 PM PDT 24
Peak memory 204028 kb
Host smart-ad388567-f7b4-4d7a-83d8-3bd0afb00723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824957769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1824957769
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2663214479
Short name T1106
Test name
Test status
Simulation time 209657784 ps
CPU time 3.03 seconds
Started Aug 15 05:11:41 PM PDT 24
Finished Aug 15 05:11:44 PM PDT 24
Peak memory 215068 kb
Host smart-c185b899-753d-41a4-891e-a8fa27f67b50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663214479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2663214479
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2376015132
Short name T1076
Test name
Test status
Simulation time 71987486 ps
CPU time 4.56 seconds
Started Aug 15 05:11:46 PM PDT 24
Finished Aug 15 05:11:50 PM PDT 24
Peak memory 215392 kb
Host smart-a493349a-ff8d-4502-8e18-5c88b4d53455
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376015132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2376015132
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1537539479
Short name T114
Test name
Test status
Simulation time 93767856 ps
CPU time 2.76 seconds
Started Aug 15 05:11:43 PM PDT 24
Finished Aug 15 05:11:46 PM PDT 24
Peak memory 216524 kb
Host smart-43527b11-1179-409b-8b28-95ddfe6d1feb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537539479 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1537539479
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.235932682
Short name T1083
Test name
Test status
Simulation time 180933596 ps
CPU time 1.37 seconds
Started Aug 15 05:11:44 PM PDT 24
Finished Aug 15 05:11:46 PM PDT 24
Peak memory 206716 kb
Host smart-ed2b8f88-2604-4933-a2d8-bbe691c2402b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235932682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.235932682
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3345447483
Short name T1016
Test name
Test status
Simulation time 15683340 ps
CPU time 0.72 seconds
Started Aug 15 05:11:43 PM PDT 24
Finished Aug 15 05:11:44 PM PDT 24
Peak memory 203708 kb
Host smart-68002152-055a-42f0-9281-9f5f2bb0f82a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345447483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3345447483
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.954031482
Short name T1068
Test name
Test status
Simulation time 60027979 ps
CPU time 1.85 seconds
Started Aug 15 05:11:45 PM PDT 24
Finished Aug 15 05:11:47 PM PDT 24
Peak memory 215136 kb
Host smart-c5305e67-9e64-47e5-8704-2f2a89f52448
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954031482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.954031482
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3878271985
Short name T111
Test name
Test status
Simulation time 740776155 ps
CPU time 4.67 seconds
Started Aug 15 05:11:43 PM PDT 24
Finished Aug 15 05:11:47 PM PDT 24
Peak memory 215228 kb
Host smart-fdc07077-2c3d-4e67-aee7-019f69ec2d42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878271985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3878271985
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1643107524
Short name T189
Test name
Test status
Simulation time 299231511 ps
CPU time 8.16 seconds
Started Aug 15 05:11:44 PM PDT 24
Finished Aug 15 05:11:53 PM PDT 24
Peak memory 215456 kb
Host smart-2a15e0ef-e5c6-45c9-951c-f65f386c1b13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643107524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1643107524
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.994069586
Short name T1085
Test name
Test status
Simulation time 427538156 ps
CPU time 3.06 seconds
Started Aug 15 05:11:44 PM PDT 24
Finished Aug 15 05:11:47 PM PDT 24
Peak memory 216672 kb
Host smart-f170b72a-ae71-483c-af6a-e96bc25e2bee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994069586 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.994069586
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4125591081
Short name T126
Test name
Test status
Simulation time 42256214 ps
CPU time 2.46 seconds
Started Aug 15 05:11:41 PM PDT 24
Finished Aug 15 05:11:44 PM PDT 24
Peak memory 207000 kb
Host smart-add9f786-729a-4ba5-b9a8-9f1cd5141821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125591081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4125591081
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2009601161
Short name T1067
Test name
Test status
Simulation time 44972629 ps
CPU time 0.7 seconds
Started Aug 15 05:11:46 PM PDT 24
Finished Aug 15 05:11:47 PM PDT 24
Peak memory 204044 kb
Host smart-bbe62405-2d15-4694-8f5a-8b4f1002d3d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009601161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2009601161
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1076880321
Short name T1035
Test name
Test status
Simulation time 73398207 ps
CPU time 1.92 seconds
Started Aug 15 05:11:45 PM PDT 24
Finished Aug 15 05:11:47 PM PDT 24
Peak memory 206660 kb
Host smart-507c9381-4eb7-480e-81e2-fce4d9117ba0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076880321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1076880321
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1003757799
Short name T119
Test name
Test status
Simulation time 431616366 ps
CPU time 5.29 seconds
Started Aug 15 05:11:41 PM PDT 24
Finished Aug 15 05:11:46 PM PDT 24
Peak memory 215184 kb
Host smart-a178cdc7-5f19-4b50-aa8c-7d1da7294aba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003757799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1003757799
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1258536555
Short name T188
Test name
Test status
Simulation time 197579372 ps
CPU time 13.94 seconds
Started Aug 15 05:11:45 PM PDT 24
Finished Aug 15 05:11:59 PM PDT 24
Peak memory 215128 kb
Host smart-7d5d0ac5-f4a8-49d1-ad06-3547155feb82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258536555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1258536555
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3653789255
Short name T121
Test name
Test status
Simulation time 346231370 ps
CPU time 3.51 seconds
Started Aug 15 05:11:49 PM PDT 24
Finished Aug 15 05:11:53 PM PDT 24
Peak memory 217312 kb
Host smart-25c46ee8-6bba-46e2-900f-43482a8e913b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653789255 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3653789255
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1638158075
Short name T1115
Test name
Test status
Simulation time 37909056 ps
CPU time 1.22 seconds
Started Aug 15 05:11:51 PM PDT 24
Finished Aug 15 05:11:52 PM PDT 24
Peak memory 206772 kb
Host smart-8ac24ab3-4311-4d36-96eb-f341832fadab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638158075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1638158075
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2181603296
Short name T1065
Test name
Test status
Simulation time 26486134 ps
CPU time 0.73 seconds
Started Aug 15 05:11:52 PM PDT 24
Finished Aug 15 05:11:53 PM PDT 24
Peak memory 203960 kb
Host smart-937b65f2-c0f6-4c6c-ab12-0db700efed79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181603296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2181603296
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2169487885
Short name T1103
Test name
Test status
Simulation time 86122171 ps
CPU time 3.3 seconds
Started Aug 15 05:11:51 PM PDT 24
Finished Aug 15 05:11:54 PM PDT 24
Peak memory 215100 kb
Host smart-3978be99-380f-4f69-a0ca-aacc56c0ec41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169487885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2169487885
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3951819806
Short name T1084
Test name
Test status
Simulation time 44733371 ps
CPU time 3 seconds
Started Aug 15 05:11:42 PM PDT 24
Finished Aug 15 05:11:45 PM PDT 24
Peak memory 216272 kb
Host smart-a96b1c6a-060e-4983-8e6d-e9479fca57ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951819806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3951819806
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.491047437
Short name T1119
Test name
Test status
Simulation time 355615915 ps
CPU time 8.86 seconds
Started Aug 15 05:11:43 PM PDT 24
Finished Aug 15 05:11:52 PM PDT 24
Peak memory 215148 kb
Host smart-b035a19b-63ff-4ee7-92e0-ef644fb886f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491047437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.491047437
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1339281335
Short name T1092
Test name
Test status
Simulation time 72565489 ps
CPU time 1.78 seconds
Started Aug 15 05:11:53 PM PDT 24
Finished Aug 15 05:11:55 PM PDT 24
Peak memory 215088 kb
Host smart-5fafdcaa-84ea-437c-8e5b-e80b9f91e757
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339281335 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1339281335
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2345914974
Short name T129
Test name
Test status
Simulation time 28567873 ps
CPU time 1.84 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:11:56 PM PDT 24
Peak memory 215120 kb
Host smart-63e5f136-3da3-4198-bcbf-3cf2b453a37e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345914974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2345914974
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2528324355
Short name T1020
Test name
Test status
Simulation time 24780423 ps
CPU time 0.73 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:11:55 PM PDT 24
Peak memory 203704 kb
Host smart-51c975c5-aff1-4d58-a0a6-8d3d54b56704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528324355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2528324355
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1849295457
Short name T1089
Test name
Test status
Simulation time 1412360547 ps
CPU time 3.76 seconds
Started Aug 15 05:11:52 PM PDT 24
Finished Aug 15 05:11:56 PM PDT 24
Peak memory 214976 kb
Host smart-315811f4-b1eb-4c1f-99d0-587376fc2a71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849295457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1849295457
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3032753781
Short name T192
Test name
Test status
Simulation time 397315338 ps
CPU time 7 seconds
Started Aug 15 05:11:53 PM PDT 24
Finished Aug 15 05:12:00 PM PDT 24
Peak memory 215560 kb
Host smart-5f0bc8a8-f32a-477a-84a8-ba3dc2968a1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032753781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3032753781
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.601578156
Short name T1074
Test name
Test status
Simulation time 100871285 ps
CPU time 2.02 seconds
Started Aug 15 05:11:51 PM PDT 24
Finished Aug 15 05:11:53 PM PDT 24
Peak memory 215168 kb
Host smart-60f642c2-c7b3-4f62-9154-ab34ca6be750
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601578156 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.601578156
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3598682924
Short name T1111
Test name
Test status
Simulation time 156371265 ps
CPU time 2.09 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:11:56 PM PDT 24
Peak memory 215124 kb
Host smart-9c8f7ff1-a2fa-415a-9fe6-f231005c7e3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598682924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3598682924
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2536321957
Short name T1029
Test name
Test status
Simulation time 13465996 ps
CPU time 0.73 seconds
Started Aug 15 05:11:52 PM PDT 24
Finished Aug 15 05:11:52 PM PDT 24
Peak memory 203692 kb
Host smart-87e0dc4b-dfb6-43c4-a5a8-1f25c42e40c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536321957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2536321957
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2080745251
Short name T1064
Test name
Test status
Simulation time 60430567 ps
CPU time 3.98 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:11:58 PM PDT 24
Peak memory 215128 kb
Host smart-2c9a96b3-4bd5-436b-b745-d1fd200caf47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080745251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2080745251
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3929903810
Short name T110
Test name
Test status
Simulation time 38262005 ps
CPU time 2.38 seconds
Started Aug 15 05:11:53 PM PDT 24
Finished Aug 15 05:11:55 PM PDT 24
Peak memory 215284 kb
Host smart-1adf99e9-9ab9-4f06-a17b-650a5786eb5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929903810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3929903810
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1178914461
Short name T1070
Test name
Test status
Simulation time 1068933006 ps
CPU time 24.54 seconds
Started Aug 15 05:11:51 PM PDT 24
Finished Aug 15 05:12:16 PM PDT 24
Peak memory 216052 kb
Host smart-09033444-2be2-482d-97c4-92360ea89a30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178914461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1178914461
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1196415272
Short name T1127
Test name
Test status
Simulation time 495735136 ps
CPU time 3.52 seconds
Started Aug 15 05:11:53 PM PDT 24
Finished Aug 15 05:11:57 PM PDT 24
Peak memory 216076 kb
Host smart-0f257f86-62ed-487f-91c3-273c6780dca8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196415272 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1196415272
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.646470266
Short name T1120
Test name
Test status
Simulation time 144651537 ps
CPU time 2.03 seconds
Started Aug 15 05:11:51 PM PDT 24
Finished Aug 15 05:11:53 PM PDT 24
Peak memory 215024 kb
Host smart-45555076-c27d-4894-b090-a354b8aeb684
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646470266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.646470266
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2566353724
Short name T1075
Test name
Test status
Simulation time 54813663 ps
CPU time 0.75 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:11:55 PM PDT 24
Peak memory 203748 kb
Host smart-9d5089d1-8ddb-4441-a029-240097e3b0a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566353724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2566353724
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2141396245
Short name T1126
Test name
Test status
Simulation time 95864644 ps
CPU time 1.9 seconds
Started Aug 15 05:11:52 PM PDT 24
Finished Aug 15 05:11:54 PM PDT 24
Peak memory 215596 kb
Host smart-d76abb73-e34b-4263-a6e8-0485b1a1f5c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141396245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2141396245
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.925093251
Short name T70
Test name
Test status
Simulation time 216241666 ps
CPU time 3.11 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:11:58 PM PDT 24
Peak memory 215256 kb
Host smart-92cbff25-5484-42d4-88aa-9a4319d381b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925093251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.925093251
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2928345700
Short name T187
Test name
Test status
Simulation time 567203102 ps
CPU time 15.62 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:12:10 PM PDT 24
Peak memory 215564 kb
Host smart-e9e81301-ecd6-4fb6-b4ac-00d461edd81d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928345700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2928345700
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1666190223
Short name T1033
Test name
Test status
Simulation time 448189222 ps
CPU time 2.93 seconds
Started Aug 15 05:11:53 PM PDT 24
Finished Aug 15 05:11:56 PM PDT 24
Peak memory 216668 kb
Host smart-85a83894-57ef-4c66-adf6-db4dec22ddcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666190223 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1666190223
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1483717780
Short name T1017
Test name
Test status
Simulation time 20206212 ps
CPU time 1.26 seconds
Started Aug 15 05:11:51 PM PDT 24
Finished Aug 15 05:11:53 PM PDT 24
Peak memory 215112 kb
Host smart-bc0007ac-f945-43a1-9085-7d0cdf253fcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483717780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1483717780
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1040882281
Short name T1042
Test name
Test status
Simulation time 12896850 ps
CPU time 0.77 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:11:55 PM PDT 24
Peak memory 203684 kb
Host smart-931a301e-74c7-41d1-bb65-6901af6a3bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040882281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1040882281
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4004726126
Short name T1047
Test name
Test status
Simulation time 160341658 ps
CPU time 4.12 seconds
Started Aug 15 05:11:53 PM PDT 24
Finished Aug 15 05:11:57 PM PDT 24
Peak memory 215064 kb
Host smart-7da4b08a-9e45-4bef-b20f-988ca5092e7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004726126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.4004726126
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2046677878
Short name T1129
Test name
Test status
Simulation time 149901122 ps
CPU time 3.91 seconds
Started Aug 15 05:11:53 PM PDT 24
Finished Aug 15 05:11:58 PM PDT 24
Peak memory 215128 kb
Host smart-ec4b5a17-4448-479a-b81f-c6c458f8b892
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046677878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2046677878
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3447681474
Short name T1096
Test name
Test status
Simulation time 294401595 ps
CPU time 19.06 seconds
Started Aug 15 05:11:51 PM PDT 24
Finished Aug 15 05:12:10 PM PDT 24
Peak memory 215508 kb
Host smart-d7a805db-be49-4924-85b1-6f2887b6a403
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447681474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3447681474
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2626835492
Short name T106
Test name
Test status
Simulation time 92978521 ps
CPU time 2.86 seconds
Started Aug 15 05:11:55 PM PDT 24
Finished Aug 15 05:11:58 PM PDT 24
Peak memory 216864 kb
Host smart-ee8542a6-9b38-4666-b3fc-386bf9a6a055
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626835492 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2626835492
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2106168535
Short name T1052
Test name
Test status
Simulation time 176715007 ps
CPU time 2.68 seconds
Started Aug 15 05:11:55 PM PDT 24
Finished Aug 15 05:11:58 PM PDT 24
Peak memory 215028 kb
Host smart-f703ab9f-f38c-4bfe-86a7-d02d7e5001c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106168535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2106168535
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3757040157
Short name T1048
Test name
Test status
Simulation time 40688518 ps
CPU time 0.7 seconds
Started Aug 15 05:11:53 PM PDT 24
Finished Aug 15 05:11:54 PM PDT 24
Peak memory 203624 kb
Host smart-4657d6bb-2aa6-4d04-b811-c3761614a004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757040157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3757040157
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4186443270
Short name T1108
Test name
Test status
Simulation time 158347154 ps
CPU time 1.98 seconds
Started Aug 15 05:11:52 PM PDT 24
Finished Aug 15 05:11:54 PM PDT 24
Peak memory 215060 kb
Host smart-0fb72b3b-40ed-4b10-8eb1-b5eb1c6b93f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186443270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4186443270
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1763669626
Short name T108
Test name
Test status
Simulation time 808200266 ps
CPU time 5.03 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:11:59 PM PDT 24
Peak memory 215280 kb
Host smart-2d2d7ee7-b95b-455e-91e7-d90670b54c5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763669626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1763669626
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1392307765
Short name T118
Test name
Test status
Simulation time 122960781 ps
CPU time 3.38 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:11:58 PM PDT 24
Peak memory 216968 kb
Host smart-4bc306da-d6e4-497a-870b-d73113f3620e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392307765 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1392307765
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3348943312
Short name T132
Test name
Test status
Simulation time 151853229 ps
CPU time 2.12 seconds
Started Aug 15 05:11:51 PM PDT 24
Finished Aug 15 05:11:53 PM PDT 24
Peak memory 215028 kb
Host smart-4b0cd3a8-a547-4961-b125-439da9047090
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348943312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3348943312
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3763531566
Short name T1098
Test name
Test status
Simulation time 38670541 ps
CPU time 0.69 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:11:54 PM PDT 24
Peak memory 203712 kb
Host smart-ac17f625-ab6d-4294-a1c3-f3e1c6374e8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763531566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3763531566
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.580792524
Short name T1116
Test name
Test status
Simulation time 26176164 ps
CPU time 1.71 seconds
Started Aug 15 05:11:51 PM PDT 24
Finished Aug 15 05:11:53 PM PDT 24
Peak memory 215128 kb
Host smart-4a0a55f0-4cc2-4843-bae2-42293fe5cfe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580792524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.580792524
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2705660611
Short name T1104
Test name
Test status
Simulation time 503177427 ps
CPU time 3.76 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:11:58 PM PDT 24
Peak memory 215400 kb
Host smart-555373c3-dba5-4a36-b12d-4d2b26275df2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705660611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2705660611
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4226345690
Short name T1130
Test name
Test status
Simulation time 17115978972 ps
CPU time 24.35 seconds
Started Aug 15 05:11:49 PM PDT 24
Finished Aug 15 05:12:13 PM PDT 24
Peak memory 215744 kb
Host smart-2820d72b-b41d-4fe3-91a9-4f081b988fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226345690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.4226345690
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.981725929
Short name T137
Test name
Test status
Simulation time 2850395768 ps
CPU time 14.68 seconds
Started Aug 15 05:11:24 PM PDT 24
Finished Aug 15 05:11:39 PM PDT 24
Peak memory 206844 kb
Host smart-3beaeddf-831a-4678-ac76-cef936f725fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981725929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.981725929
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2988345705
Short name T127
Test name
Test status
Simulation time 2818846700 ps
CPU time 43.42 seconds
Started Aug 15 05:11:26 PM PDT 24
Finished Aug 15 05:12:10 PM PDT 24
Peak memory 215064 kb
Host smart-aed7b7c7-3538-4bf5-945c-5470ff11cd68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988345705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2988345705
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.693230401
Short name T90
Test name
Test status
Simulation time 172374905 ps
CPU time 1.48 seconds
Started Aug 15 05:11:26 PM PDT 24
Finished Aug 15 05:11:28 PM PDT 24
Peak memory 215020 kb
Host smart-c434dff7-2424-4710-8a02-2035689f318d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693230401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.693230401
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1864321038
Short name T1027
Test name
Test status
Simulation time 151681667 ps
CPU time 2.75 seconds
Started Aug 15 05:11:25 PM PDT 24
Finished Aug 15 05:11:28 PM PDT 24
Peak memory 216708 kb
Host smart-96b03c8b-d5c8-43b4-ad11-e69a895a7f27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864321038 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1864321038
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2062734578
Short name T123
Test name
Test status
Simulation time 158925148 ps
CPU time 2.41 seconds
Started Aug 15 05:11:25 PM PDT 24
Finished Aug 15 05:11:28 PM PDT 24
Peak memory 215040 kb
Host smart-2f08460e-d3bf-460f-b497-9155af8fd9eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062734578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
062734578
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3110503503
Short name T1041
Test name
Test status
Simulation time 35357057 ps
CPU time 0.76 seconds
Started Aug 15 05:11:24 PM PDT 24
Finished Aug 15 05:11:25 PM PDT 24
Peak memory 203832 kb
Host smart-83719b00-69b0-413f-8bbf-db01a38d2630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110503503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
110503503
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1470400678
Short name T131
Test name
Test status
Simulation time 585812714 ps
CPU time 1.71 seconds
Started Aug 15 05:11:25 PM PDT 24
Finished Aug 15 05:11:27 PM PDT 24
Peak memory 215060 kb
Host smart-f988f41f-f769-42cf-bebe-9dd81fdc608f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470400678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1470400678
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3119905409
Short name T1030
Test name
Test status
Simulation time 22710801 ps
CPU time 0.69 seconds
Started Aug 15 05:11:24 PM PDT 24
Finished Aug 15 05:11:25 PM PDT 24
Peak memory 203500 kb
Host smart-f81356ca-d89e-4d02-9248-b81502002d3a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119905409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3119905409
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1440092966
Short name T1039
Test name
Test status
Simulation time 2852179795 ps
CPU time 3.79 seconds
Started Aug 15 05:11:24 PM PDT 24
Finished Aug 15 05:11:28 PM PDT 24
Peak memory 215148 kb
Host smart-14ce0d3d-96bf-4fb6-97ca-a9a1e451ad2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440092966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1440092966
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.833291982
Short name T112
Test name
Test status
Simulation time 487586142 ps
CPU time 3.29 seconds
Started Aug 15 05:11:24 PM PDT 24
Finished Aug 15 05:11:28 PM PDT 24
Peak memory 216188 kb
Host smart-d648bfba-0a22-49cc-93e1-849e4b6b8303
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833291982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.833291982
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2507604047
Short name T1086
Test name
Test status
Simulation time 21752037 ps
CPU time 0.75 seconds
Started Aug 15 05:11:55 PM PDT 24
Finished Aug 15 05:11:56 PM PDT 24
Peak memory 203744 kb
Host smart-ea0fe567-c3a5-4374-a294-b2632ead8bab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507604047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2507604047
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1574782517
Short name T1045
Test name
Test status
Simulation time 40800540 ps
CPU time 0.72 seconds
Started Aug 15 05:11:53 PM PDT 24
Finished Aug 15 05:11:54 PM PDT 24
Peak memory 203672 kb
Host smart-1db0aa76-5040-4031-8ecd-240cc1c60607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574782517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1574782517
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4246198364
Short name T1051
Test name
Test status
Simulation time 31905068 ps
CPU time 0.72 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:11:55 PM PDT 24
Peak memory 203688 kb
Host smart-688d50b9-8034-4430-a15d-805cac0ce213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246198364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4246198364
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3195518594
Short name T1099
Test name
Test status
Simulation time 24566153 ps
CPU time 0.76 seconds
Started Aug 15 05:11:53 PM PDT 24
Finished Aug 15 05:11:54 PM PDT 24
Peak memory 203644 kb
Host smart-8ac65dc5-cc91-4b73-9319-9645146af8cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195518594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3195518594
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2422428581
Short name T1078
Test name
Test status
Simulation time 54618345 ps
CPU time 0.73 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:11:54 PM PDT 24
Peak memory 203676 kb
Host smart-4595c3f9-bcc5-4480-827b-7dc3cc0b745b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422428581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2422428581
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2344668954
Short name T1036
Test name
Test status
Simulation time 47245924 ps
CPU time 0.7 seconds
Started Aug 15 05:11:52 PM PDT 24
Finished Aug 15 05:11:53 PM PDT 24
Peak memory 203984 kb
Host smart-efed5415-3764-472e-94c5-5f4122d26517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344668954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2344668954
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.810563164
Short name T1123
Test name
Test status
Simulation time 22888232 ps
CPU time 0.78 seconds
Started Aug 15 05:11:54 PM PDT 24
Finished Aug 15 05:11:55 PM PDT 24
Peak memory 203684 kb
Host smart-050fd33e-ab5a-4d60-8686-fdaba88fc7e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810563164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.810563164
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2492067629
Short name T1063
Test name
Test status
Simulation time 50101749 ps
CPU time 0.74 seconds
Started Aug 15 05:11:51 PM PDT 24
Finished Aug 15 05:11:52 PM PDT 24
Peak memory 203536 kb
Host smart-f8f6d8aa-59bb-42c6-ac04-a58546307236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492067629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2492067629
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3544454956
Short name T1021
Test name
Test status
Simulation time 53886687 ps
CPU time 0.78 seconds
Started Aug 15 05:11:55 PM PDT 24
Finished Aug 15 05:11:56 PM PDT 24
Peak memory 203692 kb
Host smart-909edb02-0920-45b4-9b0f-523b27d080cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544454956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3544454956
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3009941228
Short name T1094
Test name
Test status
Simulation time 15017285 ps
CPU time 0.76 seconds
Started Aug 15 05:11:51 PM PDT 24
Finished Aug 15 05:11:52 PM PDT 24
Peak memory 203668 kb
Host smart-c2c5814b-f017-4ef8-8008-76e356c38be8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009941228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3009941228
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1608095797
Short name T136
Test name
Test status
Simulation time 627499779 ps
CPU time 21.92 seconds
Started Aug 15 05:11:32 PM PDT 24
Finished Aug 15 05:11:54 PM PDT 24
Peak memory 215032 kb
Host smart-9635a85c-240e-4e4a-892d-beca8889a208
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608095797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1608095797
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1706900721
Short name T138
Test name
Test status
Simulation time 357584322 ps
CPU time 12.2 seconds
Started Aug 15 05:11:32 PM PDT 24
Finished Aug 15 05:11:45 PM PDT 24
Peak memory 215048 kb
Host smart-120ed143-bfe9-4d3c-a76b-4d97a055cd95
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706900721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1706900721
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.610257255
Short name T91
Test name
Test status
Simulation time 22137949 ps
CPU time 0.99 seconds
Started Aug 15 05:11:31 PM PDT 24
Finished Aug 15 05:11:32 PM PDT 24
Peak memory 206592 kb
Host smart-b40e50ef-a4b2-4158-820d-2210e4e3a4e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610257255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.610257255
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2528232894
Short name T1081
Test name
Test status
Simulation time 56829835 ps
CPU time 1.83 seconds
Started Aug 15 05:11:36 PM PDT 24
Finished Aug 15 05:11:38 PM PDT 24
Peak memory 215068 kb
Host smart-6fd71f08-bfe2-4c61-ab27-f51bf982219d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528232894 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2528232894
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2001060175
Short name T122
Test name
Test status
Simulation time 64532181 ps
CPU time 1.87 seconds
Started Aug 15 05:11:31 PM PDT 24
Finished Aug 15 05:11:33 PM PDT 24
Peak memory 214956 kb
Host smart-02e061d9-d600-4b5d-be12-01539f3688d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001060175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
001060175
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2823135583
Short name T1056
Test name
Test status
Simulation time 50362078 ps
CPU time 0.77 seconds
Started Aug 15 05:11:32 PM PDT 24
Finished Aug 15 05:11:33 PM PDT 24
Peak memory 203984 kb
Host smart-cc7ff6c3-3713-4716-9bec-b6f586e9b439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823135583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
823135583
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.279329201
Short name T1079
Test name
Test status
Simulation time 262149031 ps
CPU time 2.68 seconds
Started Aug 15 05:11:32 PM PDT 24
Finished Aug 15 05:11:35 PM PDT 24
Peak memory 215104 kb
Host smart-95bd2ba0-d561-465d-b8d7-4e97bc6cfeec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279329201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.279329201
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4022877662
Short name T1049
Test name
Test status
Simulation time 21162079 ps
CPU time 0.66 seconds
Started Aug 15 05:11:30 PM PDT 24
Finished Aug 15 05:11:31 PM PDT 24
Peak memory 202328 kb
Host smart-630a974d-5fb0-45ee-9362-f8c05721e4b9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022877662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4022877662
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3855201023
Short name T1025
Test name
Test status
Simulation time 59974886 ps
CPU time 3.69 seconds
Started Aug 15 05:11:32 PM PDT 24
Finished Aug 15 05:11:35 PM PDT 24
Peak memory 215104 kb
Host smart-300220c5-dad7-48b9-b443-ed5a63a238f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855201023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3855201023
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.259062047
Short name T1090
Test name
Test status
Simulation time 1458439674 ps
CPU time 5.53 seconds
Started Aug 15 05:11:23 PM PDT 24
Finished Aug 15 05:11:28 PM PDT 24
Peak memory 215228 kb
Host smart-998bce85-5a9b-44ee-946a-38e0570cdca8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259062047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.259062047
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.788127002
Short name T1121
Test name
Test status
Simulation time 224218068 ps
CPU time 6.4 seconds
Started Aug 15 05:11:33 PM PDT 24
Finished Aug 15 05:11:40 PM PDT 24
Peak memory 215096 kb
Host smart-d561e9f1-cdab-4bf9-9959-1b45ebdddc32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788127002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.788127002
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.184511169
Short name T1034
Test name
Test status
Simulation time 167526364 ps
CPU time 0.82 seconds
Started Aug 15 05:12:03 PM PDT 24
Finished Aug 15 05:12:04 PM PDT 24
Peak memory 204052 kb
Host smart-c401f675-03c2-45fb-bb84-7eaf40be8004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184511169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.184511169
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.668646584
Short name T1093
Test name
Test status
Simulation time 20831772 ps
CPU time 0.76 seconds
Started Aug 15 05:12:04 PM PDT 24
Finished Aug 15 05:12:05 PM PDT 24
Peak memory 203740 kb
Host smart-ccca27a8-0a63-4abd-9834-361789373118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668646584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.668646584
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3343014000
Short name T1066
Test name
Test status
Simulation time 16582335 ps
CPU time 0.77 seconds
Started Aug 15 05:12:03 PM PDT 24
Finished Aug 15 05:12:04 PM PDT 24
Peak memory 203704 kb
Host smart-194446cf-9869-42f2-a491-93f5a05b50f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343014000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3343014000
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1836176937
Short name T1107
Test name
Test status
Simulation time 25317731 ps
CPU time 0.72 seconds
Started Aug 15 05:12:02 PM PDT 24
Finished Aug 15 05:12:03 PM PDT 24
Peak memory 203732 kb
Host smart-34110c29-7ac8-4776-b4d2-eb8e4316c941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836176937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1836176937
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1642300289
Short name T1054
Test name
Test status
Simulation time 31567876 ps
CPU time 0.73 seconds
Started Aug 15 05:12:04 PM PDT 24
Finished Aug 15 05:12:05 PM PDT 24
Peak memory 204024 kb
Host smart-7f11fc82-b6dd-4df2-b3b5-87f72a0da73f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642300289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1642300289
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3188427494
Short name T1022
Test name
Test status
Simulation time 44728991 ps
CPU time 0.77 seconds
Started Aug 15 05:12:03 PM PDT 24
Finished Aug 15 05:12:04 PM PDT 24
Peak memory 203716 kb
Host smart-ac1cd4d5-b433-4ea4-9d61-1efe752e50cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188427494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3188427494
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1987508669
Short name T1031
Test name
Test status
Simulation time 16827487 ps
CPU time 0.78 seconds
Started Aug 15 05:12:03 PM PDT 24
Finished Aug 15 05:12:03 PM PDT 24
Peak memory 204044 kb
Host smart-19c2bedc-b553-46d8-a563-d13811dfe986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987508669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1987508669
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1693505289
Short name T1023
Test name
Test status
Simulation time 18824755 ps
CPU time 0.74 seconds
Started Aug 15 05:12:03 PM PDT 24
Finished Aug 15 05:12:05 PM PDT 24
Peak memory 204036 kb
Host smart-1bedda5c-d678-40f9-b0a6-a84e61a5697b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693505289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1693505289
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2519529812
Short name T1124
Test name
Test status
Simulation time 59752058 ps
CPU time 0.7 seconds
Started Aug 15 05:12:04 PM PDT 24
Finished Aug 15 05:12:05 PM PDT 24
Peak memory 204012 kb
Host smart-7082fd35-bf22-481f-9a60-a6838effe8b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519529812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2519529812
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1857190229
Short name T1097
Test name
Test status
Simulation time 17230486 ps
CPU time 0.77 seconds
Started Aug 15 05:12:03 PM PDT 24
Finished Aug 15 05:12:04 PM PDT 24
Peak memory 203704 kb
Host smart-0d5a5ce1-2a6f-47e5-9ee8-1364084a1925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857190229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1857190229
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3971041000
Short name T124
Test name
Test status
Simulation time 1705396118 ps
CPU time 19.81 seconds
Started Aug 15 05:11:33 PM PDT 24
Finished Aug 15 05:11:53 PM PDT 24
Peak memory 215048 kb
Host smart-96e19c32-8ec0-4671-8d4f-a81fd7d79952
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971041000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3971041000
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3950290437
Short name T1069
Test name
Test status
Simulation time 634512583 ps
CPU time 13.47 seconds
Started Aug 15 05:11:32 PM PDT 24
Finished Aug 15 05:11:46 PM PDT 24
Peak memory 206852 kb
Host smart-ab7dd2f1-1af8-4d5e-84c0-66817952f4db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950290437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3950290437
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.887008031
Short name T1131
Test name
Test status
Simulation time 24558692 ps
CPU time 1.02 seconds
Started Aug 15 05:11:32 PM PDT 24
Finished Aug 15 05:11:33 PM PDT 24
Peak memory 206736 kb
Host smart-972256fe-7bd4-4334-a3b2-a10a0197fd09
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887008031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.887008031
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3550616674
Short name T1082
Test name
Test status
Simulation time 26212894 ps
CPU time 1.72 seconds
Started Aug 15 05:11:34 PM PDT 24
Finished Aug 15 05:11:36 PM PDT 24
Peak memory 216208 kb
Host smart-b1ec23b3-70de-4eff-b56e-3986162eef82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550616674 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3550616674
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2259289831
Short name T1128
Test name
Test status
Simulation time 551438025 ps
CPU time 2.42 seconds
Started Aug 15 05:11:33 PM PDT 24
Finished Aug 15 05:11:36 PM PDT 24
Peak memory 214960 kb
Host smart-f9ec572a-6446-4bb1-ab65-6109b4796337
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259289831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
259289831
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.928168444
Short name T1105
Test name
Test status
Simulation time 73171188 ps
CPU time 0.73 seconds
Started Aug 15 05:11:32 PM PDT 24
Finished Aug 15 05:11:33 PM PDT 24
Peak memory 203664 kb
Host smart-e2f3c3b0-28a2-407d-8c4a-cbad02a63554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928168444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.928168444
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1454946162
Short name T125
Test name
Test status
Simulation time 25553552 ps
CPU time 1.82 seconds
Started Aug 15 05:11:33 PM PDT 24
Finished Aug 15 05:11:35 PM PDT 24
Peak memory 215040 kb
Host smart-293127da-b864-4295-9397-ff0bde503905
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454946162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1454946162
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1787317959
Short name T1044
Test name
Test status
Simulation time 17374974 ps
CPU time 0.68 seconds
Started Aug 15 05:11:35 PM PDT 24
Finished Aug 15 05:11:36 PM PDT 24
Peak memory 203524 kb
Host smart-223d7dc8-c6a2-4f7d-b514-4b232fc1fdb3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787317959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1787317959
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2108475115
Short name T163
Test name
Test status
Simulation time 477859669 ps
CPU time 2.85 seconds
Started Aug 15 05:11:34 PM PDT 24
Finished Aug 15 05:11:37 PM PDT 24
Peak memory 215036 kb
Host smart-1cf6b7c8-12b6-49cf-b9a3-b37b2e498974
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108475115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2108475115
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3702580789
Short name T1057
Test name
Test status
Simulation time 395384929 ps
CPU time 1.95 seconds
Started Aug 15 05:11:32 PM PDT 24
Finished Aug 15 05:11:34 PM PDT 24
Peak memory 215296 kb
Host smart-53c6e01c-67e9-46a1-8302-3dc874b5b26e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702580789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
702580789
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4282180432
Short name T104
Test name
Test status
Simulation time 4236692706 ps
CPU time 22.23 seconds
Started Aug 15 05:11:31 PM PDT 24
Finished Aug 15 05:11:54 PM PDT 24
Peak memory 215108 kb
Host smart-b6de2273-caaa-44a1-96b9-caed262cbdf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282180432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.4282180432
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3976189932
Short name T1053
Test name
Test status
Simulation time 36221460 ps
CPU time 0.82 seconds
Started Aug 15 05:12:03 PM PDT 24
Finished Aug 15 05:12:04 PM PDT 24
Peak memory 203776 kb
Host smart-57ca5242-5c53-4bbf-9583-39855a15df3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976189932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3976189932
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3515401322
Short name T1112
Test name
Test status
Simulation time 22630797 ps
CPU time 0.74 seconds
Started Aug 15 05:12:05 PM PDT 24
Finished Aug 15 05:12:06 PM PDT 24
Peak memory 203732 kb
Host smart-e0ddfe9b-8a7d-477a-b73f-a32cb34d0912
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515401322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3515401322
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3266166815
Short name T1019
Test name
Test status
Simulation time 19620080 ps
CPU time 0.77 seconds
Started Aug 15 05:12:05 PM PDT 24
Finished Aug 15 05:12:06 PM PDT 24
Peak memory 203692 kb
Host smart-f1f27e9c-05f0-4aee-9e76-0a9ab5ddc2cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266166815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3266166815
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2033245593
Short name T1050
Test name
Test status
Simulation time 166187374 ps
CPU time 0.76 seconds
Started Aug 15 05:12:04 PM PDT 24
Finished Aug 15 05:12:05 PM PDT 24
Peak memory 203744 kb
Host smart-01a11e95-8585-415b-ac6f-7a3ee113410b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033245593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2033245593
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1374879916
Short name T1040
Test name
Test status
Simulation time 47067372 ps
CPU time 0.81 seconds
Started Aug 15 05:12:03 PM PDT 24
Finished Aug 15 05:12:03 PM PDT 24
Peak memory 203700 kb
Host smart-ba001d1b-ae00-4cdb-857e-c180c7987f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374879916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1374879916
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.647447396
Short name T1028
Test name
Test status
Simulation time 13734783 ps
CPU time 0.72 seconds
Started Aug 15 05:12:09 PM PDT 24
Finished Aug 15 05:12:10 PM PDT 24
Peak memory 204044 kb
Host smart-0fdfd465-24d9-4a84-bb16-7d85b0dbde7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647447396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.647447396
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3593386165
Short name T1102
Test name
Test status
Simulation time 41863580 ps
CPU time 0.7 seconds
Started Aug 15 05:12:09 PM PDT 24
Finished Aug 15 05:12:10 PM PDT 24
Peak memory 203696 kb
Host smart-53fa573f-3606-4334-a3dc-0bffacb99a8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593386165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3593386165
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2538799280
Short name T1043
Test name
Test status
Simulation time 31791456 ps
CPU time 0.76 seconds
Started Aug 15 05:12:03 PM PDT 24
Finished Aug 15 05:12:04 PM PDT 24
Peak memory 203620 kb
Host smart-1dbf063b-c8c2-4365-9623-92b6fb4cb336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538799280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2538799280
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2448731526
Short name T1072
Test name
Test status
Simulation time 58110279 ps
CPU time 0.77 seconds
Started Aug 15 05:12:04 PM PDT 24
Finished Aug 15 05:12:05 PM PDT 24
Peak memory 203940 kb
Host smart-f4cf74b4-62e2-432e-b3c1-6e9eee7491f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448731526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2448731526
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2493238801
Short name T1015
Test name
Test status
Simulation time 146105825 ps
CPU time 0.73 seconds
Started Aug 15 05:12:03 PM PDT 24
Finished Aug 15 05:12:05 PM PDT 24
Peak memory 203724 kb
Host smart-e575feee-7a8c-48c5-ad80-b04a5cf2206d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493238801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2493238801
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1069183950
Short name T102
Test name
Test status
Simulation time 204816123 ps
CPU time 3.55 seconds
Started Aug 15 05:11:31 PM PDT 24
Finished Aug 15 05:11:35 PM PDT 24
Peak memory 216844 kb
Host smart-ae221e5b-cf27-4b60-b1b7-2bafc7c4c4ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069183950 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1069183950
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3008864869
Short name T130
Test name
Test status
Simulation time 143409304 ps
CPU time 1.25 seconds
Started Aug 15 05:11:31 PM PDT 24
Finished Aug 15 05:11:33 PM PDT 24
Peak memory 215132 kb
Host smart-f2018c59-ca7a-4278-9957-9e2d52dc3267
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008864869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
008864869
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2883190737
Short name T1037
Test name
Test status
Simulation time 17601208 ps
CPU time 0.73 seconds
Started Aug 15 05:11:34 PM PDT 24
Finished Aug 15 05:11:35 PM PDT 24
Peak memory 203716 kb
Host smart-42baf1cc-0bb2-4b66-9093-bdde306617f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883190737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
883190737
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2231765390
Short name T1071
Test name
Test status
Simulation time 893486467 ps
CPU time 4.63 seconds
Started Aug 15 05:11:34 PM PDT 24
Finished Aug 15 05:11:39 PM PDT 24
Peak memory 215028 kb
Host smart-81a65ef6-ec5c-4f0b-8b23-572f79846c25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231765390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2231765390
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.806927801
Short name T116
Test name
Test status
Simulation time 32340775 ps
CPU time 2.07 seconds
Started Aug 15 05:11:32 PM PDT 24
Finished Aug 15 05:11:34 PM PDT 24
Peak memory 215168 kb
Host smart-51c41285-7e62-4101-8f73-c21847f383cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806927801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.806927801
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4076066299
Short name T190
Test name
Test status
Simulation time 2392283628 ps
CPU time 13.27 seconds
Started Aug 15 05:11:31 PM PDT 24
Finished Aug 15 05:11:45 PM PDT 24
Peak memory 216724 kb
Host smart-200eeaff-bcce-4118-b142-6c1458f65e25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076066299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.4076066299
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3719255965
Short name T72
Test name
Test status
Simulation time 75688815 ps
CPU time 1.72 seconds
Started Aug 15 05:11:45 PM PDT 24
Finished Aug 15 05:11:47 PM PDT 24
Peak memory 216220 kb
Host smart-84cbb6a5-f114-495c-a251-095fa86f1f21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719255965 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3719255965
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.710346786
Short name T134
Test name
Test status
Simulation time 1666466849 ps
CPU time 2.41 seconds
Started Aug 15 05:11:31 PM PDT 24
Finished Aug 15 05:11:34 PM PDT 24
Peak memory 215116 kb
Host smart-8b93ea68-409d-4fe9-ba7e-e0ef6e5e286b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710346786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.710346786
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1636645621
Short name T1046
Test name
Test status
Simulation time 39002810 ps
CPU time 0.71 seconds
Started Aug 15 05:11:32 PM PDT 24
Finished Aug 15 05:11:33 PM PDT 24
Peak memory 203636 kb
Host smart-99cd7b70-2211-45cd-bd4d-eba5adfcc061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636645621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
636645621
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1685104632
Short name T165
Test name
Test status
Simulation time 72074185 ps
CPU time 1.99 seconds
Started Aug 15 05:11:40 PM PDT 24
Finished Aug 15 05:11:42 PM PDT 24
Peak memory 215056 kb
Host smart-9c15c69d-da79-49a9-977b-4b2b8e057356
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685104632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1685104632
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.703580316
Short name T1088
Test name
Test status
Simulation time 78539465 ps
CPU time 4.39 seconds
Started Aug 15 05:11:35 PM PDT 24
Finished Aug 15 05:11:39 PM PDT 24
Peak memory 215296 kb
Host smart-438f7395-c64d-49b3-903a-8d64022bfb79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703580316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.703580316
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.115613352
Short name T1091
Test name
Test status
Simulation time 198987582 ps
CPU time 11.67 seconds
Started Aug 15 05:11:34 PM PDT 24
Finished Aug 15 05:11:46 PM PDT 24
Peak memory 215120 kb
Host smart-90cd24a4-47b5-4c49-ad38-9f80fc82fe14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115613352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.115613352
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2237699210
Short name T120
Test name
Test status
Simulation time 281578859 ps
CPU time 3.52 seconds
Started Aug 15 05:11:41 PM PDT 24
Finished Aug 15 05:11:45 PM PDT 24
Peak memory 217240 kb
Host smart-6ae9c315-83ef-46a7-8209-054cd61baf8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237699210 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2237699210
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3027704752
Short name T162
Test name
Test status
Simulation time 145767610 ps
CPU time 2.11 seconds
Started Aug 15 05:11:42 PM PDT 24
Finished Aug 15 05:11:44 PM PDT 24
Peak memory 214912 kb
Host smart-34d86420-1c94-420a-9cb3-db24079890f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027704752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
027704752
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.195003321
Short name T1114
Test name
Test status
Simulation time 19909137 ps
CPU time 0.77 seconds
Started Aug 15 05:11:43 PM PDT 24
Finished Aug 15 05:11:44 PM PDT 24
Peak memory 203708 kb
Host smart-5f89ccc0-2344-45f1-a040-7433a235bee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195003321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.195003321
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1728790021
Short name T164
Test name
Test status
Simulation time 208091721 ps
CPU time 4.37 seconds
Started Aug 15 05:11:43 PM PDT 24
Finished Aug 15 05:11:48 PM PDT 24
Peak memory 215124 kb
Host smart-4ea1fb65-69ef-4c7a-b62a-6b19044f2f3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728790021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1728790021
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3079769101
Short name T183
Test name
Test status
Simulation time 63910697 ps
CPU time 3.96 seconds
Started Aug 15 05:11:41 PM PDT 24
Finished Aug 15 05:11:45 PM PDT 24
Peak memory 215400 kb
Host smart-d79d33ee-ea0f-4334-ba6a-891bfb022f89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079769101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
079769101
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2879683319
Short name T186
Test name
Test status
Simulation time 563892470 ps
CPU time 14.8 seconds
Started Aug 15 05:11:41 PM PDT 24
Finished Aug 15 05:11:56 PM PDT 24
Peak memory 215144 kb
Host smart-95de64b1-cc35-485e-a1b0-027a8aaab208
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879683319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2879683319
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3634217960
Short name T1109
Test name
Test status
Simulation time 190663339 ps
CPU time 2.91 seconds
Started Aug 15 05:11:43 PM PDT 24
Finished Aug 15 05:11:46 PM PDT 24
Peak memory 217732 kb
Host smart-3e68f876-fd69-4965-8366-893aeb50eb50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634217960 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3634217960
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2020689537
Short name T133
Test name
Test status
Simulation time 61233831 ps
CPU time 1.35 seconds
Started Aug 15 05:11:45 PM PDT 24
Finished Aug 15 05:11:46 PM PDT 24
Peak memory 215080 kb
Host smart-4319053e-3c99-4278-bfe6-3f06966db9c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020689537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
020689537
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2684800560
Short name T1026
Test name
Test status
Simulation time 16271604 ps
CPU time 0.69 seconds
Started Aug 15 05:11:43 PM PDT 24
Finished Aug 15 05:11:44 PM PDT 24
Peak memory 203732 kb
Host smart-8cf41e7b-88f0-4479-a78b-e3e693e09120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684800560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
684800560
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3438996832
Short name T1113
Test name
Test status
Simulation time 138525003 ps
CPU time 3.83 seconds
Started Aug 15 05:11:43 PM PDT 24
Finished Aug 15 05:11:47 PM PDT 24
Peak memory 215040 kb
Host smart-a97abcd3-073a-4a0b-9f94-62a49b715500
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438996832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3438996832
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3424905023
Short name T184
Test name
Test status
Simulation time 180976310 ps
CPU time 4.93 seconds
Started Aug 15 05:11:44 PM PDT 24
Finished Aug 15 05:11:49 PM PDT 24
Peak memory 215280 kb
Host smart-f5ff0852-c8c4-4fb8-96d8-61480424064d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424905023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
424905023
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1954676257
Short name T103
Test name
Test status
Simulation time 271399123 ps
CPU time 12.37 seconds
Started Aug 15 05:11:42 PM PDT 24
Finished Aug 15 05:11:55 PM PDT 24
Peak memory 215116 kb
Host smart-6a596547-a4c3-4706-b035-3a6500b5eeb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954676257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1954676257
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1883944135
Short name T1087
Test name
Test status
Simulation time 60922992 ps
CPU time 4.43 seconds
Started Aug 15 05:11:44 PM PDT 24
Finished Aug 15 05:11:49 PM PDT 24
Peak memory 217128 kb
Host smart-b011a372-45c1-40cc-a40b-32d1449a3a49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883944135 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1883944135
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2791823716
Short name T1032
Test name
Test status
Simulation time 34227921 ps
CPU time 1.2 seconds
Started Aug 15 05:11:41 PM PDT 24
Finished Aug 15 05:11:42 PM PDT 24
Peak memory 206796 kb
Host smart-95d772ec-6998-43b5-904a-b5eebecaee29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791823716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
791823716
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.579409569
Short name T1073
Test name
Test status
Simulation time 15776777 ps
CPU time 0.72 seconds
Started Aug 15 05:11:42 PM PDT 24
Finished Aug 15 05:11:43 PM PDT 24
Peak memory 203716 kb
Host smart-be4c7399-8a6d-44ba-9e25-bd5234cba54e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579409569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.579409569
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2080071747
Short name T1080
Test name
Test status
Simulation time 266829724 ps
CPU time 2.06 seconds
Started Aug 15 05:11:46 PM PDT 24
Finished Aug 15 05:11:48 PM PDT 24
Peak memory 215032 kb
Host smart-de92e4ec-8d05-4fe7-8725-3e77d1eac208
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080071747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2080071747
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.505080587
Short name T109
Test name
Test status
Simulation time 86184435 ps
CPU time 2.22 seconds
Started Aug 15 05:11:41 PM PDT 24
Finished Aug 15 05:11:43 PM PDT 24
Peak memory 215272 kb
Host smart-eae54648-a491-4c40-8991-b952ddfa7217
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505080587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.505080587
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3360868498
Short name T1077
Test name
Test status
Simulation time 263354126 ps
CPU time 7.2 seconds
Started Aug 15 05:11:41 PM PDT 24
Finished Aug 15 05:11:48 PM PDT 24
Peak memory 222872 kb
Host smart-33044caa-b444-4fe1-a09b-8daf1822370f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360868498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3360868498
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2217560021
Short name T946
Test name
Test status
Simulation time 5030683918 ps
CPU time 10.18 seconds
Started Aug 15 05:13:12 PM PDT 24
Finished Aug 15 05:13:23 PM PDT 24
Peak memory 233648 kb
Host smart-0a457088-f3cf-4c29-84c2-5de9c8bd758b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217560021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2217560021
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2999530218
Short name T392
Test name
Test status
Simulation time 34334987 ps
CPU time 0.86 seconds
Started Aug 15 05:13:02 PM PDT 24
Finished Aug 15 05:13:03 PM PDT 24
Peak memory 207716 kb
Host smart-6229b1b9-9b3d-45f8-94dc-621f40b643cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999530218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2999530218
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2280937082
Short name T235
Test name
Test status
Simulation time 280375927 ps
CPU time 8.2 seconds
Started Aug 15 05:13:00 PM PDT 24
Finished Aug 15 05:13:08 PM PDT 24
Peak memory 233396 kb
Host smart-3145caaf-4008-4fa9-86f0-6e717fbf48c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280937082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2280937082
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.648537446
Short name T739
Test name
Test status
Simulation time 190538290499 ps
CPU time 291.7 seconds
Started Aug 15 05:13:09 PM PDT 24
Finished Aug 15 05:18:01 PM PDT 24
Peak memory 240792 kb
Host smart-a9fa245d-a907-483c-b526-b9fe66e78b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648537446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
648537446
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3566473423
Short name T518
Test name
Test status
Simulation time 1690760423 ps
CPU time 14.34 seconds
Started Aug 15 05:13:09 PM PDT 24
Finished Aug 15 05:13:24 PM PDT 24
Peak memory 225240 kb
Host smart-e66c64b5-a54b-4e15-800b-c3ec71979396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566473423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3566473423
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1008583430
Short name T706
Test name
Test status
Simulation time 477233320 ps
CPU time 10.71 seconds
Started Aug 15 05:13:03 PM PDT 24
Finished Aug 15 05:13:14 PM PDT 24
Peak memory 225344 kb
Host smart-3b28baba-ac2f-423d-9645-e9c620d0eb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008583430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1008583430
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1840201358
Short name T976
Test name
Test status
Simulation time 2495715392 ps
CPU time 7.16 seconds
Started Aug 15 05:13:08 PM PDT 24
Finished Aug 15 05:13:16 PM PDT 24
Peak memory 233716 kb
Host smart-d4ce6f24-c422-4fce-b569-0c58dc38d435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840201358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1840201358
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4265819249
Short name T632
Test name
Test status
Simulation time 9320862176 ps
CPU time 28.47 seconds
Started Aug 15 05:13:00 PM PDT 24
Finished Aug 15 05:13:28 PM PDT 24
Peak memory 250060 kb
Host smart-d1f9caba-47ae-4c59-b544-1b2ea152561e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265819249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4265819249
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.411829145
Short name T695
Test name
Test status
Simulation time 5622696569 ps
CPU time 8.54 seconds
Started Aug 15 05:13:11 PM PDT 24
Finished Aug 15 05:13:20 PM PDT 24
Peak memory 222532 kb
Host smart-4754cb4c-01dc-473e-b508-72058dbe0950
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=411829145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.411829145
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.258633346
Short name T861
Test name
Test status
Simulation time 32343355396 ps
CPU time 313.8 seconds
Started Aug 15 05:13:12 PM PDT 24
Finished Aug 15 05:18:26 PM PDT 24
Peak memory 255676 kb
Host smart-c17e2d30-97cf-4cd0-9bbf-d0b17fb715ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258633346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.258633346
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1494299183
Short name T797
Test name
Test status
Simulation time 2202960066 ps
CPU time 18.69 seconds
Started Aug 15 05:13:11 PM PDT 24
Finished Aug 15 05:13:30 PM PDT 24
Peak memory 217436 kb
Host smart-926f27fe-cd79-464b-8559-09580725da0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494299183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1494299183
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3527946870
Short name T497
Test name
Test status
Simulation time 2742282022 ps
CPU time 7.27 seconds
Started Aug 15 05:13:02 PM PDT 24
Finished Aug 15 05:13:10 PM PDT 24
Peak memory 217332 kb
Host smart-75245c10-bcb9-442e-9c15-a63b28a0e524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527946870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3527946870
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2681627380
Short name T967
Test name
Test status
Simulation time 466463670 ps
CPU time 1.02 seconds
Started Aug 15 05:13:02 PM PDT 24
Finished Aug 15 05:13:03 PM PDT 24
Peak memory 207816 kb
Host smart-d1cab839-9e2b-4019-95e0-555ac9b7f0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681627380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2681627380
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2134036385
Short name T785
Test name
Test status
Simulation time 55385223 ps
CPU time 0.89 seconds
Started Aug 15 05:13:11 PM PDT 24
Finished Aug 15 05:13:12 PM PDT 24
Peak memory 206816 kb
Host smart-a60240d6-39b8-4751-bc31-2704839c7ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134036385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2134036385
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2883098744
Short name T26
Test name
Test status
Simulation time 12610152776 ps
CPU time 11.89 seconds
Started Aug 15 05:13:01 PM PDT 24
Finished Aug 15 05:13:13 PM PDT 24
Peak memory 241428 kb
Host smart-8bb5c971-96b6-45e5-96d2-96bfc858f5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883098744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2883098744
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.42514620
Short name T411
Test name
Test status
Simulation time 14982869 ps
CPU time 0.75 seconds
Started Aug 15 05:13:10 PM PDT 24
Finished Aug 15 05:13:11 PM PDT 24
Peak memory 205716 kb
Host smart-5d6c6540-1804-4e8a-8316-471bb142cf4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42514620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.42514620
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2532417703
Short name T498
Test name
Test status
Simulation time 486952750 ps
CPU time 6.49 seconds
Started Aug 15 05:13:02 PM PDT 24
Finished Aug 15 05:13:08 PM PDT 24
Peak memory 233508 kb
Host smart-4a2f84b2-c690-4299-ade3-edc7aded6c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532417703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2532417703
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.357027911
Short name T792
Test name
Test status
Simulation time 17480445 ps
CPU time 0.81 seconds
Started Aug 15 05:13:12 PM PDT 24
Finished Aug 15 05:13:13 PM PDT 24
Peak memory 206648 kb
Host smart-6e22121d-47a9-42ba-876e-c3bc35650a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357027911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.357027911
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2413543498
Short name T291
Test name
Test status
Simulation time 81527799536 ps
CPU time 553.18 seconds
Started Aug 15 05:13:11 PM PDT 24
Finished Aug 15 05:22:25 PM PDT 24
Peak memory 269120 kb
Host smart-e9da7ba7-257d-4f0c-a8e1-7538e0786e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413543498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2413543498
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1004863217
Short name T599
Test name
Test status
Simulation time 6590692942 ps
CPU time 114.2 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:15:12 PM PDT 24
Peak memory 254240 kb
Host smart-7c45d9d1-9527-409c-93af-6f38d58490fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004863217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1004863217
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3928070460
Short name T905
Test name
Test status
Simulation time 130549025792 ps
CPU time 360.05 seconds
Started Aug 15 05:13:09 PM PDT 24
Finished Aug 15 05:19:10 PM PDT 24
Peak memory 268876 kb
Host smart-69449300-408b-48d0-8dc9-ec435f6c4322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928070460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3928070460
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.505151489
Short name T437
Test name
Test status
Simulation time 256918729 ps
CPU time 3.89 seconds
Started Aug 15 05:13:11 PM PDT 24
Finished Aug 15 05:13:15 PM PDT 24
Peak memory 225388 kb
Host smart-b21e9efa-525e-4baf-9f11-abd0c867fa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505151489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.505151489
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3849275553
Short name T576
Test name
Test status
Simulation time 118398075 ps
CPU time 0.73 seconds
Started Aug 15 05:13:10 PM PDT 24
Finished Aug 15 05:13:11 PM PDT 24
Peak memory 216620 kb
Host smart-da6b01e4-d2d8-4d00-a8f4-5b2897debdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849275553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3849275553
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1899695809
Short name T232
Test name
Test status
Simulation time 209918623 ps
CPU time 3.88 seconds
Started Aug 15 05:13:11 PM PDT 24
Finished Aug 15 05:13:15 PM PDT 24
Peak memory 225312 kb
Host smart-9d7a6214-f505-4585-bb41-e4f6dea6eb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899695809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1899695809
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1361132244
Short name T829
Test name
Test status
Simulation time 67996716967 ps
CPU time 166.08 seconds
Started Aug 15 05:13:06 PM PDT 24
Finished Aug 15 05:15:53 PM PDT 24
Peak memory 241536 kb
Host smart-2539de2b-ade4-42aa-beed-3fcacaf9b28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361132244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1361132244
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.466147283
Short name T439
Test name
Test status
Simulation time 590056756 ps
CPU time 4.62 seconds
Started Aug 15 05:13:02 PM PDT 24
Finished Aug 15 05:13:07 PM PDT 24
Peak memory 225128 kb
Host smart-bc3c6db4-23d6-47d3-a010-ff7581af1ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466147283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
466147283
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1451315717
Short name T791
Test name
Test status
Simulation time 339891447 ps
CPU time 3.92 seconds
Started Aug 15 05:13:12 PM PDT 24
Finished Aug 15 05:13:16 PM PDT 24
Peak memory 225348 kb
Host smart-6263bf30-dca0-486b-be20-2a369142aac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451315717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1451315717
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3024032839
Short name T389
Test name
Test status
Simulation time 3392892538 ps
CPU time 25.36 seconds
Started Aug 15 05:13:10 PM PDT 24
Finished Aug 15 05:13:35 PM PDT 24
Peak memory 221552 kb
Host smart-e8678859-313b-4847-9050-0df058f7061b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3024032839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3024032839
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3159084493
Short name T76
Test name
Test status
Simulation time 36007268 ps
CPU time 0.97 seconds
Started Aug 15 05:13:10 PM PDT 24
Finished Aug 15 05:13:11 PM PDT 24
Peak memory 237164 kb
Host smart-7b70739c-1daa-4fe9-a2f5-e4a08c23f10b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159084493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3159084493
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1795568764
Short name T166
Test name
Test status
Simulation time 12955459811 ps
CPU time 205.5 seconds
Started Aug 15 05:13:09 PM PDT 24
Finished Aug 15 05:16:34 PM PDT 24
Peak memory 265788 kb
Host smart-b0fa500b-31b4-4910-ad82-4db9788edc49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795568764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1795568764
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1704372517
Short name T304
Test name
Test status
Simulation time 27584797457 ps
CPU time 38.06 seconds
Started Aug 15 05:13:09 PM PDT 24
Finished Aug 15 05:13:48 PM PDT 24
Peak memory 217260 kb
Host smart-37fb2253-284d-4c5e-aa72-b995ebf30050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704372517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1704372517
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.175429701
Short name T651
Test name
Test status
Simulation time 59848866 ps
CPU time 0.75 seconds
Started Aug 15 05:13:01 PM PDT 24
Finished Aug 15 05:13:02 PM PDT 24
Peak memory 206512 kb
Host smart-ec968a40-4424-4450-a254-202ae05ed7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175429701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.175429701
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2262167024
Short name T582
Test name
Test status
Simulation time 100965882 ps
CPU time 2.29 seconds
Started Aug 15 05:13:02 PM PDT 24
Finished Aug 15 05:13:05 PM PDT 24
Peak memory 217112 kb
Host smart-5b917baf-380e-4e30-be39-f7ab0f0ad5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262167024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2262167024
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3738339946
Short name T507
Test name
Test status
Simulation time 23394963 ps
CPU time 0.75 seconds
Started Aug 15 05:13:12 PM PDT 24
Finished Aug 15 05:13:13 PM PDT 24
Peak memory 206772 kb
Host smart-7ab9c7ca-81bb-4d3f-8734-00acd5ae96d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738339946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3738339946
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2727393511
Short name T395
Test name
Test status
Simulation time 5766954495 ps
CPU time 20.33 seconds
Started Aug 15 05:13:09 PM PDT 24
Finished Aug 15 05:13:29 PM PDT 24
Peak memory 233704 kb
Host smart-1ec15d3c-ba38-4d37-826a-30c591f7b7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727393511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2727393511
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2599852851
Short name T67
Test name
Test status
Simulation time 40613044 ps
CPU time 0.76 seconds
Started Aug 15 05:14:03 PM PDT 24
Finished Aug 15 05:14:04 PM PDT 24
Peak memory 206248 kb
Host smart-67413e66-563c-4d6e-87b4-f215c982cfa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599852851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2599852851
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3280614210
Short name T265
Test name
Test status
Simulation time 726066667 ps
CPU time 4.94 seconds
Started Aug 15 05:14:03 PM PDT 24
Finished Aug 15 05:14:09 PM PDT 24
Peak memory 225320 kb
Host smart-75c9f1e0-9c09-473c-8185-e83af494b950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280614210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3280614210
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.501618221
Short name T772
Test name
Test status
Simulation time 63568269 ps
CPU time 0.81 seconds
Started Aug 15 05:13:55 PM PDT 24
Finished Aug 15 05:13:56 PM PDT 24
Peak memory 207308 kb
Host smart-03cc82c7-c17e-40b6-a42e-4068091d064e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501618221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.501618221
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.450247458
Short name T912
Test name
Test status
Simulation time 49946339523 ps
CPU time 100.73 seconds
Started Aug 15 05:14:04 PM PDT 24
Finished Aug 15 05:15:45 PM PDT 24
Peak memory 250088 kb
Host smart-bfdcac27-3deb-45ba-8421-4b254e18bb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450247458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.450247458
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2920681714
Short name T713
Test name
Test status
Simulation time 7910197002 ps
CPU time 103.21 seconds
Started Aug 15 05:14:05 PM PDT 24
Finished Aug 15 05:15:49 PM PDT 24
Peak memory 252864 kb
Host smart-cbf1226c-b137-4300-90f7-3df2acc94672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920681714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2920681714
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1314435039
Short name T297
Test name
Test status
Simulation time 4041996245 ps
CPU time 22.93 seconds
Started Aug 15 05:14:01 PM PDT 24
Finished Aug 15 05:14:24 PM PDT 24
Peak memory 233620 kb
Host smart-0fe4234b-bfe9-4fc4-a36e-df1d005e5437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314435039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1314435039
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.439931348
Short name T519
Test name
Test status
Simulation time 25000267942 ps
CPU time 43.6 seconds
Started Aug 15 05:14:01 PM PDT 24
Finished Aug 15 05:14:45 PM PDT 24
Peak memory 241900 kb
Host smart-490944a9-0b71-499a-9e8c-154f5dc1af50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439931348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.439931348
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3441456838
Short name T251
Test name
Test status
Simulation time 452322537 ps
CPU time 3.69 seconds
Started Aug 15 05:14:07 PM PDT 24
Finished Aug 15 05:14:11 PM PDT 24
Peak memory 233532 kb
Host smart-5b03840c-a7bf-494a-b07a-b01e883440b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441456838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3441456838
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3211064772
Short name T489
Test name
Test status
Simulation time 3194522332 ps
CPU time 26.35 seconds
Started Aug 15 05:14:02 PM PDT 24
Finished Aug 15 05:14:29 PM PDT 24
Peak memory 236080 kb
Host smart-ee775cfb-b87d-4e65-875e-17bfce77aa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211064772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3211064772
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3027811257
Short name T591
Test name
Test status
Simulation time 74874042 ps
CPU time 2.3 seconds
Started Aug 15 05:14:02 PM PDT 24
Finished Aug 15 05:14:04 PM PDT 24
Peak memory 224936 kb
Host smart-7fd12210-548c-4752-aae2-224b61b1e854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027811257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3027811257
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3284745836
Short name T179
Test name
Test status
Simulation time 4199685515 ps
CPU time 11.4 seconds
Started Aug 15 05:14:03 PM PDT 24
Finished Aug 15 05:14:14 PM PDT 24
Peak memory 234664 kb
Host smart-07dedbc2-b4c2-4f59-88ab-575ed2d694f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284745836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3284745836
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.834607753
Short name T939
Test name
Test status
Simulation time 1235052674 ps
CPU time 9.27 seconds
Started Aug 15 05:14:01 PM PDT 24
Finished Aug 15 05:14:10 PM PDT 24
Peak memory 219576 kb
Host smart-ba06c243-40e3-449a-a919-3fde7b7cf5fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=834607753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.834607753
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3687958106
Short name T891
Test name
Test status
Simulation time 3131921944 ps
CPU time 22.97 seconds
Started Aug 15 05:13:55 PM PDT 24
Finished Aug 15 05:14:18 PM PDT 24
Peak memory 217348 kb
Host smart-a61f326d-2f62-4136-85c9-b8688d23db76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687958106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3687958106
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.885038546
Short name T532
Test name
Test status
Simulation time 26298329288 ps
CPU time 13.42 seconds
Started Aug 15 05:13:54 PM PDT 24
Finished Aug 15 05:14:08 PM PDT 24
Peak memory 217196 kb
Host smart-e4d614ce-d23c-4ee7-a2b5-7e5a1dac2a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885038546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.885038546
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2963453505
Short name T702
Test name
Test status
Simulation time 20924857 ps
CPU time 0.86 seconds
Started Aug 15 05:14:01 PM PDT 24
Finished Aug 15 05:14:02 PM PDT 24
Peak memory 206796 kb
Host smart-c9ecb954-0513-4459-9cf9-34834fc2629a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963453505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2963453505
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1292539221
Short name T761
Test name
Test status
Simulation time 129330605 ps
CPU time 0.91 seconds
Started Aug 15 05:14:01 PM PDT 24
Finished Aug 15 05:14:02 PM PDT 24
Peak memory 206760 kb
Host smart-decbdf67-782f-4bb3-8ede-9707ff6d6e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292539221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1292539221
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2114987806
Short name T825
Test name
Test status
Simulation time 2192281353 ps
CPU time 8.68 seconds
Started Aug 15 05:14:08 PM PDT 24
Finished Aug 15 05:14:17 PM PDT 24
Peak memory 241812 kb
Host smart-02e77c53-64e8-42d6-9a7d-fad11c0d5682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114987806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2114987806
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1738784087
Short name T178
Test name
Test status
Simulation time 39675526 ps
CPU time 0.77 seconds
Started Aug 15 05:14:05 PM PDT 24
Finished Aug 15 05:14:06 PM PDT 24
Peak memory 206576 kb
Host smart-7138f236-08cf-4b2c-a900-748f3c8f295d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738784087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1738784087
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2179239380
Short name T317
Test name
Test status
Simulation time 138001239 ps
CPU time 2.25 seconds
Started Aug 15 05:14:04 PM PDT 24
Finished Aug 15 05:14:06 PM PDT 24
Peak memory 224480 kb
Host smart-37c8543c-214b-465a-aeb2-e1566cd21c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179239380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2179239380
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1731810424
Short name T327
Test name
Test status
Simulation time 49213444 ps
CPU time 0.82 seconds
Started Aug 15 05:14:04 PM PDT 24
Finished Aug 15 05:14:05 PM PDT 24
Peak memory 207384 kb
Host smart-b082a141-2440-4dcb-a104-bb0da8a7b58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731810424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1731810424
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3138895142
Short name T181
Test name
Test status
Simulation time 11151545414 ps
CPU time 76.57 seconds
Started Aug 15 05:14:08 PM PDT 24
Finished Aug 15 05:15:24 PM PDT 24
Peak memory 255976 kb
Host smart-8a632b07-5676-4e41-aba6-1f73035f612a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138895142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3138895142
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1661771343
Short name T152
Test name
Test status
Simulation time 4366037110 ps
CPU time 103.63 seconds
Started Aug 15 05:14:02 PM PDT 24
Finished Aug 15 05:15:45 PM PDT 24
Peak memory 257156 kb
Host smart-a8185665-1088-4de8-a3e5-8a51d668382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661771343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1661771343
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3863549554
Short name T459
Test name
Test status
Simulation time 18469965065 ps
CPU time 77.85 seconds
Started Aug 15 05:14:04 PM PDT 24
Finished Aug 15 05:15:22 PM PDT 24
Peak memory 252916 kb
Host smart-bff63533-cc87-4f52-bc23-29d1c18cbbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863549554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3863549554
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.253975337
Short name T714
Test name
Test status
Simulation time 280183075 ps
CPU time 6.5 seconds
Started Aug 15 05:14:02 PM PDT 24
Finished Aug 15 05:14:09 PM PDT 24
Peak memory 225376 kb
Host smart-438a729c-849f-4870-8910-77273ac1b5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253975337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.253975337
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3786395096
Short name T783
Test name
Test status
Simulation time 84438664372 ps
CPU time 188 seconds
Started Aug 15 05:14:01 PM PDT 24
Finished Aug 15 05:17:09 PM PDT 24
Peak memory 251500 kb
Host smart-9e9b03d4-f275-45f6-bd01-e33506611588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786395096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3786395096
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.645386886
Short name T528
Test name
Test status
Simulation time 7403040250 ps
CPU time 22.11 seconds
Started Aug 15 05:14:01 PM PDT 24
Finished Aug 15 05:14:23 PM PDT 24
Peak memory 233728 kb
Host smart-5a07ab62-2262-4165-8731-8b726f6e110d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645386886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.645386886
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.622050897
Short name T974
Test name
Test status
Simulation time 54050840 ps
CPU time 2.6 seconds
Started Aug 15 05:14:03 PM PDT 24
Finished Aug 15 05:14:06 PM PDT 24
Peak memory 233272 kb
Host smart-4a3fcb22-8ae9-4b43-9a77-e0e77f3cf26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622050897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.622050897
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3318653977
Short name T433
Test name
Test status
Simulation time 860745302 ps
CPU time 9.43 seconds
Started Aug 15 05:14:02 PM PDT 24
Finished Aug 15 05:14:11 PM PDT 24
Peak memory 225316 kb
Host smart-6fe11e33-6f80-4703-a043-d13dba16687b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318653977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3318653977
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1791436991
Short name T774
Test name
Test status
Simulation time 1181218773 ps
CPU time 3.64 seconds
Started Aug 15 05:14:09 PM PDT 24
Finished Aug 15 05:14:12 PM PDT 24
Peak memory 233516 kb
Host smart-6b83bb5d-5dff-4eda-9590-d7ffe717e63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791436991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1791436991
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2795342615
Short name T839
Test name
Test status
Simulation time 196677928 ps
CPU time 4.01 seconds
Started Aug 15 05:14:03 PM PDT 24
Finished Aug 15 05:14:08 PM PDT 24
Peak memory 223692 kb
Host smart-e7b32a6e-eb76-4745-9299-799d770bcce7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2795342615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2795342615
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2540007299
Short name T405
Test name
Test status
Simulation time 89297471323 ps
CPU time 172.65 seconds
Started Aug 15 05:14:06 PM PDT 24
Finished Aug 15 05:16:59 PM PDT 24
Peak memory 250044 kb
Host smart-54a9b7d1-fd6a-4bad-96b4-eb09f2b75d77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540007299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2540007299
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1489844991
Short name T503
Test name
Test status
Simulation time 2259280464 ps
CPU time 9.46 seconds
Started Aug 15 05:14:01 PM PDT 24
Finished Aug 15 05:14:11 PM PDT 24
Peak memory 217188 kb
Host smart-aa469117-3937-4e48-bc52-3f25fbb2e456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489844991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1489844991
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2407574663
Short name T996
Test name
Test status
Simulation time 598843849 ps
CPU time 1.58 seconds
Started Aug 15 05:14:03 PM PDT 24
Finished Aug 15 05:14:04 PM PDT 24
Peak memory 208672 kb
Host smart-7dc0f0d6-63bf-4d77-a928-31ef53a58309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407574663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2407574663
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1221435388
Short name T777
Test name
Test status
Simulation time 47474936 ps
CPU time 2.03 seconds
Started Aug 15 05:14:03 PM PDT 24
Finished Aug 15 05:14:05 PM PDT 24
Peak memory 217212 kb
Host smart-9502e8cf-e3d7-4c86-8a38-075bf4167a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221435388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1221435388
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2694316012
Short name T751
Test name
Test status
Simulation time 120250933 ps
CPU time 0.84 seconds
Started Aug 15 05:14:05 PM PDT 24
Finished Aug 15 05:14:06 PM PDT 24
Peak memory 206768 kb
Host smart-c1dc51ad-9cfe-4fbc-ab81-06485b74dc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694316012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2694316012
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.228209567
Short name T983
Test name
Test status
Simulation time 422693744 ps
CPU time 3.88 seconds
Started Aug 15 05:14:03 PM PDT 24
Finished Aug 15 05:14:07 PM PDT 24
Peak memory 225300 kb
Host smart-3a5e2d54-ecb7-4b3f-b3ab-994c89f7f12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228209567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.228209567
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.786549991
Short name T646
Test name
Test status
Simulation time 10643332 ps
CPU time 0.71 seconds
Started Aug 15 05:14:13 PM PDT 24
Finished Aug 15 05:14:13 PM PDT 24
Peak memory 206280 kb
Host smart-a7efa35e-a609-49b8-a8f6-893e830a82da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786549991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.786549991
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3704398333
Short name T842
Test name
Test status
Simulation time 415313864 ps
CPU time 4.4 seconds
Started Aug 15 05:14:02 PM PDT 24
Finished Aug 15 05:14:07 PM PDT 24
Peak memory 233604 kb
Host smart-d6b43866-ff45-44b3-8388-8f896a01045b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704398333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3704398333
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1615966247
Short name T581
Test name
Test status
Simulation time 27239102 ps
CPU time 0.74 seconds
Started Aug 15 05:14:03 PM PDT 24
Finished Aug 15 05:14:04 PM PDT 24
Peak memory 206600 kb
Host smart-9c5ef8b2-4a1d-4dcb-8e2c-ab5da94577f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615966247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1615966247
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2509619893
Short name T452
Test name
Test status
Simulation time 768008935 ps
CPU time 14.21 seconds
Started Aug 15 05:14:11 PM PDT 24
Finished Aug 15 05:14:25 PM PDT 24
Peak memory 233524 kb
Host smart-4a72c0af-5a4f-4a59-96ff-92d7b40522e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509619893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2509619893
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3215321650
Short name T56
Test name
Test status
Simulation time 173012873798 ps
CPU time 372.48 seconds
Started Aug 15 05:14:11 PM PDT 24
Finished Aug 15 05:20:23 PM PDT 24
Peak memory 258120 kb
Host smart-dd7c840e-c5da-446e-b487-66f96470415f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215321650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3215321650
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1887764897
Short name T61
Test name
Test status
Simulation time 2618920964 ps
CPU time 73.34 seconds
Started Aug 15 05:14:13 PM PDT 24
Finished Aug 15 05:15:27 PM PDT 24
Peak memory 257872 kb
Host smart-7eaf9c94-d3f6-4877-9b31-ddf74de2bc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887764897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1887764897
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2446120547
Short name T952
Test name
Test status
Simulation time 5447478823 ps
CPU time 14.79 seconds
Started Aug 15 05:14:02 PM PDT 24
Finished Aug 15 05:14:16 PM PDT 24
Peak memory 235196 kb
Host smart-452e15b0-2eb5-41ad-bbf9-369ec6efddf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446120547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2446120547
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2357283715
Short name T374
Test name
Test status
Simulation time 271340278198 ps
CPU time 277.36 seconds
Started Aug 15 05:14:03 PM PDT 24
Finished Aug 15 05:18:40 PM PDT 24
Peak memory 250060 kb
Host smart-cbb0dc88-921e-4f78-b626-a98aaef1f009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357283715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2357283715
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.4076084335
Short name T434
Test name
Test status
Simulation time 1335503892 ps
CPU time 13.16 seconds
Started Aug 15 05:14:08 PM PDT 24
Finished Aug 15 05:14:21 PM PDT 24
Peak memory 233540 kb
Host smart-c88df0c9-3ef1-4d95-890c-7eb5e329b4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076084335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.4076084335
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2814215920
Short name T908
Test name
Test status
Simulation time 3783766109 ps
CPU time 26.3 seconds
Started Aug 15 05:14:02 PM PDT 24
Finished Aug 15 05:14:29 PM PDT 24
Peak memory 250336 kb
Host smart-3759e5e2-f88e-4ce1-9dec-4d3f2f9b4777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814215920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2814215920
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3097036229
Short name T481
Test name
Test status
Simulation time 123421371 ps
CPU time 2.08 seconds
Started Aug 15 05:14:03 PM PDT 24
Finished Aug 15 05:14:06 PM PDT 24
Peak memory 225308 kb
Host smart-a8bc792c-68c2-4da5-a700-f1c5aaec72ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097036229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3097036229
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.380930841
Short name T853
Test name
Test status
Simulation time 1023940180 ps
CPU time 5.41 seconds
Started Aug 15 05:14:03 PM PDT 24
Finished Aug 15 05:14:09 PM PDT 24
Peak memory 233552 kb
Host smart-c4532bec-0011-486f-bdc0-0ed2229724fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380930841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.380930841
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.681131143
Short name T664
Test name
Test status
Simulation time 1142264153 ps
CPU time 5.42 seconds
Started Aug 15 05:14:07 PM PDT 24
Finished Aug 15 05:14:12 PM PDT 24
Peak memory 220096 kb
Host smart-030fb863-7d69-4a41-a72a-2305f9dee6af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=681131143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.681131143
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.148053489
Short name T170
Test name
Test status
Simulation time 75369085 ps
CPU time 1.14 seconds
Started Aug 15 05:14:10 PM PDT 24
Finished Aug 15 05:14:12 PM PDT 24
Peak memory 215944 kb
Host smart-2b45f7e3-6121-4ff5-b6aa-8f8acfd0cc2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148053489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.148053489
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1457583424
Short name T779
Test name
Test status
Simulation time 27995050718 ps
CPU time 22.73 seconds
Started Aug 15 05:14:01 PM PDT 24
Finished Aug 15 05:14:24 PM PDT 24
Peak memory 217268 kb
Host smart-0249f42a-a2c1-4cd0-aa7e-485ca8f0bf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457583424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1457583424
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3655678818
Short name T934
Test name
Test status
Simulation time 70376356 ps
CPU time 1.94 seconds
Started Aug 15 05:14:04 PM PDT 24
Finished Aug 15 05:14:07 PM PDT 24
Peak memory 217120 kb
Host smart-8d01ae49-5dfc-4cb7-8309-6b0dd06cfbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655678818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3655678818
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3014588553
Short name T666
Test name
Test status
Simulation time 17099049 ps
CPU time 0.77 seconds
Started Aug 15 05:14:02 PM PDT 24
Finished Aug 15 05:14:03 PM PDT 24
Peak memory 206764 kb
Host smart-1a22a069-4283-428c-bb61-9064522aa088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014588553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3014588553
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.890254640
Short name T988
Test name
Test status
Simulation time 114074010 ps
CPU time 2.48 seconds
Started Aug 15 05:14:03 PM PDT 24
Finished Aug 15 05:14:05 PM PDT 24
Peak memory 225304 kb
Host smart-e822b56c-dbd5-4543-acfe-82737cb51a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890254640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.890254640
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2225805339
Short name T615
Test name
Test status
Simulation time 42189304 ps
CPU time 0.72 seconds
Started Aug 15 05:14:12 PM PDT 24
Finished Aug 15 05:14:13 PM PDT 24
Peak memory 206232 kb
Host smart-d8017aea-fa47-49f1-9978-3dbf522e2d01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225805339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2225805339
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.82508151
Short name T561
Test name
Test status
Simulation time 575334678 ps
CPU time 4.46 seconds
Started Aug 15 05:14:12 PM PDT 24
Finished Aug 15 05:14:17 PM PDT 24
Peak memory 225412 kb
Host smart-bbe3e970-74fd-49fd-a93f-3dedf1832df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82508151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.82508151
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3132725383
Short name T470
Test name
Test status
Simulation time 51305696 ps
CPU time 0.8 seconds
Started Aug 15 05:14:15 PM PDT 24
Finished Aug 15 05:14:16 PM PDT 24
Peak memory 206636 kb
Host smart-79e22188-3b69-4b00-bd8f-9ff864d88cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132725383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3132725383
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1996101170
Short name T602
Test name
Test status
Simulation time 16626518027 ps
CPU time 107.18 seconds
Started Aug 15 05:14:12 PM PDT 24
Finished Aug 15 05:15:59 PM PDT 24
Peak memory 266436 kb
Host smart-5ab9d948-33a2-44ce-bae3-a12378f6b876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996101170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1996101170
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.4245943246
Short name T25
Test name
Test status
Simulation time 21010703873 ps
CPU time 124.07 seconds
Started Aug 15 05:14:15 PM PDT 24
Finished Aug 15 05:16:19 PM PDT 24
Peak memory 258336 kb
Host smart-dca1433d-b34f-4c2c-9212-54a18baea251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245943246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.4245943246
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3624104370
Short name T365
Test name
Test status
Simulation time 31049925979 ps
CPU time 309.23 seconds
Started Aug 15 05:14:12 PM PDT 24
Finished Aug 15 05:19:21 PM PDT 24
Peak memory 273812 kb
Host smart-4bc7a8ae-cc06-48c5-98ad-77629cda23f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624104370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3624104370
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1566895470
Short name T557
Test name
Test status
Simulation time 2861043562 ps
CPU time 15.62 seconds
Started Aug 15 05:14:12 PM PDT 24
Finished Aug 15 05:14:28 PM PDT 24
Peak memory 241708 kb
Host smart-7e2394e9-4ba9-46d8-be3b-ef1d7cb5e305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566895470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1566895470
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2798866450
Short name T872
Test name
Test status
Simulation time 1251562779 ps
CPU time 13.64 seconds
Started Aug 15 05:14:13 PM PDT 24
Finished Aug 15 05:14:27 PM PDT 24
Peak memory 228652 kb
Host smart-3a2e9b7f-b8ad-4d05-b7d8-62aafb4a2ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798866450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2798866450
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1244990864
Short name T893
Test name
Test status
Simulation time 111755654 ps
CPU time 3.74 seconds
Started Aug 15 05:14:12 PM PDT 24
Finished Aug 15 05:14:16 PM PDT 24
Peak memory 233608 kb
Host smart-d0739544-ac19-472a-ba24-4e9386efa1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244990864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1244990864
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.37434885
Short name T385
Test name
Test status
Simulation time 115180431 ps
CPU time 2.11 seconds
Started Aug 15 05:14:14 PM PDT 24
Finished Aug 15 05:14:16 PM PDT 24
Peak memory 224836 kb
Host smart-1425f780-7415-4bac-9992-ba4b74aadbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37434885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.37434885
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1007301087
Short name T570
Test name
Test status
Simulation time 1378865344 ps
CPU time 5.01 seconds
Started Aug 15 05:14:13 PM PDT 24
Finished Aug 15 05:14:18 PM PDT 24
Peak memory 233568 kb
Host smart-1c3972d2-1069-4bf7-a18c-f8ddf988aaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007301087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1007301087
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.583869932
Short name T363
Test name
Test status
Simulation time 6074339249 ps
CPU time 9.08 seconds
Started Aug 15 05:14:13 PM PDT 24
Finished Aug 15 05:14:23 PM PDT 24
Peak memory 222148 kb
Host smart-9aa31f98-ed8f-4c64-86d1-923774c008e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=583869932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.583869932
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2617281874
Short name T690
Test name
Test status
Simulation time 486090476 ps
CPU time 5.81 seconds
Started Aug 15 05:14:12 PM PDT 24
Finished Aug 15 05:14:18 PM PDT 24
Peak memory 217520 kb
Host smart-d878e596-1c1d-427c-bb58-6193116662b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617281874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2617281874
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2437847463
Short name T367
Test name
Test status
Simulation time 662012456 ps
CPU time 1.96 seconds
Started Aug 15 05:14:16 PM PDT 24
Finished Aug 15 05:14:18 PM PDT 24
Peak memory 216872 kb
Host smart-dbc22d4e-4d05-4277-8480-43803c3d6f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437847463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2437847463
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1507908947
Short name T672
Test name
Test status
Simulation time 109067653 ps
CPU time 1.67 seconds
Started Aug 15 05:14:12 PM PDT 24
Finished Aug 15 05:14:14 PM PDT 24
Peak memory 208988 kb
Host smart-e8abf313-3527-4293-801f-d68f77292f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507908947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1507908947
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2986794336
Short name T394
Test name
Test status
Simulation time 34183001 ps
CPU time 0.74 seconds
Started Aug 15 05:14:14 PM PDT 24
Finished Aug 15 05:14:15 PM PDT 24
Peak memory 206772 kb
Host smart-6302ca2b-f16b-4b3d-869e-ce1fd46ae2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986794336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2986794336
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1208382055
Short name T200
Test name
Test status
Simulation time 20199156521 ps
CPU time 26.23 seconds
Started Aug 15 05:14:13 PM PDT 24
Finished Aug 15 05:14:40 PM PDT 24
Peak memory 225512 kb
Host smart-6baec309-5758-4c5a-9736-79601b1135c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208382055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1208382055
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2225336705
Short name T352
Test name
Test status
Simulation time 25590303 ps
CPU time 0.74 seconds
Started Aug 15 05:14:13 PM PDT 24
Finished Aug 15 05:14:14 PM PDT 24
Peak memory 205656 kb
Host smart-ad74e419-97fd-42d6-a727-3e17db57e4d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225336705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2225336705
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2905215003
Short name T536
Test name
Test status
Simulation time 313316367 ps
CPU time 3.33 seconds
Started Aug 15 05:14:14 PM PDT 24
Finished Aug 15 05:14:18 PM PDT 24
Peak memory 233496 kb
Host smart-8f63e651-bd3b-4608-bb20-40a24a006220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905215003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2905215003
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2015508928
Short name T880
Test name
Test status
Simulation time 64944829 ps
CPU time 0.85 seconds
Started Aug 15 05:14:15 PM PDT 24
Finished Aug 15 05:14:16 PM PDT 24
Peak memory 207588 kb
Host smart-e0085c58-fe4a-41a3-96c0-aa050ffbabba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015508928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2015508928
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2908284952
Short name T495
Test name
Test status
Simulation time 1908087171 ps
CPU time 34.74 seconds
Started Aug 15 05:14:11 PM PDT 24
Finished Aug 15 05:14:46 PM PDT 24
Peak memory 255204 kb
Host smart-9bc15e2e-fabe-4390-9e29-9a80eac5b1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908284952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2908284952
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.866267546
Short name T889
Test name
Test status
Simulation time 27000477051 ps
CPU time 40.89 seconds
Started Aug 15 05:14:13 PM PDT 24
Finished Aug 15 05:14:54 PM PDT 24
Peak memory 241800 kb
Host smart-9f519b9f-da4d-4995-96e1-7dcedd2a8825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866267546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.866267546
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3588159841
Short name T351
Test name
Test status
Simulation time 16462007523 ps
CPU time 124.29 seconds
Started Aug 15 05:14:13 PM PDT 24
Finished Aug 15 05:16:18 PM PDT 24
Peak memory 253564 kb
Host smart-4683180d-aaa4-4f8f-b700-077082c0b5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588159841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3588159841
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.408813406
Short name T636
Test name
Test status
Simulation time 4154959942 ps
CPU time 13.02 seconds
Started Aug 15 05:14:15 PM PDT 24
Finished Aug 15 05:14:28 PM PDT 24
Peak memory 233696 kb
Host smart-b981b347-00e4-409b-8818-76dfa3aa7b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408813406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.408813406
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3632160518
Short name T538
Test name
Test status
Simulation time 7108281624 ps
CPU time 18.79 seconds
Started Aug 15 05:14:14 PM PDT 24
Finished Aug 15 05:14:33 PM PDT 24
Peak memory 233720 kb
Host smart-2c53bac8-dfa2-4cdf-9a60-93d1170bc6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632160518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3632160518
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.705530090
Short name T606
Test name
Test status
Simulation time 2333495281 ps
CPU time 12.67 seconds
Started Aug 15 05:14:15 PM PDT 24
Finished Aug 15 05:14:28 PM PDT 24
Peak memory 233632 kb
Host smart-82834bf0-777e-40a2-b651-2f7f5c53b754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705530090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.705530090
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1802921283
Short name T883
Test name
Test status
Simulation time 19361433521 ps
CPU time 11.34 seconds
Started Aug 15 05:14:12 PM PDT 24
Finished Aug 15 05:14:23 PM PDT 24
Peak memory 240336 kb
Host smart-cec372ce-d261-4469-8e68-0858faee6af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802921283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1802921283
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3965913006
Short name T571
Test name
Test status
Simulation time 1331802979 ps
CPU time 4.65 seconds
Started Aug 15 05:14:15 PM PDT 24
Finished Aug 15 05:14:19 PM PDT 24
Peak memory 223812 kb
Host smart-61195f79-7af5-4ad9-918e-5adaa0ec283a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3965913006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3965913006
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.731954072
Short name T335
Test name
Test status
Simulation time 10453671874 ps
CPU time 7.18 seconds
Started Aug 15 05:14:13 PM PDT 24
Finished Aug 15 05:14:21 PM PDT 24
Peak memory 217220 kb
Host smart-453ad78b-50b3-405b-92fe-282f4130648c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731954072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.731954072
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3026931283
Short name T343
Test name
Test status
Simulation time 95160068 ps
CPU time 1.51 seconds
Started Aug 15 05:14:13 PM PDT 24
Finished Aug 15 05:14:15 PM PDT 24
Peak memory 217156 kb
Host smart-5c7efad8-c2a7-46d5-be29-17ba0fadc789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026931283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3026931283
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3262316450
Short name T936
Test name
Test status
Simulation time 23831376 ps
CPU time 0.77 seconds
Started Aug 15 05:14:13 PM PDT 24
Finished Aug 15 05:14:14 PM PDT 24
Peak memory 206816 kb
Host smart-f89b4a68-845e-4a1d-9a66-b1b7c7ca3060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262316450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3262316450
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1495941776
Short name T262
Test name
Test status
Simulation time 158754892 ps
CPU time 2.37 seconds
Started Aug 15 05:14:16 PM PDT 24
Finished Aug 15 05:14:18 PM PDT 24
Peak memory 219660 kb
Host smart-d90c2f5e-f708-447d-b227-8f8a3b792e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495941776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1495941776
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1649519317
Short name T368
Test name
Test status
Simulation time 26567370 ps
CPU time 0.71 seconds
Started Aug 15 05:14:21 PM PDT 24
Finished Aug 15 05:14:22 PM PDT 24
Peak memory 205844 kb
Host smart-ff9a1a6e-36d8-4e9f-b082-6e497cf10e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649519317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1649519317
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1521707207
Short name T874
Test name
Test status
Simulation time 273336649 ps
CPU time 2.55 seconds
Started Aug 15 05:14:19 PM PDT 24
Finished Aug 15 05:14:22 PM PDT 24
Peak memory 233500 kb
Host smart-09ffd5a5-b0c8-48e9-b513-b2e179534677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521707207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1521707207
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.416081541
Short name T670
Test name
Test status
Simulation time 90261200 ps
CPU time 0.78 seconds
Started Aug 15 05:14:16 PM PDT 24
Finished Aug 15 05:14:17 PM PDT 24
Peak memory 207372 kb
Host smart-288daf4b-511a-4429-8fba-af2b504b12e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416081541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.416081541
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3900555665
Short name T49
Test name
Test status
Simulation time 159333966192 ps
CPU time 139.93 seconds
Started Aug 15 05:14:22 PM PDT 24
Finished Aug 15 05:16:42 PM PDT 24
Peak memory 252776 kb
Host smart-3c0181b9-d12e-4eb4-b0ac-cc4dd3fd5b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900555665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3900555665
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3844245314
Short name T267
Test name
Test status
Simulation time 159566884917 ps
CPU time 171.24 seconds
Started Aug 15 05:14:20 PM PDT 24
Finished Aug 15 05:17:11 PM PDT 24
Peak memory 250236 kb
Host smart-6b429f74-df67-4cda-a3e7-a4088b9e04e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844245314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3844245314
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.472802995
Short name T464
Test name
Test status
Simulation time 71950880741 ps
CPU time 146.12 seconds
Started Aug 15 05:14:23 PM PDT 24
Finished Aug 15 05:16:49 PM PDT 24
Peak memory 254088 kb
Host smart-c8061cc2-eb32-434f-bd89-016f16de9bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472802995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.472802995
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3417119386
Short name T869
Test name
Test status
Simulation time 3874832420 ps
CPU time 28.07 seconds
Started Aug 15 05:14:24 PM PDT 24
Finished Aug 15 05:14:52 PM PDT 24
Peak memory 225460 kb
Host smart-5a0bbe93-3633-42b7-bb8b-8bb2ea928776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417119386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3417119386
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.4090785034
Short name T55
Test name
Test status
Simulation time 12395964323 ps
CPU time 41.05 seconds
Started Aug 15 05:14:22 PM PDT 24
Finished Aug 15 05:15:03 PM PDT 24
Peak memory 238884 kb
Host smart-a23ae79d-73a3-469c-92d3-2c8c367bb33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090785034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.4090785034
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.698728966
Short name T1008
Test name
Test status
Simulation time 1695022555 ps
CPU time 5.73 seconds
Started Aug 15 05:14:21 PM PDT 24
Finished Aug 15 05:14:26 PM PDT 24
Peak memory 233576 kb
Host smart-c30eab62-c145-4c3a-9041-3753966dcc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698728966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.698728966
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3887752014
Short name T665
Test name
Test status
Simulation time 7772616470 ps
CPU time 22.63 seconds
Started Aug 15 05:14:20 PM PDT 24
Finished Aug 15 05:14:43 PM PDT 24
Peak memory 225468 kb
Host smart-7e4bc5fb-f772-4df2-982b-c149a0660e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887752014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3887752014
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2162621550
Short name T982
Test name
Test status
Simulation time 2417497820 ps
CPU time 9.85 seconds
Started Aug 15 05:14:21 PM PDT 24
Finished Aug 15 05:14:31 PM PDT 24
Peak memory 233668 kb
Host smart-ab69dc4e-b06c-4de4-bf49-feb51559417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162621550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2162621550
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.4116739857
Short name T1000
Test name
Test status
Simulation time 692901804 ps
CPU time 6.48 seconds
Started Aug 15 05:14:22 PM PDT 24
Finished Aug 15 05:14:28 PM PDT 24
Peak memory 233516 kb
Host smart-7032560c-22a7-439e-8592-6e24c64f3ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116739857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.4116739857
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3410671640
Short name T692
Test name
Test status
Simulation time 1352856897 ps
CPU time 14.89 seconds
Started Aug 15 05:14:19 PM PDT 24
Finished Aug 15 05:14:34 PM PDT 24
Peak memory 224000 kb
Host smart-cb9f65ff-ca90-4019-bec3-4529f58e8515
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3410671640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3410671640
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.788205141
Short name T956
Test name
Test status
Simulation time 22698435468 ps
CPU time 224.33 seconds
Started Aug 15 05:14:24 PM PDT 24
Finished Aug 15 05:18:08 PM PDT 24
Peak memory 250324 kb
Host smart-d49227f0-b459-46df-ab18-479ae88ca654
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788205141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.788205141
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2693814251
Short name T831
Test name
Test status
Simulation time 2700365137 ps
CPU time 20.61 seconds
Started Aug 15 05:14:21 PM PDT 24
Finished Aug 15 05:14:41 PM PDT 24
Peak memory 217228 kb
Host smart-a6db1bd0-b6a0-4e12-b99a-f9a0277ef054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693814251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2693814251
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.54212843
Short name T1009
Test name
Test status
Simulation time 2647926211 ps
CPU time 9.41 seconds
Started Aug 15 05:14:12 PM PDT 24
Finished Aug 15 05:14:21 PM PDT 24
Peak memory 217292 kb
Host smart-e0ae25dd-c552-4db2-aa18-d461c33e0564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54212843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.54212843
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.483020113
Short name T87
Test name
Test status
Simulation time 45055177 ps
CPU time 2.89 seconds
Started Aug 15 05:14:20 PM PDT 24
Finished Aug 15 05:14:23 PM PDT 24
Peak memory 208908 kb
Host smart-9ad2c7aa-da5a-4c59-8b9c-5c940c9c50f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483020113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.483020113
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1304471286
Short name T906
Test name
Test status
Simulation time 119482011 ps
CPU time 0.77 seconds
Started Aug 15 05:14:26 PM PDT 24
Finished Aug 15 05:14:26 PM PDT 24
Peak memory 206816 kb
Host smart-d2a58f05-c334-4e4c-a867-eed6e68052dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304471286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1304471286
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.49705447
Short name T531
Test name
Test status
Simulation time 1992310638 ps
CPU time 10.04 seconds
Started Aug 15 05:14:20 PM PDT 24
Finished Aug 15 05:14:31 PM PDT 24
Peak memory 233492 kb
Host smart-f23693ed-4710-44c1-9ce8-53e35d6ed35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49705447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.49705447
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.58571102
Short name T894
Test name
Test status
Simulation time 32928679 ps
CPU time 0.69 seconds
Started Aug 15 05:14:22 PM PDT 24
Finished Aug 15 05:14:23 PM PDT 24
Peak memory 206264 kb
Host smart-c110b003-ea14-40ba-9dee-e12962fe0af0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58571102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.58571102
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3451620889
Short name T471
Test name
Test status
Simulation time 313004114 ps
CPU time 3.59 seconds
Started Aug 15 05:14:22 PM PDT 24
Finished Aug 15 05:14:26 PM PDT 24
Peak memory 225380 kb
Host smart-2f996ca3-d4d1-406e-9554-67367b636e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451620889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3451620889
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1261743684
Short name T8
Test name
Test status
Simulation time 16274510 ps
CPU time 0.75 seconds
Started Aug 15 05:14:19 PM PDT 24
Finished Aug 15 05:14:20 PM PDT 24
Peak memory 206608 kb
Host smart-ff637606-f5dd-4179-b618-d390d5b21c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261743684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1261743684
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2185945886
Short name T207
Test name
Test status
Simulation time 1388406379 ps
CPU time 36.52 seconds
Started Aug 15 05:14:24 PM PDT 24
Finished Aug 15 05:15:00 PM PDT 24
Peak memory 251668 kb
Host smart-6e41374a-3fb8-49ff-be73-026c0cab3ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185945886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2185945886
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3467069073
Short name T732
Test name
Test status
Simulation time 86188984010 ps
CPU time 142.89 seconds
Started Aug 15 05:14:26 PM PDT 24
Finished Aug 15 05:16:49 PM PDT 24
Peak memory 273668 kb
Host smart-8bba185a-299c-483e-881c-a9a6121d556f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467069073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3467069073
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3519662535
Short name T863
Test name
Test status
Simulation time 16152621207 ps
CPU time 142.38 seconds
Started Aug 15 05:14:25 PM PDT 24
Finished Aug 15 05:16:47 PM PDT 24
Peak memory 258352 kb
Host smart-7ba69959-41a5-43a9-9ff5-f4dbb95ca11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519662535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3519662535
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3667732710
Short name T659
Test name
Test status
Simulation time 663884665 ps
CPU time 13.31 seconds
Started Aug 15 05:14:22 PM PDT 24
Finished Aug 15 05:14:35 PM PDT 24
Peak memory 233536 kb
Host smart-66eb7951-3804-44bc-b08f-6130a1379c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667732710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3667732710
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3636513568
Short name T219
Test name
Test status
Simulation time 44041808160 ps
CPU time 54.71 seconds
Started Aug 15 05:14:23 PM PDT 24
Finished Aug 15 05:15:18 PM PDT 24
Peak memory 244008 kb
Host smart-6d28cc5a-8df0-480a-a5c3-0f7bacf073ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636513568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3636513568
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3825721054
Short name T728
Test name
Test status
Simulation time 480235804 ps
CPU time 2.75 seconds
Started Aug 15 05:14:22 PM PDT 24
Finished Aug 15 05:14:24 PM PDT 24
Peak memory 225288 kb
Host smart-ba7971e0-9829-4d5e-91f4-2d8f515c5c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825721054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3825721054
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.86147451
Short name T448
Test name
Test status
Simulation time 839176616 ps
CPU time 4.35 seconds
Started Aug 15 05:14:19 PM PDT 24
Finished Aug 15 05:14:23 PM PDT 24
Peak memory 225324 kb
Host smart-3d534cb5-e0e9-459d-9400-51e9c5831fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86147451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.86147451
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3516798972
Short name T260
Test name
Test status
Simulation time 6574822708 ps
CPU time 13.77 seconds
Started Aug 15 05:14:22 PM PDT 24
Finished Aug 15 05:14:36 PM PDT 24
Peak memory 250092 kb
Host smart-764c8782-c48f-40c2-8e0b-baedca91f759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516798972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3516798972
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2699302340
Short name T945
Test name
Test status
Simulation time 588353381 ps
CPU time 2.49 seconds
Started Aug 15 05:14:20 PM PDT 24
Finished Aug 15 05:14:23 PM PDT 24
Peak memory 233556 kb
Host smart-9822c625-7cac-4110-92f5-ed47eb22e3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699302340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2699302340
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3427969975
Short name T370
Test name
Test status
Simulation time 4187484641 ps
CPU time 9.98 seconds
Started Aug 15 05:14:24 PM PDT 24
Finished Aug 15 05:14:34 PM PDT 24
Peak memory 220392 kb
Host smart-0c4fd08c-a5fe-4ae3-b914-09998d92af99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3427969975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3427969975
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3656872599
Short name T143
Test name
Test status
Simulation time 133183958294 ps
CPU time 253.57 seconds
Started Aug 15 05:14:23 PM PDT 24
Finished Aug 15 05:18:37 PM PDT 24
Peak memory 258336 kb
Host smart-e4a6d1ce-bf0e-4c86-9dec-024f8b606e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656872599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3656872599
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.944708775
Short name T955
Test name
Test status
Simulation time 3765962983 ps
CPU time 30.48 seconds
Started Aug 15 05:14:21 PM PDT 24
Finished Aug 15 05:14:51 PM PDT 24
Peak memory 220928 kb
Host smart-0652ccbe-283e-4df3-8096-90a530b95f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944708775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.944708775
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1940637517
Short name T790
Test name
Test status
Simulation time 2381533235 ps
CPU time 2.81 seconds
Started Aug 15 05:14:24 PM PDT 24
Finished Aug 15 05:14:27 PM PDT 24
Peak memory 208892 kb
Host smart-0a5ca331-5a9a-4333-a4e5-39dfdc4438df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940637517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1940637517
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2379362246
Short name T699
Test name
Test status
Simulation time 45355249 ps
CPU time 1.34 seconds
Started Aug 15 05:14:21 PM PDT 24
Finished Aug 15 05:14:23 PM PDT 24
Peak memory 217120 kb
Host smart-e7a6173c-fc21-495b-b89b-8508948ecad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379362246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2379362246
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1437505459
Short name T1013
Test name
Test status
Simulation time 61504364 ps
CPU time 0.93 seconds
Started Aug 15 05:14:21 PM PDT 24
Finished Aug 15 05:14:22 PM PDT 24
Peak memory 207288 kb
Host smart-720e6973-7d15-4a4e-a789-6f9605cf0f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437505459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1437505459
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1088268038
Short name T762
Test name
Test status
Simulation time 13524266464 ps
CPU time 12.3 seconds
Started Aug 15 05:14:21 PM PDT 24
Finished Aug 15 05:14:34 PM PDT 24
Peak memory 224816 kb
Host smart-84a219f2-3c64-4aca-8048-07a1e242aaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088268038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1088268038
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.980202899
Short name T755
Test name
Test status
Simulation time 50423435 ps
CPU time 0.72 seconds
Started Aug 15 05:14:28 PM PDT 24
Finished Aug 15 05:14:29 PM PDT 24
Peak memory 205632 kb
Host smart-e0d1cc0e-2ca5-48cc-88d3-04f819e49502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980202899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.980202899
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1042091701
Short name T480
Test name
Test status
Simulation time 441896872 ps
CPU time 4.36 seconds
Started Aug 15 05:14:31 PM PDT 24
Finished Aug 15 05:14:35 PM PDT 24
Peak memory 225404 kb
Host smart-d3670709-c66c-418c-9b56-604b70373b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042091701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1042091701
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.110306111
Short name T485
Test name
Test status
Simulation time 21972457 ps
CPU time 0.77 seconds
Started Aug 15 05:14:26 PM PDT 24
Finished Aug 15 05:14:26 PM PDT 24
Peak memory 207388 kb
Host smart-b4da1b6e-bea6-4ea3-b055-b186352670f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110306111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.110306111
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1870740292
Short name T865
Test name
Test status
Simulation time 70867688894 ps
CPU time 81.74 seconds
Started Aug 15 05:14:34 PM PDT 24
Finished Aug 15 05:15:56 PM PDT 24
Peak memory 250980 kb
Host smart-fd0e3bcb-4246-4d2c-a578-a8f8c506c96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870740292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1870740292
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3630977522
Short name T241
Test name
Test status
Simulation time 11036796509 ps
CPU time 98.2 seconds
Started Aug 15 05:14:27 PM PDT 24
Finished Aug 15 05:16:06 PM PDT 24
Peak memory 250160 kb
Host smart-1b564317-bbe1-4ae6-9bef-e42ea450d765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630977522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3630977522
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2936520155
Short name T159
Test name
Test status
Simulation time 375197845 ps
CPU time 9.88 seconds
Started Aug 15 05:14:31 PM PDT 24
Finished Aug 15 05:14:41 PM PDT 24
Peak memory 225408 kb
Host smart-9fb58ffd-dd6c-4893-8192-b55dd975f823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936520155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2936520155
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2047371861
Short name T446
Test name
Test status
Simulation time 14605476386 ps
CPU time 38.8 seconds
Started Aug 15 05:14:29 PM PDT 24
Finished Aug 15 05:15:08 PM PDT 24
Peak memory 250420 kb
Host smart-9f78513c-9aa0-4086-9546-a6fff2f67ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047371861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2047371861
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2819241651
Short name T871
Test name
Test status
Simulation time 206124617 ps
CPU time 3.62 seconds
Started Aug 15 05:14:32 PM PDT 24
Finished Aug 15 05:14:36 PM PDT 24
Peak memory 224724 kb
Host smart-6d98f08d-9a87-49f6-8321-b8b49acba684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819241651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2819241651
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2323034132
Short name T294
Test name
Test status
Simulation time 7416582093 ps
CPU time 13.13 seconds
Started Aug 15 05:14:30 PM PDT 24
Finished Aug 15 05:14:43 PM PDT 24
Peak memory 240636 kb
Host smart-03c63798-962e-4a26-8e34-6cb06b692c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323034132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2323034132
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1542628532
Short name T914
Test name
Test status
Simulation time 4518914189 ps
CPU time 21.22 seconds
Started Aug 15 05:14:29 PM PDT 24
Finished Aug 15 05:14:50 PM PDT 24
Peak memory 253816 kb
Host smart-4fc65344-467e-43c2-886c-3ae6958711d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542628532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1542628532
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1792053706
Short name T540
Test name
Test status
Simulation time 159121711 ps
CPU time 3.73 seconds
Started Aug 15 05:14:33 PM PDT 24
Finished Aug 15 05:14:37 PM PDT 24
Peak memory 223992 kb
Host smart-40cd8358-c117-41cf-a4c2-05685d2033ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1792053706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1792053706
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1508541660
Short name T155
Test name
Test status
Simulation time 262373987226 ps
CPU time 618.35 seconds
Started Aug 15 05:14:29 PM PDT 24
Finished Aug 15 05:24:48 PM PDT 24
Peak memory 283608 kb
Host smart-cde189f0-308a-44a7-a125-f0538ee7b25b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508541660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1508541660
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2605264491
Short name T305
Test name
Test status
Simulation time 14584694422 ps
CPU time 17.13 seconds
Started Aug 15 05:14:24 PM PDT 24
Finished Aug 15 05:14:41 PM PDT 24
Peak memory 217432 kb
Host smart-9d44ff99-fbe2-460c-853e-f52e74d35d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605264491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2605264491
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3000615603
Short name T32
Test name
Test status
Simulation time 276580873 ps
CPU time 1.99 seconds
Started Aug 15 05:14:26 PM PDT 24
Finished Aug 15 05:14:29 PM PDT 24
Peak memory 216940 kb
Host smart-6ff2cbe4-368b-451b-a9da-a2524237abbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000615603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3000615603
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2254883397
Short name T85
Test name
Test status
Simulation time 30076657 ps
CPU time 1.2 seconds
Started Aug 15 05:14:21 PM PDT 24
Finished Aug 15 05:14:22 PM PDT 24
Peak memory 208556 kb
Host smart-d4e23b90-29df-4741-abae-5b1450c010d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254883397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2254883397
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2532923705
Short name T312
Test name
Test status
Simulation time 136800737 ps
CPU time 0.85 seconds
Started Aug 15 05:14:20 PM PDT 24
Finished Aug 15 05:14:21 PM PDT 24
Peak memory 206840 kb
Host smart-05f146ac-ec57-4910-b7e3-b86cd3c1ea70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532923705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2532923705
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3928115215
Short name T520
Test name
Test status
Simulation time 167623842 ps
CPU time 2.67 seconds
Started Aug 15 05:14:30 PM PDT 24
Finished Aug 15 05:14:32 PM PDT 24
Peak memory 233512 kb
Host smart-c54e46a5-6ee2-4fb4-91dd-1d1a82219e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928115215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3928115215
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2127203680
Short name T957
Test name
Test status
Simulation time 28062481 ps
CPU time 0.71 seconds
Started Aug 15 05:14:39 PM PDT 24
Finished Aug 15 05:14:40 PM PDT 24
Peak memory 205676 kb
Host smart-d0433eca-7b44-4245-bd2c-434f2ed5fabf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127203680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2127203680
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2252615497
Short name T959
Test name
Test status
Simulation time 984565683 ps
CPU time 6.65 seconds
Started Aug 15 05:14:30 PM PDT 24
Finished Aug 15 05:14:37 PM PDT 24
Peak memory 233584 kb
Host smart-c4e4bb83-14e8-400c-a0ac-c73c3fe50f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252615497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2252615497
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3497999352
Short name T332
Test name
Test status
Simulation time 15508138 ps
CPU time 0.77 seconds
Started Aug 15 05:14:28 PM PDT 24
Finished Aug 15 05:14:29 PM PDT 24
Peak memory 207408 kb
Host smart-21da73e3-ff64-4fd3-ad46-aeabc5e374ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497999352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3497999352
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.41515592
Short name T543
Test name
Test status
Simulation time 422236695774 ps
CPU time 191.25 seconds
Started Aug 15 05:14:33 PM PDT 24
Finished Aug 15 05:17:44 PM PDT 24
Peak memory 258200 kb
Host smart-deed19c9-f5e6-4e03-8d89-85db2ac3d56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41515592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.41515592
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3214288114
Short name T917
Test name
Test status
Simulation time 8431742572 ps
CPU time 41.24 seconds
Started Aug 15 05:14:30 PM PDT 24
Finished Aug 15 05:15:11 PM PDT 24
Peak memory 239384 kb
Host smart-c7ddf24e-bda7-4558-9a71-bc4ca6d1a26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214288114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3214288114
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2945405594
Short name T586
Test name
Test status
Simulation time 45844501878 ps
CPU time 101.83 seconds
Started Aug 15 05:14:49 PM PDT 24
Finished Aug 15 05:16:31 PM PDT 24
Peak memory 250604 kb
Host smart-ca65c826-a60a-4d83-80b1-fdbcc74df06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945405594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2945405594
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2769455873
Short name T300
Test name
Test status
Simulation time 495461126 ps
CPU time 9.27 seconds
Started Aug 15 05:14:32 PM PDT 24
Finished Aug 15 05:14:41 PM PDT 24
Peak memory 224624 kb
Host smart-098f4994-e687-48bf-9ef0-a4985dca4ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769455873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2769455873
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.4020033211
Short name T931
Test name
Test status
Simulation time 2814811286 ps
CPU time 7.2 seconds
Started Aug 15 05:14:30 PM PDT 24
Finished Aug 15 05:14:37 PM PDT 24
Peak memory 233744 kb
Host smart-0d4e8159-26fd-490c-99c2-1ef7e146c16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020033211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.4020033211
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.544989894
Short name T558
Test name
Test status
Simulation time 2454267482 ps
CPU time 11.12 seconds
Started Aug 15 05:14:32 PM PDT 24
Finished Aug 15 05:14:43 PM PDT 24
Peak memory 220784 kb
Host smart-ad9a1702-8fd2-4d3a-8869-513e56f1e5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544989894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.544989894
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.213888415
Short name T330
Test name
Test status
Simulation time 114495361 ps
CPU time 2.31 seconds
Started Aug 15 05:14:32 PM PDT 24
Finished Aug 15 05:14:35 PM PDT 24
Peak memory 233200 kb
Host smart-17ccbd69-4556-4e0f-981f-f05ed78cfaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213888415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.213888415
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.764578576
Short name T325
Test name
Test status
Simulation time 7308297351 ps
CPU time 17.55 seconds
Started Aug 15 05:14:30 PM PDT 24
Finished Aug 15 05:14:48 PM PDT 24
Peak memory 225408 kb
Host smart-de72d819-8559-4362-a530-b2fedf31e1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764578576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.764578576
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2105630517
Short name T676
Test name
Test status
Simulation time 171834544 ps
CPU time 4.37 seconds
Started Aug 15 05:14:33 PM PDT 24
Finished Aug 15 05:14:37 PM PDT 24
Peak memory 223616 kb
Host smart-a1f2c34a-0da3-407c-9045-a9d779c015cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2105630517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2105630517
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3373306507
Short name T35
Test name
Test status
Simulation time 6164286623 ps
CPU time 21.21 seconds
Started Aug 15 05:14:47 PM PDT 24
Finished Aug 15 05:15:09 PM PDT 24
Peak memory 218860 kb
Host smart-e95728ac-e4ec-4abb-930e-5c541681b9fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373306507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3373306507
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.989891627
Short name T786
Test name
Test status
Simulation time 1471319353 ps
CPU time 9.04 seconds
Started Aug 15 05:14:30 PM PDT 24
Finished Aug 15 05:14:39 PM PDT 24
Peak memory 217212 kb
Host smart-6a8a73f2-e9c9-4840-ad24-782188295474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989891627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.989891627
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1836883772
Short name T780
Test name
Test status
Simulation time 60430978 ps
CPU time 1.54 seconds
Started Aug 15 05:14:30 PM PDT 24
Finished Aug 15 05:14:31 PM PDT 24
Peak memory 216964 kb
Host smart-2ac9395b-9443-400b-b70a-33caf55682b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836883772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1836883772
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3718775
Short name T642
Test name
Test status
Simulation time 41217885 ps
CPU time 0.75 seconds
Started Aug 15 05:14:32 PM PDT 24
Finished Aug 15 05:14:33 PM PDT 24
Peak memory 206764 kb
Host smart-03f916d6-e3d8-4eb2-8586-08696a288ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3718775
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3206471584
Short name T100
Test name
Test status
Simulation time 5439557374 ps
CPU time 12.4 seconds
Started Aug 15 05:14:33 PM PDT 24
Finished Aug 15 05:14:45 PM PDT 24
Peak memory 241716 kb
Host smart-e668b5b7-ad4c-484e-a798-6e3c8f0dabe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206471584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3206471584
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3486729917
Short name T852
Test name
Test status
Simulation time 10974948 ps
CPU time 0.74 seconds
Started Aug 15 05:14:39 PM PDT 24
Finished Aug 15 05:14:40 PM PDT 24
Peak memory 206244 kb
Host smart-ffcffc3d-01eb-4dd6-bf09-9193ee4bfd80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486729917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3486729917
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1726438377
Short name T821
Test name
Test status
Simulation time 622949342 ps
CPU time 6.25 seconds
Started Aug 15 05:14:37 PM PDT 24
Finished Aug 15 05:14:43 PM PDT 24
Peak memory 225236 kb
Host smart-1401316e-5faa-4c5e-af13-176b7001e14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726438377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1726438377
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3954471830
Short name T968
Test name
Test status
Simulation time 27511359 ps
CPU time 0.76 seconds
Started Aug 15 05:14:48 PM PDT 24
Finished Aug 15 05:14:49 PM PDT 24
Peak memory 206648 kb
Host smart-70fb0b7f-b688-4a3d-b80f-f8e84470e4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954471830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3954471830
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.410435899
Short name T886
Test name
Test status
Simulation time 84006129679 ps
CPU time 90.93 seconds
Started Aug 15 05:14:48 PM PDT 24
Finished Aug 15 05:16:19 PM PDT 24
Peak memory 240820 kb
Host smart-3a3cf5a3-7bec-42a8-97bd-62d56b4b4428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410435899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.410435899
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2268542905
Short name T752
Test name
Test status
Simulation time 88622023660 ps
CPU time 211.8 seconds
Started Aug 15 05:14:39 PM PDT 24
Finished Aug 15 05:18:11 PM PDT 24
Peak memory 250228 kb
Host smart-6dac43d8-b4d0-4166-9886-e15f31ba37a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268542905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2268542905
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2841710650
Short name T455
Test name
Test status
Simulation time 1222117688 ps
CPU time 4.94 seconds
Started Aug 15 05:14:36 PM PDT 24
Finished Aug 15 05:14:41 PM PDT 24
Peak memory 233412 kb
Host smart-84807d7c-1215-47bf-9a9f-8fc6588fe246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841710650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2841710650
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3097131353
Short name T239
Test name
Test status
Simulation time 30990143841 ps
CPU time 52.11 seconds
Started Aug 15 05:14:39 PM PDT 24
Finished Aug 15 05:15:31 PM PDT 24
Peak memory 250072 kb
Host smart-5371558b-ad02-424a-9e8f-d098a3136efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097131353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3097131353
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1331834656
Short name T322
Test name
Test status
Simulation time 255533901 ps
CPU time 2.29 seconds
Started Aug 15 05:14:37 PM PDT 24
Finished Aug 15 05:14:40 PM PDT 24
Peak memory 233260 kb
Host smart-6246de00-c0f0-4c89-a70a-4bfc5641cb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331834656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1331834656
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1758295688
Short name T429
Test name
Test status
Simulation time 4772682186 ps
CPU time 24.07 seconds
Started Aug 15 05:14:37 PM PDT 24
Finished Aug 15 05:15:01 PM PDT 24
Peak memory 251460 kb
Host smart-c564249a-f2fa-499b-a0cd-5c9a0622b7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758295688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1758295688
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3597138660
Short name T276
Test name
Test status
Simulation time 7807426411 ps
CPU time 7.35 seconds
Started Aug 15 05:14:48 PM PDT 24
Finished Aug 15 05:14:56 PM PDT 24
Peak memory 233660 kb
Host smart-7f412fe6-62a7-4dc6-b5df-f92ce0a3c677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597138660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3597138660
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1887412968
Short name T687
Test name
Test status
Simulation time 26356585557 ps
CPU time 10.62 seconds
Started Aug 15 05:14:49 PM PDT 24
Finished Aug 15 05:15:00 PM PDT 24
Peak memory 225444 kb
Host smart-f23bb28f-7c90-417a-b9e6-23c6707e795b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887412968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1887412968
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.328189902
Short name T547
Test name
Test status
Simulation time 326235416 ps
CPU time 6.19 seconds
Started Aug 15 05:14:37 PM PDT 24
Finished Aug 15 05:14:44 PM PDT 24
Peak memory 222976 kb
Host smart-fa78a2e1-0766-4a17-a82d-1982211e7511
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=328189902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.328189902
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.505962320
Short name T750
Test name
Test status
Simulation time 79913325 ps
CPU time 0.97 seconds
Started Aug 15 05:14:38 PM PDT 24
Finished Aug 15 05:14:39 PM PDT 24
Peak memory 207476 kb
Host smart-70c38961-bc0f-4a11-9013-4c578921d33c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505962320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.505962320
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1837926777
Short name T308
Test name
Test status
Simulation time 4591611129 ps
CPU time 15.52 seconds
Started Aug 15 05:14:39 PM PDT 24
Finished Aug 15 05:14:54 PM PDT 24
Peak memory 217304 kb
Host smart-ae68cabc-8b6d-4b82-96da-d66938b3aa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837926777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1837926777
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2159329765
Short name T514
Test name
Test status
Simulation time 255013065 ps
CPU time 1.7 seconds
Started Aug 15 05:14:38 PM PDT 24
Finished Aug 15 05:14:40 PM PDT 24
Peak memory 208732 kb
Host smart-99ae4b59-7c8e-4dc9-8c19-39315fb55ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159329765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2159329765
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2376096305
Short name T431
Test name
Test status
Simulation time 96262472 ps
CPU time 2.03 seconds
Started Aug 15 05:14:38 PM PDT 24
Finished Aug 15 05:14:40 PM PDT 24
Peak memory 217140 kb
Host smart-af39afca-c434-4db3-aecd-46b58bff2459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376096305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2376096305
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3062596953
Short name T524
Test name
Test status
Simulation time 233733215 ps
CPU time 1.02 seconds
Started Aug 15 05:14:37 PM PDT 24
Finished Aug 15 05:14:38 PM PDT 24
Peak memory 207888 kb
Host smart-2f2f1835-12d3-4a9c-8838-c15893eb79ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062596953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3062596953
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1961793860
Short name T610
Test name
Test status
Simulation time 839028402 ps
CPU time 6.7 seconds
Started Aug 15 05:14:37 PM PDT 24
Finished Aug 15 05:14:44 PM PDT 24
Peak memory 233596 kb
Host smart-1a017986-6255-4bac-b27a-2e3e88e5232f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961793860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1961793860
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.776188991
Short name T932
Test name
Test status
Simulation time 20685014 ps
CPU time 0.78 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:13:19 PM PDT 24
Peak memory 205728 kb
Host smart-e68cc7ca-2f52-405f-97b6-a2dae4eaeb7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776188991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.776188991
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1657348565
Short name T552
Test name
Test status
Simulation time 1356606091 ps
CPU time 3.87 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:13:22 PM PDT 24
Peak memory 233512 kb
Host smart-98347d72-e1e2-4e4a-9559-f71891b64ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657348565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1657348565
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.817412901
Short name T735
Test name
Test status
Simulation time 55481742 ps
CPU time 0.8 seconds
Started Aug 15 05:13:10 PM PDT 24
Finished Aug 15 05:13:11 PM PDT 24
Peak memory 207692 kb
Host smart-2c3656ec-8216-4a65-8ec3-703135899f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817412901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.817412901
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3438973884
Short name T633
Test name
Test status
Simulation time 41141543595 ps
CPU time 327.5 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:18:46 PM PDT 24
Peak memory 250104 kb
Host smart-bdf655ec-2928-418b-9efc-e424e34d7397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438973884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3438973884
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2413454112
Short name T624
Test name
Test status
Simulation time 25640941235 ps
CPU time 189.31 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:16:27 PM PDT 24
Peak memory 258260 kb
Host smart-421fd2fc-e42c-4537-bdc9-601ffe1210f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413454112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2413454112
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3482935768
Short name T479
Test name
Test status
Simulation time 3025725804 ps
CPU time 35.82 seconds
Started Aug 15 05:13:27 PM PDT 24
Finished Aug 15 05:14:03 PM PDT 24
Peak memory 233660 kb
Host smart-0b4e0c03-3400-45c5-ade4-081684c8e1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482935768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3482935768
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1991994559
Short name T680
Test name
Test status
Simulation time 8785400517 ps
CPU time 44 seconds
Started Aug 15 05:13:19 PM PDT 24
Finished Aug 15 05:14:03 PM PDT 24
Peak memory 252460 kb
Host smart-8043d8be-d765-437e-befb-bdd2a7003537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991994559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1991994559
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2367871672
Short name T530
Test name
Test status
Simulation time 3697528721 ps
CPU time 13.28 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:13:32 PM PDT 24
Peak memory 233636 kb
Host smart-5c808ab1-11ba-4564-a585-cf536b419b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367871672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2367871672
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3979155091
Short name T778
Test name
Test status
Simulation time 60770956 ps
CPU time 2.42 seconds
Started Aug 15 05:13:17 PM PDT 24
Finished Aug 15 05:13:20 PM PDT 24
Peak memory 233192 kb
Host smart-9d3ef4d6-f089-46ac-b57d-e3a97baa611c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979155091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3979155091
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2851573491
Short name T585
Test name
Test status
Simulation time 774729340 ps
CPU time 6.69 seconds
Started Aug 15 05:13:11 PM PDT 24
Finished Aug 15 05:13:18 PM PDT 24
Peak memory 233460 kb
Host smart-a2b55e6b-0c86-4f61-8f09-ec39c49b7f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851573491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2851573491
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1147784402
Short name T390
Test name
Test status
Simulation time 964018381 ps
CPU time 13.88 seconds
Started Aug 15 05:13:20 PM PDT 24
Finished Aug 15 05:13:34 PM PDT 24
Peak memory 219552 kb
Host smart-7d3ecdf5-e4fc-4119-8b26-9668f189f9de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1147784402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1147784402
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2058815455
Short name T74
Test name
Test status
Simulation time 37410060 ps
CPU time 0.99 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:13:20 PM PDT 24
Peak memory 236536 kb
Host smart-5ddda497-ec7a-42db-bbf3-edb488a387b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058815455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2058815455
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2166579312
Short name T15
Test name
Test status
Simulation time 21748618836 ps
CPU time 265.42 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:17:43 PM PDT 24
Peak memory 265372 kb
Host smart-9332963c-6791-4956-9615-7d6a856648b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166579312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2166579312
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.4074822419
Short name T401
Test name
Test status
Simulation time 10948778276 ps
CPU time 4.23 seconds
Started Aug 15 05:13:11 PM PDT 24
Finished Aug 15 05:13:16 PM PDT 24
Peak memory 217276 kb
Host smart-adbb96a6-a655-4414-8d12-50d9d616d41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074822419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.4074822419
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2345654055
Short name T629
Test name
Test status
Simulation time 4506662692 ps
CPU time 3.58 seconds
Started Aug 15 05:13:10 PM PDT 24
Finished Aug 15 05:13:13 PM PDT 24
Peak memory 217260 kb
Host smart-0459d9e7-9912-43b0-8876-15acdc9226a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345654055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2345654055
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3406340141
Short name T33
Test name
Test status
Simulation time 18588907 ps
CPU time 1.19 seconds
Started Aug 15 05:13:11 PM PDT 24
Finished Aug 15 05:13:13 PM PDT 24
Peak memory 216800 kb
Host smart-a6eb07c8-95b8-403d-8d65-3e2746e4c79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406340141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3406340141
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3033299625
Short name T331
Test name
Test status
Simulation time 44014273 ps
CPU time 0.72 seconds
Started Aug 15 05:13:09 PM PDT 24
Finished Aug 15 05:13:10 PM PDT 24
Peak memory 206768 kb
Host smart-c6d7284e-c61e-4487-ac42-b3b8dc571325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033299625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3033299625
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3356813301
Short name T691
Test name
Test status
Simulation time 542243907 ps
CPU time 2.56 seconds
Started Aug 15 05:13:10 PM PDT 24
Finished Aug 15 05:13:13 PM PDT 24
Peak memory 225324 kb
Host smart-23a5001b-c75d-4a3f-b8c1-78afb862a393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356813301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3356813301
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.4083183817
Short name T923
Test name
Test status
Simulation time 42832142 ps
CPU time 0.7 seconds
Started Aug 15 05:14:44 PM PDT 24
Finished Aug 15 05:14:46 PM PDT 24
Peak memory 206188 kb
Host smart-bd1b6680-ced0-4098-854e-d316003ab31b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083183817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
4083183817
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3573085551
Short name T910
Test name
Test status
Simulation time 118329828 ps
CPU time 2.42 seconds
Started Aug 15 05:14:47 PM PDT 24
Finished Aug 15 05:14:49 PM PDT 24
Peak memory 225288 kb
Host smart-70b6c127-c9c8-4796-a381-b78947aa0f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573085551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3573085551
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.119300670
Short name T870
Test name
Test status
Simulation time 18557649 ps
CPU time 0.73 seconds
Started Aug 15 05:14:36 PM PDT 24
Finished Aug 15 05:14:37 PM PDT 24
Peak memory 206688 kb
Host smart-8122480a-4756-48df-b111-d84438077659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119300670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.119300670
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.4008889546
Short name T475
Test name
Test status
Simulation time 52781807 ps
CPU time 0.97 seconds
Started Aug 15 05:14:46 PM PDT 24
Finished Aug 15 05:14:47 PM PDT 24
Peak memory 216852 kb
Host smart-c96fa869-ee87-4a68-85fb-ceae0e6bd912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008889546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.4008889546
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.970756101
Short name T215
Test name
Test status
Simulation time 363675212940 ps
CPU time 403.04 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:21:29 PM PDT 24
Peak memory 258392 kb
Host smart-c7479565-75eb-4e4c-a1d7-fdf1975d01f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970756101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.970756101
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1868369435
Short name T565
Test name
Test status
Simulation time 45790368292 ps
CPU time 305.74 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:19:51 PM PDT 24
Peak memory 250228 kb
Host smart-8c51bb85-6e78-4b30-96c5-64c7610274a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868369435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1868369435
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2033681626
Short name T756
Test name
Test status
Simulation time 198515423 ps
CPU time 3.38 seconds
Started Aug 15 05:14:46 PM PDT 24
Finished Aug 15 05:14:50 PM PDT 24
Peak memory 225352 kb
Host smart-a505de88-50d0-43a1-9770-66060c653743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033681626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2033681626
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2413255545
Short name T1014
Test name
Test status
Simulation time 524994630 ps
CPU time 5.52 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:14:50 PM PDT 24
Peak memory 233464 kb
Host smart-99f74bc7-f5c9-4405-9c46-a15684e540e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413255545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2413255545
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2110720172
Short name T716
Test name
Test status
Simulation time 541301507 ps
CPU time 2.36 seconds
Started Aug 15 05:14:46 PM PDT 24
Finished Aug 15 05:14:49 PM PDT 24
Peak memory 233224 kb
Host smart-85272894-5ebc-4e9b-8333-b1c079d349c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110720172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2110720172
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.4121811123
Short name T252
Test name
Test status
Simulation time 12036466908 ps
CPU time 12.87 seconds
Started Aug 15 05:14:47 PM PDT 24
Finished Aug 15 05:14:59 PM PDT 24
Peak memory 233612 kb
Host smart-09b85608-0c79-4d8c-b152-c5a22f946be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121811123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4121811123
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1333880978
Short name T404
Test name
Test status
Simulation time 2295128155 ps
CPU time 13.13 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:14:59 PM PDT 24
Peak memory 220200 kb
Host smart-69941610-8b31-43b6-a8de-9103e6d4c157
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1333880978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1333880978
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2610209699
Short name T991
Test name
Test status
Simulation time 59867956 ps
CPU time 1.15 seconds
Started Aug 15 05:14:47 PM PDT 24
Finished Aug 15 05:14:48 PM PDT 24
Peak memory 207616 kb
Host smart-04bd94fa-fcb0-46cd-a0cb-53e0376315cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610209699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2610209699
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2829433774
Short name T555
Test name
Test status
Simulation time 4659205656 ps
CPU time 17.9 seconds
Started Aug 15 05:14:41 PM PDT 24
Finished Aug 15 05:14:59 PM PDT 24
Peak memory 217604 kb
Host smart-6d809f54-96a9-4eb3-a3f8-66c1fc598bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829433774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2829433774
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3816348320
Short name T472
Test name
Test status
Simulation time 533699470 ps
CPU time 1.73 seconds
Started Aug 15 05:14:37 PM PDT 24
Finished Aug 15 05:14:39 PM PDT 24
Peak memory 208692 kb
Host smart-b2140956-4b86-48f9-a08c-71dd94eabd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816348320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3816348320
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.177068963
Short name T643
Test name
Test status
Simulation time 107124798 ps
CPU time 2.01 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:14:48 PM PDT 24
Peak memory 217136 kb
Host smart-3d4182b9-4e22-4393-82ed-97deaaed4fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177068963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.177068963
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1100834508
Short name T338
Test name
Test status
Simulation time 22078755 ps
CPU time 0.74 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:14:46 PM PDT 24
Peak memory 206848 kb
Host smart-011b3d6c-5cb6-4fc6-bbdb-525cc76b8674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100834508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1100834508
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.4141622252
Short name T3
Test name
Test status
Simulation time 22003785344 ps
CPU time 16.27 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:15:02 PM PDT 24
Peak memory 225380 kb
Host smart-6813200f-9c9f-4785-9747-5e267ae50d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141622252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4141622252
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3996044905
Short name T141
Test name
Test status
Simulation time 15121145 ps
CPU time 0.74 seconds
Started Aug 15 05:14:44 PM PDT 24
Finished Aug 15 05:14:46 PM PDT 24
Peak memory 205628 kb
Host smart-e343b785-f096-4ffe-803c-6d1763fc71dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996044905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3996044905
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1415181545
Short name T379
Test name
Test status
Simulation time 265477309 ps
CPU time 2.89 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:14:49 PM PDT 24
Peak memory 225216 kb
Host smart-4ede574a-bb56-4e6d-9e1f-e9feb0f25af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415181545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1415181545
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3605093168
Short name T416
Test name
Test status
Simulation time 27017864 ps
CPU time 0.78 seconds
Started Aug 15 05:14:44 PM PDT 24
Finished Aug 15 05:14:45 PM PDT 24
Peak memory 206700 kb
Host smart-cf7def15-bf16-42c3-ae76-2d4d4dafc1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605093168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3605093168
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2142529929
Short name T631
Test name
Test status
Simulation time 92268826162 ps
CPU time 141.18 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:17:06 PM PDT 24
Peak memory 251940 kb
Host smart-464fc7ce-4a69-4a70-b2d5-795fee805bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142529929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2142529929
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3984351898
Short name T473
Test name
Test status
Simulation time 923205385 ps
CPU time 10.36 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:14:56 PM PDT 24
Peak memory 220364 kb
Host smart-2f9af3bc-21c0-4db3-b874-2af538da9ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984351898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3984351898
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1619842065
Short name T1005
Test name
Test status
Simulation time 110192012102 ps
CPU time 240.86 seconds
Started Aug 15 05:14:50 PM PDT 24
Finished Aug 15 05:18:51 PM PDT 24
Peak memory 261936 kb
Host smart-28e632f1-eeea-40d5-bb43-a0529874fea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619842065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1619842065
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3938449822
Short name T856
Test name
Test status
Simulation time 8892073582 ps
CPU time 31.7 seconds
Started Aug 15 05:14:46 PM PDT 24
Finished Aug 15 05:15:18 PM PDT 24
Peak memory 225484 kb
Host smart-a286fd85-5c54-4e9c-b63e-57c87abc9b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938449822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3938449822
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.408592988
Short name T412
Test name
Test status
Simulation time 25148607765 ps
CPU time 59.01 seconds
Started Aug 15 05:14:46 PM PDT 24
Finished Aug 15 05:15:45 PM PDT 24
Peak memory 250028 kb
Host smart-ccd4072a-e40b-4689-a1db-8bade4a8a51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408592988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.408592988
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2773456669
Short name T811
Test name
Test status
Simulation time 101672019 ps
CPU time 3.48 seconds
Started Aug 15 05:14:46 PM PDT 24
Finished Aug 15 05:14:50 PM PDT 24
Peak memory 225324 kb
Host smart-8eb60a2b-3846-4ec0-90d2-d418c98e8fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773456669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2773456669
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.962307208
Short name T220
Test name
Test status
Simulation time 3049332428 ps
CPU time 18.95 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:15:04 PM PDT 24
Peak memory 225440 kb
Host smart-1bfb794e-9d87-44fc-a9b9-4dbfbff49d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962307208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.962307208
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2163514551
Short name T573
Test name
Test status
Simulation time 625822204 ps
CPU time 9.89 seconds
Started Aug 15 05:14:48 PM PDT 24
Finished Aug 15 05:14:58 PM PDT 24
Peak memory 236764 kb
Host smart-b92603f3-e42e-48e5-9997-43a091d15410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163514551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2163514551
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3888706134
Short name T763
Test name
Test status
Simulation time 287030869 ps
CPU time 5.85 seconds
Started Aug 15 05:14:46 PM PDT 24
Finished Aug 15 05:14:52 PM PDT 24
Peak memory 225276 kb
Host smart-07b538e6-61b4-4bd9-b253-f33f2f2172b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888706134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3888706134
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.117127119
Short name T641
Test name
Test status
Simulation time 7131058704 ps
CPU time 7.8 seconds
Started Aug 15 05:14:48 PM PDT 24
Finished Aug 15 05:14:56 PM PDT 24
Peak memory 220156 kb
Host smart-c27620ae-310d-4264-b5b6-6638956ed3d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=117127119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.117127119
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2963753882
Short name T736
Test name
Test status
Simulation time 65734372306 ps
CPU time 623.02 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:25:09 PM PDT 24
Peak memory 271868 kb
Host smart-7635d111-786e-4048-a304-9be0fa1a833b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963753882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2963753882
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2818919705
Short name T387
Test name
Test status
Simulation time 4912287826 ps
CPU time 20.79 seconds
Started Aug 15 05:14:47 PM PDT 24
Finished Aug 15 05:15:08 PM PDT 24
Peak memory 221404 kb
Host smart-e0843ece-3eee-45b5-8c7e-f188e5cfa8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818919705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2818919705
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2140593431
Short name T640
Test name
Test status
Simulation time 1316958083 ps
CPU time 3.05 seconds
Started Aug 15 05:14:49 PM PDT 24
Finished Aug 15 05:14:53 PM PDT 24
Peak memory 216912 kb
Host smart-54dd7ad1-318e-4c56-977f-10aa12d1c621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140593431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2140593431
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.4151333904
Short name T527
Test name
Test status
Simulation time 404739219 ps
CPU time 2.48 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:14:47 PM PDT 24
Peak memory 217156 kb
Host smart-49db42a9-be1e-469a-b6aa-95504773d213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151333904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.4151333904
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2026964736
Short name T950
Test name
Test status
Simulation time 21564214 ps
CPU time 0.79 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:14:46 PM PDT 24
Peak memory 206832 kb
Host smart-e7d31006-b394-4283-8c37-89fbee7488c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026964736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2026964736
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.539047177
Short name T794
Test name
Test status
Simulation time 5524458878 ps
CPU time 18.21 seconds
Started Aug 15 05:14:46 PM PDT 24
Finished Aug 15 05:15:04 PM PDT 24
Peak memory 241864 kb
Host smart-04ad2b3c-1df9-4ab3-a007-b985fd29f1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539047177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.539047177
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.369471973
Short name T421
Test name
Test status
Simulation time 24603468 ps
CPU time 0.69 seconds
Started Aug 15 05:14:52 PM PDT 24
Finished Aug 15 05:14:53 PM PDT 24
Peak memory 206596 kb
Host smart-47b6072a-9598-4e05-ad16-1e8f9c3ff364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369471973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.369471973
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3310934732
Short name T574
Test name
Test status
Simulation time 2085928975 ps
CPU time 25.93 seconds
Started Aug 15 05:14:56 PM PDT 24
Finished Aug 15 05:15:22 PM PDT 24
Peak memory 225312 kb
Host smart-90a29627-7556-4107-8bc1-a86634d9e082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310934732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3310934732
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.4270518089
Short name T458
Test name
Test status
Simulation time 22503929 ps
CPU time 0.86 seconds
Started Aug 15 05:14:46 PM PDT 24
Finished Aug 15 05:14:47 PM PDT 24
Peak memory 207400 kb
Host smart-9bd4683e-729d-4000-9cc6-ca3cb6f6583f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270518089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4270518089
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3575188593
Short name T605
Test name
Test status
Simulation time 115870915734 ps
CPU time 80.24 seconds
Started Aug 15 05:14:56 PM PDT 24
Finished Aug 15 05:16:16 PM PDT 24
Peak memory 241996 kb
Host smart-61efe755-0b6d-469b-8226-ded026515517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575188593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3575188593
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.809675931
Short name T54
Test name
Test status
Simulation time 10425539887 ps
CPU time 51.43 seconds
Started Aug 15 05:14:54 PM PDT 24
Finished Aug 15 05:15:46 PM PDT 24
Peak memory 257672 kb
Host smart-0d97a556-01fd-4367-b4bc-2552c3beecaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809675931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.809675931
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1058633860
Short name T721
Test name
Test status
Simulation time 19624606396 ps
CPU time 76.89 seconds
Started Aug 15 05:14:54 PM PDT 24
Finished Aug 15 05:16:11 PM PDT 24
Peak memory 256740 kb
Host smart-cbb8abfb-cbc2-4a33-9e1a-19b257b2e756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058633860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1058633860
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.275610368
Short name T372
Test name
Test status
Simulation time 623491759 ps
CPU time 10.09 seconds
Started Aug 15 05:14:55 PM PDT 24
Finished Aug 15 05:15:05 PM PDT 24
Peak memory 225348 kb
Host smart-38838dad-6f00-488a-975d-fce5007fae5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275610368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.275610368
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1698308215
Short name T689
Test name
Test status
Simulation time 1414943428 ps
CPU time 9.05 seconds
Started Aug 15 05:14:55 PM PDT 24
Finished Aug 15 05:15:04 PM PDT 24
Peak memory 235608 kb
Host smart-e4475310-9706-436d-a3e4-1fb3137d89c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698308215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1698308215
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.189193879
Short name T212
Test name
Test status
Simulation time 6789212817 ps
CPU time 12.64 seconds
Started Aug 15 05:14:56 PM PDT 24
Finished Aug 15 05:15:08 PM PDT 24
Peak memory 225416 kb
Host smart-7b815562-96b2-48af-8ed9-6f728024b6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189193879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.189193879
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.180113160
Short name T323
Test name
Test status
Simulation time 1112380212 ps
CPU time 7.8 seconds
Started Aug 15 05:14:53 PM PDT 24
Finished Aug 15 05:15:01 PM PDT 24
Peak memory 225316 kb
Host smart-7f36b2fd-ad38-44d3-b6d2-93316ce10c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180113160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.180113160
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3945107301
Short name T873
Test name
Test status
Simulation time 3833630863 ps
CPU time 11.89 seconds
Started Aug 15 05:14:46 PM PDT 24
Finished Aug 15 05:14:58 PM PDT 24
Peak memory 233524 kb
Host smart-a61481d8-2a45-4a37-96af-e4c788770ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945107301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3945107301
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1331897038
Short name T233
Test name
Test status
Simulation time 12973522200 ps
CPU time 38.28 seconds
Started Aug 15 05:14:47 PM PDT 24
Finished Aug 15 05:15:26 PM PDT 24
Peak memory 236312 kb
Host smart-6d6bd46c-b71a-460a-bcb5-2972f4ead895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331897038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1331897038
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1350323694
Short name T986
Test name
Test status
Simulation time 259119474 ps
CPU time 3.87 seconds
Started Aug 15 05:14:54 PM PDT 24
Finished Aug 15 05:14:58 PM PDT 24
Peak memory 223904 kb
Host smart-66d12640-6721-4db3-a7fa-b85332158c79
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1350323694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1350323694
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3062065240
Short name T172
Test name
Test status
Simulation time 98966844 ps
CPU time 0.99 seconds
Started Aug 15 05:14:54 PM PDT 24
Finished Aug 15 05:14:55 PM PDT 24
Peak memory 206688 kb
Host smart-59707043-6dc6-4c2f-90b1-165707963241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062065240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3062065240
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2446185850
Short name T523
Test name
Test status
Simulation time 13257035 ps
CPU time 0.72 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:14:46 PM PDT 24
Peak memory 206520 kb
Host smart-9c75e335-347b-4a3d-bde2-80fec775d53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446185850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2446185850
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1207643279
Short name T551
Test name
Test status
Simulation time 3379833605 ps
CPU time 13.48 seconds
Started Aug 15 05:14:47 PM PDT 24
Finished Aug 15 05:15:00 PM PDT 24
Peak memory 217312 kb
Host smart-b0daf227-56e8-425a-84f6-99fc19ec2bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207643279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1207643279
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2649257150
Short name T490
Test name
Test status
Simulation time 344981929 ps
CPU time 2.94 seconds
Started Aug 15 05:14:45 PM PDT 24
Finished Aug 15 05:14:48 PM PDT 24
Peak memory 217200 kb
Host smart-0321e823-51fe-46ce-bfc3-d7c5ea54149d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649257150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2649257150
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3048495867
Short name T895
Test name
Test status
Simulation time 68826433 ps
CPU time 0.9 seconds
Started Aug 15 05:14:49 PM PDT 24
Finished Aug 15 05:14:50 PM PDT 24
Peak memory 207832 kb
Host smart-d14ee0cf-f3ca-49df-9463-8d5a2da0ea8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048495867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3048495867
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1852029754
Short name T546
Test name
Test status
Simulation time 1605110962 ps
CPU time 5.64 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:15:09 PM PDT 24
Peak memory 225340 kb
Host smart-3debc621-cff5-4e09-b82b-18492fbf4ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852029754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1852029754
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3822007951
Short name T1006
Test name
Test status
Simulation time 192263238 ps
CPU time 0.72 seconds
Started Aug 15 05:14:55 PM PDT 24
Finished Aug 15 05:14:56 PM PDT 24
Peak memory 206540 kb
Host smart-802044d5-d010-4fa7-925c-6b23ae43eac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822007951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3822007951
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.23764942
Short name T795
Test name
Test status
Simulation time 5719883587 ps
CPU time 13.86 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:15:17 PM PDT 24
Peak memory 225396 kb
Host smart-585bf2de-310b-4cd6-9cc7-122f25d87dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23764942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.23764942
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.506832271
Short name T977
Test name
Test status
Simulation time 23370652 ps
CPU time 0.8 seconds
Started Aug 15 05:14:57 PM PDT 24
Finished Aug 15 05:14:58 PM PDT 24
Peak memory 207404 kb
Host smart-6f904a5d-b78a-4e9b-b366-0a51ce9e2ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506832271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.506832271
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3202054931
Short name T204
Test name
Test status
Simulation time 63055107501 ps
CPU time 401.13 seconds
Started Aug 15 05:14:54 PM PDT 24
Finished Aug 15 05:21:35 PM PDT 24
Peak memory 266500 kb
Host smart-2928c45a-b407-4eca-90a8-4daebb9426e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202054931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3202054931
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3259228946
Short name T882
Test name
Test status
Simulation time 76312688459 ps
CPU time 170.9 seconds
Started Aug 15 05:14:57 PM PDT 24
Finished Aug 15 05:17:48 PM PDT 24
Peak memory 270980 kb
Host smart-1f043965-4737-407b-85ec-c32d56f38f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259228946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3259228946
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1991203138
Short name T529
Test name
Test status
Simulation time 15220090641 ps
CPU time 88.41 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:16:32 PM PDT 24
Peak memory 250184 kb
Host smart-306efef7-5b35-4a24-ab94-3ee1bf2b774c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991203138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1991203138
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2910364960
Short name T875
Test name
Test status
Simulation time 631524424 ps
CPU time 14.65 seconds
Started Aug 15 05:14:56 PM PDT 24
Finished Aug 15 05:15:11 PM PDT 24
Peak memory 233512 kb
Host smart-6d3cdca5-e506-4bf8-b484-bed69fc2e11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910364960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2910364960
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2515983780
Short name T627
Test name
Test status
Simulation time 77604665077 ps
CPU time 124.11 seconds
Started Aug 15 05:14:56 PM PDT 24
Finished Aug 15 05:17:01 PM PDT 24
Peak memory 250136 kb
Host smart-aee8571e-a81c-4023-a0fd-ff480a66cb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515983780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2515983780
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1707984136
Short name T505
Test name
Test status
Simulation time 325553679 ps
CPU time 2.47 seconds
Started Aug 15 05:14:54 PM PDT 24
Finished Aug 15 05:14:57 PM PDT 24
Peak memory 233264 kb
Host smart-909034e4-6b65-49e8-86d0-45511c673b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707984136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1707984136
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3835789773
Short name T7
Test name
Test status
Simulation time 15258407219 ps
CPU time 28.54 seconds
Started Aug 15 05:14:57 PM PDT 24
Finished Aug 15 05:15:26 PM PDT 24
Peak memory 233628 kb
Host smart-d53f91fd-949b-425c-b779-4a4c6d51fda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835789773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3835789773
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3333072384
Short name T261
Test name
Test status
Simulation time 2965847503 ps
CPU time 6.71 seconds
Started Aug 15 05:14:53 PM PDT 24
Finished Aug 15 05:15:00 PM PDT 24
Peak memory 233692 kb
Host smart-15345897-c5c4-4aeb-84cc-25719214e364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333072384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3333072384
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.507300678
Short name T420
Test name
Test status
Simulation time 11860246548 ps
CPU time 13.84 seconds
Started Aug 15 05:14:53 PM PDT 24
Finished Aug 15 05:15:07 PM PDT 24
Peak memory 233604 kb
Host smart-56ed5e77-c6cc-4b4b-943d-424fbf21fa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507300678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.507300678
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.572452751
Short name T346
Test name
Test status
Simulation time 885667512 ps
CPU time 5.18 seconds
Started Aug 15 05:14:56 PM PDT 24
Finished Aug 15 05:15:01 PM PDT 24
Peak memory 223480 kb
Host smart-98083f21-fdef-40bd-aec0-c2334ea66fd4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=572452751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.572452751
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3365120852
Short name T443
Test name
Test status
Simulation time 2325204779 ps
CPU time 7.93 seconds
Started Aug 15 05:14:53 PM PDT 24
Finished Aug 15 05:15:01 PM PDT 24
Peak memory 217452 kb
Host smart-009898f6-5a75-4b23-8e85-b29f23369edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365120852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3365120852
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1530218958
Short name T28
Test name
Test status
Simulation time 884260785 ps
CPU time 2.71 seconds
Started Aug 15 05:14:56 PM PDT 24
Finished Aug 15 05:14:59 PM PDT 24
Peak memory 217152 kb
Host smart-fe838b21-c9c4-4b94-8078-11e57f651e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530218958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1530218958
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2923973864
Short name T483
Test name
Test status
Simulation time 376046537 ps
CPU time 1.18 seconds
Started Aug 15 05:14:56 PM PDT 24
Finished Aug 15 05:14:58 PM PDT 24
Peak memory 217172 kb
Host smart-73a22c17-5610-460f-9eb6-8b6f158bf7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923973864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2923973864
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2066058329
Short name T94
Test name
Test status
Simulation time 26827516 ps
CPU time 0.86 seconds
Started Aug 15 05:14:56 PM PDT 24
Finished Aug 15 05:14:57 PM PDT 24
Peak memory 206808 kb
Host smart-1d8385da-9d59-4eb0-a99b-e9ae90a0a447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066058329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2066058329
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3629693345
Short name T537
Test name
Test status
Simulation time 2573125310 ps
CPU time 4.79 seconds
Started Aug 15 05:14:56 PM PDT 24
Finished Aug 15 05:15:01 PM PDT 24
Peak memory 225348 kb
Host smart-35fc6399-01c9-4b5a-8255-b110565b23bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629693345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3629693345
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2765348563
Short name T432
Test name
Test status
Simulation time 14753498 ps
CPU time 0.74 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:15:04 PM PDT 24
Peak memory 205684 kb
Host smart-f58e0c38-8c6a-4703-a435-dad86d28b216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765348563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2765348563
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1387356077
Short name T460
Test name
Test status
Simulation time 1108620018 ps
CPU time 3.29 seconds
Started Aug 15 05:15:07 PM PDT 24
Finished Aug 15 05:15:10 PM PDT 24
Peak memory 225384 kb
Host smart-25f80a0c-77da-451c-9396-8a82a33b8754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387356077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1387356077
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1970476168
Short name T998
Test name
Test status
Simulation time 18473344 ps
CPU time 0.8 seconds
Started Aug 15 05:14:56 PM PDT 24
Finished Aug 15 05:14:57 PM PDT 24
Peak memory 207392 kb
Host smart-719aabd4-b835-4e41-9912-6560fc207378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970476168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1970476168
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3379666362
Short name T278
Test name
Test status
Simulation time 272353600043 ps
CPU time 290.78 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:19:54 PM PDT 24
Peak memory 258188 kb
Host smart-5e1cbf17-58ac-4d05-aad2-f192abb84c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379666362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3379666362
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.4025568966
Short name T315
Test name
Test status
Simulation time 41291352441 ps
CPU time 132.75 seconds
Started Aug 15 05:15:02 PM PDT 24
Finished Aug 15 05:17:15 PM PDT 24
Peak memory 255108 kb
Host smart-da9db2cc-a36b-4e48-b3d3-e179c1b84d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025568966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.4025568966
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3580848655
Short name T279
Test name
Test status
Simulation time 33113031822 ps
CPU time 74.66 seconds
Started Aug 15 05:15:05 PM PDT 24
Finished Aug 15 05:16:20 PM PDT 24
Peak memory 233716 kb
Host smart-cbcc3521-0e51-4fb3-9b1f-6662d9be9f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580848655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3580848655
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1361274325
Short name T1004
Test name
Test status
Simulation time 747291786 ps
CPU time 15.74 seconds
Started Aug 15 05:15:02 PM PDT 24
Finished Aug 15 05:15:18 PM PDT 24
Peak memory 233444 kb
Host smart-da72c31a-c197-4fb4-ae46-3d4c5984465f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361274325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1361274325
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.499504185
Short name T566
Test name
Test status
Simulation time 375164330266 ps
CPU time 165.99 seconds
Started Aug 15 05:15:04 PM PDT 24
Finished Aug 15 05:17:50 PM PDT 24
Peak memory 249972 kb
Host smart-0bfb046e-0690-4fb9-aca9-820e59d3bd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499504185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.499504185
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.324287808
Short name T423
Test name
Test status
Simulation time 3948373817 ps
CPU time 19.76 seconds
Started Aug 15 05:15:11 PM PDT 24
Finished Aug 15 05:15:31 PM PDT 24
Peak memory 233692 kb
Host smart-3f8d7a6f-9f15-4502-a904-a9c6f00b615d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324287808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.324287808
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1841676203
Short name T764
Test name
Test status
Simulation time 5084968532 ps
CPU time 45.11 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:15:48 PM PDT 24
Peak memory 233604 kb
Host smart-f7d6d48b-549b-4338-8f80-b0a265797ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841676203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1841676203
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3471524366
Short name T1012
Test name
Test status
Simulation time 7069937159 ps
CPU time 12.64 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:15:16 PM PDT 24
Peak memory 233696 kb
Host smart-d60b6354-6eac-4f69-b668-74674db55aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471524366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3471524366
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1917295154
Short name T787
Test name
Test status
Simulation time 7177014203 ps
CPU time 21.02 seconds
Started Aug 15 05:15:01 PM PDT 24
Finished Aug 15 05:15:22 PM PDT 24
Peak memory 225508 kb
Host smart-108dfb07-b5c8-4a75-906f-fff5a434074e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917295154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1917295154
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1237706091
Short name T415
Test name
Test status
Simulation time 354647862 ps
CPU time 6.01 seconds
Started Aug 15 05:15:11 PM PDT 24
Finished Aug 15 05:15:17 PM PDT 24
Peak memory 222968 kb
Host smart-50482817-fbed-4812-83a7-9cd010fb5b56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1237706091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1237706091
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.481730548
Short name T289
Test name
Test status
Simulation time 50198929309 ps
CPU time 221.23 seconds
Started Aug 15 05:15:02 PM PDT 24
Finished Aug 15 05:18:43 PM PDT 24
Peak memory 273748 kb
Host smart-4acc1f3d-5ac6-4fb1-9105-947c7129b9f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481730548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.481730548
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.739733021
Short name T648
Test name
Test status
Simulation time 1946930009 ps
CPU time 12.19 seconds
Started Aug 15 05:15:01 PM PDT 24
Finished Aug 15 05:15:14 PM PDT 24
Peak memory 217212 kb
Host smart-30ba7296-c97c-4eb6-9c32-94c8c0d960b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739733021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.739733021
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.408642720
Short name T311
Test name
Test status
Simulation time 957441657 ps
CPU time 7.52 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:15:11 PM PDT 24
Peak memory 217148 kb
Host smart-df20ee0d-b017-4fba-8ed3-5d2354ac849e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408642720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.408642720
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.792996712
Short name T12
Test name
Test status
Simulation time 166449116 ps
CPU time 5.67 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:15:09 PM PDT 24
Peak memory 217140 kb
Host smart-9b91feb0-491d-4ce2-85a2-5a1b25ad066b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792996712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.792996712
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3618685685
Short name T711
Test name
Test status
Simulation time 32146065 ps
CPU time 0.77 seconds
Started Aug 15 05:15:11 PM PDT 24
Finished Aug 15 05:15:12 PM PDT 24
Peak memory 206848 kb
Host smart-805c6edf-8bf0-440e-8c94-482932675fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618685685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3618685685
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2365755096
Short name T710
Test name
Test status
Simulation time 27318031601 ps
CPU time 23.65 seconds
Started Aug 15 05:15:05 PM PDT 24
Finished Aug 15 05:15:29 PM PDT 24
Peak memory 241808 kb
Host smart-4ef7dbf6-a487-47c5-8c6e-9e2b2f17b938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365755096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2365755096
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.638816660
Short name T748
Test name
Test status
Simulation time 12972187 ps
CPU time 0.74 seconds
Started Aug 15 05:15:01 PM PDT 24
Finished Aug 15 05:15:02 PM PDT 24
Peak memory 205676 kb
Host smart-11443f33-a0d3-4e2c-a1b5-64cd20b985b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638816660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.638816660
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2758328110
Short name T264
Test name
Test status
Simulation time 117468723 ps
CPU time 3.34 seconds
Started Aug 15 05:15:01 PM PDT 24
Finished Aug 15 05:15:04 PM PDT 24
Peak memory 233500 kb
Host smart-b72314c4-3e86-4fa1-9fbf-70eceac01290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758328110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2758328110
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.832523904
Short name T857
Test name
Test status
Simulation time 101919360 ps
CPU time 0.74 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:15:04 PM PDT 24
Peak memory 206684 kb
Host smart-35f515c4-44de-4b4c-8dbc-8639a35f9495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832523904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.832523904
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1888850271
Short name T269
Test name
Test status
Simulation time 37082553565 ps
CPU time 185.11 seconds
Started Aug 15 05:15:06 PM PDT 24
Finished Aug 15 05:18:12 PM PDT 24
Peak memory 254804 kb
Host smart-fac95015-d7f1-4ed8-86ed-a413d795db26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888850271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1888850271
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2233401462
Short name T409
Test name
Test status
Simulation time 4040674226 ps
CPU time 40.41 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:15:44 PM PDT 24
Peak memory 249260 kb
Host smart-7618cb78-b709-4009-9766-25bf0a89306c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233401462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2233401462
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.4185299231
Short name T441
Test name
Test status
Simulation time 7395169954 ps
CPU time 63.65 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:16:07 PM PDT 24
Peak memory 258132 kb
Host smart-a53ee457-b7ee-47b5-906c-690859a5f9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185299231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.4185299231
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3360460665
Short name T668
Test name
Test status
Simulation time 162007309 ps
CPU time 4.2 seconds
Started Aug 15 05:15:05 PM PDT 24
Finished Aug 15 05:15:10 PM PDT 24
Peak memory 224880 kb
Host smart-ae0f0ef9-8f2c-4292-b9d0-70fb9535dd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360460665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3360460665
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3443254317
Short name T892
Test name
Test status
Simulation time 23070741392 ps
CPU time 161.28 seconds
Started Aug 15 05:15:11 PM PDT 24
Finished Aug 15 05:17:52 PM PDT 24
Peak memory 252940 kb
Host smart-e97d3959-590d-4dc8-93b3-ef77d246e8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443254317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3443254317
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1165384744
Short name T510
Test name
Test status
Simulation time 53207619 ps
CPU time 2.52 seconds
Started Aug 15 05:15:05 PM PDT 24
Finished Aug 15 05:15:07 PM PDT 24
Peak memory 233192 kb
Host smart-fc416bfd-2f6d-492b-9867-ed7d09e07aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165384744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1165384744
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.540072387
Short name T358
Test name
Test status
Simulation time 293452530 ps
CPU time 3.7 seconds
Started Aug 15 05:15:02 PM PDT 24
Finished Aug 15 05:15:05 PM PDT 24
Peak memory 233588 kb
Host smart-399adafd-a3d2-4ba9-8b10-ffe44d38cb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540072387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.540072387
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4105339893
Short name T947
Test name
Test status
Simulation time 2385558751 ps
CPU time 9.46 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:15:12 PM PDT 24
Peak memory 233636 kb
Host smart-af43e21a-0d5a-4dc0-8d3d-7cf547f66621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105339893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4105339893
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1875794985
Short name T511
Test name
Test status
Simulation time 775923491 ps
CPU time 4.46 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:15:08 PM PDT 24
Peak memory 225264 kb
Host smart-c62ef890-267c-48ca-90ec-9a0bf18e4f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875794985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1875794985
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.741987226
Short name T684
Test name
Test status
Simulation time 1244629945 ps
CPU time 4.89 seconds
Started Aug 15 05:15:11 PM PDT 24
Finished Aug 15 05:15:16 PM PDT 24
Peak memory 223936 kb
Host smart-39d2eda7-d9ab-4e9e-92c4-d4b4d76a4fb0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=741987226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.741987226
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3672689582
Short name T22
Test name
Test status
Simulation time 11170172491 ps
CPU time 37.76 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:15:41 PM PDT 24
Peak memory 250048 kb
Host smart-051024d1-1ba5-42fa-bc54-e59c8faa9077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672689582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3672689582
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.690913115
Short name T30
Test name
Test status
Simulation time 3006420021 ps
CPU time 20.54 seconds
Started Aug 15 05:15:02 PM PDT 24
Finished Aug 15 05:15:22 PM PDT 24
Peak memory 221236 kb
Host smart-5d0d30f3-4c9f-4a0b-b74c-20525e939ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690913115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.690913115
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3287338414
Short name T669
Test name
Test status
Simulation time 4326328604 ps
CPU time 12.67 seconds
Started Aug 15 05:15:11 PM PDT 24
Finished Aug 15 05:15:24 PM PDT 24
Peak memory 217248 kb
Host smart-49bf3b44-bcca-4882-9c9d-f06cc97d2422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287338414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3287338414
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2579084794
Short name T769
Test name
Test status
Simulation time 80023410 ps
CPU time 0.97 seconds
Started Aug 15 05:15:06 PM PDT 24
Finished Aug 15 05:15:07 PM PDT 24
Peak memory 207868 kb
Host smart-6d6cfb9b-6af9-4569-bbed-4b09be9ccfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579084794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2579084794
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.115286153
Short name T564
Test name
Test status
Simulation time 461614142 ps
CPU time 0.95 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:15:04 PM PDT 24
Peak memory 206848 kb
Host smart-7c7358f7-1f76-498e-83d7-3b1c9c6f586c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115286153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.115286153
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.781319793
Short name T850
Test name
Test status
Simulation time 1806079902 ps
CPU time 12.62 seconds
Started Aug 15 05:15:05 PM PDT 24
Finished Aug 15 05:15:18 PM PDT 24
Peak memory 249776 kb
Host smart-7255f1f5-0c68-41ca-a447-dcc2098d4fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781319793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.781319793
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3397928527
Short name T918
Test name
Test status
Simulation time 50322154 ps
CPU time 0.74 seconds
Started Aug 15 05:15:12 PM PDT 24
Finished Aug 15 05:15:13 PM PDT 24
Peak memory 205624 kb
Host smart-5188f0a3-fa3c-43e2-8b66-3ea74b44e48c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397928527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3397928527
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.679296038
Short name T539
Test name
Test status
Simulation time 7157149047 ps
CPU time 12.46 seconds
Started Aug 15 05:15:13 PM PDT 24
Finished Aug 15 05:15:25 PM PDT 24
Peak memory 233640 kb
Host smart-b690aaf6-533e-4802-bf7e-8d55ac57d1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679296038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.679296038
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.458011611
Short name T326
Test name
Test status
Simulation time 100170531 ps
CPU time 0.72 seconds
Started Aug 15 05:15:02 PM PDT 24
Finished Aug 15 05:15:03 PM PDT 24
Peak memory 206380 kb
Host smart-0092b033-c4df-45d3-b41c-4f50dd6c4414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458011611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.458011611
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.802828889
Short name T273
Test name
Test status
Simulation time 58345272780 ps
CPU time 437.18 seconds
Started Aug 15 05:15:12 PM PDT 24
Finished Aug 15 05:22:29 PM PDT 24
Peak memory 255980 kb
Host smart-58f26e2d-c5ee-4d7d-962d-b72563bd4f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802828889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.802828889
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1001682287
Short name T815
Test name
Test status
Simulation time 26806304238 ps
CPU time 35.73 seconds
Started Aug 15 05:15:14 PM PDT 24
Finished Aug 15 05:15:49 PM PDT 24
Peak memory 252232 kb
Host smart-d8ef63ca-e85b-4180-88ee-c5cec35d11de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001682287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1001682287
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1731742697
Short name T553
Test name
Test status
Simulation time 9141210693 ps
CPU time 23.35 seconds
Started Aug 15 05:15:17 PM PDT 24
Finished Aug 15 05:15:40 PM PDT 24
Peak memory 224716 kb
Host smart-762a37ed-26a1-45fb-98c7-6e2ee15dfa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731742697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1731742697
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1074083542
Short name T768
Test name
Test status
Simulation time 817702767 ps
CPU time 18.15 seconds
Started Aug 15 05:15:12 PM PDT 24
Finished Aug 15 05:15:30 PM PDT 24
Peak memory 254044 kb
Host smart-53cd4b6d-94c9-4a2c-9584-da78191e4e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074083542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1074083542
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1938969778
Short name T688
Test name
Test status
Simulation time 7081967689 ps
CPU time 30.71 seconds
Started Aug 15 05:15:13 PM PDT 24
Finished Aug 15 05:15:44 PM PDT 24
Peak memory 253200 kb
Host smart-133ca255-ac72-4756-b7a0-fa6d30464f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938969778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1938969778
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1028608706
Short name T723
Test name
Test status
Simulation time 1901754290 ps
CPU time 19.78 seconds
Started Aug 15 05:15:01 PM PDT 24
Finished Aug 15 05:15:21 PM PDT 24
Peak memory 225432 kb
Host smart-352a4cb3-0ada-4604-bafd-48c186925d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028608706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1028608706
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2323710205
Short name T450
Test name
Test status
Simulation time 98342693 ps
CPU time 2.48 seconds
Started Aug 15 05:15:04 PM PDT 24
Finished Aug 15 05:15:07 PM PDT 24
Peak memory 225284 kb
Host smart-43a84a9f-f308-407e-b156-6fa9190adcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323710205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2323710205
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.608789400
Short name T79
Test name
Test status
Simulation time 113315698 ps
CPU time 2.52 seconds
Started Aug 15 05:15:05 PM PDT 24
Finished Aug 15 05:15:08 PM PDT 24
Peak memory 233240 kb
Host smart-a92ed022-b827-4a64-96a3-64e5db32b097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608789400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.608789400
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1755987396
Short name T213
Test name
Test status
Simulation time 288833077 ps
CPU time 2.95 seconds
Started Aug 15 05:15:02 PM PDT 24
Finished Aug 15 05:15:05 PM PDT 24
Peak memory 225220 kb
Host smart-2d6bff6a-9270-4c34-8217-e7f59f694701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755987396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1755987396
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.821297093
Short name T156
Test name
Test status
Simulation time 2451018313 ps
CPU time 16.03 seconds
Started Aug 15 05:15:15 PM PDT 24
Finished Aug 15 05:15:31 PM PDT 24
Peak memory 222524 kb
Host smart-0d04da92-18c7-4d0b-9c8d-f909374b7ffa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=821297093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.821297093
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2092711484
Short name T168
Test name
Test status
Simulation time 490877417014 ps
CPU time 319.79 seconds
Started Aug 15 05:15:17 PM PDT 24
Finished Aug 15 05:20:37 PM PDT 24
Peak memory 291076 kb
Host smart-e7c03d9b-7226-4f78-a982-ecf6f502b41f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092711484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2092711484
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1657422114
Short name T726
Test name
Test status
Simulation time 26756628922 ps
CPU time 35.37 seconds
Started Aug 15 05:15:01 PM PDT 24
Finished Aug 15 05:15:36 PM PDT 24
Peak memory 221592 kb
Host smart-cc39f1c1-04d2-42dd-87aa-1d41bb985e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657422114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1657422114
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2888317794
Short name T516
Test name
Test status
Simulation time 2290060017 ps
CPU time 10.52 seconds
Started Aug 15 05:15:05 PM PDT 24
Finished Aug 15 05:15:16 PM PDT 24
Peak memory 216840 kb
Host smart-795db1a4-e1a9-433c-b4f5-32d2822026da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888317794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2888317794
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1384009784
Short name T309
Test name
Test status
Simulation time 513032037 ps
CPU time 2.26 seconds
Started Aug 15 05:15:03 PM PDT 24
Finished Aug 15 05:15:05 PM PDT 24
Peak memory 217144 kb
Host smart-df6e2892-63e0-434a-9d33-7634385ec5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384009784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1384009784
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2350841052
Short name T583
Test name
Test status
Simulation time 62634066 ps
CPU time 0.92 seconds
Started Aug 15 05:15:01 PM PDT 24
Finished Aug 15 05:15:02 PM PDT 24
Peak memory 206772 kb
Host smart-5caeca30-3b05-4b0d-9780-4209b74c7074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350841052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2350841052
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.754236754
Short name T476
Test name
Test status
Simulation time 998601591 ps
CPU time 6.35 seconds
Started Aug 15 05:15:12 PM PDT 24
Finished Aug 15 05:15:18 PM PDT 24
Peak memory 233540 kb
Host smart-b3624e52-e66a-461f-a3fe-717a6193bca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754236754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.754236754
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1660840076
Short name T361
Test name
Test status
Simulation time 43017164 ps
CPU time 0.73 seconds
Started Aug 15 05:15:12 PM PDT 24
Finished Aug 15 05:15:13 PM PDT 24
Peak memory 206220 kb
Host smart-55950cc6-8246-4059-afe5-ad7c71e638a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660840076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1660840076
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.504041983
Short name T328
Test name
Test status
Simulation time 935050459 ps
CPU time 8.56 seconds
Started Aug 15 05:15:15 PM PDT 24
Finished Aug 15 05:15:24 PM PDT 24
Peak memory 225352 kb
Host smart-270f5dc4-e51b-47b9-9f5e-e86f2aa93fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504041983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.504041983
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2800540744
Short name T65
Test name
Test status
Simulation time 27120389 ps
CPU time 0.75 seconds
Started Aug 15 05:15:17 PM PDT 24
Finished Aug 15 05:15:18 PM PDT 24
Peak memory 206696 kb
Host smart-8c0de416-22f7-4e33-b82d-062b2f1d3760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800540744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2800540744
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1554610628
Short name T428
Test name
Test status
Simulation time 34067687589 ps
CPU time 112.05 seconds
Started Aug 15 05:15:13 PM PDT 24
Finished Aug 15 05:17:05 PM PDT 24
Peak memory 250084 kb
Host smart-dc485bed-d39b-4a3d-be29-4b9f42c204fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554610628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1554610628
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1697630005
Short name T556
Test name
Test status
Simulation time 130321901178 ps
CPU time 299.74 seconds
Started Aug 15 05:15:14 PM PDT 24
Finished Aug 15 05:20:14 PM PDT 24
Peak memory 251208 kb
Host smart-11aa7271-9893-4fb9-8382-656b14c392ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697630005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1697630005
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3912913230
Short name T282
Test name
Test status
Simulation time 10879928763 ps
CPU time 177.91 seconds
Started Aug 15 05:15:12 PM PDT 24
Finished Aug 15 05:18:10 PM PDT 24
Peak memory 274724 kb
Host smart-66e1c6a3-24c9-4817-85f4-bea89dd3b2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912913230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3912913230
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2368142623
Short name T985
Test name
Test status
Simulation time 647262797 ps
CPU time 4.95 seconds
Started Aug 15 05:15:17 PM PDT 24
Finished Aug 15 05:15:22 PM PDT 24
Peak memory 233452 kb
Host smart-fcc83a4d-8934-4b52-820c-69ffc6da8442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368142623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2368142623
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1686317876
Short name T548
Test name
Test status
Simulation time 10494185191 ps
CPU time 62.76 seconds
Started Aug 15 05:15:13 PM PDT 24
Finished Aug 15 05:16:16 PM PDT 24
Peak memory 254368 kb
Host smart-19cf3e9f-2af2-4475-8d0e-e986161d646e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686317876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1686317876
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3934858863
Short name T221
Test name
Test status
Simulation time 148425359 ps
CPU time 3.58 seconds
Started Aug 15 05:15:14 PM PDT 24
Finished Aug 15 05:15:18 PM PDT 24
Peak memory 233544 kb
Host smart-c2a968ef-4e95-4a13-a18a-4371a0782d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934858863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3934858863
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.4006098449
Short name T804
Test name
Test status
Simulation time 4351725134 ps
CPU time 29.97 seconds
Started Aug 15 05:15:14 PM PDT 24
Finished Aug 15 05:15:45 PM PDT 24
Peak memory 225488 kb
Host smart-73473e56-ecf6-42f4-83a5-abf1d23f2514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006098449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4006098449
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4082866857
Short name T630
Test name
Test status
Simulation time 76022386 ps
CPU time 2.03 seconds
Started Aug 15 05:15:12 PM PDT 24
Finished Aug 15 05:15:14 PM PDT 24
Peak memory 219400 kb
Host smart-d787de45-09f5-46cf-9a69-cb35fb695a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082866857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4082866857
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3490248030
Short name T658
Test name
Test status
Simulation time 1009352760 ps
CPU time 5.52 seconds
Started Aug 15 05:15:13 PM PDT 24
Finished Aug 15 05:15:18 PM PDT 24
Peak memory 225212 kb
Host smart-53eccd0f-9cb5-4312-8c28-93a5285aba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490248030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3490248030
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.313826821
Short name T781
Test name
Test status
Simulation time 3359936129 ps
CPU time 19.69 seconds
Started Aug 15 05:15:14 PM PDT 24
Finished Aug 15 05:15:34 PM PDT 24
Peak memory 223544 kb
Host smart-6d003592-612e-43cc-ba18-fe799f2649d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=313826821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.313826821
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.169719135
Short name T671
Test name
Test status
Simulation time 20176473917 ps
CPU time 30.41 seconds
Started Aug 15 05:15:14 PM PDT 24
Finished Aug 15 05:15:45 PM PDT 24
Peak memory 217244 kb
Host smart-5fa89f28-a3a5-4937-8f99-47204b5a05e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169719135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.169719135
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1524842594
Short name T1007
Test name
Test status
Simulation time 8010298735 ps
CPU time 19.64 seconds
Started Aug 15 05:15:15 PM PDT 24
Finished Aug 15 05:15:35 PM PDT 24
Peak memory 217344 kb
Host smart-88110021-d619-4730-8eda-c1e59e5dba1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524842594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1524842594
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1137226843
Short name T876
Test name
Test status
Simulation time 105153891 ps
CPU time 3.46 seconds
Started Aug 15 05:15:15 PM PDT 24
Finished Aug 15 05:15:19 PM PDT 24
Peak memory 217188 kb
Host smart-ede709d4-a965-424a-b955-ba16960af0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137226843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1137226843
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1733294655
Short name T987
Test name
Test status
Simulation time 284597794 ps
CPU time 0.98 seconds
Started Aug 15 05:15:13 PM PDT 24
Finished Aug 15 05:15:14 PM PDT 24
Peak memory 207888 kb
Host smart-cff3a218-c3fc-4ec4-b393-394d639702a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733294655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1733294655
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1576080789
Short name T718
Test name
Test status
Simulation time 1717204269 ps
CPU time 10.36 seconds
Started Aug 15 05:15:17 PM PDT 24
Finished Aug 15 05:15:28 PM PDT 24
Peak memory 225344 kb
Host smart-6ec0d58e-d859-439f-bc3a-e445f324f612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576080789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1576080789
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1364665735
Short name T920
Test name
Test status
Simulation time 19376137 ps
CPU time 0.73 seconds
Started Aug 15 05:15:21 PM PDT 24
Finished Aug 15 05:15:22 PM PDT 24
Peak memory 205676 kb
Host smart-79a3fde9-1922-4e1d-956c-9a51252aaece
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364665735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1364665735
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3073032661
Short name T542
Test name
Test status
Simulation time 761966399 ps
CPU time 5.9 seconds
Started Aug 15 05:15:18 PM PDT 24
Finished Aug 15 05:15:24 PM PDT 24
Peak memory 225304 kb
Host smart-cb7bc181-8b92-4e8d-b75f-33d014bf536f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073032661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3073032661
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2415157168
Short name T357
Test name
Test status
Simulation time 38990336 ps
CPU time 0.85 seconds
Started Aug 15 05:15:18 PM PDT 24
Finished Aug 15 05:15:19 PM PDT 24
Peak memory 207412 kb
Host smart-df4b8d53-7fe3-49ec-b5f8-9bf8827f36dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415157168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2415157168
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2197752232
Short name T287
Test name
Test status
Simulation time 50166250588 ps
CPU time 159.23 seconds
Started Aug 15 05:15:23 PM PDT 24
Finished Aug 15 05:18:02 PM PDT 24
Peak memory 256952 kb
Host smart-780826a1-5d0e-432e-ae14-89fa83ee9342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197752232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2197752232
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3092935252
Short name T725
Test name
Test status
Simulation time 107640531303 ps
CPU time 253.3 seconds
Started Aug 15 05:15:17 PM PDT 24
Finished Aug 15 05:19:31 PM PDT 24
Peak memory 251192 kb
Host smart-640f363e-27ca-4f34-814d-82e2712038db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092935252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3092935252
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2614474892
Short name T284
Test name
Test status
Simulation time 21988859108 ps
CPU time 101.75 seconds
Started Aug 15 05:15:22 PM PDT 24
Finished Aug 15 05:17:04 PM PDT 24
Peak memory 274004 kb
Host smart-2c7e1e8c-8af1-4537-8082-4acdbe692fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614474892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2614474892
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4009838046
Short name T933
Test name
Test status
Simulation time 1813915586 ps
CPU time 15.11 seconds
Started Aug 15 05:15:21 PM PDT 24
Finished Aug 15 05:15:36 PM PDT 24
Peak memory 235484 kb
Host smart-08109463-fdb6-4147-8017-1a4761b73fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009838046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4009838046
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.745181428
Short name T272
Test name
Test status
Simulation time 23747526052 ps
CPU time 151.28 seconds
Started Aug 15 05:15:17 PM PDT 24
Finished Aug 15 05:17:48 PM PDT 24
Peak memory 258264 kb
Host smart-c7884120-19d2-478f-8de6-4e3465117211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745181428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.745181428
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2308032523
Short name T98
Test name
Test status
Simulation time 118713757 ps
CPU time 2.76 seconds
Started Aug 15 05:15:19 PM PDT 24
Finished Aug 15 05:15:21 PM PDT 24
Peak memory 233596 kb
Host smart-94dc5147-b15e-4198-aa84-c9914248b362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308032523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2308032523
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.4038697206
Short name T634
Test name
Test status
Simulation time 2755981094 ps
CPU time 22.87 seconds
Started Aug 15 05:15:17 PM PDT 24
Finished Aug 15 05:15:40 PM PDT 24
Peak memory 241840 kb
Host smart-fc76ce6b-e7c9-4b7a-9599-b44e1bd5dcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038697206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4038697206
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2277779734
Short name T280
Test name
Test status
Simulation time 7773841930 ps
CPU time 10.19 seconds
Started Aug 15 05:15:18 PM PDT 24
Finished Aug 15 05:15:28 PM PDT 24
Peak memory 233716 kb
Host smart-c8fb0f2d-b863-4421-a9f9-97795598f836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277779734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2277779734
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.629374200
Short name T903
Test name
Test status
Simulation time 543630364 ps
CPU time 4.18 seconds
Started Aug 15 05:15:17 PM PDT 24
Finished Aug 15 05:15:21 PM PDT 24
Peak memory 225264 kb
Host smart-743f660c-19e9-41b7-88c5-e78c04078787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629374200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.629374200
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3056380904
Short name T46
Test name
Test status
Simulation time 289814140 ps
CPU time 4.01 seconds
Started Aug 15 05:15:17 PM PDT 24
Finished Aug 15 05:15:21 PM PDT 24
Peak memory 223884 kb
Host smart-e994a550-658d-44ed-9822-ab959ee0275b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3056380904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3056380904
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2431185948
Short name T461
Test name
Test status
Simulation time 472568308 ps
CPU time 1.06 seconds
Started Aug 15 05:15:18 PM PDT 24
Finished Aug 15 05:15:19 PM PDT 24
Peak memory 207840 kb
Host smart-f6c51385-f272-4764-a5b7-1ddaec9286b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431185948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2431185948
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1063671028
Short name T612
Test name
Test status
Simulation time 14324912941 ps
CPU time 26.09 seconds
Started Aug 15 05:15:12 PM PDT 24
Finished Aug 15 05:15:38 PM PDT 24
Peak memory 217316 kb
Host smart-ff52ccd8-136a-41c0-b2aa-4fd71627b404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063671028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1063671028
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.885242463
Short name T517
Test name
Test status
Simulation time 56680598 ps
CPU time 0.71 seconds
Started Aug 15 05:15:12 PM PDT 24
Finished Aug 15 05:15:13 PM PDT 24
Peak memory 206532 kb
Host smart-ce069b69-b14e-4955-808f-83f2484dc5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885242463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.885242463
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3339956795
Short name T386
Test name
Test status
Simulation time 223923731 ps
CPU time 1.82 seconds
Started Aug 15 05:15:13 PM PDT 24
Finished Aug 15 05:15:15 PM PDT 24
Peak memory 217128 kb
Host smart-4720fead-2120-49b6-97d6-5b67f0a327bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339956795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3339956795
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1738872227
Short name T340
Test name
Test status
Simulation time 96284173 ps
CPU time 0.76 seconds
Started Aug 15 05:15:18 PM PDT 24
Finished Aug 15 05:15:19 PM PDT 24
Peak memory 206872 kb
Host smart-21070b07-ac72-433e-83f2-2972d9d8fc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738872227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1738872227
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2225580626
Short name T572
Test name
Test status
Simulation time 599644018 ps
CPU time 6.14 seconds
Started Aug 15 05:15:16 PM PDT 24
Finished Aug 15 05:15:23 PM PDT 24
Peak memory 225392 kb
Host smart-08d35973-3288-410f-928a-8a9b672c8d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225580626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2225580626
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3101231689
Short name T679
Test name
Test status
Simulation time 43420987 ps
CPU time 0.71 seconds
Started Aug 15 05:15:23 PM PDT 24
Finished Aug 15 05:15:24 PM PDT 24
Peak memory 206240 kb
Host smart-4c148036-cf6d-4d92-b107-60093be5f511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101231689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3101231689
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2703172063
Short name T436
Test name
Test status
Simulation time 274666058 ps
CPU time 2.36 seconds
Started Aug 15 05:15:17 PM PDT 24
Finished Aug 15 05:15:20 PM PDT 24
Peak memory 225392 kb
Host smart-98a6fde8-5664-4fe7-bd52-b24ef8c971de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703172063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2703172063
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2096551995
Short name T356
Test name
Test status
Simulation time 37906561 ps
CPU time 0.89 seconds
Started Aug 15 05:15:18 PM PDT 24
Finished Aug 15 05:15:19 PM PDT 24
Peak memory 207364 kb
Host smart-682c511b-7684-4c66-81fe-3666b0ff780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096551995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2096551995
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1002699677
Short name T579
Test name
Test status
Simulation time 26485140935 ps
CPU time 132.51 seconds
Started Aug 15 05:15:19 PM PDT 24
Finished Aug 15 05:17:31 PM PDT 24
Peak memory 259632 kb
Host smart-119f2cf6-e45c-46ec-a059-82656cd0e13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002699677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1002699677
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.547578592
Short name T95
Test name
Test status
Simulation time 35314620865 ps
CPU time 94.78 seconds
Started Aug 15 05:15:18 PM PDT 24
Finished Aug 15 05:16:53 PM PDT 24
Peak memory 250228 kb
Host smart-3b0d1746-7a01-4994-a9df-fc5b3acf2930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547578592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.547578592
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2918549120
Short name T307
Test name
Test status
Simulation time 8303911392 ps
CPU time 28.55 seconds
Started Aug 15 05:15:20 PM PDT 24
Finished Aug 15 05:15:49 PM PDT 24
Peak memory 225616 kb
Host smart-05443fb9-3328-4080-87dc-679d9b6ce15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918549120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2918549120
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.977932328
Short name T717
Test name
Test status
Simulation time 642248185 ps
CPU time 15.18 seconds
Started Aug 15 05:15:24 PM PDT 24
Finished Aug 15 05:15:39 PM PDT 24
Peak memory 233584 kb
Host smart-7f640950-bfe6-474b-b21b-1f150c98c32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977932328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.977932328
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3134089565
Short name T902
Test name
Test status
Simulation time 1966352798 ps
CPU time 23.04 seconds
Started Aug 15 05:15:21 PM PDT 24
Finished Aug 15 05:15:45 PM PDT 24
Peak memory 233580 kb
Host smart-2842a629-33c8-4c64-8b20-efc12a3b5fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134089565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3134089565
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3960750378
Short name T667
Test name
Test status
Simulation time 1170226131 ps
CPU time 8.41 seconds
Started Aug 15 05:15:18 PM PDT 24
Finished Aug 15 05:15:26 PM PDT 24
Peak memory 225412 kb
Host smart-fb933af3-aac0-4f14-9c25-b81146f4aa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960750378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3960750378
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3552917716
Short name T657
Test name
Test status
Simulation time 34165538 ps
CPU time 2.16 seconds
Started Aug 15 05:15:18 PM PDT 24
Finished Aug 15 05:15:21 PM PDT 24
Peak memory 233188 kb
Host smart-e9b90fef-6d09-44c3-b5ad-d6c757e0140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552917716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3552917716
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3788747944
Short name T255
Test name
Test status
Simulation time 8524269322 ps
CPU time 16.78 seconds
Started Aug 15 05:15:18 PM PDT 24
Finished Aug 15 05:15:35 PM PDT 24
Peak memory 233680 kb
Host smart-429b7598-29fa-4152-94c1-acb184bd83b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788747944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3788747944
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1024138853
Short name T456
Test name
Test status
Simulation time 4364794640 ps
CPU time 13.43 seconds
Started Aug 15 05:15:23 PM PDT 24
Finished Aug 15 05:15:36 PM PDT 24
Peak memory 235716 kb
Host smart-fe167e97-643a-458e-bded-d3a396f033fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024138853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1024138853
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1124875656
Short name T353
Test name
Test status
Simulation time 386203704 ps
CPU time 4.89 seconds
Started Aug 15 05:15:20 PM PDT 24
Finished Aug 15 05:15:25 PM PDT 24
Peak memory 220300 kb
Host smart-318d36ef-399e-41f0-b496-31f7db2f2c85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1124875656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1124875656
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2349919390
Short name T398
Test name
Test status
Simulation time 51835469 ps
CPU time 0.99 seconds
Started Aug 15 05:15:17 PM PDT 24
Finished Aug 15 05:15:18 PM PDT 24
Peak memory 207588 kb
Host smart-2537ceff-c30e-41d6-bb49-5f463c7793fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349919390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2349919390
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4155108269
Short name T597
Test name
Test status
Simulation time 5111814791 ps
CPU time 31.63 seconds
Started Aug 15 05:15:23 PM PDT 24
Finished Aug 15 05:15:54 PM PDT 24
Peak memory 217248 kb
Host smart-32cf944e-dff2-4a70-833d-fc850cc9d920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155108269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4155108269
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.945493285
Short name T344
Test name
Test status
Simulation time 6235104511 ps
CPU time 6.45 seconds
Started Aug 15 05:15:18 PM PDT 24
Finished Aug 15 05:15:24 PM PDT 24
Peak memory 217240 kb
Host smart-f431efc1-709a-477d-a8a2-982743d3cb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945493285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.945493285
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.471685986
Short name T382
Test name
Test status
Simulation time 183211495 ps
CPU time 2.51 seconds
Started Aug 15 05:15:17 PM PDT 24
Finished Aug 15 05:15:20 PM PDT 24
Peak memory 217180 kb
Host smart-8b081ac6-bde5-41d3-8350-ec5c2e7e6a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471685986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.471685986
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.758895348
Short name T466
Test name
Test status
Simulation time 123047314 ps
CPU time 0.82 seconds
Started Aug 15 05:15:17 PM PDT 24
Finished Aug 15 05:15:18 PM PDT 24
Peak memory 206684 kb
Host smart-c3aa28dd-22ad-4c5a-a90f-46a44304216f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758895348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.758895348
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2081203216
Short name T176
Test name
Test status
Simulation time 2771016913 ps
CPU time 5.28 seconds
Started Aug 15 05:15:20 PM PDT 24
Finished Aug 15 05:15:26 PM PDT 24
Peak memory 225432 kb
Host smart-3dee2166-7382-4ac4-9886-45f66f683f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081203216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2081203216
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1904694046
Short name T68
Test name
Test status
Simulation time 31036243 ps
CPU time 0.72 seconds
Started Aug 15 05:13:29 PM PDT 24
Finished Aug 15 05:13:31 PM PDT 24
Peak memory 206200 kb
Host smart-cadd28e3-c366-42bc-9c6f-3a12c89ff7cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904694046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
904694046
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2450231950
Short name T849
Test name
Test status
Simulation time 1838820746 ps
CPU time 10.18 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:13:28 PM PDT 24
Peak memory 233576 kb
Host smart-aa5b14c2-14c1-4c5d-9a98-ef456288b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450231950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2450231950
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1044041996
Short name T407
Test name
Test status
Simulation time 49094758 ps
CPU time 0.73 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:13:19 PM PDT 24
Peak memory 206724 kb
Host smart-441d441d-6c78-4b8c-b6f0-12633e50d25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044041996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1044041996
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2567927402
Short name T270
Test name
Test status
Simulation time 20651464928 ps
CPU time 167.7 seconds
Started Aug 15 05:13:27 PM PDT 24
Finished Aug 15 05:16:15 PM PDT 24
Peak memory 256880 kb
Host smart-430071d5-a15d-4a84-adef-d042ce9dc92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567927402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2567927402
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.578536491
Short name T228
Test name
Test status
Simulation time 7357475650 ps
CPU time 27.4 seconds
Started Aug 15 05:13:26 PM PDT 24
Finished Aug 15 05:13:53 PM PDT 24
Peak memory 250004 kb
Host smart-19ed0179-64a5-4cfd-ba68-7c7c172640c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578536491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.578536491
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.537594368
Short name T709
Test name
Test status
Simulation time 106282123261 ps
CPU time 211.07 seconds
Started Aug 15 05:13:29 PM PDT 24
Finished Aug 15 05:17:01 PM PDT 24
Peak memory 242004 kb
Host smart-fbe7e08d-716a-4f1e-b300-b52f81172538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537594368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
537594368
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2375629882
Short name T324
Test name
Test status
Simulation time 3062877258 ps
CPU time 13.64 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:13:32 PM PDT 24
Peak memory 237236 kb
Host smart-f1dd08d6-db8d-4119-bc6c-6ca7c9437e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375629882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2375629882
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2275836335
Short name T203
Test name
Test status
Simulation time 104110873252 ps
CPU time 304.46 seconds
Started Aug 15 05:13:20 PM PDT 24
Finished Aug 15 05:18:24 PM PDT 24
Peak memory 254008 kb
Host smart-f55ba984-5fb6-41e3-bb47-400803579336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275836335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2275836335
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2759047139
Short name T488
Test name
Test status
Simulation time 531091149 ps
CPU time 4.21 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:13:22 PM PDT 24
Peak memory 219640 kb
Host smart-1c906c7f-ef3a-4f8c-aea2-22fe5d42d59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759047139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2759047139
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2970855801
Short name T500
Test name
Test status
Simulation time 6910309894 ps
CPU time 34.4 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:13:52 PM PDT 24
Peak memory 225420 kb
Host smart-c950f410-c55b-461f-a1b4-75a6814a7a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970855801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2970855801
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2989244641
Short name T355
Test name
Test status
Simulation time 345976084 ps
CPU time 3.03 seconds
Started Aug 15 05:13:26 PM PDT 24
Finished Aug 15 05:13:29 PM PDT 24
Peak memory 233496 kb
Host smart-e3a1b26f-4c4a-4236-a356-feff161a8396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989244641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2989244641
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1931331201
Short name T611
Test name
Test status
Simulation time 14124211821 ps
CPU time 8.45 seconds
Started Aug 15 05:13:24 PM PDT 24
Finished Aug 15 05:13:33 PM PDT 24
Peak memory 233612 kb
Host smart-c7042f56-89fb-4fb4-8553-398add628a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931331201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1931331201
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1592776060
Short name T47
Test name
Test status
Simulation time 142635649 ps
CPU time 3.92 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:13:22 PM PDT 24
Peak memory 223968 kb
Host smart-c4f4839d-4b06-444b-bdf9-4523bec3cc3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1592776060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1592776060
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3858476986
Short name T77
Test name
Test status
Simulation time 38368548 ps
CPU time 1.02 seconds
Started Aug 15 05:13:30 PM PDT 24
Finished Aug 15 05:13:31 PM PDT 24
Peak memory 237060 kb
Host smart-af8ad652-66de-4d33-928c-debd98a2460b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858476986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3858476986
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1119594987
Short name T623
Test name
Test status
Simulation time 42785938 ps
CPU time 0.97 seconds
Started Aug 15 05:13:27 PM PDT 24
Finished Aug 15 05:13:28 PM PDT 24
Peak memory 207516 kb
Host smart-9f26b3b1-14f2-4cc8-abe8-e882644fe837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119594987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1119594987
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1456016463
Short name T499
Test name
Test status
Simulation time 2312214277 ps
CPU time 16.01 seconds
Started Aug 15 05:13:25 PM PDT 24
Finished Aug 15 05:13:41 PM PDT 24
Peak memory 217536 kb
Host smart-6c75d10e-91d1-4794-9a28-1ca18d9ca3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456016463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1456016463
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2897285359
Short name T337
Test name
Test status
Simulation time 21431702 ps
CPU time 0.7 seconds
Started Aug 15 05:13:20 PM PDT 24
Finished Aug 15 05:13:21 PM PDT 24
Peak memory 206472 kb
Host smart-3e4fa722-5275-4e51-8bed-596a6fde959c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897285359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2897285359
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3651600524
Short name T782
Test name
Test status
Simulation time 43283941 ps
CPU time 0.83 seconds
Started Aug 15 05:13:26 PM PDT 24
Finished Aug 15 05:13:27 PM PDT 24
Peak memory 206760 kb
Host smart-ad21b6e3-3f46-437b-89cd-ed1665ab70c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651600524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3651600524
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3348999622
Short name T696
Test name
Test status
Simulation time 69318560 ps
CPU time 0.78 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:13:19 PM PDT 24
Peak memory 206832 kb
Host smart-431e6d9e-cfc7-480b-bbdf-8c7bf17294c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348999622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3348999622
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.505987485
Short name T217
Test name
Test status
Simulation time 3106122109 ps
CPU time 14.17 seconds
Started Aug 15 05:13:18 PM PDT 24
Finished Aug 15 05:13:32 PM PDT 24
Peak memory 241796 kb
Host smart-6c8a3312-9933-431f-866d-ee4cdb9525b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505987485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.505987485
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3846713194
Short name T319
Test name
Test status
Simulation time 12145605 ps
CPU time 0.75 seconds
Started Aug 15 05:15:29 PM PDT 24
Finished Aug 15 05:15:30 PM PDT 24
Peak memory 205576 kb
Host smart-aba85dfa-73ba-4d5f-9582-4805ece444a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846713194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3846713194
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3425364974
Short name T867
Test name
Test status
Simulation time 53681247 ps
CPU time 2.59 seconds
Started Aug 15 05:15:31 PM PDT 24
Finished Aug 15 05:15:33 PM PDT 24
Peak memory 233496 kb
Host smart-48414ac1-961f-4423-a5bb-d44dae299ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425364974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3425364974
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2724331378
Short name T708
Test name
Test status
Simulation time 106743073 ps
CPU time 0.79 seconds
Started Aug 15 05:15:18 PM PDT 24
Finished Aug 15 05:15:19 PM PDT 24
Peak memory 207344 kb
Host smart-7b82858d-0e7f-4003-98fe-b13746d96eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724331378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2724331378
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.817087827
Short name T384
Test name
Test status
Simulation time 6338438895 ps
CPU time 36.88 seconds
Started Aug 15 05:15:28 PM PDT 24
Finished Aug 15 05:16:05 PM PDT 24
Peak memory 250116 kb
Host smart-225d934c-f3ab-4e9a-adf7-a683b214ee74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817087827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.817087827
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2752119396
Short name T930
Test name
Test status
Simulation time 6030938347 ps
CPU time 122.82 seconds
Started Aug 15 05:15:30 PM PDT 24
Finished Aug 15 05:17:33 PM PDT 24
Peak memory 267360 kb
Host smart-32f4267d-4f01-4381-b2ef-ce674aa60113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752119396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2752119396
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.148044149
Short name T607
Test name
Test status
Simulation time 4688395651 ps
CPU time 79.36 seconds
Started Aug 15 05:15:28 PM PDT 24
Finished Aug 15 05:16:48 PM PDT 24
Peak memory 252280 kb
Host smart-d11b8fa8-43ed-463b-a9ef-6ae12b39c662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148044149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.148044149
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4243356525
Short name T677
Test name
Test status
Simulation time 4297407429 ps
CPU time 31.03 seconds
Started Aug 15 05:15:28 PM PDT 24
Finished Aug 15 05:15:59 PM PDT 24
Peak memory 236460 kb
Host smart-8e09c5e4-0849-4433-a230-c3bc3fa4c7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243356525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4243356525
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2393367090
Short name T194
Test name
Test status
Simulation time 11702188082 ps
CPU time 120.89 seconds
Started Aug 15 05:15:27 PM PDT 24
Finished Aug 15 05:17:28 PM PDT 24
Peak memory 258208 kb
Host smart-98caf26d-172e-4e6b-a43b-bb03cd55d520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393367090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2393367090
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2747492071
Short name T226
Test name
Test status
Simulation time 1102351636 ps
CPU time 5.76 seconds
Started Aug 15 05:15:33 PM PDT 24
Finished Aug 15 05:15:39 PM PDT 24
Peak memory 225268 kb
Host smart-ee0f9593-8463-43a1-ab60-4e210d19fbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747492071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2747492071
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2022293288
Short name T924
Test name
Test status
Simulation time 2016321718 ps
CPU time 11.9 seconds
Started Aug 15 05:15:28 PM PDT 24
Finished Aug 15 05:15:40 PM PDT 24
Peak memory 233472 kb
Host smart-f0837a69-0cc8-409d-be12-cb43a353c9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022293288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2022293288
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2835267549
Short name T964
Test name
Test status
Simulation time 1046608063 ps
CPU time 8.25 seconds
Started Aug 15 05:15:30 PM PDT 24
Finished Aug 15 05:15:39 PM PDT 24
Peak memory 233556 kb
Host smart-b8343ee2-d553-45e2-a8db-f604d284545b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835267549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2835267549
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1214211904
Short name T757
Test name
Test status
Simulation time 271660935 ps
CPU time 3.19 seconds
Started Aug 15 05:15:30 PM PDT 24
Finished Aug 15 05:15:33 PM PDT 24
Peak memory 225200 kb
Host smart-87bbac3a-0ee2-475d-baf4-f24750cb142b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214211904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1214211904
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1024110785
Short name T999
Test name
Test status
Simulation time 18152077536 ps
CPU time 11.46 seconds
Started Aug 15 05:15:30 PM PDT 24
Finished Aug 15 05:15:41 PM PDT 24
Peak memory 219996 kb
Host smart-c339b88c-2de3-47cc-b0d0-9364ee55ab38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1024110785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1024110785
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2817022651
Short name T211
Test name
Test status
Simulation time 59753302961 ps
CPU time 429.12 seconds
Started Aug 15 05:15:31 PM PDT 24
Finished Aug 15 05:22:40 PM PDT 24
Peak memory 258356 kb
Host smart-c7b2997e-5c4c-40f0-90fe-77523e9697b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817022651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2817022651
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.157047832
Short name T303
Test name
Test status
Simulation time 3478151245 ps
CPU time 25.82 seconds
Started Aug 15 05:15:17 PM PDT 24
Finished Aug 15 05:15:43 PM PDT 24
Peak memory 217576 kb
Host smart-53874c2b-f774-43b8-b6f6-796a254f9682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157047832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.157047832
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1235321042
Short name T402
Test name
Test status
Simulation time 7647169019 ps
CPU time 13.27 seconds
Started Aug 15 05:15:23 PM PDT 24
Finished Aug 15 05:15:36 PM PDT 24
Peak memory 217228 kb
Host smart-bc2bc0d5-6231-48f0-bc3d-71522192c09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235321042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1235321042
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4144014576
Short name T408
Test name
Test status
Simulation time 58722528 ps
CPU time 0.88 seconds
Started Aug 15 05:15:29 PM PDT 24
Finished Aug 15 05:15:30 PM PDT 24
Peak memory 207844 kb
Host smart-558c344d-8799-4e53-bc0a-8162788134d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144014576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4144014576
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3787384135
Short name T504
Test name
Test status
Simulation time 36914131 ps
CPU time 0.91 seconds
Started Aug 15 05:15:27 PM PDT 24
Finished Aug 15 05:15:28 PM PDT 24
Peak memory 207796 kb
Host smart-28e6f517-13b6-4fec-923d-fd85fa9c988f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787384135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3787384135
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1738915473
Short name T345
Test name
Test status
Simulation time 2548150872 ps
CPU time 9.95 seconds
Started Aug 15 05:15:29 PM PDT 24
Finished Aug 15 05:15:39 PM PDT 24
Peak memory 233568 kb
Host smart-486067ce-ef87-4611-8e57-c921316548d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738915473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1738915473
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3760923446
Short name T522
Test name
Test status
Simulation time 17439644 ps
CPU time 0.74 seconds
Started Aug 15 05:15:38 PM PDT 24
Finished Aug 15 05:15:39 PM PDT 24
Peak memory 206224 kb
Host smart-6ca5e34a-e005-4915-ae16-a59d8858843c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760923446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3760923446
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2028215769
Short name T39
Test name
Test status
Simulation time 2217670136 ps
CPU time 9.61 seconds
Started Aug 15 05:15:30 PM PDT 24
Finished Aug 15 05:15:40 PM PDT 24
Peak memory 233712 kb
Host smart-a65e23e9-0ed6-495c-ad04-aedd41f16210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028215769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2028215769
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1541530655
Short name T534
Test name
Test status
Simulation time 65000895 ps
CPU time 0.81 seconds
Started Aug 15 05:15:34 PM PDT 24
Finished Aug 15 05:15:35 PM PDT 24
Peak memory 207416 kb
Host smart-de610a0d-235a-4667-960c-159cc9287baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541530655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1541530655
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2139163517
Short name T960
Test name
Test status
Simulation time 30500104813 ps
CPU time 212.46 seconds
Started Aug 15 05:15:38 PM PDT 24
Finished Aug 15 05:19:11 PM PDT 24
Peak memory 250148 kb
Host smart-765683a8-aa03-4320-91d2-ee6e8db5ac42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139163517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2139163517
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3993620367
Short name T40
Test name
Test status
Simulation time 16676726745 ps
CPU time 64.08 seconds
Started Aug 15 05:15:36 PM PDT 24
Finished Aug 15 05:16:40 PM PDT 24
Peak memory 250164 kb
Host smart-f04f076e-4727-423c-93fd-bd555266d7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993620367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3993620367
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3668936473
Short name T318
Test name
Test status
Simulation time 289445254 ps
CPU time 2.82 seconds
Started Aug 15 05:15:36 PM PDT 24
Finished Aug 15 05:15:39 PM PDT 24
Peak memory 233512 kb
Host smart-eb6244d6-66e3-4797-bd6c-1fc26c0b91ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668936473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3668936473
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3647220216
Short name T608
Test name
Test status
Simulation time 714771063 ps
CPU time 14.59 seconds
Started Aug 15 05:15:35 PM PDT 24
Finished Aug 15 05:15:49 PM PDT 24
Peak memory 249872 kb
Host smart-5e7797dd-1657-499a-bc84-02026eaecbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647220216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3647220216
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.419983246
Short name T660
Test name
Test status
Simulation time 301774055 ps
CPU time 5.67 seconds
Started Aug 15 05:15:28 PM PDT 24
Finished Aug 15 05:15:34 PM PDT 24
Peak memory 220580 kb
Host smart-981ae344-34b5-47d9-a8c7-a7c87c4451e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419983246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.419983246
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3725329815
Short name T11
Test name
Test status
Simulation time 1973486931 ps
CPU time 24.67 seconds
Started Aug 15 05:15:29 PM PDT 24
Finished Aug 15 05:15:54 PM PDT 24
Peak memory 249796 kb
Host smart-ee130847-2ddf-4cb8-975e-53a837e51f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725329815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3725329815
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3848669710
Short name T4
Test name
Test status
Simulation time 2467778346 ps
CPU time 12.17 seconds
Started Aug 15 05:15:29 PM PDT 24
Finished Aug 15 05:15:42 PM PDT 24
Peak memory 241864 kb
Host smart-f11ef124-b912-4ead-8b82-ee6a3df44bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848669710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3848669710
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1139534641
Short name T766
Test name
Test status
Simulation time 15608868868 ps
CPU time 7.67 seconds
Started Aug 15 05:15:27 PM PDT 24
Finished Aug 15 05:15:35 PM PDT 24
Peak memory 225388 kb
Host smart-473907d1-7d3e-4d74-bfea-f0b0b78b182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139534641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1139534641
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2869553349
Short name T545
Test name
Test status
Simulation time 69095620 ps
CPU time 3.7 seconds
Started Aug 15 05:15:53 PM PDT 24
Finished Aug 15 05:15:56 PM PDT 24
Peak memory 223872 kb
Host smart-5281fd34-dd87-4892-b7d5-b69af1ff1468
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2869553349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2869553349
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1764264868
Short name T151
Test name
Test status
Simulation time 130892172515 ps
CPU time 393.35 seconds
Started Aug 15 05:15:39 PM PDT 24
Finished Aug 15 05:22:12 PM PDT 24
Peak memory 265596 kb
Host smart-8a931785-b7ae-4b61-accf-fc88aaec4e5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764264868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1764264868
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2300736518
Short name T145
Test name
Test status
Simulation time 8699179212 ps
CPU time 30.08 seconds
Started Aug 15 05:15:28 PM PDT 24
Finished Aug 15 05:15:59 PM PDT 24
Peak memory 217308 kb
Host smart-232b59ab-98a3-4e40-989d-9cbbd40abaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300736518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2300736518
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.815641548
Short name T741
Test name
Test status
Simulation time 4103344579 ps
CPU time 16.49 seconds
Started Aug 15 05:15:27 PM PDT 24
Finished Aug 15 05:15:44 PM PDT 24
Peak memory 217320 kb
Host smart-f36a8378-9eef-432d-851e-c5a03c351b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815641548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.815641548
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2967719418
Short name T577
Test name
Test status
Simulation time 42113233 ps
CPU time 1.77 seconds
Started Aug 15 05:15:27 PM PDT 24
Finished Aug 15 05:15:29 PM PDT 24
Peak memory 217092 kb
Host smart-b2157dd3-5b2e-4e28-b59e-397ebd905a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967719418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2967719418
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3067056244
Short name T496
Test name
Test status
Simulation time 323573920 ps
CPU time 0.98 seconds
Started Aug 15 05:15:28 PM PDT 24
Finished Aug 15 05:15:30 PM PDT 24
Peak memory 207900 kb
Host smart-54f62bc2-7205-4b29-bfc1-f53c7e757dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067056244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3067056244
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.826765094
Short name T784
Test name
Test status
Simulation time 12443522100 ps
CPU time 12.11 seconds
Started Aug 15 05:15:29 PM PDT 24
Finished Aug 15 05:15:41 PM PDT 24
Peak memory 233608 kb
Host smart-0df27959-3950-45ea-ade9-d094533246b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826765094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.826765094
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1104672362
Short name T592
Test name
Test status
Simulation time 44059655 ps
CPU time 0.7 seconds
Started Aug 15 05:15:36 PM PDT 24
Finished Aug 15 05:15:36 PM PDT 24
Peak memory 205712 kb
Host smart-b3739493-8c70-4a2d-a4b1-b57b995c8028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104672362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1104672362
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.4049362765
Short name T478
Test name
Test status
Simulation time 40501252350 ps
CPU time 27.2 seconds
Started Aug 15 05:15:38 PM PDT 24
Finished Aug 15 05:16:06 PM PDT 24
Peak memory 233692 kb
Host smart-65786d87-047e-4fba-8b2e-8dae2ee35b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049362765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.4049362765
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.15693224
Short name T806
Test name
Test status
Simulation time 64752768 ps
CPU time 0.75 seconds
Started Aug 15 05:15:39 PM PDT 24
Finished Aug 15 05:15:40 PM PDT 24
Peak memory 207360 kb
Host smart-d6793880-c1c9-44d1-9db2-f49926843853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15693224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.15693224
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1442485193
Short name T590
Test name
Test status
Simulation time 67363697265 ps
CPU time 142.79 seconds
Started Aug 15 05:15:40 PM PDT 24
Finished Aug 15 05:18:03 PM PDT 24
Peak memory 254700 kb
Host smart-e4c85655-d2cd-4421-84d4-01ed183f9457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442485193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1442485193
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.488665517
Short name T31
Test name
Test status
Simulation time 61648251409 ps
CPU time 334 seconds
Started Aug 15 05:15:38 PM PDT 24
Finished Aug 15 05:21:12 PM PDT 24
Peak memory 256304 kb
Host smart-d9310450-864d-4d30-a4d2-66a50742975b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488665517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.488665517
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2267846948
Short name T588
Test name
Test status
Simulation time 18163471847 ps
CPU time 52.6 seconds
Started Aug 15 05:15:38 PM PDT 24
Finished Aug 15 05:16:31 PM PDT 24
Peak memory 266612 kb
Host smart-6789a175-7673-4dde-bb17-14c53798a426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267846948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2267846948
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3480697993
Short name T798
Test name
Test status
Simulation time 42826439804 ps
CPU time 133.83 seconds
Started Aug 15 05:15:36 PM PDT 24
Finished Aug 15 05:17:49 PM PDT 24
Peak memory 258280 kb
Host smart-ca8605ea-67a5-475c-96bb-f5897a1aa1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480697993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3480697993
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1516122841
Short name T457
Test name
Test status
Simulation time 12438753165 ps
CPU time 19.91 seconds
Started Aug 15 05:15:38 PM PDT 24
Finished Aug 15 05:15:58 PM PDT 24
Peak memory 233664 kb
Host smart-576f8f1e-4062-4631-a751-5943187d0124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516122841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1516122841
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.834269366
Short name T746
Test name
Test status
Simulation time 134780221 ps
CPU time 2.65 seconds
Started Aug 15 05:15:36 PM PDT 24
Finished Aug 15 05:15:39 PM PDT 24
Peak memory 233536 kb
Host smart-76864978-63ef-420c-b175-0399c25b9a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834269366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.834269366
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2945320939
Short name T254
Test name
Test status
Simulation time 4952736049 ps
CPU time 16.3 seconds
Started Aug 15 05:15:38 PM PDT 24
Finished Aug 15 05:15:55 PM PDT 24
Peak memory 225400 kb
Host smart-5cfe32e9-0296-42f3-ab8f-926dba7ad843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945320939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2945320939
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2410086584
Short name T738
Test name
Test status
Simulation time 16153885179 ps
CPU time 27.38 seconds
Started Aug 15 05:15:38 PM PDT 24
Finished Aug 15 05:16:06 PM PDT 24
Peak memory 225480 kb
Host smart-53d4a947-4a58-4136-b723-5ca5cab7a0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410086584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2410086584
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.50992646
Short name T512
Test name
Test status
Simulation time 1284368185 ps
CPU time 14.56 seconds
Started Aug 15 05:15:36 PM PDT 24
Finished Aug 15 05:15:50 PM PDT 24
Peak memory 220316 kb
Host smart-c55d55ac-f71d-4fa7-81b0-4313ed71474d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=50992646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direc
t.50992646
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4284550560
Short name T202
Test name
Test status
Simulation time 175435723073 ps
CPU time 336.05 seconds
Started Aug 15 05:15:37 PM PDT 24
Finished Aug 15 05:21:13 PM PDT 24
Peak memory 264516 kb
Host smart-05af56ea-08a3-4c3f-98ee-52e07b5c9a0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284550560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4284550560
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.316878578
Short name T808
Test name
Test status
Simulation time 3373069936 ps
CPU time 17.03 seconds
Started Aug 15 05:15:35 PM PDT 24
Finished Aug 15 05:15:52 PM PDT 24
Peak memory 217216 kb
Host smart-cd560654-8fc5-4fa8-be62-42d3ad075ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316878578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.316878578
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1048476974
Short name T406
Test name
Test status
Simulation time 10014268404 ps
CPU time 5.23 seconds
Started Aug 15 05:15:37 PM PDT 24
Finished Aug 15 05:15:43 PM PDT 24
Peak memory 218684 kb
Host smart-a7225189-2cf7-4ae3-b086-fb5d4e326096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048476974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1048476974
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1775129293
Short name T810
Test name
Test status
Simulation time 80404410 ps
CPU time 1.25 seconds
Started Aug 15 05:15:36 PM PDT 24
Finished Aug 15 05:15:37 PM PDT 24
Peak memory 216980 kb
Host smart-c731ce92-87fd-406a-a221-4bac03a59fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775129293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1775129293
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.4169240148
Short name T673
Test name
Test status
Simulation time 82714739 ps
CPU time 0.84 seconds
Started Aug 15 05:15:38 PM PDT 24
Finished Aug 15 05:15:39 PM PDT 24
Peak memory 206840 kb
Host smart-5723a42b-ce28-4da3-88e3-b31a6cd7b24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169240148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.4169240148
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1465897362
Short name T349
Test name
Test status
Simulation time 9185220286 ps
CPU time 11.65 seconds
Started Aug 15 05:15:35 PM PDT 24
Finished Aug 15 05:15:47 PM PDT 24
Peak memory 233612 kb
Host smart-e086a367-4fc4-47d6-b640-ca9268983e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465897362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1465897362
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4244547705
Short name T329
Test name
Test status
Simulation time 14708924 ps
CPU time 0.74 seconds
Started Aug 15 05:15:44 PM PDT 24
Finished Aug 15 05:15:45 PM PDT 24
Peak memory 206584 kb
Host smart-1947713f-0e07-4e83-a145-9916192199ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244547705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4244547705
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1406963089
Short name T753
Test name
Test status
Simulation time 2746993378 ps
CPU time 27.21 seconds
Started Aug 15 05:15:48 PM PDT 24
Finished Aug 15 05:16:15 PM PDT 24
Peak memory 225452 kb
Host smart-f75572c2-7106-47bf-82e1-4d57ecbb62b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406963089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1406963089
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2219537650
Short name T342
Test name
Test status
Simulation time 57005051 ps
CPU time 0.79 seconds
Started Aug 15 05:15:35 PM PDT 24
Finished Aug 15 05:15:36 PM PDT 24
Peak memory 206324 kb
Host smart-69698d2a-9897-4816-a8d1-b34ed7d3a511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219537650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2219537650
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.622421748
Short name T293
Test name
Test status
Simulation time 7057226563 ps
CPU time 56.08 seconds
Started Aug 15 05:15:46 PM PDT 24
Finished Aug 15 05:16:43 PM PDT 24
Peak memory 249988 kb
Host smart-408bc81b-82f0-4acb-9d91-f5061a5d5779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622421748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.622421748
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.82663940
Short name T253
Test name
Test status
Simulation time 3510314204 ps
CPU time 82.26 seconds
Started Aug 15 05:15:44 PM PDT 24
Finished Aug 15 05:17:07 PM PDT 24
Peak memory 257248 kb
Host smart-2dad6f43-5e7f-446e-8b07-f2e467657366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82663940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.82663940
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2842254442
Short name T587
Test name
Test status
Simulation time 4284131804 ps
CPU time 12.81 seconds
Started Aug 15 05:15:43 PM PDT 24
Finished Aug 15 05:15:56 PM PDT 24
Peak memory 224528 kb
Host smart-926890eb-2523-45c3-bfeb-0b7c2ffb7004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842254442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2842254442
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2108409791
Short name T833
Test name
Test status
Simulation time 4991758019 ps
CPU time 16.9 seconds
Started Aug 15 05:15:42 PM PDT 24
Finished Aug 15 05:15:59 PM PDT 24
Peak memory 233772 kb
Host smart-b252a2b7-db5a-48fa-bf82-8dbf3f16f628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108409791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2108409791
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3411071725
Short name T193
Test name
Test status
Simulation time 46779364810 ps
CPU time 180.55 seconds
Started Aug 15 05:15:44 PM PDT 24
Finished Aug 15 05:18:45 PM PDT 24
Peak memory 258248 kb
Host smart-9498094a-4fee-4ca9-b370-9fecf29cf253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411071725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3411071725
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3625365211
Short name T210
Test name
Test status
Simulation time 2600060578 ps
CPU time 12.71 seconds
Started Aug 15 05:15:45 PM PDT 24
Finished Aug 15 05:15:58 PM PDT 24
Peak memory 233700 kb
Host smart-a3f82c6c-7136-473a-8807-07a88fb7e4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625365211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3625365211
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.362166345
Short name T388
Test name
Test status
Simulation time 71884975464 ps
CPU time 168.16 seconds
Started Aug 15 05:15:44 PM PDT 24
Finished Aug 15 05:18:32 PM PDT 24
Peak memory 250972 kb
Host smart-1d5f3b15-122b-4b07-87f2-0f5fd4cc5607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362166345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.362166345
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1598254372
Short name T53
Test name
Test status
Simulation time 1528014975 ps
CPU time 5.77 seconds
Started Aug 15 05:15:44 PM PDT 24
Finished Aug 15 05:15:50 PM PDT 24
Peak memory 225328 kb
Host smart-7bf03777-c69f-4af3-83b4-a8cdc28880f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598254372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1598254372
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3641131471
Short name T559
Test name
Test status
Simulation time 2296634551 ps
CPU time 9.04 seconds
Started Aug 15 05:15:44 PM PDT 24
Finished Aug 15 05:15:53 PM PDT 24
Peak memory 225444 kb
Host smart-9f086e1f-85fd-4fc6-84b0-6e9121c6592f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641131471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3641131471
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3834380994
Short name T451
Test name
Test status
Simulation time 792913522 ps
CPU time 6.78 seconds
Started Aug 15 05:15:44 PM PDT 24
Finished Aug 15 05:15:51 PM PDT 24
Peak memory 219700 kb
Host smart-16a2813f-2d10-46ef-8cd2-553d736583d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3834380994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3834380994
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2009897568
Short name T20
Test name
Test status
Simulation time 49535703828 ps
CPU time 121.24 seconds
Started Aug 15 05:15:43 PM PDT 24
Finished Aug 15 05:17:45 PM PDT 24
Peak memory 250164 kb
Host smart-2c90fc75-a737-4234-8514-57f81238c81c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009897568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2009897568
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.402160145
Short name T584
Test name
Test status
Simulation time 1474392850 ps
CPU time 13.62 seconds
Started Aug 15 05:15:35 PM PDT 24
Finished Aug 15 05:15:49 PM PDT 24
Peak memory 217340 kb
Host smart-8352c354-1261-4b4f-9843-149213c82885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402160145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.402160145
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3271899917
Short name T366
Test name
Test status
Simulation time 1253328759 ps
CPU time 1.76 seconds
Started Aug 15 05:15:35 PM PDT 24
Finished Aug 15 05:15:37 PM PDT 24
Peak memory 208732 kb
Host smart-10703b4b-8070-42c4-aa2f-06b26eeaae5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271899917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3271899917
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2509811119
Short name T148
Test name
Test status
Simulation time 70440943 ps
CPU time 1.29 seconds
Started Aug 15 05:15:43 PM PDT 24
Finished Aug 15 05:15:45 PM PDT 24
Peak memory 217196 kb
Host smart-14e55ae7-b083-41c8-8f44-d602273ad955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509811119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2509811119
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1054406927
Short name T851
Test name
Test status
Simulation time 233542357 ps
CPU time 0.89 seconds
Started Aug 15 05:15:43 PM PDT 24
Finished Aug 15 05:15:44 PM PDT 24
Peak memory 206856 kb
Host smart-e275d071-0c7c-46c2-8a43-40f3bdc3b155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054406927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1054406927
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2560474590
Short name T435
Test name
Test status
Simulation time 558141954 ps
CPU time 5.14 seconds
Started Aug 15 05:15:42 PM PDT 24
Finished Aug 15 05:15:47 PM PDT 24
Peak memory 236048 kb
Host smart-f6ac7d42-7fa1-4d83-8e9e-46084d01b291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560474590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2560474590
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.407889884
Short name T935
Test name
Test status
Simulation time 17134277 ps
CPU time 0.85 seconds
Started Aug 15 05:15:44 PM PDT 24
Finished Aug 15 05:15:45 PM PDT 24
Peak memory 206240 kb
Host smart-a0cc48d7-b5cd-43f9-8ad3-f2228b1c7789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407889884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.407889884
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.173579418
Short name T838
Test name
Test status
Simulation time 327488717 ps
CPU time 2.33 seconds
Started Aug 15 05:15:46 PM PDT 24
Finished Aug 15 05:15:48 PM PDT 24
Peak memory 225180 kb
Host smart-54a09284-c3e4-4110-924f-e86abb39b163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173579418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.173579418
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2091770018
Short name T841
Test name
Test status
Simulation time 38471974 ps
CPU time 0.84 seconds
Started Aug 15 05:15:46 PM PDT 24
Finished Aug 15 05:15:46 PM PDT 24
Peak memory 207740 kb
Host smart-3ef3f232-f3f7-4fb4-ae97-fb88c4270493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091770018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2091770018
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1079146624
Short name T214
Test name
Test status
Simulation time 56107166838 ps
CPU time 110.42 seconds
Started Aug 15 05:15:46 PM PDT 24
Finished Aug 15 05:17:37 PM PDT 24
Peak memory 250076 kb
Host smart-c97a1220-cebc-4fb9-8beb-295e8663a891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079146624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1079146624
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2661473106
Short name T603
Test name
Test status
Simulation time 3357426885 ps
CPU time 24.1 seconds
Started Aug 15 05:15:45 PM PDT 24
Finished Aug 15 05:16:09 PM PDT 24
Peak memory 218792 kb
Host smart-63be0acb-d1ed-4a54-ade5-50d7f50db956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661473106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2661473106
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1777343649
Short name T801
Test name
Test status
Simulation time 2227656007 ps
CPU time 41.46 seconds
Started Aug 15 05:15:45 PM PDT 24
Finished Aug 15 05:16:26 PM PDT 24
Peak memory 251184 kb
Host smart-3e094af8-c7a0-489a-9224-cf547831a5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777343649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1777343649
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1519343468
Short name T993
Test name
Test status
Simulation time 4002237424 ps
CPU time 29.38 seconds
Started Aug 15 05:15:45 PM PDT 24
Finished Aug 15 05:16:14 PM PDT 24
Peak memory 241856 kb
Host smart-306be8f3-8115-4d30-90fa-42a0e1e4554b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519343468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1519343468
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1612327090
Short name T727
Test name
Test status
Simulation time 28189024927 ps
CPU time 61.74 seconds
Started Aug 15 05:15:46 PM PDT 24
Finished Aug 15 05:16:48 PM PDT 24
Peak memory 249980 kb
Host smart-dabc1687-8f20-471b-8b5e-de1903a28e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612327090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1612327090
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.329202167
Short name T719
Test name
Test status
Simulation time 1073072777 ps
CPU time 10.4 seconds
Started Aug 15 05:15:45 PM PDT 24
Finished Aug 15 05:15:56 PM PDT 24
Peak memory 233548 kb
Host smart-946457fe-1f68-44d5-9778-6a1f5b3ddea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329202167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.329202167
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.439731867
Short name T837
Test name
Test status
Simulation time 101067805 ps
CPU time 2.23 seconds
Started Aug 15 05:15:46 PM PDT 24
Finished Aug 15 05:15:49 PM PDT 24
Peak memory 224528 kb
Host smart-77811871-a799-44c1-a8a9-fd167b49e8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439731867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.439731867
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.425281413
Short name T256
Test name
Test status
Simulation time 19206600858 ps
CPU time 29.5 seconds
Started Aug 15 05:15:44 PM PDT 24
Finished Aug 15 05:16:14 PM PDT 24
Peak memory 252472 kb
Host smart-fb9deae3-4fc2-4c42-b918-be617ce6552d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425281413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.425281413
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3439092582
Short name T879
Test name
Test status
Simulation time 8327067091 ps
CPU time 24.69 seconds
Started Aug 15 05:15:47 PM PDT 24
Finished Aug 15 05:16:12 PM PDT 24
Peak memory 225464 kb
Host smart-30905946-3244-459f-8d77-a84c90ee90a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439092582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3439092582
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2029678962
Short name T730
Test name
Test status
Simulation time 4746725644 ps
CPU time 13.25 seconds
Started Aug 15 05:15:58 PM PDT 24
Finished Aug 15 05:16:12 PM PDT 24
Peak memory 224044 kb
Host smart-0738206b-9935-4793-8902-503f2e8c4009
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2029678962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2029678962
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3656887009
Short name T675
Test name
Test status
Simulation time 67058856471 ps
CPU time 214.7 seconds
Started Aug 15 05:15:46 PM PDT 24
Finished Aug 15 05:19:20 PM PDT 24
Peak memory 251692 kb
Host smart-92b2ae0c-590a-420a-b1c5-11293045bc40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656887009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3656887009
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3243626362
Short name T928
Test name
Test status
Simulation time 31800374588 ps
CPU time 31.46 seconds
Started Aug 15 05:15:44 PM PDT 24
Finished Aug 15 05:16:15 PM PDT 24
Peak memory 217196 kb
Host smart-03c01de3-53c3-40f3-923d-68a6e5042047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243626362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3243626362
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1676878945
Short name T789
Test name
Test status
Simulation time 5529079126 ps
CPU time 16.82 seconds
Started Aug 15 05:15:43 PM PDT 24
Finished Aug 15 05:15:59 PM PDT 24
Peak memory 217240 kb
Host smart-8055d58e-f4ad-42b9-ad20-759ccb2bf208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676878945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1676878945
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.738806060
Short name T622
Test name
Test status
Simulation time 221629704 ps
CPU time 2.32 seconds
Started Aug 15 05:15:45 PM PDT 24
Finished Aug 15 05:15:48 PM PDT 24
Peak memory 217164 kb
Host smart-30507c7d-812b-4190-af99-97158c6d5e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738806060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.738806060
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3562197985
Short name T703
Test name
Test status
Simulation time 14053899 ps
CPU time 0.76 seconds
Started Aug 15 05:15:45 PM PDT 24
Finished Aug 15 05:15:46 PM PDT 24
Peak memory 206692 kb
Host smart-fb509c70-0821-4d8f-9aed-06f9b4effe41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562197985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3562197985
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.15544560
Short name T655
Test name
Test status
Simulation time 517111381 ps
CPU time 3.13 seconds
Started Aug 15 05:15:46 PM PDT 24
Finished Aug 15 05:15:49 PM PDT 24
Peak memory 233556 kb
Host smart-5a14b490-e27d-4f39-b3dd-e887b045a1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15544560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.15544560
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3756516833
Short name T454
Test name
Test status
Simulation time 14609484 ps
CPU time 0.76 seconds
Started Aug 15 05:16:10 PM PDT 24
Finished Aug 15 05:16:11 PM PDT 24
Peak memory 205668 kb
Host smart-c6bfffd8-7fb3-467a-8ac5-c751aa75be65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756516833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3756516833
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2455401568
Short name T97
Test name
Test status
Simulation time 106517061 ps
CPU time 3.3 seconds
Started Aug 15 05:15:54 PM PDT 24
Finished Aug 15 05:15:57 PM PDT 24
Peak memory 233504 kb
Host smart-ed51ac32-9dcb-400e-96f4-7def6bb4db53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455401568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2455401568
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2745852829
Short name T639
Test name
Test status
Simulation time 24027524 ps
CPU time 0.82 seconds
Started Aug 15 05:15:55 PM PDT 24
Finished Aug 15 05:15:56 PM PDT 24
Peak memory 207392 kb
Host smart-8fe4d363-55b2-49cd-8ca5-7f062da1b2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745852829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2745852829
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3643650089
Short name T760
Test name
Test status
Simulation time 12958636802 ps
CPU time 29.19 seconds
Started Aug 15 05:15:55 PM PDT 24
Finished Aug 15 05:16:24 PM PDT 24
Peak memory 251512 kb
Host smart-9da2637c-0680-4963-81b4-ae9e27f2b926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643650089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3643650089
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1323865029
Short name T596
Test name
Test status
Simulation time 13062611268 ps
CPU time 65.85 seconds
Started Aug 15 05:15:56 PM PDT 24
Finished Aug 15 05:17:02 PM PDT 24
Peak memory 255292 kb
Host smart-faed8f60-4cd8-43f4-aa4a-ea7628e65e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323865029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1323865029
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2587855089
Short name T447
Test name
Test status
Simulation time 27852441463 ps
CPU time 80.73 seconds
Started Aug 15 05:15:54 PM PDT 24
Finished Aug 15 05:17:15 PM PDT 24
Peak memory 250232 kb
Host smart-5f4bff75-bef6-429e-8df4-aecb51f2dddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587855089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2587855089
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1078503399
Short name T175
Test name
Test status
Simulation time 275420802 ps
CPU time 3.82 seconds
Started Aug 15 05:15:54 PM PDT 24
Finished Aug 15 05:15:58 PM PDT 24
Peak memory 233608 kb
Host smart-25d9699d-4cf9-448c-b718-378b448ede69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078503399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1078503399
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2103565112
Short name T51
Test name
Test status
Simulation time 1672316302 ps
CPU time 21.27 seconds
Started Aug 15 05:15:54 PM PDT 24
Finished Aug 15 05:16:16 PM PDT 24
Peak memory 233516 kb
Host smart-b91c4d42-6152-4e5c-a61c-49ad77737981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103565112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2103565112
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2114015519
Short name T984
Test name
Test status
Simulation time 586702444 ps
CPU time 10.03 seconds
Started Aug 15 05:15:56 PM PDT 24
Finished Aug 15 05:16:06 PM PDT 24
Peak memory 225248 kb
Host smart-6a5302c5-a20e-49a9-84c5-f1248a34a28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114015519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2114015519
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.57645378
Short name T237
Test name
Test status
Simulation time 7525835777 ps
CPU time 30.26 seconds
Started Aug 15 05:15:52 PM PDT 24
Finished Aug 15 05:16:22 PM PDT 24
Peak memory 241592 kb
Host smart-bf64bb7e-2955-4e9f-9a72-7cb28e5ceb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57645378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.57645378
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.4168512081
Short name T740
Test name
Test status
Simulation time 9036416814 ps
CPU time 11.13 seconds
Started Aug 15 05:15:53 PM PDT 24
Finished Aug 15 05:16:05 PM PDT 24
Peak memory 233624 kb
Host smart-9aadaccc-8ccb-4976-8f87-f65f24d72da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168512081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.4168512081
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.400325566
Short name T647
Test name
Test status
Simulation time 8576423045 ps
CPU time 12.41 seconds
Started Aug 15 05:15:53 PM PDT 24
Finished Aug 15 05:16:05 PM PDT 24
Peak memory 233692 kb
Host smart-807b7c8e-7944-4105-a7a9-a13c0a78bba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400325566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.400325566
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4132946572
Short name T859
Test name
Test status
Simulation time 195087505 ps
CPU time 4.19 seconds
Started Aug 15 05:15:53 PM PDT 24
Finished Aug 15 05:15:57 PM PDT 24
Peak memory 221000 kb
Host smart-93eb0bd7-e411-4861-936a-aa883f8f7bec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4132946572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4132946572
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.4038148791
Short name T62
Test name
Test status
Simulation time 133762013983 ps
CPU time 313.9 seconds
Started Aug 15 05:15:54 PM PDT 24
Finished Aug 15 05:21:08 PM PDT 24
Peak memory 257144 kb
Host smart-3eaa1be8-7220-4b6c-a436-8a8cb37dddbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038148791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.4038148791
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2898243727
Short name T474
Test name
Test status
Simulation time 7307306434 ps
CPU time 24.99 seconds
Started Aug 15 05:15:55 PM PDT 24
Finished Aug 15 05:16:20 PM PDT 24
Peak memory 217268 kb
Host smart-f91afe60-c41a-47e8-8951-988f0cadf765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898243727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2898243727
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3272113609
Short name T759
Test name
Test status
Simulation time 17504658 ps
CPU time 0.69 seconds
Started Aug 15 05:15:56 PM PDT 24
Finished Aug 15 05:15:57 PM PDT 24
Peak memory 206456 kb
Host smart-ab3f765c-0745-46e5-b588-25529aad34ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272113609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3272113609
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1269341530
Short name T438
Test name
Test status
Simulation time 76877177 ps
CPU time 1.03 seconds
Started Aug 15 05:15:53 PM PDT 24
Finished Aug 15 05:15:54 PM PDT 24
Peak memory 207856 kb
Host smart-afeab139-83dc-4418-ba94-945cec985fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269341530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1269341530
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3759855646
Short name T818
Test name
Test status
Simulation time 11320080 ps
CPU time 0.69 seconds
Started Aug 15 05:15:54 PM PDT 24
Finished Aug 15 05:15:55 PM PDT 24
Peak memory 206368 kb
Host smart-f37c613e-6f76-4941-9d91-33ee391d69e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759855646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3759855646
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2707694173
Short name T2
Test name
Test status
Simulation time 42839798 ps
CPU time 2.3 seconds
Started Aug 15 05:15:52 PM PDT 24
Finished Aug 15 05:15:55 PM PDT 24
Peak memory 225024 kb
Host smart-48a6a820-bcf9-49af-aaa3-f97cb9c438db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707694173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2707694173
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3867908155
Short name T826
Test name
Test status
Simulation time 28282663 ps
CPU time 0.7 seconds
Started Aug 15 05:16:00 PM PDT 24
Finished Aug 15 05:16:00 PM PDT 24
Peak memory 206188 kb
Host smart-fe7fc0c4-6387-47e7-82c3-71c6f37f81cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867908155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3867908155
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2017105851
Short name T245
Test name
Test status
Simulation time 77103708 ps
CPU time 2.23 seconds
Started Aug 15 05:16:06 PM PDT 24
Finished Aug 15 05:16:08 PM PDT 24
Peak memory 225312 kb
Host smart-c6576111-0453-4f09-a806-d4dac8f9370e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017105851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2017105851
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3994909218
Short name T468
Test name
Test status
Simulation time 20076739 ps
CPU time 0.79 seconds
Started Aug 15 05:15:53 PM PDT 24
Finished Aug 15 05:15:54 PM PDT 24
Peak memory 207344 kb
Host smart-627ce859-e98e-4349-a4d9-ef2422d4e4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994909218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3994909218
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2332680225
Short name T199
Test name
Test status
Simulation time 9643055849 ps
CPU time 62.46 seconds
Started Aug 15 05:16:01 PM PDT 24
Finished Aug 15 05:17:04 PM PDT 24
Peak memory 225568 kb
Host smart-ee7df238-4ed6-4f57-93ae-9984dae623c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332680225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2332680225
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2883663748
Short name T48
Test name
Test status
Simulation time 24173363532 ps
CPU time 81.22 seconds
Started Aug 15 05:16:05 PM PDT 24
Finished Aug 15 05:17:26 PM PDT 24
Peak memory 257224 kb
Host smart-c879ef5b-9f5c-4364-ac64-36e628831e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883663748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2883663748
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1919510438
Short name T793
Test name
Test status
Simulation time 367501329 ps
CPU time 11.5 seconds
Started Aug 15 05:16:01 PM PDT 24
Finished Aug 15 05:16:13 PM PDT 24
Peak memory 241556 kb
Host smart-51463a06-2d17-4cd0-973d-1ee986105830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919510438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1919510438
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.4021170636
Short name T417
Test name
Test status
Simulation time 15038623883 ps
CPU time 39.96 seconds
Started Aug 15 05:16:01 PM PDT 24
Finished Aug 15 05:16:41 PM PDT 24
Peak memory 250120 kb
Host smart-39305898-f557-4e92-a731-9ac3f3df83ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021170636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.4021170636
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2483703939
Short name T828
Test name
Test status
Simulation time 167173462 ps
CPU time 3.72 seconds
Started Aug 15 05:15:56 PM PDT 24
Finished Aug 15 05:15:59 PM PDT 24
Peak memory 225332 kb
Host smart-4e04a5e0-2d58-4ff3-82c8-408752ae9961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483703939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2483703939
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1039712385
Short name T425
Test name
Test status
Simulation time 19547629700 ps
CPU time 42.86 seconds
Started Aug 15 05:15:53 PM PDT 24
Finished Aug 15 05:16:36 PM PDT 24
Peak memory 239540 kb
Host smart-48eb2869-084c-4b09-b0e4-75fdb10902b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039712385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1039712385
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3381927287
Short name T292
Test name
Test status
Simulation time 13095333689 ps
CPU time 13.54 seconds
Started Aug 15 05:15:54 PM PDT 24
Finished Aug 15 05:16:07 PM PDT 24
Peak memory 241892 kb
Host smart-8b4c02f0-3411-4a9b-9741-631b8573fbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381927287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3381927287
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3075831109
Short name T927
Test name
Test status
Simulation time 156767436 ps
CPU time 2.82 seconds
Started Aug 15 05:15:57 PM PDT 24
Finished Aug 15 05:16:00 PM PDT 24
Peak memory 225304 kb
Host smart-1dacc343-50cc-4a46-ad4c-e87414286a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075831109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3075831109
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.32291588
Short name T373
Test name
Test status
Simulation time 361006859 ps
CPU time 3.7 seconds
Started Aug 15 05:16:03 PM PDT 24
Finished Aug 15 05:16:07 PM PDT 24
Peak memory 223504 kb
Host smart-cd20a1de-efaa-4f9c-b196-3820b1ae7f4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=32291588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direc
t.32291588
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1318308724
Short name T283
Test name
Test status
Simulation time 390150452260 ps
CPU time 247.47 seconds
Started Aug 15 05:16:03 PM PDT 24
Finished Aug 15 05:20:10 PM PDT 24
Peak memory 269896 kb
Host smart-cfae80db-4e53-4d87-b426-85e7e6728a21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318308724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1318308724
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1689175346
Short name T306
Test name
Test status
Simulation time 4210218722 ps
CPU time 27.52 seconds
Started Aug 15 05:15:54 PM PDT 24
Finished Aug 15 05:16:22 PM PDT 24
Peak memory 217216 kb
Host smart-8ed640f7-8d14-4dc2-a6a7-600eb901318e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689175346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1689175346
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1438360453
Short name T817
Test name
Test status
Simulation time 1216450459 ps
CPU time 4.12 seconds
Started Aug 15 05:15:57 PM PDT 24
Finished Aug 15 05:16:01 PM PDT 24
Peak memory 217180 kb
Host smart-57f33df8-b498-4168-9107-14f3ee954970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438360453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1438360453
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2193916819
Short name T805
Test name
Test status
Simulation time 91400790 ps
CPU time 4.87 seconds
Started Aug 15 05:15:53 PM PDT 24
Finished Aug 15 05:15:58 PM PDT 24
Peak memory 217068 kb
Host smart-04fef37b-319d-49fb-b432-30fbefa176fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193916819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2193916819
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.187207910
Short name T427
Test name
Test status
Simulation time 64103930 ps
CPU time 0.8 seconds
Started Aug 15 05:15:53 PM PDT 24
Finished Aug 15 05:15:54 PM PDT 24
Peak memory 206752 kb
Host smart-d3b8a818-f58c-4b10-830c-faabbc88f98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187207910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.187207910
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2296091391
Short name T1
Test name
Test status
Simulation time 4065077739 ps
CPU time 13.14 seconds
Started Aug 15 05:15:55 PM PDT 24
Finished Aug 15 05:16:08 PM PDT 24
Peak memory 225460 kb
Host smart-7b806734-2c9d-415d-8984-5c15e308414a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296091391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2296091391
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1008760711
Short name T616
Test name
Test status
Simulation time 41450285 ps
CPU time 0.74 seconds
Started Aug 15 05:16:06 PM PDT 24
Finished Aug 15 05:16:07 PM PDT 24
Peak memory 206184 kb
Host smart-3e379bf6-0a42-4315-8c35-deec07ccb9ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008760711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1008760711
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1228623763
Short name T799
Test name
Test status
Simulation time 4067594248 ps
CPU time 10.38 seconds
Started Aug 15 05:16:02 PM PDT 24
Finished Aug 15 05:16:13 PM PDT 24
Peak memory 233644 kb
Host smart-42aef2b5-c0e1-488c-81a6-41170e83c33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228623763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1228623763
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2254497542
Short name T375
Test name
Test status
Simulation time 47927772 ps
CPU time 0.74 seconds
Started Aug 15 05:16:01 PM PDT 24
Finished Aug 15 05:16:02 PM PDT 24
Peak memory 206648 kb
Host smart-07b24104-fac7-4427-9648-96e37e54176a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254497542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2254497542
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3718076167
Short name T144
Test name
Test status
Simulation time 4006653241 ps
CPU time 47.18 seconds
Started Aug 15 05:16:03 PM PDT 24
Finished Aug 15 05:16:50 PM PDT 24
Peak memory 239572 kb
Host smart-bd5e7b9a-2a72-4126-8f69-3a304db0ab18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718076167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3718076167
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3747221903
Short name T663
Test name
Test status
Simulation time 5753060541 ps
CPU time 87.37 seconds
Started Aug 15 05:15:59 PM PDT 24
Finished Aug 15 05:17:27 PM PDT 24
Peak memory 266572 kb
Host smart-3bdc14dc-ab6c-4ef2-9fb3-afe483a00355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747221903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3747221903
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1846481119
Short name T890
Test name
Test status
Simulation time 12644871107 ps
CPU time 63.62 seconds
Started Aug 15 05:16:02 PM PDT 24
Finished Aug 15 05:17:06 PM PDT 24
Peak memory 250304 kb
Host smart-c03a623b-60f5-4e50-8564-9c35db806180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846481119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1846481119
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.395595028
Short name T298
Test name
Test status
Simulation time 2027448882 ps
CPU time 22.17 seconds
Started Aug 15 05:15:59 PM PDT 24
Finished Aug 15 05:16:21 PM PDT 24
Peak memory 225392 kb
Host smart-0a34f512-d640-455d-93c8-ef6775efa068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395595028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.395595028
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2172196987
Short name T177
Test name
Test status
Simulation time 35237125235 ps
CPU time 60.6 seconds
Started Aug 15 05:16:01 PM PDT 24
Finished Aug 15 05:17:02 PM PDT 24
Peak memory 257552 kb
Host smart-f2b641ba-7c9d-4256-9261-d179834627be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172196987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2172196987
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3004207343
Short name T965
Test name
Test status
Simulation time 401656946 ps
CPU time 4.4 seconds
Started Aug 15 05:16:02 PM PDT 24
Finished Aug 15 05:16:07 PM PDT 24
Peak memory 233516 kb
Host smart-9ab7d72d-9399-4028-9bf2-8b19ee379889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004207343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3004207343
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3965821971
Short name T953
Test name
Test status
Simulation time 382390837 ps
CPU time 5.31 seconds
Started Aug 15 05:16:04 PM PDT 24
Finished Aug 15 05:16:10 PM PDT 24
Peak memory 225308 kb
Host smart-a7d5cef2-3e0b-44c2-836f-a172cc105e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965821971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3965821971
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3443566602
Short name T625
Test name
Test status
Simulation time 1343783393 ps
CPU time 9.5 seconds
Started Aug 15 05:16:01 PM PDT 24
Finished Aug 15 05:16:11 PM PDT 24
Peak memory 233548 kb
Host smart-ca44f6df-d4d7-4b56-bb94-2efd71627145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443566602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3443566602
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1456504949
Short name T147
Test name
Test status
Simulation time 917173596 ps
CPU time 4.77 seconds
Started Aug 15 05:16:02 PM PDT 24
Finished Aug 15 05:16:07 PM PDT 24
Peak memory 225220 kb
Host smart-895043b5-1a10-4132-9f83-8d780480c7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456504949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1456504949
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3901124832
Short name T626
Test name
Test status
Simulation time 286384811 ps
CPU time 4.04 seconds
Started Aug 15 05:16:06 PM PDT 24
Finished Aug 15 05:16:10 PM PDT 24
Peak memory 223916 kb
Host smart-b6526bd6-3bcc-4dca-9de3-6cab901c8eac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3901124832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3901124832
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1426699208
Short name T961
Test name
Test status
Simulation time 34316752691 ps
CPU time 116.63 seconds
Started Aug 15 05:16:02 PM PDT 24
Finished Aug 15 05:17:58 PM PDT 24
Peak memory 250412 kb
Host smart-774fb13a-99b8-4ec5-9229-f5542bf4a40c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426699208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1426699208
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1543048254
Short name T881
Test name
Test status
Simulation time 3305264469 ps
CPU time 23.17 seconds
Started Aug 15 05:15:59 PM PDT 24
Finished Aug 15 05:16:23 PM PDT 24
Peak memory 217296 kb
Host smart-3e9971e1-910b-4638-8df7-fb6ce167fd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543048254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1543048254
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2743525318
Short name T901
Test name
Test status
Simulation time 11628179070 ps
CPU time 11.44 seconds
Started Aug 15 05:16:01 PM PDT 24
Finished Aug 15 05:16:13 PM PDT 24
Peak memory 217224 kb
Host smart-eac5a5c3-07cc-4100-8ac7-44ff3d9a6250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743525318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2743525318
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1036986771
Short name T397
Test name
Test status
Simulation time 189355557 ps
CPU time 1.49 seconds
Started Aug 15 05:16:07 PM PDT 24
Finished Aug 15 05:16:09 PM PDT 24
Peak memory 217064 kb
Host smart-34f5f243-ee80-4820-b38b-bca108112f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036986771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1036986771
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1864966749
Short name T707
Test name
Test status
Simulation time 32939361 ps
CPU time 0.8 seconds
Started Aug 15 05:16:02 PM PDT 24
Finished Aug 15 05:16:03 PM PDT 24
Peak memory 206824 kb
Host smart-74c40dc0-fce6-43ad-b087-581583eed8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864966749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1864966749
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2111621344
Short name T866
Test name
Test status
Simulation time 3381225762 ps
CPU time 15.04 seconds
Started Aug 15 05:16:03 PM PDT 24
Finished Aug 15 05:16:18 PM PDT 24
Peak memory 225304 kb
Host smart-263a5add-b5e0-4c4a-8995-f61ac061e5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111621344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2111621344
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2226078656
Short name T354
Test name
Test status
Simulation time 45309735 ps
CPU time 0.72 seconds
Started Aug 15 05:16:09 PM PDT 24
Finished Aug 15 05:16:10 PM PDT 24
Peak memory 206520 kb
Host smart-6f579ee5-2f06-4aa2-bf54-83f2de7fb65f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226078656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2226078656
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2602859259
Short name T937
Test name
Test status
Simulation time 10489827338 ps
CPU time 20.73 seconds
Started Aug 15 05:16:01 PM PDT 24
Finished Aug 15 05:16:22 PM PDT 24
Peak memory 225516 kb
Host smart-c9a73854-c64c-43d1-a3ac-333beeece522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602859259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2602859259
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1820862820
Short name T541
Test name
Test status
Simulation time 23931603 ps
CPU time 0.84 seconds
Started Aug 15 05:16:01 PM PDT 24
Finished Aug 15 05:16:02 PM PDT 24
Peak memory 207344 kb
Host smart-488f8b89-a792-4335-946a-837fc7f1da45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820862820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1820862820
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.680217910
Short name T944
Test name
Test status
Simulation time 2272341720 ps
CPU time 38.89 seconds
Started Aug 15 05:16:01 PM PDT 24
Finished Aug 15 05:16:40 PM PDT 24
Peak memory 241888 kb
Host smart-c54e1b9e-f070-49f7-997b-220b7db2201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680217910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.680217910
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1761506802
Short name T954
Test name
Test status
Simulation time 2144263317 ps
CPU time 27.32 seconds
Started Aug 15 05:16:03 PM PDT 24
Finished Aug 15 05:16:30 PM PDT 24
Peak memory 249240 kb
Host smart-d7ee4559-6311-4fe3-b4ab-a17acee81a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761506802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1761506802
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2425802869
Short name T989
Test name
Test status
Simulation time 190888088 ps
CPU time 7.52 seconds
Started Aug 15 05:16:04 PM PDT 24
Finished Aug 15 05:16:12 PM PDT 24
Peak memory 241060 kb
Host smart-c5f3e534-5ff6-48da-b21a-0cf7ee518d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425802869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2425802869
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.330744745
Short name T884
Test name
Test status
Simulation time 14186225595 ps
CPU time 86.7 seconds
Started Aug 15 05:16:05 PM PDT 24
Finished Aug 15 05:17:31 PM PDT 24
Peak memory 255676 kb
Host smart-7b7b8336-49e5-4109-9089-74ca59abaa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330744745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.330744745
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.378330956
Short name T809
Test name
Test status
Simulation time 857154404 ps
CPU time 10.4 seconds
Started Aug 15 05:16:02 PM PDT 24
Finished Aug 15 05:16:13 PM PDT 24
Peak memory 233584 kb
Host smart-2292cb4b-f001-46d8-a328-0e035bc9a8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378330956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.378330956
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1098208351
Short name T963
Test name
Test status
Simulation time 13182191345 ps
CPU time 47.19 seconds
Started Aug 15 05:16:02 PM PDT 24
Finished Aug 15 05:16:49 PM PDT 24
Peak memory 250032 kb
Host smart-b83e10a6-d90c-4358-9cbb-5e3e6b563531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098208351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1098208351
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3710082907
Short name T598
Test name
Test status
Simulation time 2466108961 ps
CPU time 4.07 seconds
Started Aug 15 05:16:00 PM PDT 24
Finished Aug 15 05:16:04 PM PDT 24
Peak memory 225504 kb
Host smart-ef0e3716-6e0e-4578-91d2-e613a7ba0b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710082907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3710082907
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2027655831
Short name T575
Test name
Test status
Simulation time 17849803563 ps
CPU time 25.56 seconds
Started Aug 15 05:16:05 PM PDT 24
Finished Aug 15 05:16:31 PM PDT 24
Peak memory 237192 kb
Host smart-a4402462-226b-48ac-b2fd-807b3b515dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027655831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2027655831
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2199923913
Short name T980
Test name
Test status
Simulation time 340462040 ps
CPU time 3.88 seconds
Started Aug 15 05:16:03 PM PDT 24
Finished Aug 15 05:16:07 PM PDT 24
Peak memory 220792 kb
Host smart-5549002a-97da-4a75-9eec-21d75d2c077d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2199923913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2199923913
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3100702795
Short name T820
Test name
Test status
Simulation time 17275945952 ps
CPU time 198.17 seconds
Started Aug 15 05:16:10 PM PDT 24
Finished Aug 15 05:19:29 PM PDT 24
Peak memory 256756 kb
Host smart-a6901fcd-22e7-4240-9652-19ef0bc78128
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100702795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3100702795
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.945003482
Short name T477
Test name
Test status
Simulation time 597552849 ps
CPU time 4.98 seconds
Started Aug 15 05:16:02 PM PDT 24
Finished Aug 15 05:16:07 PM PDT 24
Peak memory 217404 kb
Host smart-2e237dbd-bb0a-4930-88f0-3fe4deeaaa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945003482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.945003482
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1912388346
Short name T878
Test name
Test status
Simulation time 1510946886 ps
CPU time 8.08 seconds
Started Aug 15 05:16:01 PM PDT 24
Finished Aug 15 05:16:09 PM PDT 24
Peak memory 217168 kb
Host smart-1dfb4f47-bcd9-4dc8-8f7c-927989c8f5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912388346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1912388346
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1438254597
Short name T812
Test name
Test status
Simulation time 41548610 ps
CPU time 2.04 seconds
Started Aug 15 05:16:00 PM PDT 24
Finished Aug 15 05:16:02 PM PDT 24
Peak memory 217120 kb
Host smart-1f52147f-2aae-47ca-b6c9-2ee87bafe946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438254597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1438254597
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2864555010
Short name T362
Test name
Test status
Simulation time 31003474 ps
CPU time 0.8 seconds
Started Aug 15 05:16:05 PM PDT 24
Finished Aug 15 05:16:06 PM PDT 24
Peak memory 206752 kb
Host smart-85c58db6-1432-46c1-bec4-a5737d973c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864555010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2864555010
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1934000466
Short name T862
Test name
Test status
Simulation time 436242791 ps
CPU time 4.98 seconds
Started Aug 15 05:16:03 PM PDT 24
Finished Aug 15 05:16:08 PM PDT 24
Peak memory 233588 kb
Host smart-2490295b-98b7-4b74-bee6-7f4a5450ee81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934000466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1934000466
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1474461026
Short name T830
Test name
Test status
Simulation time 19148847 ps
CPU time 0.68 seconds
Started Aug 15 05:16:09 PM PDT 24
Finished Aug 15 05:16:10 PM PDT 24
Peak memory 205620 kb
Host smart-8baf83dd-344e-4af0-a208-a72908eac194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474461026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1474461026
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3920903554
Short name T743
Test name
Test status
Simulation time 141917591 ps
CPU time 2.59 seconds
Started Aug 15 05:16:13 PM PDT 24
Finished Aug 15 05:16:16 PM PDT 24
Peak memory 233488 kb
Host smart-23c4f314-4695-42ce-9b3e-032e96d07d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920903554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3920903554
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.602253321
Short name T465
Test name
Test status
Simulation time 16323346 ps
CPU time 0.82 seconds
Started Aug 15 05:16:13 PM PDT 24
Finished Aug 15 05:16:14 PM PDT 24
Peak memory 207380 kb
Host smart-ab0bdc7d-bfd3-44b8-a2c1-07172927ca47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602253321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.602253321
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.648134346
Short name T754
Test name
Test status
Simulation time 8148031929 ps
CPU time 65.51 seconds
Started Aug 15 05:16:14 PM PDT 24
Finished Aug 15 05:17:20 PM PDT 24
Peak memory 256600 kb
Host smart-a978201b-1e0a-4d42-a839-0df5b748ce79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648134346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.648134346
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3831754296
Short name T855
Test name
Test status
Simulation time 2505186770 ps
CPU time 28.57 seconds
Started Aug 15 05:16:09 PM PDT 24
Finished Aug 15 05:16:38 PM PDT 24
Peak memory 255800 kb
Host smart-1bbe1b69-785f-416f-b121-8c2549ae922d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831754296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3831754296
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3542001710
Short name T413
Test name
Test status
Simulation time 40062320624 ps
CPU time 153.89 seconds
Started Aug 15 05:16:12 PM PDT 24
Finished Aug 15 05:18:46 PM PDT 24
Peak memory 250460 kb
Host smart-d2993526-7d57-4000-bdef-ffee35dd9c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542001710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3542001710
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3197510281
Short name T157
Test name
Test status
Simulation time 704741098 ps
CPU time 10.15 seconds
Started Aug 15 05:16:09 PM PDT 24
Finished Aug 15 05:16:19 PM PDT 24
Peak memory 234600 kb
Host smart-fb9a321b-8fdd-4466-8d0f-9c00ae624746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197510281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3197510281
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2985184593
Short name T231
Test name
Test status
Simulation time 3275608102 ps
CPU time 30.12 seconds
Started Aug 15 05:16:09 PM PDT 24
Finished Aug 15 05:16:40 PM PDT 24
Peak memory 250820 kb
Host smart-7cd1dfa3-4848-4e4f-9f41-f3d8b5f57aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985184593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2985184593
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2983898432
Short name T580
Test name
Test status
Simulation time 8188050762 ps
CPU time 18.22 seconds
Started Aug 15 05:16:10 PM PDT 24
Finished Aug 15 05:16:28 PM PDT 24
Peak memory 233728 kb
Host smart-b03ed7f7-cbc7-459f-ab99-82bb42fb32fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983898432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2983898432
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.762248257
Short name T720
Test name
Test status
Simulation time 135510997650 ps
CPU time 73.54 seconds
Started Aug 15 05:16:08 PM PDT 24
Finished Aug 15 05:17:22 PM PDT 24
Peak memory 233716 kb
Host smart-0fd37528-a2b6-48f2-98da-9b6a975f75ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762248257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.762248257
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2747125102
Short name T257
Test name
Test status
Simulation time 597170275 ps
CPU time 3.41 seconds
Started Aug 15 05:16:11 PM PDT 24
Finished Aug 15 05:16:15 PM PDT 24
Peak memory 225360 kb
Host smart-3a24657d-2035-4091-9feb-a48438d2974f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747125102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2747125102
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3823172911
Short name T182
Test name
Test status
Simulation time 887025908 ps
CPU time 7.17 seconds
Started Aug 15 05:16:10 PM PDT 24
Finished Aug 15 05:16:17 PM PDT 24
Peak memory 233556 kb
Host smart-035219ab-eb21-4573-a588-ed413b23f9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823172911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3823172911
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3713034178
Short name T491
Test name
Test status
Simulation time 771240945 ps
CPU time 6.71 seconds
Started Aug 15 05:16:08 PM PDT 24
Finished Aug 15 05:16:15 PM PDT 24
Peak memory 223372 kb
Host smart-85347b42-5348-4b0c-bcb8-95177b49c522
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3713034178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3713034178
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1790062130
Short name T410
Test name
Test status
Simulation time 7349962377 ps
CPU time 21.1 seconds
Started Aug 15 05:16:12 PM PDT 24
Finished Aug 15 05:16:33 PM PDT 24
Peak memory 217252 kb
Host smart-2987cfa6-71af-4f11-85f9-e6a8a51d648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790062130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1790062130
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1425792332
Short name T943
Test name
Test status
Simulation time 531608667 ps
CPU time 4.24 seconds
Started Aug 15 05:16:06 PM PDT 24
Finished Aug 15 05:16:11 PM PDT 24
Peak memory 217176 kb
Host smart-9e8b0590-4813-4240-b88f-3d5a435de8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425792332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1425792332
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1612800400
Short name T381
Test name
Test status
Simulation time 39976616 ps
CPU time 1.19 seconds
Started Aug 15 05:16:16 PM PDT 24
Finished Aug 15 05:16:17 PM PDT 24
Peak memory 217124 kb
Host smart-df045442-302f-4566-8300-c81473dbdbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612800400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1612800400
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.185030758
Short name T823
Test name
Test status
Simulation time 27954452 ps
CPU time 0.8 seconds
Started Aug 15 05:16:09 PM PDT 24
Finished Aug 15 05:16:10 PM PDT 24
Peak memory 206808 kb
Host smart-984c36bc-a8b1-406c-a912-9a84ddb44f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185030758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.185030758
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1559349924
Short name T509
Test name
Test status
Simulation time 6025520022 ps
CPU time 7.87 seconds
Started Aug 15 05:16:07 PM PDT 24
Finished Aug 15 05:16:15 PM PDT 24
Peak memory 233688 kb
Host smart-de905055-29df-448e-bf34-b0720a6b3078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559349924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1559349924
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1124034073
Short name T418
Test name
Test status
Simulation time 30523029 ps
CPU time 0.72 seconds
Started Aug 15 05:13:27 PM PDT 24
Finished Aug 15 05:13:28 PM PDT 24
Peak memory 206604 kb
Host smart-740d99c4-65e7-4b72-a87a-ca9e431910c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124034073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
124034073
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1872985638
Short name T949
Test name
Test status
Simulation time 164635904 ps
CPU time 3.16 seconds
Started Aug 15 05:13:28 PM PDT 24
Finished Aug 15 05:13:31 PM PDT 24
Peak memory 225372 kb
Host smart-e55ea756-c9c0-43e5-9306-30b90b59ee50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872985638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1872985638
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1623886013
Short name T589
Test name
Test status
Simulation time 62560591 ps
CPU time 0.76 seconds
Started Aug 15 05:13:28 PM PDT 24
Finished Aug 15 05:13:29 PM PDT 24
Peak memory 206380 kb
Host smart-e03719b0-9df4-497d-ab87-55562b46bcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623886013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1623886013
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3576037056
Short name T463
Test name
Test status
Simulation time 12114278658 ps
CPU time 63.41 seconds
Started Aug 15 05:13:27 PM PDT 24
Finished Aug 15 05:14:31 PM PDT 24
Peak memory 249984 kb
Host smart-77ab6e98-d561-44a3-a1bf-d40ccce76981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576037056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3576037056
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1018520657
Short name T60
Test name
Test status
Simulation time 20912544656 ps
CPU time 196.21 seconds
Started Aug 15 05:13:26 PM PDT 24
Finished Aug 15 05:16:42 PM PDT 24
Peak memory 258372 kb
Host smart-4dc4453d-640e-45e3-b5ea-14d85d91c529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018520657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1018520657
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1447377786
Short name T286
Test name
Test status
Simulation time 8693075453 ps
CPU time 119.49 seconds
Started Aug 15 05:13:27 PM PDT 24
Finished Aug 15 05:15:26 PM PDT 24
Peak memory 257032 kb
Host smart-67f22aac-dd04-4f71-976b-51c67af39d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447377786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1447377786
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.731084733
Short name T38
Test name
Test status
Simulation time 4787370895 ps
CPU time 20.41 seconds
Started Aug 15 05:13:30 PM PDT 24
Finished Aug 15 05:13:51 PM PDT 24
Peak memory 250076 kb
Host smart-be59108a-5e0e-4a07-aaae-018c510bc03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731084733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.731084733
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2010254656
Short name T904
Test name
Test status
Simulation time 14754816 ps
CPU time 0.76 seconds
Started Aug 15 05:13:27 PM PDT 24
Finished Aug 15 05:13:28 PM PDT 24
Peak memory 216620 kb
Host smart-f9b96955-58cb-4a97-bb75-aea07f9fe41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010254656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2010254656
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3890584229
Short name T501
Test name
Test status
Simulation time 4686947149 ps
CPU time 43.76 seconds
Started Aug 15 05:13:29 PM PDT 24
Finished Aug 15 05:14:13 PM PDT 24
Peak memory 241492 kb
Host smart-1dc22ec9-1a1b-4b86-b58f-ac0b76309564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890584229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3890584229
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1134117222
Short name T180
Test name
Test status
Simulation time 213902638 ps
CPU time 5.73 seconds
Started Aug 15 05:13:27 PM PDT 24
Finished Aug 15 05:13:33 PM PDT 24
Peak memory 225312 kb
Host smart-09c86069-f9e1-4462-b982-c427b25906a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134117222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1134117222
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1140006492
Short name T513
Test name
Test status
Simulation time 1655664914 ps
CPU time 4.38 seconds
Started Aug 15 05:13:28 PM PDT 24
Finished Aug 15 05:13:32 PM PDT 24
Peak memory 233548 kb
Host smart-e66b1165-e5ae-4406-831a-6c54e17c568c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140006492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1140006492
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3984445914
Short name T250
Test name
Test status
Simulation time 432492432 ps
CPU time 6.63 seconds
Started Aug 15 05:13:28 PM PDT 24
Finished Aug 15 05:13:35 PM PDT 24
Peak memory 233472 kb
Host smart-bcfacd0d-f372-4aae-8f0d-408adc9804cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984445914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3984445914
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.4185892658
Short name T595
Test name
Test status
Simulation time 760070964 ps
CPU time 4.85 seconds
Started Aug 15 05:13:29 PM PDT 24
Finished Aug 15 05:13:35 PM PDT 24
Peak memory 221352 kb
Host smart-0562c536-6299-4ee9-be45-574667d25db6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4185892658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.4185892658
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.4226981319
Short name T78
Test name
Test status
Simulation time 409582902 ps
CPU time 1.09 seconds
Started Aug 15 05:13:29 PM PDT 24
Finished Aug 15 05:13:30 PM PDT 24
Peak memory 237212 kb
Host smart-20740fcf-ae2a-413d-9e08-62a9b76b2dfd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226981319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4226981319
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2311973202
Short name T167
Test name
Test status
Simulation time 48707285 ps
CPU time 1.1 seconds
Started Aug 15 05:13:30 PM PDT 24
Finished Aug 15 05:13:32 PM PDT 24
Peak memory 207656 kb
Host smart-673e6286-3a9f-4bdc-92e9-c1d9321d91c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311973202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2311973202
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1089745758
Short name T765
Test name
Test status
Simulation time 203038272 ps
CPU time 2.71 seconds
Started Aug 15 05:13:27 PM PDT 24
Finished Aug 15 05:13:30 PM PDT 24
Peak memory 217156 kb
Host smart-75b098e5-f085-4e7c-982e-0e4e82e75282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089745758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1089745758
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2935657068
Short name T843
Test name
Test status
Simulation time 8002614328 ps
CPU time 8.05 seconds
Started Aug 15 05:13:29 PM PDT 24
Finished Aug 15 05:13:38 PM PDT 24
Peak memory 218672 kb
Host smart-da0662df-868e-4fce-bfda-b52b1c136da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935657068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2935657068
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.972730821
Short name T613
Test name
Test status
Simulation time 117452846 ps
CPU time 1.16 seconds
Started Aug 15 05:13:29 PM PDT 24
Finished Aug 15 05:13:31 PM PDT 24
Peak memory 208692 kb
Host smart-4aff5aac-7bc8-4bb3-ada5-4273773116a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972730821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.972730821
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2358466158
Short name T313
Test name
Test status
Simulation time 136311188 ps
CPU time 0.79 seconds
Started Aug 15 05:13:30 PM PDT 24
Finished Aug 15 05:13:31 PM PDT 24
Peak memory 206840 kb
Host smart-38eeb42e-0b86-4356-89fa-05051f46e242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358466158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2358466158
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3272087158
Short name T445
Test name
Test status
Simulation time 4971726803 ps
CPU time 20.58 seconds
Started Aug 15 05:13:28 PM PDT 24
Finished Aug 15 05:13:49 PM PDT 24
Peak memory 233640 kb
Host smart-508d6e40-272a-4382-944c-4925d95b250f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272087158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3272087158
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1414526085
Short name T907
Test name
Test status
Simulation time 20258530 ps
CPU time 0.69 seconds
Started Aug 15 05:16:18 PM PDT 24
Finished Aug 15 05:16:19 PM PDT 24
Peak memory 206192 kb
Host smart-0af734e5-6530-4789-bf38-14d0cc12e97c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414526085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1414526085
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2279273955
Short name T347
Test name
Test status
Simulation time 191189149 ps
CPU time 4.46 seconds
Started Aug 15 05:16:18 PM PDT 24
Finished Aug 15 05:16:23 PM PDT 24
Peak memory 233568 kb
Host smart-78762d06-bd06-40fe-89d5-56c94dde1ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279273955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2279273955
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4001441463
Short name T66
Test name
Test status
Simulation time 253589928 ps
CPU time 0.82 seconds
Started Aug 15 05:16:14 PM PDT 24
Finished Aug 15 05:16:15 PM PDT 24
Peak memory 207356 kb
Host smart-656c85cf-98e2-4040-b8d4-30dde2dfccf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001441463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4001441463
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3257284721
Short name T796
Test name
Test status
Simulation time 12981450027 ps
CPU time 86.94 seconds
Started Aug 15 05:16:20 PM PDT 24
Finished Aug 15 05:17:47 PM PDT 24
Peak memory 239184 kb
Host smart-030c9771-b1fb-4e59-92c8-2c332a41c5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257284721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3257284721
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1747521762
Short name T966
Test name
Test status
Simulation time 150373858417 ps
CPU time 528.95 seconds
Started Aug 15 05:16:19 PM PDT 24
Finished Aug 15 05:25:08 PM PDT 24
Peak memory 273816 kb
Host smart-bce3a983-2a98-4711-a08a-2832661cd66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747521762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1747521762
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2538163061
Short name T301
Test name
Test status
Simulation time 3414306662 ps
CPU time 14.89 seconds
Started Aug 15 05:16:18 PM PDT 24
Finished Aug 15 05:16:33 PM PDT 24
Peak memory 225636 kb
Host smart-5990d554-32e4-4181-a163-fc87c944e9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538163061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2538163061
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4142293228
Short name T990
Test name
Test status
Simulation time 353567018 ps
CPU time 7.31 seconds
Started Aug 15 05:16:18 PM PDT 24
Finished Aug 15 05:16:26 PM PDT 24
Peak memory 237392 kb
Host smart-289d864d-2ca4-4b4d-afef-63f0b75af35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142293228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4142293228
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.628691185
Short name T275
Test name
Test status
Simulation time 8565759651 ps
CPU time 116.29 seconds
Started Aug 15 05:16:21 PM PDT 24
Finished Aug 15 05:18:17 PM PDT 24
Peak memory 258204 kb
Host smart-cbce08d2-06b5-459b-bcbd-2c2b8cab3fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628691185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.628691185
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3305320702
Short name T819
Test name
Test status
Simulation time 5878085186 ps
CPU time 13.89 seconds
Started Aug 15 05:16:08 PM PDT 24
Finished Aug 15 05:16:22 PM PDT 24
Peak memory 225416 kb
Host smart-5722896f-c9a8-47af-8396-4e292b55d62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305320702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3305320702
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.923658076
Short name T836
Test name
Test status
Simulation time 11889131889 ps
CPU time 85.08 seconds
Started Aug 15 05:16:10 PM PDT 24
Finished Aug 15 05:17:35 PM PDT 24
Peak memory 233704 kb
Host smart-74447a72-68e0-4a4a-aea5-59bd25bc42a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923658076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.923658076
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.32795787
Short name T645
Test name
Test status
Simulation time 263960759 ps
CPU time 4.47 seconds
Started Aug 15 05:16:08 PM PDT 24
Finished Aug 15 05:16:12 PM PDT 24
Peak memory 233568 kb
Host smart-25b06cc2-6a98-4fcd-86d4-47c872348303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32795787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.32795787
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3643956719
Short name T1010
Test name
Test status
Simulation time 8293130280 ps
CPU time 14.6 seconds
Started Aug 15 05:16:09 PM PDT 24
Finished Aug 15 05:16:24 PM PDT 24
Peak memory 233720 kb
Host smart-08f763ed-77de-4ddb-a357-9b8ad639023c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643956719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3643956719
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3817959781
Short name T426
Test name
Test status
Simulation time 353933335 ps
CPU time 5.11 seconds
Started Aug 15 05:16:21 PM PDT 24
Finished Aug 15 05:16:26 PM PDT 24
Peak memory 223552 kb
Host smart-62c71941-b5d1-4cec-a7ea-3b800cd9146c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3817959781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3817959781
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3869106967
Short name T578
Test name
Test status
Simulation time 32536864008 ps
CPU time 44.41 seconds
Started Aug 15 05:16:09 PM PDT 24
Finished Aug 15 05:16:54 PM PDT 24
Peak memory 217228 kb
Host smart-8e737591-3aeb-43a3-9306-6bfccc31dacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869106967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3869106967
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2898046827
Short name T414
Test name
Test status
Simulation time 34353544488 ps
CPU time 15.73 seconds
Started Aug 15 05:16:10 PM PDT 24
Finished Aug 15 05:16:26 PM PDT 24
Peak memory 217416 kb
Host smart-33da265f-4272-4db0-9a00-9eb5094591dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898046827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2898046827
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2196214863
Short name T29
Test name
Test status
Simulation time 66727701 ps
CPU time 1.52 seconds
Started Aug 15 05:16:10 PM PDT 24
Finished Aug 15 05:16:12 PM PDT 24
Peak memory 217140 kb
Host smart-0fc5847a-f05a-4556-88dd-f624c38f1ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196214863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2196214863
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.875636646
Short name T788
Test name
Test status
Simulation time 319866711 ps
CPU time 1 seconds
Started Aug 15 05:16:07 PM PDT 24
Finished Aug 15 05:16:09 PM PDT 24
Peak memory 207864 kb
Host smart-9b128ec5-a420-48c1-a9f6-fe71d8fc6001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875636646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.875636646
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3466362576
Short name T230
Test name
Test status
Simulation time 3213186279 ps
CPU time 5.97 seconds
Started Aug 15 05:16:20 PM PDT 24
Finished Aug 15 05:16:26 PM PDT 24
Peak memory 225512 kb
Host smart-fbc0e9ae-38d2-4567-bf50-bb1541b729a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466362576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3466362576
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3542327218
Short name T742
Test name
Test status
Simulation time 32094705 ps
CPU time 0.75 seconds
Started Aug 15 05:16:28 PM PDT 24
Finished Aug 15 05:16:28 PM PDT 24
Peak memory 205700 kb
Host smart-72613f50-b9d9-4352-923d-1854c84fc874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542327218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3542327218
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1476751103
Short name T911
Test name
Test status
Simulation time 446106747 ps
CPU time 2.63 seconds
Started Aug 15 05:16:20 PM PDT 24
Finished Aug 15 05:16:22 PM PDT 24
Peak memory 225408 kb
Host smart-0f2b0363-16b9-4098-a8b0-1d46ccfd8e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476751103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1476751103
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1306698126
Short name T341
Test name
Test status
Simulation time 77869568 ps
CPU time 0.74 seconds
Started Aug 15 05:16:19 PM PDT 24
Finished Aug 15 05:16:20 PM PDT 24
Peak memory 206372 kb
Host smart-d96b5cae-b130-4f01-ab68-42ed75e792f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306698126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1306698126
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.583545506
Short name T150
Test name
Test status
Simulation time 40255288642 ps
CPU time 61.74 seconds
Started Aug 15 05:16:19 PM PDT 24
Finished Aug 15 05:17:21 PM PDT 24
Peak memory 273412 kb
Host smart-5a3f3a6c-5109-4605-9881-832b85b634d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583545506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.583545506
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3704601617
Short name T594
Test name
Test status
Simulation time 82438600488 ps
CPU time 400.67 seconds
Started Aug 15 05:16:20 PM PDT 24
Finished Aug 15 05:23:01 PM PDT 24
Peak memory 265612 kb
Host smart-107b92f6-f883-4b95-92be-21093f41e67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704601617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3704601617
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2031972160
Short name T685
Test name
Test status
Simulation time 1248874128 ps
CPU time 6.59 seconds
Started Aug 15 05:16:20 PM PDT 24
Finished Aug 15 05:16:27 PM PDT 24
Peak memory 249988 kb
Host smart-ea298da0-f0c6-433b-a2f4-556ff80f64f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031972160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2031972160
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.974721600
Short name T776
Test name
Test status
Simulation time 2304607032 ps
CPU time 17.05 seconds
Started Aug 15 05:16:17 PM PDT 24
Finished Aug 15 05:16:34 PM PDT 24
Peak memory 236888 kb
Host smart-5df1e0a8-174b-4bfa-bd91-34d7067bd1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974721600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.974721600
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2735291941
Short name T749
Test name
Test status
Simulation time 732954988 ps
CPU time 2.33 seconds
Started Aug 15 05:16:18 PM PDT 24
Finished Aug 15 05:16:21 PM PDT 24
Peak memory 224852 kb
Host smart-b3ee17c8-65f1-42b0-826f-316baadd7a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735291941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2735291941
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2819171510
Short name T995
Test name
Test status
Simulation time 106515850 ps
CPU time 2.2 seconds
Started Aug 15 05:16:20 PM PDT 24
Finished Aug 15 05:16:22 PM PDT 24
Peak memory 224780 kb
Host smart-fd33562d-1251-407c-b279-6771afd18441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819171510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2819171510
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2422675489
Short name T848
Test name
Test status
Simulation time 536818777 ps
CPU time 3.83 seconds
Started Aug 15 05:16:22 PM PDT 24
Finished Aug 15 05:16:26 PM PDT 24
Peak memory 233536 kb
Host smart-66a7a828-78d8-44f0-8372-33d3c394f5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422675489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2422675489
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4008243242
Short name T628
Test name
Test status
Simulation time 5591218069 ps
CPU time 17.62 seconds
Started Aug 15 05:16:21 PM PDT 24
Finished Aug 15 05:16:39 PM PDT 24
Peak memory 233660 kb
Host smart-7fec3e31-1742-4a63-9cce-5067b84b2883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008243242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4008243242
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2216074057
Short name T160
Test name
Test status
Simulation time 191473404 ps
CPU time 3.79 seconds
Started Aug 15 05:16:18 PM PDT 24
Finished Aug 15 05:16:22 PM PDT 24
Peak memory 224016 kb
Host smart-0b813ae7-7478-42ed-8217-555e709d11ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2216074057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2216074057
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3615876535
Short name T940
Test name
Test status
Simulation time 3872679575 ps
CPU time 34.59 seconds
Started Aug 15 05:16:19 PM PDT 24
Finished Aug 15 05:16:54 PM PDT 24
Peak memory 234252 kb
Host smart-7df71044-3404-44b5-a142-ef31f80cace5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615876535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3615876535
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.933639913
Short name T650
Test name
Test status
Simulation time 6266371128 ps
CPU time 10.58 seconds
Started Aug 15 05:16:21 PM PDT 24
Finished Aug 15 05:16:32 PM PDT 24
Peak memory 217232 kb
Host smart-09fd06b5-9ec5-456e-9455-896a379db4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933639913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.933639913
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1180720711
Short name T712
Test name
Test status
Simulation time 2659585465 ps
CPU time 5.03 seconds
Started Aug 15 05:16:19 PM PDT 24
Finished Aug 15 05:16:25 PM PDT 24
Peak memory 217184 kb
Host smart-2c881f3f-9d12-4ecd-a5a6-64b762054458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180720711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1180720711
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1049125374
Short name T656
Test name
Test status
Simulation time 316709223 ps
CPU time 4.76 seconds
Started Aug 15 05:16:21 PM PDT 24
Finished Aug 15 05:16:26 PM PDT 24
Peak memory 217084 kb
Host smart-59a83e1d-de9c-4a22-a477-2b0670211324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049125374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1049125374
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3392078428
Short name T617
Test name
Test status
Simulation time 319161996 ps
CPU time 0.9 seconds
Started Aug 15 05:16:19 PM PDT 24
Finished Aug 15 05:16:20 PM PDT 24
Peak memory 206860 kb
Host smart-4a27c620-17d4-4735-ae1a-0f885468e949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392078428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3392078428
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1614557274
Short name T222
Test name
Test status
Simulation time 902342111 ps
CPU time 5.56 seconds
Started Aug 15 05:16:18 PM PDT 24
Finished Aug 15 05:16:24 PM PDT 24
Peak memory 239776 kb
Host smart-15a1959e-9c3c-4c1c-9cab-5a3d5de0f3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614557274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1614557274
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3195324460
Short name T544
Test name
Test status
Simulation time 29450652 ps
CPU time 0.7 seconds
Started Aug 15 05:16:30 PM PDT 24
Finished Aug 15 05:16:31 PM PDT 24
Peak memory 205704 kb
Host smart-9a645929-831e-4ba9-9454-d7482838c427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195324460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3195324460
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2698458178
Short name T266
Test name
Test status
Simulation time 947723627 ps
CPU time 7.15 seconds
Started Aug 15 05:16:33 PM PDT 24
Finished Aug 15 05:16:41 PM PDT 24
Peak memory 233472 kb
Host smart-6245d77b-1bfc-4beb-b693-dd98f6ba9845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698458178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2698458178
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.4167872147
Short name T922
Test name
Test status
Simulation time 25903478 ps
CPU time 0.78 seconds
Started Aug 15 05:16:36 PM PDT 24
Finished Aug 15 05:16:37 PM PDT 24
Peak memory 207392 kb
Host smart-62afb0cc-f1a8-443a-b3fc-9ec179a3cdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167872147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.4167872147
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3032979670
Short name T259
Test name
Test status
Simulation time 1960142793 ps
CPU time 45.57 seconds
Started Aug 15 05:16:28 PM PDT 24
Finished Aug 15 05:17:14 PM PDT 24
Peak memory 251372 kb
Host smart-5b57cf27-d101-48cb-9dd9-4e6b66f52d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032979670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3032979670
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3568709794
Short name T320
Test name
Test status
Simulation time 222010624 ps
CPU time 3.81 seconds
Started Aug 15 05:16:28 PM PDT 24
Finished Aug 15 05:16:32 PM PDT 24
Peak memory 225320 kb
Host smart-c1465753-1462-47ec-bad0-989ed0597361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568709794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3568709794
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3362197302
Short name T840
Test name
Test status
Simulation time 1473382132 ps
CPU time 14.57 seconds
Started Aug 15 05:16:31 PM PDT 24
Finished Aug 15 05:16:46 PM PDT 24
Peak memory 233552 kb
Host smart-7ba36301-1aea-44c0-aa22-3223549ccb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362197302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3362197302
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.406866926
Short name T909
Test name
Test status
Simulation time 35900931968 ps
CPU time 42.94 seconds
Started Aug 15 05:16:29 PM PDT 24
Finished Aug 15 05:17:12 PM PDT 24
Peak memory 238528 kb
Host smart-72c52b6e-3b96-4736-b6b4-2cbdaad27e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406866926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.406866926
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2530158638
Short name T767
Test name
Test status
Simulation time 738539404 ps
CPU time 7.4 seconds
Started Aug 15 05:16:30 PM PDT 24
Finished Aug 15 05:16:38 PM PDT 24
Peak memory 233552 kb
Host smart-959eb67e-d617-4606-b92f-fa5c2c5646c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530158638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2530158638
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1257431479
Short name T13
Test name
Test status
Simulation time 584207852 ps
CPU time 4.35 seconds
Started Aug 15 05:16:30 PM PDT 24
Finished Aug 15 05:16:34 PM PDT 24
Peak memory 233552 kb
Host smart-2d40acfc-239d-4965-91e6-a7aa6da37cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257431479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1257431479
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1173890027
Short name T396
Test name
Test status
Simulation time 709986378 ps
CPU time 4.21 seconds
Started Aug 15 05:16:29 PM PDT 24
Finished Aug 15 05:16:34 PM PDT 24
Peak memory 221052 kb
Host smart-718aae3a-93a3-437f-97d5-5f1bab385d43
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1173890027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1173890027
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2964515993
Short name T153
Test name
Test status
Simulation time 135242911521 ps
CPU time 289.22 seconds
Started Aug 15 05:16:29 PM PDT 24
Finished Aug 15 05:21:19 PM PDT 24
Peak memory 258108 kb
Host smart-719134b0-616f-4556-b071-1eb0cb02f28e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964515993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2964515993
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1729623154
Short name T302
Test name
Test status
Simulation time 8013266339 ps
CPU time 42.99 seconds
Started Aug 15 05:16:30 PM PDT 24
Finished Aug 15 05:17:13 PM PDT 24
Peak memory 221316 kb
Host smart-94fc9635-a0d5-436a-bb12-8880bdc17da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729623154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1729623154
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.509286389
Short name T770
Test name
Test status
Simulation time 4291270343 ps
CPU time 6.2 seconds
Started Aug 15 05:16:30 PM PDT 24
Finished Aug 15 05:16:36 PM PDT 24
Peak memory 217084 kb
Host smart-80b98a2d-d404-4219-b4eb-a7020a2f8b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509286389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.509286389
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1247137054
Short name T377
Test name
Test status
Simulation time 144713563 ps
CPU time 3.07 seconds
Started Aug 15 05:16:29 PM PDT 24
Finished Aug 15 05:16:32 PM PDT 24
Peak memory 217048 kb
Host smart-fc250be0-193a-4516-b365-3580f0573c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247137054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1247137054
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3206214257
Short name T722
Test name
Test status
Simulation time 12612942 ps
CPU time 0.73 seconds
Started Aug 15 05:16:30 PM PDT 24
Finished Aug 15 05:16:31 PM PDT 24
Peak memory 206444 kb
Host smart-cddf1362-bd36-4549-b712-4b523606e2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206214257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3206214257
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2532020663
Short name T88
Test name
Test status
Simulation time 34631914168 ps
CPU time 32.42 seconds
Started Aug 15 05:16:32 PM PDT 24
Finished Aug 15 05:17:05 PM PDT 24
Peak memory 233624 kb
Host smart-094def40-1c73-474b-9ef1-8156313dbb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532020663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2532020663
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1609011577
Short name T844
Test name
Test status
Simulation time 36646187 ps
CPU time 0.75 seconds
Started Aug 15 05:16:29 PM PDT 24
Finished Aug 15 05:16:30 PM PDT 24
Peak memory 206480 kb
Host smart-5076cefd-4a0b-4b1c-8b74-fe28c5cf76ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609011577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1609011577
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4185477937
Short name T525
Test name
Test status
Simulation time 719195613 ps
CPU time 7.86 seconds
Started Aug 15 05:16:30 PM PDT 24
Finished Aug 15 05:16:38 PM PDT 24
Peak memory 225400 kb
Host smart-67b4adbb-781c-4b8c-bd94-ac63aba9b654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185477937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4185477937
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3634123034
Short name T747
Test name
Test status
Simulation time 20202968 ps
CPU time 0.79 seconds
Started Aug 15 05:16:30 PM PDT 24
Finished Aug 15 05:16:31 PM PDT 24
Peak memory 207708 kb
Host smart-b64dabf1-ef0e-4fb0-93a1-45bb053de10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634123034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3634123034
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1449552235
Short name T360
Test name
Test status
Simulation time 109826830960 ps
CPU time 182.6 seconds
Started Aug 15 05:16:36 PM PDT 24
Finished Aug 15 05:19:39 PM PDT 24
Peak memory 250436 kb
Host smart-fa6c37a0-1358-46de-b315-86c7b65cbfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449552235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1449552235
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1725962883
Short name T533
Test name
Test status
Simulation time 26550827 ps
CPU time 0.86 seconds
Started Aug 15 05:16:31 PM PDT 24
Finished Aug 15 05:16:32 PM PDT 24
Peak memory 217824 kb
Host smart-382b0551-d616-487e-b80f-809e498303d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725962883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1725962883
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.603231814
Short name T139
Test name
Test status
Simulation time 3392717530 ps
CPU time 47.93 seconds
Started Aug 15 05:16:31 PM PDT 24
Finished Aug 15 05:17:20 PM PDT 24
Peak memory 250648 kb
Host smart-7a8c9348-331e-4586-b365-5ac6fbfcd8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603231814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.603231814
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4217477821
Short name T419
Test name
Test status
Simulation time 949372383 ps
CPU time 8.54 seconds
Started Aug 15 05:16:29 PM PDT 24
Finished Aug 15 05:16:38 PM PDT 24
Peak memory 233568 kb
Host smart-da268249-a857-42d7-bf76-e19473a9baa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217477821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4217477821
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3128869200
Short name T601
Test name
Test status
Simulation time 355548964284 ps
CPU time 572.81 seconds
Started Aug 15 05:16:29 PM PDT 24
Finished Aug 15 05:26:03 PM PDT 24
Peak memory 265556 kb
Host smart-c7ca01f3-9e77-4e68-836c-369430b87868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128869200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3128869200
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.4074985404
Short name T1001
Test name
Test status
Simulation time 5758664485 ps
CPU time 14.2 seconds
Started Aug 15 05:16:30 PM PDT 24
Finished Aug 15 05:16:45 PM PDT 24
Peak memory 225312 kb
Host smart-f811f952-aee9-43b5-8862-00b7eb73aac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074985404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4074985404
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1255778783
Short name T242
Test name
Test status
Simulation time 440454536 ps
CPU time 6.81 seconds
Started Aug 15 05:16:30 PM PDT 24
Finished Aug 15 05:16:37 PM PDT 24
Peak memory 225312 kb
Host smart-b35b2c0e-3116-4347-9749-bce5085266b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255778783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1255778783
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3926086162
Short name T715
Test name
Test status
Simulation time 47371875 ps
CPU time 2.56 seconds
Started Aug 15 05:16:30 PM PDT 24
Finished Aug 15 05:16:33 PM PDT 24
Peak memory 233256 kb
Host smart-db6c9555-b1b4-4eb6-bf3e-29090f63500e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926086162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3926086162
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3285882968
Short name T369
Test name
Test status
Simulation time 250998439 ps
CPU time 4.68 seconds
Started Aug 15 05:16:30 PM PDT 24
Finished Aug 15 05:16:35 PM PDT 24
Peak memory 225348 kb
Host smart-86f6c76a-1e23-4d27-a67b-bb86d1e47639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285882968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3285882968
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4101572133
Short name T896
Test name
Test status
Simulation time 190211060 ps
CPU time 3.71 seconds
Started Aug 15 05:16:31 PM PDT 24
Finished Aug 15 05:16:34 PM PDT 24
Peak memory 223496 kb
Host smart-f5cb998e-3f86-479f-9064-3a9915347b78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4101572133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4101572133
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1034869531
Short name T86
Test name
Test status
Simulation time 2012042256 ps
CPU time 13.47 seconds
Started Aug 15 05:16:29 PM PDT 24
Finished Aug 15 05:16:42 PM PDT 24
Peak memory 225464 kb
Host smart-c426c2d2-f458-4e64-8a68-68f5c230b4fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034869531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1034869531
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3544401662
Short name T146
Test name
Test status
Simulation time 6445346338 ps
CPU time 11.44 seconds
Started Aug 15 05:16:33 PM PDT 24
Finished Aug 15 05:16:45 PM PDT 24
Peak memory 220844 kb
Host smart-2e30cbff-f91f-4eb1-87fe-d5979d8310ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544401662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3544401662
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.41195640
Short name T63
Test name
Test status
Simulation time 1072808829 ps
CPU time 2.4 seconds
Started Aug 15 05:16:31 PM PDT 24
Finished Aug 15 05:16:33 PM PDT 24
Peak memory 208740 kb
Host smart-c3b99ada-92aa-41ae-9fd5-f71c330d432f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41195640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.41195640
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.281053229
Short name T888
Test name
Test status
Simulation time 37586232 ps
CPU time 1.22 seconds
Started Aug 15 05:16:28 PM PDT 24
Finished Aug 15 05:16:29 PM PDT 24
Peak memory 217184 kb
Host smart-67af904a-01cb-4d1c-8768-861305a280f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281053229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.281053229
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.626994491
Short name T847
Test name
Test status
Simulation time 15203713 ps
CPU time 0.73 seconds
Started Aug 15 05:16:28 PM PDT 24
Finished Aug 15 05:16:29 PM PDT 24
Peak memory 206824 kb
Host smart-8dfbd0d2-4288-403b-a21d-478aace6580a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626994491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.626994491
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1433006979
Short name T619
Test name
Test status
Simulation time 11493972174 ps
CPU time 13.68 seconds
Started Aug 15 05:16:36 PM PDT 24
Finished Aug 15 05:16:50 PM PDT 24
Peak memory 225396 kb
Host smart-4171df9c-6efb-4693-892f-d0ba222b402c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433006979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1433006979
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1317468326
Short name T494
Test name
Test status
Simulation time 14651859 ps
CPU time 0.7 seconds
Started Aug 15 05:16:38 PM PDT 24
Finished Aug 15 05:16:39 PM PDT 24
Peak memory 206600 kb
Host smart-2e01b5eb-34e6-4677-add2-0aaf85945823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317468326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1317468326
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3229665110
Short name T198
Test name
Test status
Simulation time 146938059 ps
CPU time 3.16 seconds
Started Aug 15 05:16:39 PM PDT 24
Finished Aug 15 05:16:43 PM PDT 24
Peak memory 225364 kb
Host smart-7c866e6d-81bc-43f8-b76b-2c52b7934320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229665110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3229665110
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.4019008662
Short name T376
Test name
Test status
Simulation time 15358337 ps
CPU time 0.79 seconds
Started Aug 15 05:16:31 PM PDT 24
Finished Aug 15 05:16:32 PM PDT 24
Peak memory 206644 kb
Host smart-8c3108b4-fe49-4d2b-ae74-cac49524acdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019008662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.4019008662
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1224217900
Short name T814
Test name
Test status
Simulation time 62299537440 ps
CPU time 441.14 seconds
Started Aug 15 05:16:42 PM PDT 24
Finished Aug 15 05:24:04 PM PDT 24
Peak memory 269612 kb
Host smart-a640b530-0024-4d66-a092-bf72c49e6d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224217900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1224217900
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.379240097
Short name T154
Test name
Test status
Simulation time 18361231817 ps
CPU time 73.22 seconds
Started Aug 15 05:16:39 PM PDT 24
Finished Aug 15 05:17:52 PM PDT 24
Peak memory 253548 kb
Host smart-4413bd33-6530-4472-9a1a-32f72d2b161e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379240097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.379240097
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.219310691
Short name T515
Test name
Test status
Simulation time 2457142308 ps
CPU time 17.29 seconds
Started Aug 15 05:16:37 PM PDT 24
Finished Aug 15 05:16:54 PM PDT 24
Peak memory 224204 kb
Host smart-78407af2-35e0-4f8d-adcb-ce8b59f8fa8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219310691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.219310691
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.495320645
Short name T195
Test name
Test status
Simulation time 44201911536 ps
CPU time 152.26 seconds
Started Aug 15 05:16:39 PM PDT 24
Finished Aug 15 05:19:12 PM PDT 24
Peak memory 250040 kb
Host smart-bbb3a8e9-0b08-4534-87a0-a968cabbc60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495320645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.495320645
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2969213734
Short name T653
Test name
Test status
Simulation time 3176677805 ps
CPU time 8.21 seconds
Started Aug 15 05:16:29 PM PDT 24
Finished Aug 15 05:16:38 PM PDT 24
Peak memory 233684 kb
Host smart-b7cb50a4-57af-4fad-9d47-2429639308d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969213734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2969213734
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3767974317
Short name T562
Test name
Test status
Simulation time 3549032786 ps
CPU time 28.66 seconds
Started Aug 15 05:16:30 PM PDT 24
Finished Aug 15 05:16:58 PM PDT 24
Peak memory 233684 kb
Host smart-e4e6a7b7-8de8-4da2-8b29-96524c703d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767974317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3767974317
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.4137576935
Short name T258
Test name
Test status
Simulation time 190403551 ps
CPU time 3.95 seconds
Started Aug 15 05:16:31 PM PDT 24
Finished Aug 15 05:16:35 PM PDT 24
Peak memory 233544 kb
Host smart-4b87c1c8-dc6f-4122-903e-1dee9ed1facc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137576935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.4137576935
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2839020707
Short name T506
Test name
Test status
Simulation time 4332282820 ps
CPU time 6.26 seconds
Started Aug 15 05:16:34 PM PDT 24
Finished Aug 15 05:16:40 PM PDT 24
Peak memory 233672 kb
Host smart-4edfa08d-f9e1-40a4-ba46-d5697e78b64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839020707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2839020707
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1414104715
Short name T724
Test name
Test status
Simulation time 2614374029 ps
CPU time 14.47 seconds
Started Aug 15 05:16:41 PM PDT 24
Finished Aug 15 05:16:55 PM PDT 24
Peak memory 223976 kb
Host smart-53fa7860-9b95-431e-90d8-f8c23adddfd5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1414104715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1414104715
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.836636101
Short name T36
Test name
Test status
Simulation time 177032327445 ps
CPU time 344.64 seconds
Started Aug 15 05:16:47 PM PDT 24
Finished Aug 15 05:22:31 PM PDT 24
Peak memory 251264 kb
Host smart-63f88518-c84b-4bbf-93b0-c7440bb819c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836636101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.836636101
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1034151734
Short name T526
Test name
Test status
Simulation time 3496207897 ps
CPU time 23.75 seconds
Started Aug 15 05:16:36 PM PDT 24
Finished Aug 15 05:17:00 PM PDT 24
Peak memory 217624 kb
Host smart-ca5af9f2-90f4-4561-b132-3c082ac79fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034151734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1034151734
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3255019403
Short name T661
Test name
Test status
Simulation time 2184751229 ps
CPU time 9.43 seconds
Started Aug 15 05:16:28 PM PDT 24
Finished Aug 15 05:16:37 PM PDT 24
Peak memory 217216 kb
Host smart-fd6e1029-da7d-437d-bb34-493daa83a612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255019403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3255019403
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2846805877
Short name T620
Test name
Test status
Simulation time 79291061 ps
CPU time 1.57 seconds
Started Aug 15 05:16:31 PM PDT 24
Finished Aug 15 05:16:33 PM PDT 24
Peak memory 217144 kb
Host smart-357038e0-e953-4ad4-a5a0-30d5370b680e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846805877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2846805877
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2252425603
Short name T745
Test name
Test status
Simulation time 88039286 ps
CPU time 0.98 seconds
Started Aug 15 05:16:30 PM PDT 24
Finished Aug 15 05:16:32 PM PDT 24
Peak memory 207788 kb
Host smart-e8e656a8-7b1c-48c6-9dbe-4ea4bfcd8272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252425603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2252425603
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1254312324
Short name T229
Test name
Test status
Simulation time 12254817267 ps
CPU time 11.1 seconds
Started Aug 15 05:16:39 PM PDT 24
Finished Aug 15 05:16:50 PM PDT 24
Peak memory 233592 kb
Host smart-8c9ef483-83ac-4549-9b5d-d7267bf016a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254312324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1254312324
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1418813220
Short name T734
Test name
Test status
Simulation time 39295297 ps
CPU time 0.73 seconds
Started Aug 15 05:16:40 PM PDT 24
Finished Aug 15 05:16:41 PM PDT 24
Peak memory 205680 kb
Host smart-01640cd1-bf37-4e22-bb8f-a335da22cd3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418813220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1418813220
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.198336757
Short name T649
Test name
Test status
Simulation time 84507758 ps
CPU time 3.79 seconds
Started Aug 15 05:16:40 PM PDT 24
Finished Aug 15 05:16:44 PM PDT 24
Peak memory 233540 kb
Host smart-9ef02c43-6e6a-4f2b-a8a5-ea7d87b0a6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198336757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.198336757
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2753219914
Short name T941
Test name
Test status
Simulation time 133642579 ps
CPU time 0.76 seconds
Started Aug 15 05:16:39 PM PDT 24
Finished Aug 15 05:16:40 PM PDT 24
Peak memory 206640 kb
Host smart-d8b8d5e5-a1db-4ca0-b211-c2944cfd36e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753219914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2753219914
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.4018434511
Short name T938
Test name
Test status
Simulation time 60927919878 ps
CPU time 51.06 seconds
Started Aug 15 05:16:40 PM PDT 24
Finished Aug 15 05:17:32 PM PDT 24
Peak memory 241800 kb
Host smart-f0ea1773-1c1f-4ce2-9ce2-3609b464c2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018434511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4018434511
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2612094581
Short name T80
Test name
Test status
Simulation time 1761920239 ps
CPU time 8.47 seconds
Started Aug 15 05:16:45 PM PDT 24
Finished Aug 15 05:16:54 PM PDT 24
Peak memory 218600 kb
Host smart-ee9b1994-2c53-4a90-a022-c39ad1071571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612094581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2612094581
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2938776922
Short name T827
Test name
Test status
Simulation time 3320569961 ps
CPU time 14.42 seconds
Started Aug 15 05:16:40 PM PDT 24
Finished Aug 15 05:16:55 PM PDT 24
Peak memory 225424 kb
Host smart-bdf7c48a-eff3-4134-b324-896c08d292d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938776922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2938776922
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.325657198
Short name T205
Test name
Test status
Simulation time 35898601697 ps
CPU time 180.4 seconds
Started Aug 15 05:16:39 PM PDT 24
Finished Aug 15 05:19:39 PM PDT 24
Peak memory 265476 kb
Host smart-e3063ff1-8f33-4934-b351-26c6f28ca34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325657198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.325657198
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1184158485
Short name T644
Test name
Test status
Simulation time 1463863090 ps
CPU time 17.22 seconds
Started Aug 15 05:16:39 PM PDT 24
Finished Aug 15 05:16:57 PM PDT 24
Peak memory 233584 kb
Host smart-0159cf2a-4e60-4398-832b-d8d2d750f58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184158485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1184158485
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3989490852
Short name T378
Test name
Test status
Simulation time 575118594 ps
CPU time 8.33 seconds
Started Aug 15 05:16:45 PM PDT 24
Finished Aug 15 05:16:53 PM PDT 24
Peak memory 240996 kb
Host smart-ed79ef2a-9d9a-43cf-907d-d8e5e7b0e724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989490852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3989490852
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.843303698
Short name T997
Test name
Test status
Simulation time 2097442214 ps
CPU time 6.85 seconds
Started Aug 15 05:16:41 PM PDT 24
Finished Aug 15 05:16:48 PM PDT 24
Peak memory 233552 kb
Host smart-52c7c06e-a3d0-4e5b-b2a4-332a3fca3c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843303698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.843303698
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1043818347
Short name T877
Test name
Test status
Simulation time 2010964009 ps
CPU time 5.84 seconds
Started Aug 15 05:16:39 PM PDT 24
Finished Aug 15 05:16:45 PM PDT 24
Peak memory 225320 kb
Host smart-3d839783-a476-49f4-878e-78ea3c6b8b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043818347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1043818347
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2590753447
Short name T832
Test name
Test status
Simulation time 370000348 ps
CPU time 4.08 seconds
Started Aug 15 05:16:38 PM PDT 24
Finished Aug 15 05:16:43 PM PDT 24
Peak memory 223588 kb
Host smart-48aa6d47-3d7f-4751-8086-1361c3105930
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2590753447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2590753447
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1904494784
Short name T568
Test name
Test status
Simulation time 14412877977 ps
CPU time 102.91 seconds
Started Aug 15 05:16:38 PM PDT 24
Finished Aug 15 05:18:21 PM PDT 24
Peak memory 247172 kb
Host smart-9a36b478-2576-4e1f-8a29-1475652b0f36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904494784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1904494784
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3950653127
Short name T951
Test name
Test status
Simulation time 7063217921 ps
CPU time 5.83 seconds
Started Aug 15 05:16:39 PM PDT 24
Finished Aug 15 05:16:45 PM PDT 24
Peak memory 217348 kb
Host smart-86fb34fd-8261-440e-98d6-c5470c6c7e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950653127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3950653127
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2767664894
Short name T773
Test name
Test status
Simulation time 3791083281 ps
CPU time 6.08 seconds
Started Aug 15 05:16:38 PM PDT 24
Finished Aug 15 05:16:45 PM PDT 24
Peak memory 217252 kb
Host smart-936bb6c1-a09c-456d-960a-05722cfc672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767664894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2767664894
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2526845082
Short name T898
Test name
Test status
Simulation time 44651686 ps
CPU time 0.75 seconds
Started Aug 15 05:16:38 PM PDT 24
Finished Aug 15 05:16:39 PM PDT 24
Peak memory 206828 kb
Host smart-884e7f7e-2d79-40a0-b6fb-db6d500492de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526845082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2526845082
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.151415863
Short name T682
Test name
Test status
Simulation time 56061736 ps
CPU time 0.85 seconds
Started Aug 15 05:16:41 PM PDT 24
Finished Aug 15 05:16:42 PM PDT 24
Peak memory 206796 kb
Host smart-f4173754-330f-4e43-a7dd-d1b8e02d1e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151415863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.151415863
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2412763682
Short name T737
Test name
Test status
Simulation time 5296542511 ps
CPU time 14.82 seconds
Started Aug 15 05:16:40 PM PDT 24
Finished Aug 15 05:16:55 PM PDT 24
Peak memory 225440 kb
Host smart-09edf675-57c8-4c53-bdd3-2586816eac63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412763682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2412763682
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3391513862
Short name T858
Test name
Test status
Simulation time 28843274 ps
CPU time 0.75 seconds
Started Aug 15 05:16:50 PM PDT 24
Finished Aug 15 05:16:50 PM PDT 24
Peak memory 205640 kb
Host smart-51eb65a4-f286-47b5-a43f-97849d5a710c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391513862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3391513862
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2632301584
Short name T502
Test name
Test status
Simulation time 2134656947 ps
CPU time 19.91 seconds
Started Aug 15 05:16:48 PM PDT 24
Finished Aug 15 05:17:08 PM PDT 24
Peak memory 225332 kb
Host smart-c77557b7-ac61-44b1-ad25-2d6cb913318c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632301584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2632301584
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2610743036
Short name T84
Test name
Test status
Simulation time 16388563 ps
CPU time 0.77 seconds
Started Aug 15 05:16:39 PM PDT 24
Finished Aug 15 05:16:40 PM PDT 24
Peak memory 206696 kb
Host smart-6e010069-a363-4d5f-8cf4-a41e9cbdbb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610743036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2610743036
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1196727690
Short name T758
Test name
Test status
Simulation time 60600101176 ps
CPU time 99.27 seconds
Started Aug 15 05:16:50 PM PDT 24
Finished Aug 15 05:18:29 PM PDT 24
Peak memory 255064 kb
Host smart-26b627c3-26b4-4903-b8af-aa0fc8c505b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196727690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1196727690
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.601013117
Short name T174
Test name
Test status
Simulation time 942188092 ps
CPU time 9.34 seconds
Started Aug 15 05:16:49 PM PDT 24
Finished Aug 15 05:16:58 PM PDT 24
Peak memory 218844 kb
Host smart-e84d2683-e03d-41e6-8adc-eba7d3016dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601013117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.601013117
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4174621297
Short name T244
Test name
Test status
Simulation time 12516061538 ps
CPU time 94.48 seconds
Started Aug 15 05:16:47 PM PDT 24
Finished Aug 15 05:18:22 PM PDT 24
Peak memory 250132 kb
Host smart-495509bd-5e96-4b55-bfa1-e62847d7a6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174621297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4174621297
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.458187069
Short name T50
Test name
Test status
Simulation time 572274329 ps
CPU time 8.47 seconds
Started Aug 15 05:16:47 PM PDT 24
Finished Aug 15 05:16:56 PM PDT 24
Peak memory 239700 kb
Host smart-6fdef377-50f9-4882-99f0-b263a3548719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458187069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.458187069
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2951314377
Short name T281
Test name
Test status
Simulation time 6061643405 ps
CPU time 57.08 seconds
Started Aug 15 05:16:50 PM PDT 24
Finished Aug 15 05:17:47 PM PDT 24
Peak memory 251708 kb
Host smart-3561d01e-8a0f-43e5-a08b-499e3dc33b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951314377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2951314377
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1282358107
Short name T913
Test name
Test status
Simulation time 76935707 ps
CPU time 2.11 seconds
Started Aug 15 05:16:38 PM PDT 24
Finished Aug 15 05:16:41 PM PDT 24
Peak memory 224644 kb
Host smart-0f969016-e2f8-4d4d-a4cb-cdc5da0dd411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282358107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1282358107
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.289236987
Short name T206
Test name
Test status
Simulation time 1013670478 ps
CPU time 14.95 seconds
Started Aug 15 05:16:38 PM PDT 24
Finished Aug 15 05:16:54 PM PDT 24
Peak memory 237284 kb
Host smart-cf5af29b-32c2-454e-ad5b-99b546b3305b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289236987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.289236987
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1452918878
Short name T694
Test name
Test status
Simulation time 8874730566 ps
CPU time 22.53 seconds
Started Aug 15 05:16:46 PM PDT 24
Finished Aug 15 05:17:09 PM PDT 24
Peak memory 225360 kb
Host smart-b94ecc2e-54ed-43e8-b91a-1529fc94c2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452918878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1452918878
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3322084207
Short name T248
Test name
Test status
Simulation time 67992336 ps
CPU time 2.42 seconds
Started Aug 15 05:16:41 PM PDT 24
Finished Aug 15 05:16:44 PM PDT 24
Peak memory 233556 kb
Host smart-339d8bf2-2495-4c4d-9019-a82fea989e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322084207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3322084207
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.141953789
Short name T521
Test name
Test status
Simulation time 1969338401 ps
CPU time 14.89 seconds
Started Aug 15 05:16:46 PM PDT 24
Finished Aug 15 05:17:01 PM PDT 24
Peak memory 222948 kb
Host smart-19ae6a82-b227-4a7b-9e03-029de0e1a408
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=141953789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.141953789
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2644101487
Short name T554
Test name
Test status
Simulation time 421785356 ps
CPU time 3.42 seconds
Started Aug 15 05:16:38 PM PDT 24
Finished Aug 15 05:16:42 PM PDT 24
Peak memory 219544 kb
Host smart-023f60e3-a1f6-4a49-bdcd-230dafa7993a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644101487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2644101487
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3407391882
Short name T860
Test name
Test status
Simulation time 592586993 ps
CPU time 2.81 seconds
Started Aug 15 05:16:39 PM PDT 24
Finished Aug 15 05:16:42 PM PDT 24
Peak memory 217128 kb
Host smart-402a62e5-2924-40ad-a688-5a9133d1ec07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407391882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3407391882
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3458375955
Short name T391
Test name
Test status
Simulation time 47367337 ps
CPU time 1.37 seconds
Started Aug 15 05:16:39 PM PDT 24
Finished Aug 15 05:16:41 PM PDT 24
Peak memory 217056 kb
Host smart-92a6a687-95b8-401f-bca4-d36c2decab84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458375955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3458375955
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.65699359
Short name T336
Test name
Test status
Simulation time 269666253 ps
CPU time 0.86 seconds
Started Aug 15 05:16:42 PM PDT 24
Finished Aug 15 05:16:43 PM PDT 24
Peak memory 206828 kb
Host smart-57b63367-9529-4ac4-8221-3845d5389b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65699359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.65699359
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.4060188694
Short name T383
Test name
Test status
Simulation time 11813286664 ps
CPU time 32.85 seconds
Started Aug 15 05:16:47 PM PDT 24
Finished Aug 15 05:17:20 PM PDT 24
Peak memory 233596 kb
Host smart-2a23cb19-ad6f-439c-bc1b-643c2aa16c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060188694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4060188694
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3469658166
Short name T69
Test name
Test status
Simulation time 36391155 ps
CPU time 0.69 seconds
Started Aug 15 05:16:51 PM PDT 24
Finished Aug 15 05:16:52 PM PDT 24
Peak memory 205680 kb
Host smart-1f94165e-e3b6-4240-bcde-69f171039a5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469658166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3469658166
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2208874130
Short name T508
Test name
Test status
Simulation time 76532107 ps
CPU time 2.66 seconds
Started Aug 15 05:16:47 PM PDT 24
Finished Aug 15 05:16:50 PM PDT 24
Peak memory 233568 kb
Host smart-b8f9627a-456e-48cc-8268-de4b5acfd48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208874130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2208874130
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.746812646
Short name T604
Test name
Test status
Simulation time 38217762 ps
CPU time 0.73 seconds
Started Aug 15 05:16:49 PM PDT 24
Finished Aug 15 05:16:50 PM PDT 24
Peak memory 206684 kb
Host smart-4a1bd61d-eb8e-4733-8927-ce5af7ba429d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746812646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.746812646
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3510989778
Short name T654
Test name
Test status
Simulation time 21987539104 ps
CPU time 85.48 seconds
Started Aug 15 05:16:52 PM PDT 24
Finished Aug 15 05:18:18 PM PDT 24
Peak memory 241856 kb
Host smart-07b68c69-b227-4b02-88dd-14f9b404e8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510989778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3510989778
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.81638856
Short name T462
Test name
Test status
Simulation time 8876556569 ps
CPU time 22.92 seconds
Started Aug 15 05:16:48 PM PDT 24
Finished Aug 15 05:17:11 PM PDT 24
Peak memory 218704 kb
Host smart-637d15b2-eab9-45a5-be4f-62b29d37da5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81638856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.81638856
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2948817162
Short name T637
Test name
Test status
Simulation time 4831303848 ps
CPU time 43.27 seconds
Started Aug 15 05:16:51 PM PDT 24
Finished Aug 15 05:17:34 PM PDT 24
Peak memory 242012 kb
Host smart-3b7fb1aa-1db7-4bf9-a3a6-fa39a631e1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948817162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2948817162
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.258836810
Short name T698
Test name
Test status
Simulation time 698702607 ps
CPU time 4.61 seconds
Started Aug 15 05:16:50 PM PDT 24
Finished Aug 15 05:16:54 PM PDT 24
Peak memory 241736 kb
Host smart-b458f7c6-33c5-47f5-9ac4-b82c0a467c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258836810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.258836810
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2711714999
Short name T99
Test name
Test status
Simulation time 7633502221 ps
CPU time 88.93 seconds
Started Aug 15 05:16:52 PM PDT 24
Finished Aug 15 05:18:21 PM PDT 24
Peak memory 250068 kb
Host smart-25717e30-5495-4886-a0ec-50024e6bc66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711714999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2711714999
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4157654875
Short name T899
Test name
Test status
Simulation time 4418717720 ps
CPU time 12 seconds
Started Aug 15 05:16:51 PM PDT 24
Finished Aug 15 05:17:03 PM PDT 24
Peak memory 220668 kb
Host smart-2347344d-42bb-4342-bb7a-5de7145bca8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157654875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4157654875
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1070862012
Short name T948
Test name
Test status
Simulation time 15021032314 ps
CPU time 37.37 seconds
Started Aug 15 05:16:48 PM PDT 24
Finished Aug 15 05:17:25 PM PDT 24
Peak memory 233560 kb
Host smart-5c47e32f-f208-4467-8e04-5c0b9877a8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070862012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1070862012
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1990779366
Short name T218
Test name
Test status
Simulation time 524721735 ps
CPU time 7.89 seconds
Started Aug 15 05:16:48 PM PDT 24
Finished Aug 15 05:16:56 PM PDT 24
Peak memory 240000 kb
Host smart-d045becc-922b-4795-bc40-c47fd79305c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990779366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1990779366
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1265976763
Short name T234
Test name
Test status
Simulation time 8156530136 ps
CPU time 18.85 seconds
Started Aug 15 05:16:47 PM PDT 24
Finished Aug 15 05:17:06 PM PDT 24
Peak memory 233680 kb
Host smart-6b53fa4d-4cbe-4141-ad15-6f95b1f94372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265976763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1265976763
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2936167519
Short name T422
Test name
Test status
Simulation time 471691967 ps
CPU time 4.77 seconds
Started Aug 15 05:16:48 PM PDT 24
Finished Aug 15 05:16:52 PM PDT 24
Peak memory 219772 kb
Host smart-f14abeaf-1698-42f8-910c-eb9b6ab901a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2936167519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2936167519
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1071933597
Short name T618
Test name
Test status
Simulation time 113837425682 ps
CPU time 70.05 seconds
Started Aug 15 05:16:50 PM PDT 24
Finished Aug 15 05:18:01 PM PDT 24
Peak memory 225556 kb
Host smart-24936170-b243-4a71-b62a-6aafb7dc8ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071933597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1071933597
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.173011367
Short name T635
Test name
Test status
Simulation time 8110306787 ps
CPU time 17.11 seconds
Started Aug 15 05:16:47 PM PDT 24
Finished Aug 15 05:17:04 PM PDT 24
Peak memory 217284 kb
Host smart-4c1c94f2-7371-42e1-a1c7-a44f9e1928ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173011367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.173011367
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3982027121
Short name T321
Test name
Test status
Simulation time 4656548195 ps
CPU time 13.12 seconds
Started Aug 15 05:16:51 PM PDT 24
Finished Aug 15 05:17:04 PM PDT 24
Peak memory 217304 kb
Host smart-ec147e58-bb59-49e2-bedc-6bfd9bf37aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982027121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3982027121
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1513559724
Short name T731
Test name
Test status
Simulation time 15514264 ps
CPU time 0.7 seconds
Started Aug 15 05:16:51 PM PDT 24
Finished Aug 15 05:16:52 PM PDT 24
Peak memory 206436 kb
Host smart-9141e3b6-ab4f-426f-b93d-f46c592ff21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513559724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1513559724
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.188686649
Short name T971
Test name
Test status
Simulation time 40105106 ps
CPU time 0.85 seconds
Started Aug 15 05:16:49 PM PDT 24
Finished Aug 15 05:16:50 PM PDT 24
Peak memory 206828 kb
Host smart-65307fa9-29a6-4664-a70b-4f4744def7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188686649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.188686649
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.388531141
Short name T678
Test name
Test status
Simulation time 28896012985 ps
CPU time 26.58 seconds
Started Aug 15 05:16:52 PM PDT 24
Finished Aug 15 05:17:18 PM PDT 24
Peak memory 233616 kb
Host smart-da8ee5eb-65ca-42d6-bd6c-605c0a91a5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388531141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.388531141
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1458950310
Short name T81
Test name
Test status
Simulation time 14830500 ps
CPU time 0.75 seconds
Started Aug 15 05:16:56 PM PDT 24
Finished Aug 15 05:16:56 PM PDT 24
Peak memory 206620 kb
Host smart-618362d8-0b5d-44e5-981a-d00f2117c40f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458950310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1458950310
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.4231380815
Short name T449
Test name
Test status
Simulation time 41977721 ps
CPU time 2.78 seconds
Started Aug 15 05:16:56 PM PDT 24
Finished Aug 15 05:16:59 PM PDT 24
Peak memory 233508 kb
Host smart-2f86e7d5-8179-424a-acce-315739739802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231380815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.4231380815
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.381653340
Short name T350
Test name
Test status
Simulation time 37005021 ps
CPU time 0.8 seconds
Started Aug 15 05:16:49 PM PDT 24
Finished Aug 15 05:16:50 PM PDT 24
Peak memory 207424 kb
Host smart-9b409c4c-188a-43cf-b85b-7c77d564b23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381653340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.381653340
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3445967854
Short name T290
Test name
Test status
Simulation time 4007074829 ps
CPU time 31.71 seconds
Started Aug 15 05:16:58 PM PDT 24
Finished Aug 15 05:17:30 PM PDT 24
Peak memory 225364 kb
Host smart-ffdd20f1-644f-45a9-89d4-c8413c1b0609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445967854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3445967854
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.376363531
Short name T442
Test name
Test status
Simulation time 202576418648 ps
CPU time 189.05 seconds
Started Aug 15 05:16:55 PM PDT 24
Finished Aug 15 05:20:05 PM PDT 24
Peak memory 251660 kb
Host smart-1520c506-3a4e-41b7-a045-2084de642a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376363531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.376363531
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2473565612
Short name T925
Test name
Test status
Simulation time 22709537152 ps
CPU time 97.38 seconds
Started Aug 15 05:16:58 PM PDT 24
Finished Aug 15 05:18:36 PM PDT 24
Peak memory 257888 kb
Host smart-20f05e88-e83b-4a11-9f88-0b11f5e62e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473565612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2473565612
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.171053461
Short name T333
Test name
Test status
Simulation time 344135769 ps
CPU time 2.97 seconds
Started Aug 15 05:16:57 PM PDT 24
Finished Aug 15 05:17:01 PM PDT 24
Peak memory 225248 kb
Host smart-cbb4df23-1903-4631-a83d-480bdd7fed21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171053461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.171053461
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1661711454
Short name T686
Test name
Test status
Simulation time 2923337736 ps
CPU time 27.98 seconds
Started Aug 15 05:16:59 PM PDT 24
Finished Aug 15 05:17:27 PM PDT 24
Peak memory 238512 kb
Host smart-9078f030-2714-477f-8a21-c6e8ab591e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661711454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1661711454
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3480195168
Short name T897
Test name
Test status
Simulation time 484870584 ps
CPU time 8.35 seconds
Started Aug 15 05:16:51 PM PDT 24
Finished Aug 15 05:17:00 PM PDT 24
Peak memory 233548 kb
Host smart-f82654a2-ff6a-4d8f-96a7-83510590f26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480195168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3480195168
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3887416494
Short name T316
Test name
Test status
Simulation time 103149437 ps
CPU time 2.29 seconds
Started Aug 15 05:16:56 PM PDT 24
Finished Aug 15 05:16:58 PM PDT 24
Peak memory 224792 kb
Host smart-a329f32b-fa99-40dd-94ab-3297ee1b6b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887416494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3887416494
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2429230419
Short name T467
Test name
Test status
Simulation time 519719759 ps
CPU time 3.72 seconds
Started Aug 15 05:16:54 PM PDT 24
Finished Aug 15 05:16:58 PM PDT 24
Peak memory 233536 kb
Host smart-99262d50-6882-4590-96cd-6eeb7a3b5d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429230419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2429230419
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2906311531
Short name T27
Test name
Test status
Simulation time 508143039 ps
CPU time 8.83 seconds
Started Aug 15 05:16:50 PM PDT 24
Finished Aug 15 05:16:59 PM PDT 24
Peak memory 233516 kb
Host smart-7505ffda-c47a-4fe7-a6b9-b7a920d6fa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906311531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2906311531
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1141248117
Short name T158
Test name
Test status
Simulation time 110346826 ps
CPU time 4.09 seconds
Started Aug 15 05:16:56 PM PDT 24
Finished Aug 15 05:17:00 PM PDT 24
Peak memory 223552 kb
Host smart-3a94f686-d896-4ffe-a7a7-4af9dda0e856
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1141248117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1141248117
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3801469556
Short name T16
Test name
Test status
Simulation time 15837548492 ps
CPU time 90.92 seconds
Started Aug 15 05:16:57 PM PDT 24
Finished Aug 15 05:18:28 PM PDT 24
Peak memory 266496 kb
Host smart-76349509-bbcb-4971-980c-4ae95d04d90e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801469556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3801469556
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1393904938
Short name T399
Test name
Test status
Simulation time 38982289 ps
CPU time 0.74 seconds
Started Aug 15 05:16:52 PM PDT 24
Finished Aug 15 05:16:53 PM PDT 24
Peak memory 206528 kb
Host smart-69d343fe-0cdc-404e-b621-c6891fce247d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393904938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1393904938
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1500217433
Short name T652
Test name
Test status
Simulation time 13486420 ps
CPU time 0.73 seconds
Started Aug 15 05:16:52 PM PDT 24
Finished Aug 15 05:16:53 PM PDT 24
Peak memory 206472 kb
Host smart-7fd5fc7e-d073-455c-bbbe-2389e6a511cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500217433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1500217433
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1041524473
Short name T6
Test name
Test status
Simulation time 88494941 ps
CPU time 1.43 seconds
Started Aug 15 05:16:49 PM PDT 24
Finished Aug 15 05:16:50 PM PDT 24
Peak memory 217124 kb
Host smart-58d6dafb-5f9e-4db9-8223-bdf7e0e3b818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041524473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1041524473
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1871891517
Short name T96
Test name
Test status
Simulation time 267394926 ps
CPU time 1.04 seconds
Started Aug 15 05:16:48 PM PDT 24
Finished Aug 15 05:16:49 PM PDT 24
Peak memory 207832 kb
Host smart-fc445cd7-0982-48ff-aa12-cafdaa16a243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871891517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1871891517
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2194904143
Short name T243
Test name
Test status
Simulation time 314886956 ps
CPU time 6.65 seconds
Started Aug 15 05:16:55 PM PDT 24
Finished Aug 15 05:17:02 PM PDT 24
Peak memory 225356 kb
Host smart-06cf226f-f0e9-4968-af73-84c00aadfca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194904143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2194904143
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.677846416
Short name T868
Test name
Test status
Simulation time 73179455 ps
CPU time 0.67 seconds
Started Aug 15 05:16:54 PM PDT 24
Finished Aug 15 05:16:55 PM PDT 24
Peak memory 206236 kb
Host smart-1592cabe-11e8-4d90-8406-17199d3a622b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677846416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.677846416
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1979596002
Short name T800
Test name
Test status
Simulation time 248801460 ps
CPU time 2.94 seconds
Started Aug 15 05:16:58 PM PDT 24
Finished Aug 15 05:17:01 PM PDT 24
Peak memory 225364 kb
Host smart-8505bc9f-9f9f-406a-bb2e-8a554c01b3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979596002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1979596002
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.686337055
Short name T816
Test name
Test status
Simulation time 23831188 ps
CPU time 0.77 seconds
Started Aug 15 05:16:55 PM PDT 24
Finished Aug 15 05:16:56 PM PDT 24
Peak memory 207432 kb
Host smart-38864f75-f1bc-43cb-b6a9-659568bcc291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686337055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.686337055
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2151724703
Short name T621
Test name
Test status
Simulation time 33682346 ps
CPU time 0.77 seconds
Started Aug 15 05:16:55 PM PDT 24
Finished Aug 15 05:16:56 PM PDT 24
Peak memory 216660 kb
Host smart-05efa041-0b70-4cf6-a29e-e993960fcd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151724703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2151724703
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2914540592
Short name T58
Test name
Test status
Simulation time 2011606730 ps
CPU time 49.45 seconds
Started Aug 15 05:16:57 PM PDT 24
Finished Aug 15 05:17:46 PM PDT 24
Peak memory 258252 kb
Host smart-5bcea21f-38ed-4f1d-9708-8a73c31162da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914540592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2914540592
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3437665868
Short name T978
Test name
Test status
Simulation time 36088030405 ps
CPU time 227.01 seconds
Started Aug 15 05:16:57 PM PDT 24
Finished Aug 15 05:20:44 PM PDT 24
Peak memory 257888 kb
Host smart-be204e45-c552-49c3-998d-1eacd2d84fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437665868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3437665868
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3203832575
Short name T295
Test name
Test status
Simulation time 2530170683 ps
CPU time 13.16 seconds
Started Aug 15 05:16:55 PM PDT 24
Finished Aug 15 05:17:09 PM PDT 24
Peak memory 241820 kb
Host smart-c36a725c-acd4-4fe3-b401-c4283a09262d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203832575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3203832575
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1791890286
Short name T196
Test name
Test status
Simulation time 14189829244 ps
CPU time 27.11 seconds
Started Aug 15 05:16:56 PM PDT 24
Finished Aug 15 05:17:23 PM PDT 24
Peak memory 235780 kb
Host smart-262dad27-5c4c-4f13-8b2f-8ba9518bca6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791890286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1791890286
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2196706689
Short name T569
Test name
Test status
Simulation time 328408741 ps
CPU time 3.96 seconds
Started Aug 15 05:16:56 PM PDT 24
Finished Aug 15 05:17:00 PM PDT 24
Peak memory 233584 kb
Host smart-e654ed96-91df-4583-bc87-f724dddc0e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196706689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2196706689
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.834606438
Short name T733
Test name
Test status
Simulation time 4793986612 ps
CPU time 11.14 seconds
Started Aug 15 05:17:01 PM PDT 24
Finished Aug 15 05:17:12 PM PDT 24
Peak memory 225364 kb
Host smart-d6a94841-ffca-43cd-89ce-0790fdc6ea1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834606438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.834606438
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1652010328
Short name T101
Test name
Test status
Simulation time 2154640749 ps
CPU time 10.39 seconds
Started Aug 15 05:16:56 PM PDT 24
Finished Aug 15 05:17:06 PM PDT 24
Peak memory 233700 kb
Host smart-5474b7b1-b916-4eca-8406-449f270d4ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652010328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1652010328
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1677510168
Short name T822
Test name
Test status
Simulation time 3242083539 ps
CPU time 11.84 seconds
Started Aug 15 05:16:55 PM PDT 24
Finished Aug 15 05:17:07 PM PDT 24
Peak memory 233628 kb
Host smart-fd108013-6962-4771-b589-fff6457e2899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677510168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1677510168
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2561167295
Short name T1002
Test name
Test status
Simulation time 525319406 ps
CPU time 4.57 seconds
Started Aug 15 05:16:57 PM PDT 24
Finished Aug 15 05:17:02 PM PDT 24
Peak memory 223928 kb
Host smart-b55ca77a-3482-48cc-85fa-7de7b3bc604f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2561167295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2561167295
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.74361672
Short name T919
Test name
Test status
Simulation time 283705213025 ps
CPU time 233.99 seconds
Started Aug 15 05:16:58 PM PDT 24
Finished Aug 15 05:20:52 PM PDT 24
Peak memory 250196 kb
Host smart-796d195b-ec23-4878-a9ff-ea7cb9056f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74361672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress
_all.74361672
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2567228843
Short name T916
Test name
Test status
Simulation time 4379542963 ps
CPU time 3.66 seconds
Started Aug 15 05:16:57 PM PDT 24
Finished Aug 15 05:17:01 PM PDT 24
Peak memory 220052 kb
Host smart-8d40acc3-a2b5-47f8-8fbe-32bcbaf4e765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567228843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2567228843
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2957933291
Short name T430
Test name
Test status
Simulation time 8397372428 ps
CPU time 15.59 seconds
Started Aug 15 05:16:56 PM PDT 24
Finished Aug 15 05:17:12 PM PDT 24
Peak memory 217196 kb
Host smart-5ebcccae-a2b0-44aa-8ba0-399a5203c671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957933291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2957933291
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1178063638
Short name T403
Test name
Test status
Simulation time 14520020 ps
CPU time 0.68 seconds
Started Aug 15 05:16:56 PM PDT 24
Finished Aug 15 05:16:57 PM PDT 24
Peak memory 206424 kb
Host smart-37ca6765-c57d-4462-ae79-00fd31393328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178063638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1178063638
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.115209413
Short name T813
Test name
Test status
Simulation time 481845031 ps
CPU time 0.89 seconds
Started Aug 15 05:17:01 PM PDT 24
Finished Aug 15 05:17:02 PM PDT 24
Peak memory 206752 kb
Host smart-19cb6542-ea37-4376-b311-6ef9e43b6829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115209413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.115209413
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2903821918
Short name T697
Test name
Test status
Simulation time 5937977399 ps
CPU time 6.55 seconds
Started Aug 15 05:17:01 PM PDT 24
Finished Aug 15 05:17:08 PM PDT 24
Peak memory 233592 kb
Host smart-fe2ef35d-53f4-4f24-863b-0032ebeabc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903821918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2903821918
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.651495958
Short name T486
Test name
Test status
Simulation time 53503422 ps
CPU time 0.72 seconds
Started Aug 15 05:13:36 PM PDT 24
Finished Aug 15 05:13:37 PM PDT 24
Peak memory 206268 kb
Host smart-fb646294-1c98-45f0-90b5-1b9694d7e51b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651495958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.651495958
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3470302848
Short name T263
Test name
Test status
Simulation time 58453798 ps
CPU time 2.15 seconds
Started Aug 15 05:13:38 PM PDT 24
Finished Aug 15 05:13:40 PM PDT 24
Peak memory 225304 kb
Host smart-6b3bb7bc-44af-4c5f-b7f9-8647ae09ca1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470302848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3470302848
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2551289767
Short name T593
Test name
Test status
Simulation time 60350850 ps
CPU time 0.8 seconds
Started Aug 15 05:13:30 PM PDT 24
Finished Aug 15 05:13:31 PM PDT 24
Peak memory 207428 kb
Host smart-aa4f387d-30e5-401b-b96a-f87515b65c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551289767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2551289767
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.654495561
Short name T535
Test name
Test status
Simulation time 40043714 ps
CPU time 0.94 seconds
Started Aug 15 05:13:35 PM PDT 24
Finished Aug 15 05:13:36 PM PDT 24
Peak memory 216824 kb
Host smart-14c41788-27aa-4e65-a5b7-7f269d12746e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654495561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.654495561
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3189198715
Short name T824
Test name
Test status
Simulation time 22173057083 ps
CPU time 256.12 seconds
Started Aug 15 05:13:42 PM PDT 24
Finished Aug 15 05:17:59 PM PDT 24
Peak memory 251196 kb
Host smart-0a48e470-1ebb-40ce-a55e-e3c5b1e3c6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189198715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3189198715
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1058094606
Short name T969
Test name
Test status
Simulation time 8697173922 ps
CPU time 23.37 seconds
Started Aug 15 05:13:37 PM PDT 24
Finished Aug 15 05:14:01 PM PDT 24
Peak memory 225156 kb
Host smart-9f174054-c6b9-431e-af6f-5e9a9fd02a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058094606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1058094606
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3063461597
Short name T807
Test name
Test status
Simulation time 2902977130 ps
CPU time 21.52 seconds
Started Aug 15 05:13:36 PM PDT 24
Finished Aug 15 05:13:58 PM PDT 24
Peak memory 233588 kb
Host smart-8fe528a2-0244-4ce2-9666-456f5d94a4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063461597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3063461597
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1640309104
Short name T662
Test name
Test status
Simulation time 29758927041 ps
CPU time 221.8 seconds
Started Aug 15 05:13:36 PM PDT 24
Finished Aug 15 05:17:18 PM PDT 24
Peak memory 255952 kb
Host smart-fe4c1900-50da-4a45-a985-e89616dde622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640309104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1640309104
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2256724080
Short name T246
Test name
Test status
Simulation time 360007722 ps
CPU time 4.12 seconds
Started Aug 15 05:13:37 PM PDT 24
Finished Aug 15 05:13:41 PM PDT 24
Peak memory 233568 kb
Host smart-e8750952-c8a7-4b6b-996c-6ad45a1f7da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256724080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2256724080
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1808441551
Short name T549
Test name
Test status
Simulation time 21492835393 ps
CPU time 58.45 seconds
Started Aug 15 05:13:35 PM PDT 24
Finished Aug 15 05:14:34 PM PDT 24
Peak memory 225488 kb
Host smart-f9a37532-ea94-4b5a-884c-09321b658b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808441551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1808441551
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2164899471
Short name T705
Test name
Test status
Simulation time 336201445 ps
CPU time 3.28 seconds
Started Aug 15 05:13:37 PM PDT 24
Finished Aug 15 05:13:41 PM PDT 24
Peak memory 225216 kb
Host smart-19412783-72c6-40a1-853e-db63cdfb4c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164899471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2164899471
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.192147335
Short name T744
Test name
Test status
Simulation time 101381504 ps
CPU time 2.32 seconds
Started Aug 15 05:13:30 PM PDT 24
Finished Aug 15 05:13:33 PM PDT 24
Peak memory 224280 kb
Host smart-b40f695f-27d0-4f79-a640-d7fbb23c3ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192147335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.192147335
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1522753045
Short name T380
Test name
Test status
Simulation time 3567835875 ps
CPU time 12.39 seconds
Started Aug 15 05:13:37 PM PDT 24
Finished Aug 15 05:13:50 PM PDT 24
Peak memory 219868 kb
Host smart-475d3917-79ef-4818-acd7-9d14c7c01ba8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1522753045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1522753045
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3724240299
Short name T19
Test name
Test status
Simulation time 108330613336 ps
CPU time 438.15 seconds
Started Aug 15 05:13:36 PM PDT 24
Finished Aug 15 05:20:54 PM PDT 24
Peak memory 265700 kb
Host smart-226c4f85-04ab-46b4-a9b3-3d91b6d49e3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724240299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3724240299
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1050519239
Short name T82
Test name
Test status
Simulation time 1975309188 ps
CPU time 5.05 seconds
Started Aug 15 05:13:29 PM PDT 24
Finished Aug 15 05:13:34 PM PDT 24
Peak memory 217124 kb
Host smart-54e6fc48-7c1b-41ef-9a5b-fe0c19eb2d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050519239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1050519239
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3360039565
Short name T704
Test name
Test status
Simulation time 22313877780 ps
CPU time 17.77 seconds
Started Aug 15 05:13:29 PM PDT 24
Finished Aug 15 05:13:48 PM PDT 24
Peak memory 218312 kb
Host smart-cf6ecfc7-f3c9-4125-bd66-c79a1278e335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360039565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3360039565
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.814907425
Short name T970
Test name
Test status
Simulation time 697423959 ps
CPU time 1.72 seconds
Started Aug 15 05:13:28 PM PDT 24
Finished Aug 15 05:13:29 PM PDT 24
Peak memory 217060 kb
Host smart-61f2393b-27c8-44a4-bfb0-691c65731960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814907425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.814907425
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1853697643
Short name T775
Test name
Test status
Simulation time 230757451 ps
CPU time 0.92 seconds
Started Aug 15 05:13:30 PM PDT 24
Finished Aug 15 05:13:31 PM PDT 24
Peak memory 206768 kb
Host smart-693126bf-b520-45d5-93df-370f8259a12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853697643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1853697643
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.214374806
Short name T1003
Test name
Test status
Simulation time 1320102768 ps
CPU time 3.01 seconds
Started Aug 15 05:13:37 PM PDT 24
Finished Aug 15 05:13:40 PM PDT 24
Peak memory 233532 kb
Host smart-3ecef181-77e0-44c6-9508-9d82bab96802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214374806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.214374806
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3624731513
Short name T681
Test name
Test status
Simulation time 24936092 ps
CPU time 0.73 seconds
Started Aug 15 05:13:36 PM PDT 24
Finished Aug 15 05:13:36 PM PDT 24
Peak memory 205684 kb
Host smart-76b8aaef-9ade-4d22-b5b2-b6112e29b92c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624731513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
624731513
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.4008966332
Short name T992
Test name
Test status
Simulation time 1902422221 ps
CPU time 5.91 seconds
Started Aug 15 05:13:38 PM PDT 24
Finished Aug 15 05:13:44 PM PDT 24
Peak memory 225336 kb
Host smart-62eeebc5-dcd3-4357-b8c5-e5b605d7e3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008966332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.4008966332
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2387106813
Short name T444
Test name
Test status
Simulation time 33193037 ps
CPU time 0.83 seconds
Started Aug 15 05:13:35 PM PDT 24
Finished Aug 15 05:13:36 PM PDT 24
Peak memory 207352 kb
Host smart-241884cc-08dc-4e9e-b099-2905c2c36973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387106813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2387106813
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1545892994
Short name T209
Test name
Test status
Simulation time 41523014232 ps
CPU time 292.47 seconds
Started Aug 15 05:13:37 PM PDT 24
Finished Aug 15 05:18:30 PM PDT 24
Peak memory 250124 kb
Host smart-1a2e1ec5-c1b4-46db-853f-e3ceba9a23fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545892994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1545892994
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3708260379
Short name T854
Test name
Test status
Simulation time 2200689558 ps
CPU time 26.97 seconds
Started Aug 15 05:13:40 PM PDT 24
Finished Aug 15 05:14:07 PM PDT 24
Peak memory 257620 kb
Host smart-e5e0cb35-e930-431e-835b-bc0cd4564134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708260379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3708260379
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.872049007
Short name T247
Test name
Test status
Simulation time 13367843161 ps
CPU time 43.1 seconds
Started Aug 15 05:13:37 PM PDT 24
Finished Aug 15 05:14:20 PM PDT 24
Peak memory 252744 kb
Host smart-67daa9d9-e114-4f11-832a-284138f4667b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872049007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
872049007
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1196098377
Short name T771
Test name
Test status
Simulation time 101420271 ps
CPU time 4.35 seconds
Started Aug 15 05:13:42 PM PDT 24
Finished Aug 15 05:13:47 PM PDT 24
Peak memory 225360 kb
Host smart-88d51fda-d851-417f-ab21-6493d7a3b074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196098377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1196098377
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2885429170
Short name T400
Test name
Test status
Simulation time 161276692 ps
CPU time 4.77 seconds
Started Aug 15 05:13:36 PM PDT 24
Finished Aug 15 05:13:41 PM PDT 24
Peak memory 233560 kb
Host smart-297c08c4-6212-41b5-94a9-203a982c9f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885429170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2885429170
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1656772436
Short name T958
Test name
Test status
Simulation time 2032971846 ps
CPU time 8.74 seconds
Started Aug 15 05:13:36 PM PDT 24
Finished Aug 15 05:13:45 PM PDT 24
Peak memory 233348 kb
Host smart-69078bed-80ac-4740-a8cd-04e6da416532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656772436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1656772436
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2383544764
Short name T674
Test name
Test status
Simulation time 320984875 ps
CPU time 2.63 seconds
Started Aug 15 05:13:35 PM PDT 24
Finished Aug 15 05:13:38 PM PDT 24
Peak memory 233224 kb
Host smart-d11371c7-0550-482d-bb14-49d5e6c6da36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383544764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2383544764
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3145785081
Short name T600
Test name
Test status
Simulation time 3213701142 ps
CPU time 15.35 seconds
Started Aug 15 05:13:50 PM PDT 24
Finished Aug 15 05:14:05 PM PDT 24
Peak memory 239176 kb
Host smart-58fc37b6-1734-4535-8f2a-638c13c5b2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145785081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3145785081
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.4046715907
Short name T563
Test name
Test status
Simulation time 121157369 ps
CPU time 4.21 seconds
Started Aug 15 05:13:40 PM PDT 24
Finished Aug 15 05:13:45 PM PDT 24
Peak memory 223904 kb
Host smart-25734efe-5158-4f39-901c-30e5426ba202
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4046715907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.4046715907
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1251920868
Short name T171
Test name
Test status
Simulation time 46946396 ps
CPU time 0.97 seconds
Started Aug 15 05:13:36 PM PDT 24
Finished Aug 15 05:13:37 PM PDT 24
Peak memory 208340 kb
Host smart-a62fa00f-91e5-4a64-bf89-9442fa95b463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251920868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1251920868
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.391361204
Short name T440
Test name
Test status
Simulation time 1240792581 ps
CPU time 17.63 seconds
Started Aug 15 05:13:36 PM PDT 24
Finished Aug 15 05:13:53 PM PDT 24
Peak memory 217212 kb
Host smart-f70eef38-33e0-47cd-8442-e74a9f61c91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391361204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.391361204
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2944846162
Short name T803
Test name
Test status
Simulation time 891349864 ps
CPU time 7.45 seconds
Started Aug 15 05:13:38 PM PDT 24
Finished Aug 15 05:13:45 PM PDT 24
Peak memory 217024 kb
Host smart-17c444c7-d9f9-4e61-9f9a-6eb772fd4054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944846162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2944846162
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2069425771
Short name T693
Test name
Test status
Simulation time 214910452 ps
CPU time 1.71 seconds
Started Aug 15 05:13:43 PM PDT 24
Finished Aug 15 05:13:45 PM PDT 24
Peak memory 217180 kb
Host smart-5cf66cc9-3f63-4871-a9fd-67e13c134800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069425771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2069425771
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.698810775
Short name T973
Test name
Test status
Simulation time 216792199 ps
CPU time 0.97 seconds
Started Aug 15 05:13:37 PM PDT 24
Finished Aug 15 05:13:38 PM PDT 24
Peak memory 206824 kb
Host smart-ec2ac38a-1312-40c9-9fbd-ffacc6a13fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698810775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.698810775
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1216438025
Short name T567
Test name
Test status
Simulation time 713657699 ps
CPU time 4.89 seconds
Started Aug 15 05:13:38 PM PDT 24
Finished Aug 15 05:13:43 PM PDT 24
Peak memory 233464 kb
Host smart-6066be66-94f4-4efe-bc53-17bc73615b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216438025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1216438025
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2881601253
Short name T701
Test name
Test status
Simulation time 24963389 ps
CPU time 0.71 seconds
Started Aug 15 05:13:44 PM PDT 24
Finished Aug 15 05:13:45 PM PDT 24
Peak memory 206240 kb
Host smart-0e3d0819-28a9-4d90-9707-a354f22fbc57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881601253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
881601253
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1221689213
Short name T487
Test name
Test status
Simulation time 33129677 ps
CPU time 2.25 seconds
Started Aug 15 05:13:45 PM PDT 24
Finished Aug 15 05:13:47 PM PDT 24
Peak memory 225344 kb
Host smart-0de91f21-e893-435f-9a1b-e5c519d6faf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221689213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1221689213
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1596472538
Short name T348
Test name
Test status
Simulation time 15994465 ps
CPU time 0.73 seconds
Started Aug 15 05:13:40 PM PDT 24
Finished Aug 15 05:13:41 PM PDT 24
Peak memory 206380 kb
Host smart-f087b825-9edb-49d8-92a2-94fdf974fe75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596472538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1596472538
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.593086490
Short name T23
Test name
Test status
Simulation time 24515652399 ps
CPU time 120.74 seconds
Started Aug 15 05:13:43 PM PDT 24
Finished Aug 15 05:15:44 PM PDT 24
Peak memory 263596 kb
Host smart-e26616dd-8eec-45ea-88a3-b8382aab3c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593086490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.593086490
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1684671521
Short name T59
Test name
Test status
Simulation time 11339310614 ps
CPU time 106.79 seconds
Started Aug 15 05:13:43 PM PDT 24
Finished Aug 15 05:15:30 PM PDT 24
Peak memory 263368 kb
Host smart-a18ca17f-8bd7-4178-bdc3-dde1c41080c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684671521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1684671521
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1683098176
Short name T962
Test name
Test status
Simulation time 31285100342 ps
CPU time 310.27 seconds
Started Aug 15 05:13:45 PM PDT 24
Finished Aug 15 05:18:55 PM PDT 24
Peak memory 250200 kb
Host smart-dd6cbbf8-724c-4965-b1f2-15d2c0a2e543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683098176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1683098176
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.116325772
Short name T142
Test name
Test status
Simulation time 245440249 ps
CPU time 5.65 seconds
Started Aug 15 05:13:45 PM PDT 24
Finished Aug 15 05:13:51 PM PDT 24
Peak memory 251192 kb
Host smart-26e07350-b9ae-49b8-9d51-683e75b02855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116325772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.116325772
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1433570312
Short name T834
Test name
Test status
Simulation time 111111382684 ps
CPU time 192.23 seconds
Started Aug 15 05:13:46 PM PDT 24
Finished Aug 15 05:16:58 PM PDT 24
Peak memory 250068 kb
Host smart-76a44dac-a2dc-4ca7-b917-c0c51d5f3b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433570312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1433570312
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3045731849
Short name T52
Test name
Test status
Simulation time 30522482060 ps
CPU time 19.28 seconds
Started Aug 15 05:13:43 PM PDT 24
Finished Aug 15 05:14:03 PM PDT 24
Peak memory 225380 kb
Host smart-a7801d3a-4f65-4218-b0d9-e2cf49d2db54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045731849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3045731849
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3803812105
Short name T83
Test name
Test status
Simulation time 24004633909 ps
CPU time 114.1 seconds
Started Aug 15 05:13:46 PM PDT 24
Finished Aug 15 05:15:40 PM PDT 24
Peak memory 233636 kb
Host smart-eb05f3e9-e589-450c-8146-61b9e9858d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803812105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3803812105
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4098661311
Short name T994
Test name
Test status
Simulation time 56679222 ps
CPU time 2.65 seconds
Started Aug 15 05:13:45 PM PDT 24
Finished Aug 15 05:13:48 PM PDT 24
Peak memory 233564 kb
Host smart-293279fb-913a-4b9d-8e72-19166f6addc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098661311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4098661311
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3605791634
Short name T424
Test name
Test status
Simulation time 1009767933 ps
CPU time 4.22 seconds
Started Aug 15 05:13:44 PM PDT 24
Finished Aug 15 05:13:49 PM PDT 24
Peak memory 225328 kb
Host smart-1c68243f-6e7f-4675-92dc-cab9f179489f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605791634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3605791634
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4053566921
Short name T453
Test name
Test status
Simulation time 6101941872 ps
CPU time 11.16 seconds
Started Aug 15 05:13:45 PM PDT 24
Finished Aug 15 05:13:57 PM PDT 24
Peak memory 223000 kb
Host smart-33b950d1-c42b-4fa8-aec3-428a0ad83e60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4053566921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4053566921
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3644055045
Short name T1011
Test name
Test status
Simulation time 257683766836 ps
CPU time 1088.49 seconds
Started Aug 15 05:13:47 PM PDT 24
Finished Aug 15 05:31:56 PM PDT 24
Peak memory 283328 kb
Host smart-c2e1cf1d-ade5-461f-8c7b-76057268ed71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644055045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3644055045
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1228046425
Short name T550
Test name
Test status
Simulation time 7066169296 ps
CPU time 39.42 seconds
Started Aug 15 05:13:44 PM PDT 24
Finished Aug 15 05:14:23 PM PDT 24
Peak memory 217240 kb
Host smart-5b75d9a1-1b9c-4ca6-a426-9fe55822ad4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228046425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1228046425
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2985792974
Short name T921
Test name
Test status
Simulation time 6094172591 ps
CPU time 8.87 seconds
Started Aug 15 05:13:47 PM PDT 24
Finished Aug 15 05:13:55 PM PDT 24
Peak memory 217240 kb
Host smart-339ac399-9f04-4b52-acb0-021dad8e1ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985792974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2985792974
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1694618111
Short name T638
Test name
Test status
Simulation time 21017383 ps
CPU time 1.3 seconds
Started Aug 15 05:13:45 PM PDT 24
Finished Aug 15 05:13:47 PM PDT 24
Peak memory 217060 kb
Host smart-3859e789-2e50-4686-9ac9-eb02ccc60a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694618111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1694618111
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4076524978
Short name T835
Test name
Test status
Simulation time 98409065 ps
CPU time 0.99 seconds
Started Aug 15 05:13:44 PM PDT 24
Finished Aug 15 05:13:45 PM PDT 24
Peak memory 207784 kb
Host smart-13b99ee4-2b9e-4c83-9e55-f5796c99ac34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076524978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4076524978
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.4280811216
Short name T173
Test name
Test status
Simulation time 2372794123 ps
CPU time 8.77 seconds
Started Aug 15 05:13:46 PM PDT 24
Finished Aug 15 05:13:54 PM PDT 24
Peak memory 225460 kb
Host smart-b62c17d1-5a04-4968-bdaa-57ddcfb478a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280811216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.4280811216
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.724764870
Short name T981
Test name
Test status
Simulation time 32374966 ps
CPU time 0.68 seconds
Started Aug 15 05:13:52 PM PDT 24
Finished Aug 15 05:13:53 PM PDT 24
Peak memory 205620 kb
Host smart-e33cbb59-27e4-4068-9700-5fc772f9d3d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724764870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.724764870
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3767233924
Short name T493
Test name
Test status
Simulation time 3800420053 ps
CPU time 8.71 seconds
Started Aug 15 05:13:53 PM PDT 24
Finished Aug 15 05:14:02 PM PDT 24
Peak memory 233716 kb
Host smart-e086d87c-68dc-4c87-8af9-d7c12e855d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767233924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3767233924
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.4124153316
Short name T364
Test name
Test status
Simulation time 20396220 ps
CPU time 0.77 seconds
Started Aug 15 05:13:41 PM PDT 24
Finished Aug 15 05:13:42 PM PDT 24
Peak memory 207372 kb
Host smart-cd46d77f-8adf-4bc4-b273-0cb371ddf595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124153316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.4124153316
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2877798696
Short name T972
Test name
Test status
Simulation time 9371681482 ps
CPU time 62.7 seconds
Started Aug 15 05:13:54 PM PDT 24
Finished Aug 15 05:14:57 PM PDT 24
Peak memory 237372 kb
Host smart-37b3d58d-4e5c-4919-a1b3-3728eccebc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877798696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2877798696
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1938618582
Short name T900
Test name
Test status
Simulation time 42284330357 ps
CPU time 201.98 seconds
Started Aug 15 05:13:53 PM PDT 24
Finished Aug 15 05:17:15 PM PDT 24
Peak memory 263152 kb
Host smart-fbea12db-402b-4445-87f9-a06096ecf05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938618582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1938618582
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.851728627
Short name T240
Test name
Test status
Simulation time 22243135599 ps
CPU time 88.78 seconds
Started Aug 15 05:13:53 PM PDT 24
Finished Aug 15 05:15:22 PM PDT 24
Peak memory 252944 kb
Host smart-07f83b39-e072-4c83-8ede-943d5c384782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851728627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
851728627
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.306690923
Short name T482
Test name
Test status
Simulation time 1715293558 ps
CPU time 7.59 seconds
Started Aug 15 05:13:53 PM PDT 24
Finished Aug 15 05:14:00 PM PDT 24
Peak memory 225192 kb
Host smart-6666940d-0319-4e32-a154-9a7ecb3035ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306690923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.306690923
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2258398986
Short name T729
Test name
Test status
Simulation time 43914509053 ps
CPU time 204.14 seconds
Started Aug 15 05:13:54 PM PDT 24
Finished Aug 15 05:17:19 PM PDT 24
Peak memory 249968 kb
Host smart-587df036-ee22-410a-9854-c10fba6d7a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258398986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2258398986
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.372981981
Short name T393
Test name
Test status
Simulation time 500539628 ps
CPU time 3.77 seconds
Started Aug 15 05:13:46 PM PDT 24
Finished Aug 15 05:13:50 PM PDT 24
Peak memory 233576 kb
Host smart-f0ca73d9-6823-4590-87d0-9c11aa33edaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372981981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.372981981
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2901583736
Short name T216
Test name
Test status
Simulation time 3633474933 ps
CPU time 6.08 seconds
Started Aug 15 05:13:50 PM PDT 24
Finished Aug 15 05:13:57 PM PDT 24
Peak memory 238848 kb
Host smart-11452568-95fd-49f4-a4fa-8ab802f558a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901583736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2901583736
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1583396082
Short name T492
Test name
Test status
Simulation time 30143982 ps
CPU time 2.63 seconds
Started Aug 15 05:13:45 PM PDT 24
Finished Aug 15 05:13:48 PM PDT 24
Peak memory 233224 kb
Host smart-ffc07978-4202-4f8a-a932-539713359485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583396082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1583396082
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4165562912
Short name T975
Test name
Test status
Simulation time 4090085233 ps
CPU time 12.5 seconds
Started Aug 15 05:13:44 PM PDT 24
Finished Aug 15 05:13:57 PM PDT 24
Peak memory 233708 kb
Host smart-8f18d122-ddb0-41f2-8508-19d59a82171d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165562912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4165562912
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.542687716
Short name T926
Test name
Test status
Simulation time 172321585 ps
CPU time 3.55 seconds
Started Aug 15 05:13:53 PM PDT 24
Finished Aug 15 05:13:57 PM PDT 24
Peak memory 223972 kb
Host smart-386c4374-7d94-4591-a333-b002650f274b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=542687716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.542687716
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2349758099
Short name T700
Test name
Test status
Simulation time 11505237131 ps
CPU time 112.23 seconds
Started Aug 15 05:13:54 PM PDT 24
Finished Aug 15 05:15:46 PM PDT 24
Peak memory 239504 kb
Host smart-24ad9abf-5d2c-46f6-a616-33187e8bd505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349758099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2349758099
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2731877908
Short name T683
Test name
Test status
Simulation time 4941252510 ps
CPU time 15.08 seconds
Started Aug 15 05:13:45 PM PDT 24
Finished Aug 15 05:14:01 PM PDT 24
Peak memory 217440 kb
Host smart-fea8e4e4-e88e-4ea0-8a20-7027b6405160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731877908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2731877908
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3476157845
Short name T887
Test name
Test status
Simulation time 592232200 ps
CPU time 5.85 seconds
Started Aug 15 05:13:47 PM PDT 24
Finished Aug 15 05:13:53 PM PDT 24
Peak memory 217180 kb
Host smart-c58ffa19-0ed1-4c4e-a25c-d2973294fc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476157845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3476157845
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1863469531
Short name T929
Test name
Test status
Simulation time 121517172 ps
CPU time 0.91 seconds
Started Aug 15 05:13:47 PM PDT 24
Finished Aug 15 05:13:48 PM PDT 24
Peak memory 207308 kb
Host smart-13007f77-98bb-4407-a175-332baef1666c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863469531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1863469531
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2841701438
Short name T560
Test name
Test status
Simulation time 139899656 ps
CPU time 0.81 seconds
Started Aug 15 05:13:45 PM PDT 24
Finished Aug 15 05:13:46 PM PDT 24
Peak memory 206788 kb
Host smart-69388c21-ebf8-49e2-bdb4-bde1d8383232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841701438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2841701438
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3345338772
Short name T5
Test name
Test status
Simulation time 49954362212 ps
CPU time 35.37 seconds
Started Aug 15 05:13:55 PM PDT 24
Finished Aug 15 05:14:30 PM PDT 24
Peak memory 239388 kb
Host smart-7823e3ac-239c-4338-a081-e5c5a192b7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345338772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3345338772
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.409268054
Short name T339
Test name
Test status
Simulation time 13360965 ps
CPU time 0.73 seconds
Started Aug 15 05:13:54 PM PDT 24
Finished Aug 15 05:13:55 PM PDT 24
Peak memory 205680 kb
Host smart-36c46859-7438-4f57-a1d5-42e965ed90dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409268054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.409268054
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.4024012184
Short name T915
Test name
Test status
Simulation time 1692009185 ps
CPU time 21.01 seconds
Started Aug 15 05:13:55 PM PDT 24
Finished Aug 15 05:14:16 PM PDT 24
Peak memory 233492 kb
Host smart-af83789c-0465-4dc0-a3e5-789cb37895e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024012184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.4024012184
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2268457601
Short name T942
Test name
Test status
Simulation time 83377151 ps
CPU time 0.8 seconds
Started Aug 15 05:13:54 PM PDT 24
Finished Aug 15 05:13:55 PM PDT 24
Peak memory 207440 kb
Host smart-e93ffe13-c867-4dd6-8630-2e151cd12afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268457601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2268457601
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3884156293
Short name T885
Test name
Test status
Simulation time 97205747389 ps
CPU time 191.68 seconds
Started Aug 15 05:13:52 PM PDT 24
Finished Aug 15 05:17:04 PM PDT 24
Peak memory 250076 kb
Host smart-d106ff16-0987-43bc-b418-fa7b7b727f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884156293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3884156293
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3432028578
Short name T979
Test name
Test status
Simulation time 491827383 ps
CPU time 7.11 seconds
Started Aug 15 05:13:54 PM PDT 24
Finished Aug 15 05:14:02 PM PDT 24
Peak memory 225368 kb
Host smart-135e8442-70df-49e9-b43c-c079a6e0abc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432028578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3432028578
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.642279826
Short name T334
Test name
Test status
Simulation time 633395490 ps
CPU time 5.3 seconds
Started Aug 15 05:13:54 PM PDT 24
Finished Aug 15 05:13:59 PM PDT 24
Peak memory 233556 kb
Host smart-82a1acb7-8379-47b3-8858-c431894fd537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642279826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.642279826
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1426369740
Short name T484
Test name
Test status
Simulation time 17956066082 ps
CPU time 114.34 seconds
Started Aug 15 05:13:54 PM PDT 24
Finished Aug 15 05:15:49 PM PDT 24
Peak memory 250072 kb
Host smart-aeb967df-47cb-481e-aa79-c7c2855a4930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426369740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1426369740
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.94067812
Short name T609
Test name
Test status
Simulation time 10836676503 ps
CPU time 27.94 seconds
Started Aug 15 05:13:54 PM PDT 24
Finished Aug 15 05:14:22 PM PDT 24
Peak memory 233708 kb
Host smart-f75c160d-9459-4e94-8b68-a2fc338836a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94067812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.94067812
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.86464393
Short name T223
Test name
Test status
Simulation time 24030961307 ps
CPU time 44.77 seconds
Started Aug 15 05:13:53 PM PDT 24
Finished Aug 15 05:14:38 PM PDT 24
Peak memory 225424 kb
Host smart-d1d2e5d0-74b4-475a-93c2-d9a24325e62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86464393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.86464393
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1226104580
Short name T614
Test name
Test status
Simulation time 630415190 ps
CPU time 3.74 seconds
Started Aug 15 05:13:54 PM PDT 24
Finished Aug 15 05:13:57 PM PDT 24
Peak memory 225260 kb
Host smart-41c2e4fb-8f61-4490-9243-abb93c5cc2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226104580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1226104580
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1089258285
Short name T802
Test name
Test status
Simulation time 911216748 ps
CPU time 3.79 seconds
Started Aug 15 05:13:55 PM PDT 24
Finished Aug 15 05:13:59 PM PDT 24
Peak memory 225292 kb
Host smart-f4154c04-60ee-4969-8f75-21b95b9eb7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089258285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1089258285
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2015363696
Short name T845
Test name
Test status
Simulation time 3799714586 ps
CPU time 11.32 seconds
Started Aug 15 05:13:55 PM PDT 24
Finished Aug 15 05:14:07 PM PDT 24
Peak memory 223996 kb
Host smart-3bd993f9-ce92-42eb-a605-5bcf55e21e3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2015363696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2015363696
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2422301829
Short name T271
Test name
Test status
Simulation time 19444604931 ps
CPU time 130.43 seconds
Started Aug 15 05:13:54 PM PDT 24
Finished Aug 15 05:16:05 PM PDT 24
Peak memory 274048 kb
Host smart-04187728-94a9-43c1-ac60-f2d3f8daa0d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422301829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2422301829
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2545297267
Short name T64
Test name
Test status
Simulation time 615892665 ps
CPU time 2.39 seconds
Started Aug 15 05:13:52 PM PDT 24
Finished Aug 15 05:13:55 PM PDT 24
Peak memory 217544 kb
Host smart-f018e8a0-13ea-48f4-91c9-b04622369dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545297267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2545297267
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3306325495
Short name T371
Test name
Test status
Simulation time 2704353501 ps
CPU time 4.61 seconds
Started Aug 15 05:13:55 PM PDT 24
Finished Aug 15 05:14:00 PM PDT 24
Peak memory 217340 kb
Host smart-3e722cf2-bba0-477b-8524-5c4b92e6f024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306325495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3306325495
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3128961226
Short name T310
Test name
Test status
Simulation time 1158661492 ps
CPU time 4.13 seconds
Started Aug 15 05:13:53 PM PDT 24
Finished Aug 15 05:13:57 PM PDT 24
Peak memory 217200 kb
Host smart-5e06c253-912d-4e7c-873d-bdf9d201c27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128961226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3128961226
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1029289576
Short name T469
Test name
Test status
Simulation time 48358475 ps
CPU time 0.69 seconds
Started Aug 15 05:13:55 PM PDT 24
Finished Aug 15 05:13:56 PM PDT 24
Peak memory 206444 kb
Host smart-09df1314-4359-4775-84ff-100fe8802c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029289576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1029289576
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2549968153
Short name T249
Test name
Test status
Simulation time 968670260 ps
CPU time 4.15 seconds
Started Aug 15 05:13:55 PM PDT 24
Finished Aug 15 05:13:59 PM PDT 24
Peak memory 233492 kb
Host smart-c0f0176d-32e0-4472-9355-2b5a3201dc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549968153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2549968153
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%