Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2597308	1			T1	985		T2	1		T3	1
all_values[1]	2597308	1			T1	985		T2	1		T3	1
all_values[2]	2597308	1			T1	985		T2	1		T3	1
all_values[3]	2597308	1			T1	985		T2	1		T3	1
all_values[4]	2597308	1			T1	985		T2	1		T3	1
all_values[5]	2597308	1			T1	985		T2	1		T3	1
all_values[6]	2597308	1			T1	985		T2	1		T3	1
all_values[7]	2597308	1			T1	985		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20358546

1

T1

7880

T2

8

T3

8

auto[1]

419918

1

T17

55

T18

131

T19

40

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20754154

1

T1

7880

T2

8

T3

8

auto[1]

24310

1

T12

494

T30

249

T17

25

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2542171	1			T1	985		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	10952	1			T12	281		T30	105		T17	2
all_values[0]	auto[1]	auto[0]	43482	1			T17	6		T18	14		T19	6
all_values[0]	auto[1]	auto[1]	703	1			T17	2		T18	6		T20	56
all_values[1]	auto[0]	auto[0]	2522018	1			T1	985		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	7268	1			T12	151		T30	87		T26	80
all_values[1]	auto[1]	auto[0]	67459	1			T17	3		T18	12		T19	5
all_values[1]	auto[1]	auto[1]	563	1			T17	2		T18	7		T19	2
all_values[2]	auto[0]	auto[0]	2495222	1			T1	985		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2738	1			T12	62		T30	57		T17	2
all_values[2]	auto[1]	auto[0]	99068	1			T17	5		T18	13		T19	7
all_values[2]	auto[1]	auto[1]	280	1			T17	3		T18	5		T19	1
all_values[3]	auto[0]	auto[0]	2544007	1			T1	985		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	202	1			T17	2		T18	5		T19	1
all_values[3]	auto[1]	auto[0]	52903	1			T17	4		T18	5		T19	1
all_values[3]	auto[1]	auto[1]	196	1			T17	3		T18	3		T20	3
all_values[4]	auto[0]	auto[0]	2584990	1			T1	985		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	202	1			T17	2		T18	10		T19	3
all_values[4]	auto[1]	auto[0]	11946	1			T17	2		T18	7		T19	1
all_values[4]	auto[1]	auto[1]	170	1			T18	5		T19	1		T21	6
all_values[5]	auto[0]	auto[0]	2509302	1			T1	985		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	152	1			T18	8		T19	2		T21	6
all_values[5]	auto[1]	auto[0]	87694	1			T17	9		T18	12		T19	2
all_values[5]	auto[1]	auto[1]	160	1			T17	1		T18	4		T19	1
all_values[6]	auto[0]	auto[0]	2552308	1			T1	985		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	188	1			T17	1		T18	2		T19	2
all_values[6]	auto[1]	auto[0]	44629	1			T17	6		T18	11		T19	4
all_values[6]	auto[1]	auto[1]	183	1			T17	3		T18	5		T19	3
all_values[7]	auto[0]	auto[0]	2586651	1			T1	985		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	175	1			T17	1		T18	4		T20	2
all_values[7]	auto[1]	auto[0]	10304	1			T17	5		T18	14		T19	5
all_values[7]	auto[1]	auto[1]	178	1			T17	1		T18	8		T19	1