Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33843	1			T3	6		T5	6		T6	6
auto[SpiFlashAddrCfg]	7555	1			T3	2		T7	4		T12	43
auto[SpiFlashAddr3b]	8736	1			T6	4		T7	2		T12	46
auto[SpiFlashAddr4b]	7356	1			T3	12		T5	2		T6	14

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33463

1

T5

8

T6

24

T7

6

auto[1]

24027

1

T3

20

T12

102

T16

166

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31044

1

T3

2

T5

4

T6

12

auto[1]

26446

1

T3

18

T5

4

T6

12

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38481	1			T3	16		T5	6		T6	10
values[1]	1044	1			T12	7		T15	2		T16	4
values[2]	1351	1			T3	4		T6	2		T7	2
values[3]	1401	1			T12	13		T16	5		T30	9
values[4]	1506	1			T12	3		T14	2		T16	3
values[5]	1359	1			T12	9		T16	4		T30	3
values[6]	1511	1			T12	15		T16	3		T30	5
values[7]	1370	1			T6	4		T12	5		T16	8
values[8]	9467	1			T5	2		T6	8		T7	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31094

1

T3

20

T5

8

T6

24

auto[1]

26396

1

T12

283

T13

1

T24

180

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54225

1

T3

10

T5

8

T6

20

write

3265

1

T3

10

T6

4

T12

17

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18412

1

T6

16

T7

6

T12

103

valids[0x1]

39078

1

T3

20

T5

8

T6

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1537	1			T5	4		T12	10		T16	7
internal_process_ops[0x5a]	1516	1			T12	10		T16	8		T30	2
internal_process_ops[0x05]	20489	1			T5	2		T6	2		T12	54
internal_process_ops[0x35]	1549	1			T3	4		T12	12		T16	7
internal_process_ops[0x15]	1535	1			T3	2		T12	14		T16	7
internal_process_ops[0x03]	1077	1			T3	4		T5	2		T6	2
internal_process_ops[0x0b]	1088	1			T12	6		T16	9		T30	7
internal_process_ops[0x3b]	1089	1			T12	2		T14	2		T16	1
internal_process_ops[0x6b]	980	1			T12	2		T13	1		T16	8
internal_process_ops[0xbb]	1014	1			T12	3		T16	5		T30	5
internal_process_ops[0xeb]	1098	1			T6	2		T12	4		T16	9

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55892

1

T3

10

T5

8

T6

24

auto[1]

1598

1

T3

10

T12

6

T16

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55233

1

T3

20

T5

8

T6

24

auto[1]

2257

1

T12

17

T16

15

T30

13

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11126

1

T5

6

T6

6

T16

146

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6024

1

T3

6

T16

113

T30

53

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1986

1

T7

4

T14

2

T16

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1858

1

T16

13

T30

17

T49

13

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2425

1

T6

4

T7

2

T15

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2128

1

T16

15

T30

21

T49

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2010

1

T5

2

T6

10

T14

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1788

1

T3

4

T16

23

T30

16

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

133

1

T16

2

T154

2

T50

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

102

1

T30

1

T49

1

T41

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

84

1

T54

1

T158

1

T159

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

123

1

T49

1

T51

2

T52

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

140

1

T16

3

T30

2

T49

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

90

1

T30

2

T50

3

T53

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

82

1

T16

1

T50

1

T99

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

121

1

T3

2

T16

1

T49

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

114

1

T50

2

T99

1

T160

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

109

1

T16

2

T41

1

T50

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

96

1

T50

4

T53

3

T87

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

113

1

T30

1

T41

2

T50

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

157

1

T6

4

T16

2

T23

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

89

1

T30

1

T50

1

T54

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

78

1

T30

3

T50

1

T87

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

118

1

T3

8

T30

2

T49

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9555

1

T12

111

T24

50

T26

64

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6336

1

T12

39

T24

20

T26

34

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1488

1

T12

16

T13

1

T24

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1361

1

T12

22

T24

17

T26

13

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1731

1

T12

22

T24

23

T26

20

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1661

1

T12

20

T24

23

T26

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1443

1

T12

21

T24

11

T26

21

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1305

1

T12

15

T24

17

T26

11

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

99

1

T12

1

T37

2

T44

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

84

1

T24

1

T86

8

T161

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

82

1

T24

1

T26

2

T37

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

95

1

T24

3

T26

2

T18

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

106

1

T26

1

T37

3

T44

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

112

1

T12

3

T24

1

T26

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

123

1

T12

2

T37

4

T44

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

88

1

T37

1

T18

5

T44

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

90

1

T12

2

T26

2

T162

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

82

1

T24

3

T44

1

T161

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

92

1

T12

2

T37

1

T18

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

95

1

T37

4

T44

5

T86

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

97

1

T12

2

T26

1

T18

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

95

1

T12

3

T26

4

T18

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

94

1

T12

2

T24

2

T37

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

82

1

T18

1

T44

3

T163

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3724	1			T6	4		T16	33		T48	14
auto[0]	values[0]	valids[0x1]	16474	1			T3	16		T5	6		T6	6
auto[0]	values[1]	valids[0x1]	523	1			T15	2		T16	4		T30	5
auto[0]	values[2]	valids[0x0]	543	1			T6	2		T7	2		T16	6
auto[0]	values[2]	valids[0x1]	255	1			T3	4		T16	1		T30	1
auto[0]	values[3]	valids[0x0]	492	1			T16	3		T30	8		T49	3
auto[0]	values[3]	valids[0x1]	273	1			T16	2		T30	1		T51	2
auto[0]	values[4]	valids[0x0]	608	1			T14	2		T16	2		T30	7
auto[0]	values[4]	valids[0x1]	288	1			T16	1		T30	4		T50	4
auto[0]	values[5]	valids[0x0]	454	1			T16	1		T30	3		T49	1
auto[0]	values[5]	valids[0x1]	291	1			T16	3		T49	2		T38	2
auto[0]	values[6]	valids[0x0]	589	1			T30	3		T49	4		T164	4
auto[0]	values[6]	valids[0x1]	308	1			T16	3		T30	2		T49	2
auto[0]	values[7]	valids[0x0]	519	1			T6	4		T16	8		T30	7
auto[0]	values[7]	valids[0x1]	290	1			T30	5		T23	2		T108	2
auto[0]	values[8]	valids[0x0]	3375	1			T6	6		T7	4		T14	2
auto[0]	values[8]	valids[0x1]	2088	1			T5	2		T6	2		T14	2
auto[1]	values[0]	valids[0x0]	3628	1			T12	52		T24	35		T26	46
auto[1]	values[0]	valids[0x1]	14655	1			T12	119		T24	55		T26	85
auto[1]	values[1]	valids[0x1]	521	1			T12	7		T24	12		T26	3
auto[1]	values[2]	valids[0x0]	350	1			T12	1		T24	4		T37	1
auto[1]	values[2]	valids[0x1]	203	1			T24	6		T26	2		T18	2
auto[1]	values[3]	valids[0x0]	374	1			T12	7		T26	4		T37	5
auto[1]	values[3]	valids[0x1]	262	1			T12	6		T26	3		T37	6
auto[1]	values[4]	valids[0x0]	369	1			T24	1		T26	4		T37	11
auto[1]	values[4]	valids[0x1]	241	1			T12	3		T26	3		T18	2
auto[1]	values[5]	valids[0x0]	373	1			T12	3		T24	2		T26	8
auto[1]	values[5]	valids[0x1]	241	1			T12	6		T24	5		T26	1
auto[1]	values[6]	valids[0x0]	379	1			T12	2		T24	7		T26	1
auto[1]	values[6]	valids[0x1]	235	1			T12	13		T26	2		T18	2
auto[1]	values[7]	valids[0x0]	317	1			T24	3		T26	8		T18	4
auto[1]	values[7]	valids[0x1]	244	1			T12	5		T24	2		T26	1
auto[1]	values[8]	valids[0x0]	2318	1			T12	38		T13	1		T24	34
auto[1]	values[8]	valids[0x1]	1686	1			T12	21		T24	14		T26	17